[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_sa.c

/*
 * Copyright 2011 Red Hat Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 */
/*
 * Authors:
 *    Jerome Glisse <glisse@freedesktop.org>
 */
/* Algorithm:
 *
 * We store the last allocated bo in "hole", we always try to allocate
 * after the last allocated bo. Principle is that in a linear GPU ring
 * progression was is after last is the oldest bo we allocated and thus
 * the first one that should no longer be in use by the GPU.
 *
 * If it's not the case we skip over the bo after last to the closest
 * done bo if such one exist. If none exist and we are not asked to
 * block we report failure to allocate.
 *
 * If we are asked to block we wait on all the oldest fence of all
 * rings. We just wait for any of those fence to complete.
 */

#include "amdgpu.h"

int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
			      struct amdgpu_sa_manager *sa_manager,
			      unsigned int size, u32 suballoc_align, u32 domain)
{
	int r;

	r = amdgpu_bo_create_kernel(adev, size, AMDGPU_GPU_PAGE_SIZE, domain,
				    &sa_manager->bo, &sa_manager->gpu_addr,
				    &sa_manager->cpu_ptr);
	if (r) {
		dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
		return r;
	}

	memset(sa_manager->cpu_ptr, 0, size);
	drm_suballoc_manager_init(&sa_manager->base, size, suballoc_align);
	return r;
}

void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
			       struct amdgpu_sa_manager *sa_manager)
{
	if (sa_manager->bo == NULL) {
		dev_err(adev->dev, "no bo for sa manager\n");
		return;
	}

	drm_suballoc_manager_fini(&sa_manager->base);

	amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
}

int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
		     struct drm_suballoc **sa_bo,
		     unsigned int size)
{
	struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
						   GFP_KERNEL, false, 0);

	if (IS_ERR(sa)) {
		*sa_bo = NULL;

		return PTR_ERR(sa);
	}

	*sa_bo = sa;
	return 0;
}

void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct drm_suballoc **sa_bo,
		       struct dma_fence *fence)
{
	if (sa_bo == NULL || *sa_bo == NULL) {
		return;
	}

	drm_suballoc_free(*sa_bo, fence);
	*sa_bo = NULL;
}

#if defined(CONFIG_DEBUG_FS)

void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
				  struct seq_file *m)
{
	struct drm_printer p = drm_seq_file_printer(m);

	drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
}
#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2011 Red Hat Inc.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sub license, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	15	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	16	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	17	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	18	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	19	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	20	*
	21	* The above copyright notice and this permission notice (including the
	22	* next paragraph) shall be included in all copies or substantial portions
	23	* of the Software.
	24	*
	25	*/
	26	/*
	27	* Authors:
	28	* Jerome Glisse <glisse@freedesktop.org>
	29	*/
	30	/* Algorithm:
	31	*
	32	* We store the last allocated bo in "hole", we always try to allocate
	33	* after the last allocated bo. Principle is that in a linear GPU ring
	34	* progression was is after last is the oldest bo we allocated and thus
	35	* the first one that should no longer be in use by the GPU.
	36	*
	37	* If it's not the case we skip over the bo after last to the closest
	38	* done bo if such one exist. If none exist and we are not asked to
	39	* block we report failure to allocate.
	40	*
	41	* If we are asked to block we wait on all the oldest fence of all
	42	* rings. We just wait for any of those fence to complete.
	43	*/
fdf2f6c5	44
d38ceaf9 AD	45	#include "amdgpu.h"
d38ceaf9 AD	46
d38ceaf9 AD	47	int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
d38ceaf9 AD	48	struct amdgpu_sa_manager *sa_manager,
c103a23f	49	unsigned int size, u32 suballoc_align, u32 domain)
d38ceaf9	50	{
c103a23f	51	int r;
d38ceaf9	52
c103a23f ML	53	r = amdgpu_bo_create_kernel(adev, size, AMDGPU_GPU_PAGE_SIZE, domain,
	54	&sa_manager->bo, &sa_manager->gpu_addr,
	55	&sa_manager->cpu_ptr);
d38ceaf9 AD	56	if (r) {
	57	dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
	58	return r;
	59	}
	60
c103a23f ML	61	memset(sa_manager->cpu_ptr, 0, size);
c103a23f ML	62	drm_suballoc_manager_init(&sa_manager->base, size, suballoc_align);
d38ceaf9 AD	63	return r;
	64	}
	65
	66	void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
f3729f7b	67	struct amdgpu_sa_manager *sa_manager)
d38ceaf9	68	{
bffe07b8 ML	69	if (sa_manager->bo == NULL) {
	70	dev_err(adev->dev, "no bo for sa manager\n");
	71	return;
	72	}
	73
c103a23f	74	drm_suballoc_manager_fini(&sa_manager->base);
d38ceaf9	75
bffe07b8	76	amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
d38ceaf9 AD	77	}
d38ceaf9 AD	78
c103a23f ML	79	int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
	80	struct drm_suballoc **sa_bo,
	81	unsigned int size)
d38ceaf9	82	{
c103a23f	83	struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size,
e2884fe8	84	GFP_KERNEL, false, 0);
d38ceaf9	85
c103a23f ML	86	if (IS_ERR(sa)) {
c103a23f ML	87	*sa_bo = NULL;
d38ceaf9	88
c103a23f	89	return PTR_ERR(sa);
d38ceaf9	90	}
d38ceaf9	91
c103a23f	92	*sa_bo = sa;
d38ceaf9 AD	93	return 0;
	94	}
	95
c103a23f	96	void amdgpu_sa_bo_free(struct amdgpu_device adev, struct drm_suballoc *sa_bo,
f54d1867	97	struct dma_fence *fence)
d38ceaf9	98	{
d38ceaf9 AD	99	if (sa_bo == NULL \|\| *sa_bo == NULL) {
	100	return;
	101	}
	102
c103a23f	103	drm_suballoc_free(*sa_bo, fence);
d38ceaf9 AD	104	*sa_bo = NULL;
	105	}
	106
	107	#if defined(CONFIG_DEBUG_FS)
4f839a24	108
d38ceaf9 AD	109	void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
	110	struct seq_file *m)
	111	{
c103a23f	112	struct drm_printer p = drm_seq_file_printer(m);
6ba60b89	113
c103a23f	114	drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
d38ceaf9 AD	115	}
d38ceaf9 AD	116	#endif