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78023016 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_RING_H__ | |
25 | #define __AMDGPU_RING_H__ | |
26 | ||
b2ff0e8a | 27 | #include <drm/amdgpu_drm.h> |
1b1f42d8 | 28 | #include <drm/gpu_scheduler.h> |
78023016 CK |
29 | |
30 | /* max number of rings */ | |
f7243053 | 31 | #define AMDGPU_MAX_RINGS 18 |
78023016 CK |
32 | #define AMDGPU_MAX_GFX_RINGS 1 |
33 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | |
34 | #define AMDGPU_MAX_VCE_RINGS 3 | |
f7243053 | 35 | #define AMDGPU_MAX_UVD_ENC_RINGS 2 |
78023016 CK |
36 | |
37 | /* some special values for the owner field */ | |
38 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | |
39 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | |
40 | ||
41 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) | |
42 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
43 | ||
44 | enum amdgpu_ring_type { | |
45 | AMDGPU_RING_TYPE_GFX, | |
46 | AMDGPU_RING_TYPE_COMPUTE, | |
47 | AMDGPU_RING_TYPE_SDMA, | |
48 | AMDGPU_RING_TYPE_UVD, | |
2068751d | 49 | AMDGPU_RING_TYPE_VCE, |
50c3e232 | 50 | AMDGPU_RING_TYPE_KIQ, |
cca69fe8 | 51 | AMDGPU_RING_TYPE_UVD_ENC, |
8ace845f LL |
52 | AMDGPU_RING_TYPE_VCN_DEC, |
53 | AMDGPU_RING_TYPE_VCN_ENC | |
78023016 CK |
54 | }; |
55 | ||
56 | struct amdgpu_device; | |
57 | struct amdgpu_ring; | |
58 | struct amdgpu_ib; | |
59 | struct amdgpu_cs_parser; | |
b2ff0e8a | 60 | struct amdgpu_job; |
78023016 CK |
61 | |
62 | /* | |
63 | * Fences. | |
64 | */ | |
65 | struct amdgpu_fence_driver { | |
66 | uint64_t gpu_addr; | |
67 | volatile uint32_t *cpu_addr; | |
68 | /* sync_seq is protected by ring emission lock */ | |
69 | uint32_t sync_seq; | |
70 | atomic_t last_seq; | |
71 | bool initialized; | |
72 | struct amdgpu_irq_src *irq_src; | |
73 | unsigned irq_type; | |
74 | struct timer_list fallback_timer; | |
75 | unsigned num_fences_mask; | |
76 | spinlock_t lock; | |
220196b3 | 77 | struct dma_fence **fences; |
78023016 CK |
78 | }; |
79 | ||
80 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | |
81 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | |
2f9d4084 | 82 | void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); |
78023016 CK |
83 | |
84 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, | |
85 | unsigned num_hw_submission); | |
86 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, | |
87 | struct amdgpu_irq_src *irq_src, | |
88 | unsigned irq_type); | |
89 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); | |
90 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | |
220196b3 | 91 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence); |
43ca8efa | 92 | int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); |
78023016 CK |
93 | void amdgpu_fence_process(struct amdgpu_ring *ring); |
94 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | |
43ca8efa | 95 | signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, |
96 | uint32_t wait_seq, | |
97 | signed long timeout); | |
78023016 CK |
98 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); |
99 | ||
100 | /* | |
101 | * Rings. | |
102 | */ | |
103 | ||
104 | /* provided by hw blocks that expose a ring buffer for commands */ | |
105 | struct amdgpu_ring_funcs { | |
21cd942e | 106 | enum amdgpu_ring_type type; |
79887142 CK |
107 | uint32_t align_mask; |
108 | u32 nop; | |
536fbf94 | 109 | bool support_64bit_ptrs; |
0eeb68b3 | 110 | unsigned vmhub; |
21cd942e | 111 | |
78023016 | 112 | /* ring read/write ptr handling */ |
536fbf94 KW |
113 | u64 (*get_rptr)(struct amdgpu_ring *ring); |
114 | u64 (*get_wptr)(struct amdgpu_ring *ring); | |
78023016 CK |
115 | void (*set_wptr)(struct amdgpu_ring *ring); |
116 | /* validating and patching of IBs */ | |
117 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | |
e12f3d7a CK |
118 | /* constants to calculate how many DW are needed for an emit */ |
119 | unsigned emit_frame_size; | |
120 | unsigned emit_ib_size; | |
78023016 CK |
121 | /* command emit functions */ |
122 | void (*emit_ib)(struct amdgpu_ring *ring, | |
123 | struct amdgpu_ib *ib, | |
c4f46f22 | 124 | unsigned vmid, bool ctx_switch); |
78023016 CK |
125 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, |
126 | uint64_t seq, unsigned flags); | |
127 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); | |
c4f46f22 | 128 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, |
5a4633c4 | 129 | unsigned pasid, uint64_t pd_addr); |
78023016 | 130 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
78023016 CK |
131 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
132 | uint32_t gds_base, uint32_t gds_size, | |
133 | uint32_t gws_base, uint32_t gws_size, | |
134 | uint32_t oa_base, uint32_t oa_size); | |
135 | /* testing functions */ | |
136 | int (*test_ring)(struct amdgpu_ring *ring); | |
137 | int (*test_ib)(struct amdgpu_ring *ring, long timeout); | |
138 | /* insert NOP packets */ | |
139 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
ef44f854 | 140 | void (*insert_start)(struct amdgpu_ring *ring); |
135d4735 | 141 | void (*insert_end)(struct amdgpu_ring *ring); |
78023016 CK |
142 | /* pad the indirect buffer to the necessary number of dw */ |
143 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
144 | unsigned (*init_cond_exec)(struct amdgpu_ring *ring); | |
145 | void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); | |
146 | /* note usage for clock and power gating */ | |
147 | void (*begin_use)(struct amdgpu_ring *ring); | |
148 | void (*end_use)(struct amdgpu_ring *ring); | |
149 | void (*emit_switch_buffer) (struct amdgpu_ring *ring); | |
150 | void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); | |
b6091c12 XY |
151 | void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); |
152 | void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); | |
c1e877da CK |
153 | void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, |
154 | uint32_t val, uint32_t mask); | |
3b4d68e9 | 155 | void (*emit_tmz)(struct amdgpu_ring *ring, bool start); |
b2ff0e8a AR |
156 | /* priority functions */ |
157 | void (*set_priority) (struct amdgpu_ring *ring, | |
1b1f42d8 | 158 | enum drm_sched_priority priority); |
78023016 CK |
159 | }; |
160 | ||
161 | struct amdgpu_ring { | |
162 | struct amdgpu_device *adev; | |
163 | const struct amdgpu_ring_funcs *funcs; | |
164 | struct amdgpu_fence_driver fence_drv; | |
1b1f42d8 | 165 | struct drm_gpu_scheduler sched; |
795f2813 | 166 | struct list_head lru_list; |
78023016 CK |
167 | |
168 | struct amdgpu_bo *ring_obj; | |
169 | volatile uint32_t *ring; | |
170 | unsigned rptr_offs; | |
536fbf94 KW |
171 | u64 wptr; |
172 | u64 wptr_old; | |
78023016 CK |
173 | unsigned ring_size; |
174 | unsigned max_dw; | |
175 | int count_dw; | |
176 | uint64_t gpu_addr; | |
536fbf94 KW |
177 | uint64_t ptr_mask; |
178 | uint32_t buf_mask; | |
78023016 | 179 | bool ready; |
78023016 CK |
180 | u32 idx; |
181 | u32 me; | |
182 | u32 pipe; | |
183 | u32 queue; | |
184 | struct amdgpu_bo *mqd_obj; | |
f3972b53 | 185 | uint64_t mqd_gpu_addr; |
59a82d7d | 186 | void *mqd_ptr; |
34534610 | 187 | uint64_t eop_gpu_addr; |
78023016 CK |
188 | u32 doorbell_index; |
189 | bool use_doorbell; | |
2ffe31de | 190 | bool use_pollmem; |
78023016 CK |
191 | unsigned wptr_offs; |
192 | unsigned fence_offs; | |
193 | uint64_t current_ctx; | |
78023016 CK |
194 | char name[16]; |
195 | unsigned cond_exe_offs; | |
196 | u64 cond_exe_gpu_addr; | |
197 | volatile u32 *cond_exe_cpu_addr; | |
4789c463 | 198 | unsigned vm_inv_eng; |
3af81440 | 199 | struct dma_fence *vmid_wait; |
dd684d31 | 200 | bool has_compute_vm_bug; |
b2ff0e8a | 201 | |
1b1f42d8 | 202 | atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; |
b2ff0e8a AR |
203 | struct mutex priority_mutex; |
204 | /* protected by priority_mutex */ | |
205 | int priority; | |
206 | ||
78023016 CK |
207 | #if defined(CONFIG_DEBUG_FS) |
208 | struct dentry *ent; | |
209 | #endif | |
210 | }; | |
211 | ||
212 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); | |
213 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); | |
214 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
215 | void amdgpu_ring_commit(struct amdgpu_ring *ring); | |
216 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | |
b2ff0e8a | 217 | void amdgpu_ring_priority_get(struct amdgpu_ring *ring, |
1b1f42d8 | 218 | enum drm_sched_priority priority); |
b2ff0e8a | 219 | void amdgpu_ring_priority_put(struct amdgpu_ring *ring, |
1b1f42d8 | 220 | enum drm_sched_priority priority); |
78023016 | 221 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, |
79887142 CK |
222 | unsigned ring_size, struct amdgpu_irq_src *irq_src, |
223 | unsigned irq_type); | |
78023016 | 224 | void amdgpu_ring_fini(struct amdgpu_ring *ring); |
35161bbc AR |
225 | int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, |
226 | int *blacklist, int num_blacklist, | |
227 | bool lru_pipe_order, struct amdgpu_ring **ring); | |
795f2813 | 228 | void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring); |
c79ecfbf ML |
229 | static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) |
230 | { | |
231 | int i = 0; | |
e09706f4 | 232 | while (i <= ring->buf_mask) |
c79ecfbf ML |
233 | ring->ring[i++] = ring->funcs->nop; |
234 | ||
235 | } | |
78023016 | 236 | |
e8110b1c CK |
237 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) |
238 | { | |
239 | if (ring->count_dw <= 0) | |
240 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); | |
241 | ring->ring[ring->wptr++ & ring->buf_mask] = v; | |
242 | ring->wptr &= ring->ptr_mask; | |
243 | ring->count_dw--; | |
244 | } | |
245 | ||
246 | static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, | |
247 | void *src, int count_dw) | |
248 | { | |
249 | unsigned occupied, chunk1, chunk2; | |
250 | void *dst; | |
251 | ||
369421cb | 252 | if (unlikely(ring->count_dw < count_dw)) |
e8110b1c | 253 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
e8110b1c CK |
254 | |
255 | occupied = ring->wptr & ring->buf_mask; | |
256 | dst = (void *)&ring->ring[occupied]; | |
257 | chunk1 = ring->buf_mask + 1 - occupied; | |
258 | chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; | |
259 | chunk2 = count_dw - chunk1; | |
260 | chunk1 <<= 2; | |
261 | chunk2 <<= 2; | |
262 | ||
263 | if (chunk1) | |
264 | memcpy(dst, src, chunk1); | |
265 | ||
266 | if (chunk2) { | |
267 | src += chunk1; | |
268 | dst = (void *)ring->ring; | |
269 | memcpy(dst, src, chunk2); | |
270 | } | |
271 | ||
272 | ring->wptr += count_dw; | |
273 | ring->wptr &= ring->ptr_mask; | |
274 | ring->count_dw -= count_dw; | |
275 | } | |
276 | ||
78023016 | 277 | #endif |