[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__

#include <drm/amdgpu_drm.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_print.h>

/* max number of rings */
#define AMDGPU_MAX_RINGS		18
#define AMDGPU_MAX_GFX_RINGS		1
#define AMDGPU_MAX_COMPUTE_RINGS	8
#define AMDGPU_MAX_VCE_RINGS		3
#define AMDGPU_MAX_UVD_ENC_RINGS	2

/* some special values for the owner field */
#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)

#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)

enum amdgpu_ring_type {
	AMDGPU_RING_TYPE_GFX,
	AMDGPU_RING_TYPE_COMPUTE,
	AMDGPU_RING_TYPE_SDMA,
	AMDGPU_RING_TYPE_UVD,
	AMDGPU_RING_TYPE_VCE,
	AMDGPU_RING_TYPE_KIQ,
	AMDGPU_RING_TYPE_UVD_ENC,
	AMDGPU_RING_TYPE_VCN_DEC,
	AMDGPU_RING_TYPE_VCN_ENC
};

struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;
struct amdgpu_job;

/*
 * Fences.
 */
struct amdgpu_fence_driver {
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint32_t			sync_seq;
	atomic_t			last_seq;
	bool				initialized;
	struct amdgpu_irq_src		*irq_src;
	unsigned			irq_type;
	struct timer_list		fallback_timer;
	unsigned			num_fences_mask;
	spinlock_t			lock;
	struct dma_fence		**fences;
};

int amdgpu_fence_driver_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);

int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
				  unsigned num_hw_submission);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
				   struct amdgpu_irq_src *irq_src,
				   unsigned irq_type);
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
		      unsigned flags);
int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
void amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
				      uint32_t wait_seq,
				      signed long timeout);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

/*
 * Rings.
 */

/* provided by hw blocks that expose a ring buffer for commands */
struct amdgpu_ring_funcs {
	enum amdgpu_ring_type	type;
	uint32_t		align_mask;
	u32			nop;
	bool			support_64bit_ptrs;
	unsigned		vmhub;

	/* ring read/write ptr handling */
	u64 (*get_rptr)(struct amdgpu_ring *ring);
	u64 (*get_wptr)(struct amdgpu_ring *ring);
	void (*set_wptr)(struct amdgpu_ring *ring);
	/* validating and patching of IBs */
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	/* constants to calculate how many DW are needed for an emit */
	unsigned emit_frame_size;
	unsigned emit_ib_size;
	/* command emit functions */
	void (*emit_ib)(struct amdgpu_ring *ring,
			struct amdgpu_ib *ib,
			unsigned vmid, bool ctx_switch);
	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
			   uint64_t seq, unsigned flags);
	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
			      uint64_t pd_addr);
	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
				uint32_t gds_base, uint32_t gds_size,
				uint32_t gws_base, uint32_t gws_size,
				uint32_t oa_base, uint32_t oa_size);
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
	void (*insert_start)(struct amdgpu_ring *ring);
	void (*insert_end)(struct amdgpu_ring *ring);
	/* pad the indirect buffer to the necessary number of dw */
	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
	/* note usage for clock and power gating */
	void (*begin_use)(struct amdgpu_ring *ring);
	void (*end_use)(struct amdgpu_ring *ring);
	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
			      uint32_t val, uint32_t mask);
	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
					uint32_t reg0, uint32_t reg1,
					uint32_t ref, uint32_t mask);
	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
	/* priority functions */
	void (*set_priority) (struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
};

struct amdgpu_ring {
	struct amdgpu_device		*adev;
	const struct amdgpu_ring_funcs	*funcs;
	struct amdgpu_fence_driver	fence_drv;
	struct drm_gpu_scheduler	sched;
	struct list_head		lru_list;

	struct amdgpu_bo	*ring_obj;
	volatile uint32_t	*ring;
	unsigned		rptr_offs;
	u64			wptr;
	u64			wptr_old;
	unsigned		ring_size;
	unsigned		max_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint64_t		ptr_mask;
	uint32_t		buf_mask;
	bool			ready;
	u32			idx;
	u32			me;
	u32			pipe;
	u32			queue;
	struct amdgpu_bo	*mqd_obj;
	uint64_t                mqd_gpu_addr;
	void                    *mqd_ptr;
	uint64_t                eop_gpu_addr;
	u32			doorbell_index;
	bool			use_doorbell;
	bool			use_pollmem;
	unsigned		wptr_offs;
	unsigned		fence_offs;
	uint64_t		current_ctx;
	char			name[16];
	unsigned		cond_exe_offs;
	u64			cond_exe_gpu_addr;
	volatile u32		*cond_exe_cpu_addr;
	unsigned		vm_inv_eng;
	struct dma_fence	*vmid_wait;
	bool			has_compute_vm_bug;

	atomic_t		num_jobs[DRM_SCHED_PRIORITY_MAX];
	struct mutex		priority_mutex;
	/* protected by priority_mutex */
	int			priority;

#if defined(CONFIG_DEBUG_FS)
	struct dentry *ent;
#endif
};

int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
		     unsigned irq_type);
void amdgpu_ring_fini(struct amdgpu_ring *ring);
int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
			int *blacklist, int num_blacklist,
			bool lru_pipe_order, struct amdgpu_ring **ring);
void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
						uint32_t reg0, uint32_t val0,
						uint32_t reg1, uint32_t val1);

static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
	int i = 0;
	while (i <= ring->buf_mask)
		ring->ring[i++] = ring->funcs->nop;

}

static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
{
	if (ring->count_dw <= 0)
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
}

static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
					      void *src, int count_dw)
{
	unsigned occupied, chunk1, chunk2;
	void *dst;

	if (unlikely(ring->count_dw < count_dw))
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	occupied = ring->wptr & ring->buf_mask;
	dst = (void *)&ring->ring[occupied];
	chunk1 = ring->buf_mask + 1 - occupied;
	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	chunk2 = count_dw - chunk1;
	chunk1 <<= 2;
	chunk2 <<= 2;

	if (chunk1)
		memcpy(dst, src, chunk1);

	if (chunk2) {
		src += chunk1;
		dst = (void *)ring->ring;
		memcpy(dst, src, chunk2);
	}

	ring->wptr += count_dw;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw -= count_dw;
}

#endif
Commit	Line	Data
78023016 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_RING_H__
	25	#define __AMDGPU_RING_H__
	26
b2ff0e8a	27	#include <drm/amdgpu_drm.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
61b100e9	29	#include <drm/drm_print.h>
78023016 CK	30
78023016 CK	31	/* max number of rings */
f7243053	32	#define AMDGPU_MAX_RINGS 18
78023016 CK	33	#define AMDGPU_MAX_GFX_RINGS 1
	34	#define AMDGPU_MAX_COMPUTE_RINGS 8
	35	#define AMDGPU_MAX_VCE_RINGS 3
f7243053	36	#define AMDGPU_MAX_UVD_ENC_RINGS 2
78023016 CK	37
78023016 CK	38	/* some special values for the owner field */
d8d019cc FK	39	#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
	40	#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
	41	#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
78023016 CK	42
	43	#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
	44	#define AMDGPU_FENCE_FLAG_INT (1 << 1)
d240cd9e	45	#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
78023016 CK	46
	47	enum amdgpu_ring_type {
	48	AMDGPU_RING_TYPE_GFX,
	49	AMDGPU_RING_TYPE_COMPUTE,
	50	AMDGPU_RING_TYPE_SDMA,
	51	AMDGPU_RING_TYPE_UVD,
2068751d	52	AMDGPU_RING_TYPE_VCE,
50c3e232	53	AMDGPU_RING_TYPE_KIQ,
cca69fe8	54	AMDGPU_RING_TYPE_UVD_ENC,
8ace845f LL	55	AMDGPU_RING_TYPE_VCN_DEC,
8ace845f LL	56	AMDGPU_RING_TYPE_VCN_ENC
78023016 CK	57	};
	58
	59	struct amdgpu_device;
	60	struct amdgpu_ring;
	61	struct amdgpu_ib;
	62	struct amdgpu_cs_parser;
b2ff0e8a	63	struct amdgpu_job;
78023016 CK	64
	65	/*
	66	* Fences.
	67	*/
	68	struct amdgpu_fence_driver {
	69	uint64_t gpu_addr;
	70	volatile uint32_t *cpu_addr;
	71	/* sync_seq is protected by ring emission lock */
	72	uint32_t sync_seq;
	73	atomic_t last_seq;
	74	bool initialized;
	75	struct amdgpu_irq_src *irq_src;
	76	unsigned irq_type;
	77	struct timer_list fallback_timer;
	78	unsigned num_fences_mask;
	79	spinlock_t lock;
220196b3	80	struct dma_fence **fences;
78023016 CK	81	};
	82
	83	int amdgpu_fence_driver_init(struct amdgpu_device *adev);
	84	void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
2f9d4084	85	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
78023016 CK	86
	87	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
	88	unsigned num_hw_submission);
	89	int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
	90	struct amdgpu_irq_src *irq_src,
	91	unsigned irq_type);
	92	void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
	93	void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
d240cd9e MO	94	int amdgpu_fence_emit(struct amdgpu_ring ring, struct dma_fence *fence,
d240cd9e MO	95	unsigned flags);
43ca8efa	96	int amdgpu_fence_emit_polling(struct amdgpu_ring ring, uint32_t s);
78023016 CK	97	void amdgpu_fence_process(struct amdgpu_ring *ring);
78023016 CK	98	int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
43ca8efa	99	signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
	100	uint32_t wait_seq,
	101	signed long timeout);
78023016 CK	102	unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
	103
	104	/*
	105	* Rings.
	106	*/
	107
	108	/* provided by hw blocks that expose a ring buffer for commands */
	109	struct amdgpu_ring_funcs {
21cd942e	110	enum amdgpu_ring_type type;
79887142 CK	111	uint32_t align_mask;
79887142 CK	112	u32 nop;
536fbf94	113	bool support_64bit_ptrs;
0eeb68b3	114	unsigned vmhub;
21cd942e	115
78023016	116	/* ring read/write ptr handling */
536fbf94 KW	117	u64 (get_rptr)(struct amdgpu_ring ring);
536fbf94 KW	118	u64 (get_wptr)(struct amdgpu_ring ring);
78023016 CK	119	void (set_wptr)(struct amdgpu_ring ring);
	120	/* validating and patching of IBs */
	121	int (parse_cs)(struct amdgpu_cs_parser p, uint32_t ib_idx);
e12f3d7a CK	122	/* constants to calculate how many DW are needed for an emit */
	123	unsigned emit_frame_size;
	124	unsigned emit_ib_size;
78023016 CK	125	/* command emit functions */
	126	void (emit_ib)(struct amdgpu_ring ring,
	127	struct amdgpu_ib *ib,
c4f46f22	128	unsigned vmid, bool ctx_switch);
78023016 CK	129	void (emit_fence)(struct amdgpu_ring ring, uint64_t addr,
	130	uint64_t seq, unsigned flags);
	131	void (emit_pipeline_sync)(struct amdgpu_ring ring);
c4f46f22	132	void (emit_vm_flush)(struct amdgpu_ring ring, unsigned vmid,
c633c00b	133	uint64_t pd_addr);
78023016	134	void (emit_hdp_flush)(struct amdgpu_ring ring);
78023016 CK	135	void (emit_gds_switch)(struct amdgpu_ring ring, uint32_t vmid,
	136	uint32_t gds_base, uint32_t gds_size,
	137	uint32_t gws_base, uint32_t gws_size,
	138	uint32_t oa_base, uint32_t oa_size);
	139	/* testing functions */
	140	int (test_ring)(struct amdgpu_ring ring);
	141	int (test_ib)(struct amdgpu_ring ring, long timeout);
	142	/* insert NOP packets */
	143	void (insert_nop)(struct amdgpu_ring ring, uint32_t count);
ef44f854	144	void (insert_start)(struct amdgpu_ring ring);
135d4735	145	void (insert_end)(struct amdgpu_ring ring);
78023016 CK	146	/* pad the indirect buffer to the necessary number of dw */
	147	void (pad_ib)(struct amdgpu_ring ring, struct amdgpu_ib *ib);
	148	unsigned (init_cond_exec)(struct amdgpu_ring ring);
	149	void (patch_cond_exec)(struct amdgpu_ring ring, unsigned offset);
	150	/* note usage for clock and power gating */
	151	void (begin_use)(struct amdgpu_ring ring);
	152	void (end_use)(struct amdgpu_ring ring);
	153	void (emit_switch_buffer) (struct amdgpu_ring ring);
	154	void (emit_cntxcntl) (struct amdgpu_ring ring, uint32_t flags);
b6091c12 XY	155	void (emit_rreg)(struct amdgpu_ring ring, uint32_t reg);
b6091c12 XY	156	void (emit_wreg)(struct amdgpu_ring ring, uint32_t reg, uint32_t val);
c1e877da CK	157	void (emit_reg_wait)(struct amdgpu_ring ring, uint32_t reg,
c1e877da CK	158	uint32_t val, uint32_t mask);
82853638 AD	159	void (emit_reg_write_reg_wait)(struct amdgpu_ring ring,
	160	uint32_t reg0, uint32_t reg1,
	161	uint32_t ref, uint32_t mask);
3b4d68e9	162	void (emit_tmz)(struct amdgpu_ring ring, bool start);
b2ff0e8a AR	163	/* priority functions */
b2ff0e8a AR	164	void (set_priority) (struct amdgpu_ring ring,
1b1f42d8	165	enum drm_sched_priority priority);
78023016 CK	166	};
	167
	168	struct amdgpu_ring {
	169	struct amdgpu_device *adev;
	170	const struct amdgpu_ring_funcs *funcs;
	171	struct amdgpu_fence_driver fence_drv;
1b1f42d8	172	struct drm_gpu_scheduler sched;
795f2813	173	struct list_head lru_list;
78023016 CK	174
	175	struct amdgpu_bo *ring_obj;
	176	volatile uint32_t *ring;
	177	unsigned rptr_offs;
536fbf94 KW	178	u64 wptr;
536fbf94 KW	179	u64 wptr_old;
78023016 CK	180	unsigned ring_size;
	181	unsigned max_dw;
	182	int count_dw;
	183	uint64_t gpu_addr;
536fbf94 KW	184	uint64_t ptr_mask;
536fbf94 KW	185	uint32_t buf_mask;
78023016	186	bool ready;
78023016 CK	187	u32 idx;
	188	u32 me;
	189	u32 pipe;
	190	u32 queue;
	191	struct amdgpu_bo *mqd_obj;
f3972b53	192	uint64_t mqd_gpu_addr;
59a82d7d	193	void *mqd_ptr;
34534610	194	uint64_t eop_gpu_addr;
78023016 CK	195	u32 doorbell_index;
78023016 CK	196	bool use_doorbell;
2ffe31de	197	bool use_pollmem;
78023016 CK	198	unsigned wptr_offs;
	199	unsigned fence_offs;
	200	uint64_t current_ctx;
78023016 CK	201	char name[16];
	202	unsigned cond_exe_offs;
	203	u64 cond_exe_gpu_addr;
	204	volatile u32 *cond_exe_cpu_addr;
4789c463	205	unsigned vm_inv_eng;
3af81440	206	struct dma_fence *vmid_wait;
dd684d31	207	bool has_compute_vm_bug;
b2ff0e8a	208
1b1f42d8	209	atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
b2ff0e8a AR	210	struct mutex priority_mutex;
	211	/* protected by priority_mutex */
	212	int priority;
	213
78023016 CK	214	#if defined(CONFIG_DEBUG_FS)
	215	struct dentry *ent;
	216	#endif
	217	};
	218
	219	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
	220	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
	221	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);
	222	void amdgpu_ring_commit(struct amdgpu_ring *ring);
	223	void amdgpu_ring_undo(struct amdgpu_ring *ring);
b2ff0e8a	224	void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
1b1f42d8	225	enum drm_sched_priority priority);
b2ff0e8a	226	void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
1b1f42d8	227	enum drm_sched_priority priority);
78023016	228	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
79887142 CK	229	unsigned ring_size, struct amdgpu_irq_src *irq_src,
79887142 CK	230	unsigned irq_type);
78023016	231	void amdgpu_ring_fini(struct amdgpu_ring *ring);
35161bbc AR	232	int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
	233	int *blacklist, int num_blacklist,
	234	bool lru_pipe_order, struct amdgpu_ring **ring);
795f2813	235	void amdgpu_ring_lru_touch(struct amdgpu_device adev, struct amdgpu_ring ring);
82853638 AD	236	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
	237	uint32_t reg0, uint32_t val0,
	238	uint32_t reg1, uint32_t val1);
	239
c79ecfbf ML	240	static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
	241	{
	242	int i = 0;
e09706f4	243	while (i <= ring->buf_mask)
c79ecfbf ML	244	ring->ring[i++] = ring->funcs->nop;
	245
	246	}
78023016	247
e8110b1c CK	248	static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
	249	{
	250	if (ring->count_dw <= 0)
	251	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	252	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	253	ring->wptr &= ring->ptr_mask;
	254	ring->count_dw--;
	255	}
	256
	257	static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
	258	void *src, int count_dw)
	259	{
	260	unsigned occupied, chunk1, chunk2;
	261	void *dst;
	262
369421cb	263	if (unlikely(ring->count_dw < count_dw))
e8110b1c	264	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
e8110b1c CK	265
	266	occupied = ring->wptr & ring->buf_mask;
	267	dst = (void *)&ring->ring[occupied];
	268	chunk1 = ring->buf_mask + 1 - occupied;
	269	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	270	chunk2 = count_dw - chunk1;
	271	chunk1 <<= 2;
	272	chunk2 <<= 2;
	273
	274	if (chunk1)
	275	memcpy(dst, src, chunk1);
	276
	277	if (chunk2) {
	278	src += chunk1;
	279	dst = (void *)ring->ring;
	280	memcpy(dst, src, chunk2);
	281	}
	282
	283	ring->wptr += count_dw;
	284	ring->wptr &= ring->ptr_mask;
	285	ring->count_dw -= count_dw;
	286	}
	287
78023016	288	#endif