[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__

#include <drm/amdgpu_drm.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_print.h>

/* max number of rings */
#define AMDGPU_MAX_RINGS		21
#define AMDGPU_MAX_GFX_RINGS		1
#define AMDGPU_MAX_COMPUTE_RINGS	8
#define AMDGPU_MAX_VCE_RINGS		3
#define AMDGPU_MAX_UVD_ENC_RINGS	2

/* some special values for the owner field */
#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)

#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)

#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

enum amdgpu_ring_type {
	AMDGPU_RING_TYPE_GFX,
	AMDGPU_RING_TYPE_COMPUTE,
	AMDGPU_RING_TYPE_SDMA,
	AMDGPU_RING_TYPE_UVD,
	AMDGPU_RING_TYPE_VCE,
	AMDGPU_RING_TYPE_KIQ,
	AMDGPU_RING_TYPE_UVD_ENC,
	AMDGPU_RING_TYPE_VCN_DEC,
	AMDGPU_RING_TYPE_VCN_ENC,
	AMDGPU_RING_TYPE_VCN_JPEG
};

struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;
struct amdgpu_job;

/*
 * Fences.
 */
struct amdgpu_fence_driver {
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint32_t			sync_seq;
	atomic_t			last_seq;
	bool				initialized;
	struct amdgpu_irq_src		*irq_src;
	unsigned			irq_type;
	unsigned			num_fences_mask;
	spinlock_t			lock;
	struct dma_fence		**fences;
};

int amdgpu_fence_driver_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);

int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
				  unsigned num_hw_submission);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
				   struct amdgpu_irq_src *irq_src,
				   unsigned irq_type);
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
		      unsigned flags);
int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
void amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
				      uint32_t wait_seq,
				      signed long timeout);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

/*
 * Rings.
 */

/* provided by hw blocks that expose a ring buffer for commands */
struct amdgpu_ring_funcs {
	enum amdgpu_ring_type	type;
	uint32_t		align_mask;
	u32			nop;
	bool			support_64bit_ptrs;
	unsigned		vmhub;
	unsigned		extra_dw;

	/* ring read/write ptr handling */
	u64 (*get_rptr)(struct amdgpu_ring *ring);
	u64 (*get_wptr)(struct amdgpu_ring *ring);
	void (*set_wptr)(struct amdgpu_ring *ring);
	/* validating and patching of IBs */
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	/* constants to calculate how many DW are needed for an emit */
	unsigned emit_frame_size;
	unsigned emit_ib_size;
	/* command emit functions */
	void (*emit_ib)(struct amdgpu_ring *ring,
			struct amdgpu_ib *ib,
			unsigned vmid, bool ctx_switch);
	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
			   uint64_t seq, unsigned flags);
	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
			      uint64_t pd_addr);
	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
				uint32_t gds_base, uint32_t gds_size,
				uint32_t gws_base, uint32_t gws_size,
				uint32_t oa_base, uint32_t oa_size);
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
	void (*insert_start)(struct amdgpu_ring *ring);
	void (*insert_end)(struct amdgpu_ring *ring);
	/* pad the indirect buffer to the necessary number of dw */
	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
	/* note usage for clock and power gating */
	void (*begin_use)(struct amdgpu_ring *ring);
	void (*end_use)(struct amdgpu_ring *ring);
	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
			      uint32_t val, uint32_t mask);
	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
					uint32_t reg0, uint32_t reg1,
					uint32_t ref, uint32_t mask);
	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
	/* priority functions */
	void (*set_priority) (struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
	/* Try to soft recover the ring to make the fence signal */
	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
};

struct amdgpu_ring {
	struct amdgpu_device		*adev;
	const struct amdgpu_ring_funcs	*funcs;
	struct amdgpu_fence_driver	fence_drv;
	struct drm_gpu_scheduler	sched;

	struct amdgpu_bo	*ring_obj;
	volatile uint32_t	*ring;
	unsigned		rptr_offs;
	u64			wptr;
	u64			wptr_old;
	unsigned		ring_size;
	unsigned		max_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint64_t		ptr_mask;
	uint32_t		buf_mask;
	bool			ready;
	u32			idx;
	u32			me;
	u32			pipe;
	u32			queue;
	struct amdgpu_bo	*mqd_obj;
	uint64_t                mqd_gpu_addr;
	void                    *mqd_ptr;
	uint64_t                eop_gpu_addr;
	u32			doorbell_index;
	bool			use_doorbell;
	bool			use_pollmem;
	unsigned		wptr_offs;
	unsigned		fence_offs;
	uint64_t		current_ctx;
	char			name[16];
	unsigned		cond_exe_offs;
	u64			cond_exe_gpu_addr;
	volatile u32		*cond_exe_cpu_addr;
	unsigned		vm_inv_eng;
	struct dma_fence	*vmid_wait;
	bool			has_compute_vm_bug;

	atomic_t		num_jobs[DRM_SCHED_PRIORITY_MAX];
	struct mutex		priority_mutex;
	/* protected by priority_mutex */
	int			priority;

#if defined(CONFIG_DEBUG_FS)
	struct dentry *ent;
#endif
};

#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
			      enum drm_sched_priority priority);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
		     unsigned irq_type);
void amdgpu_ring_fini(struct amdgpu_ring *ring);
void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
						uint32_t reg0, uint32_t val0,
						uint32_t reg1, uint32_t val1);
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
			       struct dma_fence *fence);

static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
	int i = 0;
	while (i <= ring->buf_mask)
		ring->ring[i++] = ring->funcs->nop;

}

static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
{
	if (ring->count_dw <= 0)
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
}

static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
					      void *src, int count_dw)
{
	unsigned occupied, chunk1, chunk2;
	void *dst;

	if (unlikely(ring->count_dw < count_dw))
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	occupied = ring->wptr & ring->buf_mask;
	dst = (void *)&ring->ring[occupied];
	chunk1 = ring->buf_mask + 1 - occupied;
	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	chunk2 = count_dw - chunk1;
	chunk1 <<= 2;
	chunk2 <<= 2;

	if (chunk1)
		memcpy(dst, src, chunk1);

	if (chunk2) {
		src += chunk1;
		dst = (void *)ring->ring;
		memcpy(dst, src, chunk2);
	}

	ring->wptr += count_dw;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw -= count_dw;
}

#endif
Commit	Line	Data
78023016 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_RING_H__
	25	#define __AMDGPU_RING_H__
	26
b2ff0e8a	27	#include <drm/amdgpu_drm.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
61b100e9	29	#include <drm/drm_print.h>
78023016 CK	30
78023016 CK	31	/* max number of rings */
3b17c622	32	#define AMDGPU_MAX_RINGS 21
78023016 CK	33	#define AMDGPU_MAX_GFX_RINGS 1
	34	#define AMDGPU_MAX_COMPUTE_RINGS 8
	35	#define AMDGPU_MAX_VCE_RINGS 3
f7243053	36	#define AMDGPU_MAX_UVD_ENC_RINGS 2
78023016 CK	37
78023016 CK	38	/* some special values for the owner field */
d8d019cc FK	39	#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
	40	#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
	41	#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
78023016 CK	42
	43	#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
	44	#define AMDGPU_FENCE_FLAG_INT (1 << 1)
d240cd9e	45	#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
78023016	46
0e28b10f CK	47	#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
0e28b10f CK	48
78023016 CK	49	enum amdgpu_ring_type {
	50	AMDGPU_RING_TYPE_GFX,
	51	AMDGPU_RING_TYPE_COMPUTE,
	52	AMDGPU_RING_TYPE_SDMA,
	53	AMDGPU_RING_TYPE_UVD,
2068751d	54	AMDGPU_RING_TYPE_VCE,
50c3e232	55	AMDGPU_RING_TYPE_KIQ,
cca69fe8	56	AMDGPU_RING_TYPE_UVD_ENC,
8ace845f	57	AMDGPU_RING_TYPE_VCN_DEC,
8e0fce5a BZ	58	AMDGPU_RING_TYPE_VCN_ENC,
8e0fce5a BZ	59	AMDGPU_RING_TYPE_VCN_JPEG
78023016 CK	60	};
	61
	62	struct amdgpu_device;
	63	struct amdgpu_ring;
	64	struct amdgpu_ib;
	65	struct amdgpu_cs_parser;
b2ff0e8a	66	struct amdgpu_job;
78023016 CK	67
	68	/*
	69	* Fences.
	70	*/
	71	struct amdgpu_fence_driver {
	72	uint64_t gpu_addr;
	73	volatile uint32_t *cpu_addr;
	74	/* sync_seq is protected by ring emission lock */
	75	uint32_t sync_seq;
	76	atomic_t last_seq;
	77	bool initialized;
	78	struct amdgpu_irq_src *irq_src;
	79	unsigned irq_type;
78023016 CK	80	unsigned num_fences_mask;
78023016 CK	81	spinlock_t lock;
220196b3	82	struct dma_fence **fences;
78023016 CK	83	};
	84
	85	int amdgpu_fence_driver_init(struct amdgpu_device *adev);
	86	void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
2f9d4084	87	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
78023016 CK	88
	89	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
	90	unsigned num_hw_submission);
	91	int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
	92	struct amdgpu_irq_src *irq_src,
	93	unsigned irq_type);
	94	void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
	95	void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
d240cd9e MO	96	int amdgpu_fence_emit(struct amdgpu_ring ring, struct dma_fence *fence,
d240cd9e MO	97	unsigned flags);
43ca8efa	98	int amdgpu_fence_emit_polling(struct amdgpu_ring ring, uint32_t s);
78023016 CK	99	void amdgpu_fence_process(struct amdgpu_ring *ring);
78023016 CK	100	int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
43ca8efa	101	signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
	102	uint32_t wait_seq,
	103	signed long timeout);
78023016 CK	104	unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
	105
	106	/*
	107	* Rings.
	108	*/
	109
	110	/* provided by hw blocks that expose a ring buffer for commands */
	111	struct amdgpu_ring_funcs {
21cd942e	112	enum amdgpu_ring_type type;
79887142 CK	113	uint32_t align_mask;
79887142 CK	114	u32 nop;
536fbf94	115	bool support_64bit_ptrs;
0eeb68b3	116	unsigned vmhub;
c8c1a1d2	117	unsigned extra_dw;
21cd942e	118
78023016	119	/* ring read/write ptr handling */
536fbf94 KW	120	u64 (get_rptr)(struct amdgpu_ring ring);
536fbf94 KW	121	u64 (get_wptr)(struct amdgpu_ring ring);
78023016 CK	122	void (set_wptr)(struct amdgpu_ring ring);
	123	/* validating and patching of IBs */
	124	int (parse_cs)(struct amdgpu_cs_parser p, uint32_t ib_idx);
9d248517	125	int (patch_cs_in_place)(struct amdgpu_cs_parser p, uint32_t ib_idx);
e12f3d7a CK	126	/* constants to calculate how many DW are needed for an emit */
	127	unsigned emit_frame_size;
	128	unsigned emit_ib_size;
78023016 CK	129	/* command emit functions */
	130	void (emit_ib)(struct amdgpu_ring ring,
	131	struct amdgpu_ib *ib,
c4f46f22	132	unsigned vmid, bool ctx_switch);
78023016 CK	133	void (emit_fence)(struct amdgpu_ring ring, uint64_t addr,
	134	uint64_t seq, unsigned flags);
	135	void (emit_pipeline_sync)(struct amdgpu_ring ring);
c4f46f22	136	void (emit_vm_flush)(struct amdgpu_ring ring, unsigned vmid,
c633c00b	137	uint64_t pd_addr);
78023016	138	void (emit_hdp_flush)(struct amdgpu_ring ring);
78023016 CK	139	void (emit_gds_switch)(struct amdgpu_ring ring, uint32_t vmid,
	140	uint32_t gds_base, uint32_t gds_size,
	141	uint32_t gws_base, uint32_t gws_size,
	142	uint32_t oa_base, uint32_t oa_size);
	143	/* testing functions */
	144	int (test_ring)(struct amdgpu_ring ring);
	145	int (test_ib)(struct amdgpu_ring ring, long timeout);
	146	/* insert NOP packets */
	147	void (insert_nop)(struct amdgpu_ring ring, uint32_t count);
ef44f854	148	void (insert_start)(struct amdgpu_ring ring);
135d4735	149	void (insert_end)(struct amdgpu_ring ring);
78023016 CK	150	/* pad the indirect buffer to the necessary number of dw */
	151	void (pad_ib)(struct amdgpu_ring ring, struct amdgpu_ib *ib);
	152	unsigned (init_cond_exec)(struct amdgpu_ring ring);
	153	void (patch_cond_exec)(struct amdgpu_ring ring, unsigned offset);
	154	/* note usage for clock and power gating */
	155	void (begin_use)(struct amdgpu_ring ring);
	156	void (end_use)(struct amdgpu_ring ring);
	157	void (emit_switch_buffer) (struct amdgpu_ring ring);
	158	void (emit_cntxcntl) (struct amdgpu_ring ring, uint32_t flags);
b6091c12 XY	159	void (emit_rreg)(struct amdgpu_ring ring, uint32_t reg);
b6091c12 XY	160	void (emit_wreg)(struct amdgpu_ring ring, uint32_t reg, uint32_t val);
c1e877da CK	161	void (emit_reg_wait)(struct amdgpu_ring ring, uint32_t reg,
c1e877da CK	162	uint32_t val, uint32_t mask);
82853638 AD	163	void (emit_reg_write_reg_wait)(struct amdgpu_ring ring,
	164	uint32_t reg0, uint32_t reg1,
	165	uint32_t ref, uint32_t mask);
3b4d68e9	166	void (emit_tmz)(struct amdgpu_ring ring, bool start);
b2ff0e8a AR	167	/* priority functions */
b2ff0e8a AR	168	void (set_priority) (struct amdgpu_ring ring,
1b1f42d8	169	enum drm_sched_priority priority);
7876fa4f CK	170	/* Try to soft recover the ring to make the fence signal */
7876fa4f CK	171	void (soft_recovery)(struct amdgpu_ring ring, unsigned vmid);
78023016 CK	172	};
	173
	174	struct amdgpu_ring {
	175	struct amdgpu_device *adev;
	176	const struct amdgpu_ring_funcs *funcs;
	177	struct amdgpu_fence_driver fence_drv;
1b1f42d8	178	struct drm_gpu_scheduler sched;
78023016 CK	179
	180	struct amdgpu_bo *ring_obj;
	181	volatile uint32_t *ring;
	182	unsigned rptr_offs;
536fbf94 KW	183	u64 wptr;
536fbf94 KW	184	u64 wptr_old;
78023016 CK	185	unsigned ring_size;
	186	unsigned max_dw;
	187	int count_dw;
	188	uint64_t gpu_addr;
536fbf94 KW	189	uint64_t ptr_mask;
536fbf94 KW	190	uint32_t buf_mask;
78023016	191	bool ready;
78023016 CK	192	u32 idx;
	193	u32 me;
	194	u32 pipe;
	195	u32 queue;
	196	struct amdgpu_bo *mqd_obj;
f3972b53	197	uint64_t mqd_gpu_addr;
59a82d7d	198	void *mqd_ptr;
34534610	199	uint64_t eop_gpu_addr;
78023016 CK	200	u32 doorbell_index;
78023016 CK	201	bool use_doorbell;
2ffe31de	202	bool use_pollmem;
78023016 CK	203	unsigned wptr_offs;
	204	unsigned fence_offs;
	205	uint64_t current_ctx;
78023016 CK	206	char name[16];
	207	unsigned cond_exe_offs;
	208	u64 cond_exe_gpu_addr;
	209	volatile u32 *cond_exe_cpu_addr;
4789c463	210	unsigned vm_inv_eng;
3af81440	211	struct dma_fence *vmid_wait;
dd684d31	212	bool has_compute_vm_bug;
b2ff0e8a	213
1b1f42d8	214	atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX];
b2ff0e8a AR	215	struct mutex priority_mutex;
	216	/* protected by priority_mutex */
	217	int priority;
	218
78023016 CK	219	#if defined(CONFIG_DEBUG_FS)
	220	struct dentry *ent;
	221	#endif
	222	};
	223
0a7845db HR	224	#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
	225	#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
	226	#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
	227	#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
	228	#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
	229	#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
	230	#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
	231	#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
	232	#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
	233	#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
	234	#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
	235	#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
	236	#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
	237	#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
	238	#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
	239	#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
	240	#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
	241	#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
	242	#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
	243	#define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
	244	#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
	245	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
	246	#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
	247
78023016 CK	248	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
	249	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
	250	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);
	251	void amdgpu_ring_commit(struct amdgpu_ring *ring);
	252	void amdgpu_ring_undo(struct amdgpu_ring *ring);
b2ff0e8a	253	void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
1b1f42d8	254	enum drm_sched_priority priority);
b2ff0e8a	255	void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
1b1f42d8	256	enum drm_sched_priority priority);
78023016	257	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
79887142 CK	258	unsigned ring_size, struct amdgpu_irq_src *irq_src,
79887142 CK	259	unsigned irq_type);
78023016	260	void amdgpu_ring_fini(struct amdgpu_ring *ring);
82853638 AD	261	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
	262	uint32_t reg0, uint32_t val0,
	263	uint32_t reg1, uint32_t val1);
7876fa4f CK	264	bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
7876fa4f CK	265	struct dma_fence *fence);
82853638	266
c79ecfbf ML	267	static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
	268	{
	269	int i = 0;
e09706f4	270	while (i <= ring->buf_mask)
c79ecfbf ML	271	ring->ring[i++] = ring->funcs->nop;
	272
	273	}
78023016	274
e8110b1c CK	275	static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
	276	{
	277	if (ring->count_dw <= 0)
	278	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	279	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	280	ring->wptr &= ring->ptr_mask;
	281	ring->count_dw--;
	282	}
	283
	284	static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
	285	void *src, int count_dw)
	286	{
	287	unsigned occupied, chunk1, chunk2;
	288	void *dst;
	289
369421cb	290	if (unlikely(ring->count_dw < count_dw))
e8110b1c	291	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
e8110b1c CK	292
	293	occupied = ring->wptr & ring->buf_mask;
	294	dst = (void *)&ring->ring[occupied];
	295	chunk1 = ring->buf_mask + 1 - occupied;
	296	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	297	chunk2 = count_dw - chunk1;
	298	chunk1 <<= 2;
	299	chunk2 <<= 2;
	300
	301	if (chunk1)
	302	memcpy(dst, src, chunk1);
	303
	304	if (chunk2) {
	305	src += chunk1;
	306	dst = (void *)ring->ring;
	307	memcpy(dst, src, chunk2);
	308	}
	309
	310	ring->wptr += count_dw;
	311	ring->wptr &= ring->ptr_mask;
	312	ring->count_dw -= count_dw;
	313	}
	314
78023016	315	#endif