[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__

#include "gpu_scheduler.h"

/* max number of rings */
#define AMDGPU_MAX_RINGS		16
#define AMDGPU_MAX_GFX_RINGS		1
#define AMDGPU_MAX_COMPUTE_RINGS	8
#define AMDGPU_MAX_VCE_RINGS		3

/* some special values for the owner field */
#define AMDGPU_FENCE_OWNER_UNDEFINED	((void*)0ul)
#define AMDGPU_FENCE_OWNER_VM		((void*)1ul)

#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
#define AMDGPU_FENCE_FLAG_INT           (1 << 1)

enum amdgpu_ring_type {
	AMDGPU_RING_TYPE_GFX,
	AMDGPU_RING_TYPE_COMPUTE,
	AMDGPU_RING_TYPE_SDMA,
	AMDGPU_RING_TYPE_UVD,
	AMDGPU_RING_TYPE_VCE
};

struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;

/*
 * Fences.
 */
struct amdgpu_fence_driver {
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint32_t			sync_seq;
	atomic_t			last_seq;
	bool				initialized;
	struct amdgpu_irq_src		*irq_src;
	unsigned			irq_type;
	struct timer_list		fallback_timer;
	unsigned			num_fences_mask;
	spinlock_t			lock;
	struct fence			**fences;
};

int amdgpu_fence_driver_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);

int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
				  unsigned num_hw_submission);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
				   struct amdgpu_irq_src *irq_src,
				   unsigned irq_type);
void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **fence);
void amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

/*
 * Rings.
 */

/* provided by hw blocks that expose a ring buffer for commands */
struct amdgpu_ring_funcs {
	enum amdgpu_ring_type	type;
	uint32_t		align_mask;
	u32			nop;

	/* ring read/write ptr handling */
	u32 (*get_rptr)(struct amdgpu_ring *ring);
	u32 (*get_wptr)(struct amdgpu_ring *ring);
	void (*set_wptr)(struct amdgpu_ring *ring);
	/* validating and patching of IBs */
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	/* constants to calculate how many DW are needed for an emit */
	unsigned emit_frame_size;
	unsigned emit_ib_size;
	/* command emit functions */
	void (*emit_ib)(struct amdgpu_ring *ring,
			struct amdgpu_ib *ib,
			unsigned vm_id, bool ctx_switch);
	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
			   uint64_t seq, unsigned flags);
	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
			      uint64_t pd_addr);
	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
	void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
				uint32_t gds_base, uint32_t gds_size,
				uint32_t gws_base, uint32_t gws_size,
				uint32_t oa_base, uint32_t oa_size);
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
	/* pad the indirect buffer to the necessary number of dw */
	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
	/* note usage for clock and power gating */
	void (*begin_use)(struct amdgpu_ring *ring);
	void (*end_use)(struct amdgpu_ring *ring);
	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
};

struct amdgpu_ring {
	struct amdgpu_device		*adev;
	const struct amdgpu_ring_funcs	*funcs;
	struct amdgpu_fence_driver	fence_drv;
	struct amd_gpu_scheduler	sched;

	struct amdgpu_bo	*ring_obj;
	volatile uint32_t	*ring;
	unsigned		rptr_offs;
	unsigned		wptr;
	unsigned		wptr_old;
	unsigned		ring_size;
	unsigned		max_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint32_t		ptr_mask;
	bool			ready;
	u32			idx;
	u32			me;
	u32			pipe;
	u32			queue;
	struct amdgpu_bo	*mqd_obj;
	u32			doorbell_index;
	bool			use_doorbell;
	unsigned		wptr_offs;
	unsigned		fence_offs;
	uint64_t		current_ctx;
	char			name[16];
	unsigned		cond_exe_offs;
	u64			cond_exe_gpu_addr;
	volatile u32		*cond_exe_cpu_addr;
#if defined(CONFIG_DEBUG_FS)
	struct dentry *ent;
#endif
};

int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned ring_size, struct amdgpu_irq_src *irq_src,
		     unsigned irq_type);
void amdgpu_ring_fini(struct amdgpu_ring *ring);

#endif
Commit	Line	Data
78023016 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_RING_H__
	25	#define __AMDGPU_RING_H__
	26
	27	#include "gpu_scheduler.h"
	28
	29	/* max number of rings */
	30	#define AMDGPU_MAX_RINGS 16
	31	#define AMDGPU_MAX_GFX_RINGS 1
	32	#define AMDGPU_MAX_COMPUTE_RINGS 8
	33	#define AMDGPU_MAX_VCE_RINGS 3
	34
	35	/* some special values for the owner field */
	36	#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
	37	#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
	38
	39	#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
	40	#define AMDGPU_FENCE_FLAG_INT (1 << 1)
	41
	42	enum amdgpu_ring_type {
	43	AMDGPU_RING_TYPE_GFX,
	44	AMDGPU_RING_TYPE_COMPUTE,
	45	AMDGPU_RING_TYPE_SDMA,
	46	AMDGPU_RING_TYPE_UVD,
	47	AMDGPU_RING_TYPE_VCE
	48	};
	49
	50	struct amdgpu_device;
	51	struct amdgpu_ring;
	52	struct amdgpu_ib;
	53	struct amdgpu_cs_parser;
	54
	55	/*
	56	* Fences.
	57	*/
	58	struct amdgpu_fence_driver {
	59	uint64_t gpu_addr;
	60	volatile uint32_t *cpu_addr;
	61	/* sync_seq is protected by ring emission lock */
	62	uint32_t sync_seq;
	63	atomic_t last_seq;
	64	bool initialized;
65	struct amdgpu_irq_src *irq_src;
66	unsigned irq_type;
67	struct timer_list fallback_timer;
68	unsigned num_fences_mask;
69	spinlock_t lock;
70	struct fence **fences;
71	};
72
73	int amdgpu_fence_driver_init(struct amdgpu_device *adev);
74	void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
75	void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
76
77	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
78	unsigned num_hw_submission);
79	int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
80	struct amdgpu_irq_src *irq_src,
81	unsigned irq_type);
82	void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
83	void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
84	int amdgpu_fence_emit(struct amdgpu_ring ring, struct fence *fence);
85	void amdgpu_fence_process(struct amdgpu_ring *ring);
86	int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
87	unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
88
89	/*
90	* Rings.
91	*/
92
93	/* provided by hw blocks that expose a ring buffer for commands */
94	struct amdgpu_ring_funcs {
21cd942e	95	enum amdgpu_ring_type type;
79887142 CK	96	uint32_t align_mask;
79887142 CK	97	u32 nop;
21cd942e	98
78023016 CK	99	/* ring read/write ptr handling */
	100	u32 (get_rptr)(struct amdgpu_ring ring);
	101	u32 (get_wptr)(struct amdgpu_ring ring);
	102	void (set_wptr)(struct amdgpu_ring ring);
	103	/* validating and patching of IBs */
	104	int (parse_cs)(struct amdgpu_cs_parser p, uint32_t ib_idx);
e12f3d7a CK	105	/* constants to calculate how many DW are needed for an emit */
	106	unsigned emit_frame_size;
	107	unsigned emit_ib_size;
78023016 CK	108	/* command emit functions */
	109	void (emit_ib)(struct amdgpu_ring ring,
	110	struct amdgpu_ib *ib,
	111	unsigned vm_id, bool ctx_switch);
	112	void (emit_fence)(struct amdgpu_ring ring, uint64_t addr,
	113	uint64_t seq, unsigned flags);
	114	void (emit_pipeline_sync)(struct amdgpu_ring ring);
	115	void (emit_vm_flush)(struct amdgpu_ring ring, unsigned vm_id,
	116	uint64_t pd_addr);
	117	void (emit_hdp_flush)(struct amdgpu_ring ring);
	118	void (emit_hdp_invalidate)(struct amdgpu_ring ring);
	119	void (emit_gds_switch)(struct amdgpu_ring ring, uint32_t vmid,
	120	uint32_t gds_base, uint32_t gds_size,
	121	uint32_t gws_base, uint32_t gws_size,
	122	uint32_t oa_base, uint32_t oa_size);
	123	/* testing functions */
	124	int (test_ring)(struct amdgpu_ring ring);
	125	int (test_ib)(struct amdgpu_ring ring, long timeout);
	126	/* insert NOP packets */
	127	void (insert_nop)(struct amdgpu_ring ring, uint32_t count);
	128	/* pad the indirect buffer to the necessary number of dw */
	129	void (pad_ib)(struct amdgpu_ring ring, struct amdgpu_ib *ib);
	130	unsigned (init_cond_exec)(struct amdgpu_ring ring);
	131	void (patch_cond_exec)(struct amdgpu_ring ring, unsigned offset);
	132	/* note usage for clock and power gating */
	133	void (begin_use)(struct amdgpu_ring ring);
	134	void (end_use)(struct amdgpu_ring ring);
	135	void (emit_switch_buffer) (struct amdgpu_ring ring);
	136	void (emit_cntxcntl) (struct amdgpu_ring ring, uint32_t flags);
78023016 CK	137	};
	138
	139	struct amdgpu_ring {
	140	struct amdgpu_device *adev;
	141	const struct amdgpu_ring_funcs *funcs;
	142	struct amdgpu_fence_driver fence_drv;
	143	struct amd_gpu_scheduler sched;
	144
	145	struct amdgpu_bo *ring_obj;
	146	volatile uint32_t *ring;
	147	unsigned rptr_offs;
	148	unsigned wptr;
	149	unsigned wptr_old;
	150	unsigned ring_size;
	151	unsigned max_dw;
	152	int count_dw;
	153	uint64_t gpu_addr;
78023016 CK	154	uint32_t ptr_mask;
78023016 CK	155	bool ready;
78023016 CK	156	u32 idx;
	157	u32 me;
	158	u32 pipe;
	159	u32 queue;
	160	struct amdgpu_bo *mqd_obj;
	161	u32 doorbell_index;
	162	bool use_doorbell;
	163	unsigned wptr_offs;
	164	unsigned fence_offs;
	165	uint64_t current_ctx;
78023016 CK	166	char name[16];
	167	unsigned cond_exe_offs;
	168	u64 cond_exe_gpu_addr;
	169	volatile u32 *cond_exe_cpu_addr;
	170	#if defined(CONFIG_DEBUG_FS)
	171	struct dentry *ent;
	172	#endif
	173	};
	174
	175	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
	176	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
	177	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);
	178	void amdgpu_ring_commit(struct amdgpu_ring *ring);
	179	void amdgpu_ring_undo(struct amdgpu_ring *ring);
	180	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
79887142 CK	181	unsigned ring_size, struct amdgpu_irq_src *irq_src,
79887142 CK	182	unsigned irq_type);
78023016 CK	183	void amdgpu_ring_fini(struct amdgpu_ring *ring);
	184
	185	#endif