[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__

#include <drm/amdgpu_drm.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_print.h>

/* max number of rings */
#define AMDGPU_MAX_RINGS		28
#define AMDGPU_MAX_HWIP_RINGS		8
#define AMDGPU_MAX_GFX_RINGS		2
#define AMDGPU_MAX_COMPUTE_RINGS	8
#define AMDGPU_MAX_VCE_RINGS		3
#define AMDGPU_MAX_UVD_ENC_RINGS	2

enum amdgpu_ring_priority_level {
	AMDGPU_RING_PRIO_0,
	AMDGPU_RING_PRIO_1,
	AMDGPU_RING_PRIO_DEFAULT = 1,
	AMDGPU_RING_PRIO_2,
	AMDGPU_RING_PRIO_MAX
};

/* some special values for the owner field */
#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)

#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)

#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

#define AMDGPU_IB_POOL_SIZE	(1024 * 1024)

enum amdgpu_ring_type {
	AMDGPU_RING_TYPE_GFX		= AMDGPU_HW_IP_GFX,
	AMDGPU_RING_TYPE_COMPUTE	= AMDGPU_HW_IP_COMPUTE,
	AMDGPU_RING_TYPE_SDMA		= AMDGPU_HW_IP_DMA,
	AMDGPU_RING_TYPE_UVD		= AMDGPU_HW_IP_UVD,
	AMDGPU_RING_TYPE_VCE		= AMDGPU_HW_IP_VCE,
	AMDGPU_RING_TYPE_UVD_ENC	= AMDGPU_HW_IP_UVD_ENC,
	AMDGPU_RING_TYPE_VCN_DEC	= AMDGPU_HW_IP_VCN_DEC,
	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
	AMDGPU_RING_TYPE_KIQ,
	AMDGPU_RING_TYPE_MES
};

enum amdgpu_ib_pool_type {
	/* Normal submissions to the top of the pipeline. */
	AMDGPU_IB_POOL_DELAYED,
	/* Immediate submissions to the bottom of the pipeline. */
	AMDGPU_IB_POOL_IMMEDIATE,
	/* Direct submission to the ring buffer during init and reset. */
	AMDGPU_IB_POOL_DIRECT,

	AMDGPU_IB_POOL_MAX
};

struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;
struct amdgpu_job;

struct amdgpu_sched {
	u32				num_scheds;
	struct drm_gpu_scheduler	*sched[AMDGPU_MAX_HWIP_RINGS];
};

/*
 * Fences.
 */
struct amdgpu_fence_driver {
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint32_t			sync_seq;
	atomic_t			last_seq;
	bool				initialized;
	struct amdgpu_irq_src		*irq_src;
	unsigned			irq_type;
	struct timer_list		fallback_timer;
	unsigned			num_fences_mask;
	spinlock_t			lock;
	struct dma_fence		**fences;
};

void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);

int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
				   struct amdgpu_irq_src *irq_src,
				   unsigned irq_type);
void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
		      unsigned flags);
int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
			      uint32_t timeout);
bool amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
				      uint32_t wait_seq,
				      signed long timeout);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

/*
 * Rings.
 */

/* provided by hw blocks that expose a ring buffer for commands */
struct amdgpu_ring_funcs {
	enum amdgpu_ring_type	type;
	uint32_t		align_mask;
	u32			nop;
	bool			support_64bit_ptrs;
	bool			no_user_fence;
	unsigned		vmhub;
	unsigned		extra_dw;

	/* ring read/write ptr handling */
	u64 (*get_rptr)(struct amdgpu_ring *ring);
	u64 (*get_wptr)(struct amdgpu_ring *ring);
	void (*set_wptr)(struct amdgpu_ring *ring);
	/* validating and patching of IBs */
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	/* constants to calculate how many DW are needed for an emit */
	unsigned emit_frame_size;
	unsigned emit_ib_size;
	/* command emit functions */
	void (*emit_ib)(struct amdgpu_ring *ring,
			struct amdgpu_job *job,
			struct amdgpu_ib *ib,
			uint32_t flags);
	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
			   uint64_t seq, unsigned flags);
	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
			      uint64_t pd_addr);
	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
				uint32_t gds_base, uint32_t gds_size,
				uint32_t gws_base, uint32_t gws_size,
				uint32_t oa_base, uint32_t oa_size);
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
	void (*insert_start)(struct amdgpu_ring *ring);
	void (*insert_end)(struct amdgpu_ring *ring);
	/* pad the indirect buffer to the necessary number of dw */
	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
	/* note usage for clock and power gating */
	void (*begin_use)(struct amdgpu_ring *ring);
	void (*end_use)(struct amdgpu_ring *ring);
	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
			  uint32_t reg_val_offs);
	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
			      uint32_t val, uint32_t mask);
	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
					uint32_t reg0, uint32_t reg1,
					uint32_t ref, uint32_t mask);
	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
				bool secure);
	/* Try to soft recover the ring to make the fence signal */
	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
	int (*preempt_ib)(struct amdgpu_ring *ring);
	void (*emit_mem_sync)(struct amdgpu_ring *ring);
	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
};

struct amdgpu_ring {
	struct amdgpu_device		*adev;
	const struct amdgpu_ring_funcs	*funcs;
	struct amdgpu_fence_driver	fence_drv;
	struct drm_gpu_scheduler	sched;

	struct amdgpu_bo	*ring_obj;
	volatile uint32_t	*ring;
	unsigned		rptr_offs;
	u64			wptr;
	u64			wptr_old;
	unsigned		ring_size;
	unsigned		max_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint64_t		ptr_mask;
	uint32_t		buf_mask;
	u32			idx;
	u32			me;
	u32			pipe;
	u32			queue;
	struct amdgpu_bo	*mqd_obj;
	uint64_t                mqd_gpu_addr;
	void                    *mqd_ptr;
	uint64_t                eop_gpu_addr;
	u32			doorbell_index;
	bool			use_doorbell;
	bool			use_pollmem;
	unsigned		wptr_offs;
	unsigned		fence_offs;
	uint64_t		current_ctx;
	char			name[16];
	u32                     trail_seq;
	unsigned		trail_fence_offs;
	u64			trail_fence_gpu_addr;
	volatile u32		*trail_fence_cpu_addr;
	unsigned		cond_exe_offs;
	u64			cond_exe_gpu_addr;
	volatile u32		*cond_exe_cpu_addr;
	unsigned		vm_inv_eng;
	struct dma_fence	*vmid_wait;
	bool			has_compute_vm_bug;
	bool			no_scheduler;
	int			hw_prio;
	unsigned 		num_hw_submission;
	atomic_t		*sched_score;
};

#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)

int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned int ring_size, struct amdgpu_irq_src *irq_src,
		     unsigned int irq_type, unsigned int prio,
		     atomic_t *sched_score);
void amdgpu_ring_fini(struct amdgpu_ring *ring);
void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
						uint32_t reg0, uint32_t val0,
						uint32_t reg1, uint32_t val1);
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
			       struct dma_fence *fence);

static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
							bool cond_exec)
{
	*ring->cond_exe_cpu_addr = cond_exec;
}

static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
	int i = 0;
	while (i <= ring->buf_mask)
		ring->ring[i++] = ring->funcs->nop;

}

static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
{
	if (ring->count_dw <= 0)
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
}

static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
					      void *src, int count_dw)
{
	unsigned occupied, chunk1, chunk2;
	void *dst;

	if (unlikely(ring->count_dw < count_dw))
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	occupied = ring->wptr & ring->buf_mask;
	dst = (void *)&ring->ring[occupied];
	chunk1 = ring->buf_mask + 1 - occupied;
	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	chunk2 = count_dw - chunk1;
	chunk1 <<= 2;
	chunk2 <<= 2;

	if (chunk1)
		memcpy(dst, src, chunk1);

	if (chunk2) {
		src += chunk1;
		dst = (void *)ring->ring;
		memcpy(dst, src, chunk2);
	}

	ring->wptr += count_dw;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw -= count_dw;
}

int amdgpu_ring_test_helper(struct amdgpu_ring *ring);

void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
			      struct amdgpu_ring *ring);
#endif
Commit	Line	Data
78023016 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_RING_H__
	25	#define __AMDGPU_RING_H__
	26
b2ff0e8a	27	#include <drm/amdgpu_drm.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
61b100e9	29	#include <drm/drm_print.h>
78023016 CK	30
78023016 CK	31	/* max number of rings */
8b75a521	32	#define AMDGPU_MAX_RINGS 28
1c6d567b	33	#define AMDGPU_MAX_HWIP_RINGS 8
a644d85a	34	#define AMDGPU_MAX_GFX_RINGS 2
78023016 CK	35	#define AMDGPU_MAX_COMPUTE_RINGS 8
78023016 CK	36	#define AMDGPU_MAX_VCE_RINGS 3
f7243053	37	#define AMDGPU_MAX_UVD_ENC_RINGS 2
78023016	38
34eaf30f ND	39	enum amdgpu_ring_priority_level {
	40	AMDGPU_RING_PRIO_0,
	41	AMDGPU_RING_PRIO_1,
	42	AMDGPU_RING_PRIO_DEFAULT = 1,
	43	AMDGPU_RING_PRIO_2,
	44	AMDGPU_RING_PRIO_MAX
	45	};
1c6d567b	46
78023016	47	/* some special values for the owner field */
d8d019cc FK	48	#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
	49	#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
	50	#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
78023016 CK	51
	52	#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
	53	#define AMDGPU_FENCE_FLAG_INT (1 << 1)
d240cd9e	54	#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
78023016	55
0e28b10f CK	56	#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
0e28b10f CK	57
9ecefb19 CK	58	#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
9ecefb19 CK	59
78023016	60	enum amdgpu_ring_type {
07e14845 ND	61	AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
	62	AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
	63	AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
	64	AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
	65	AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
	66	AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
	67	AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
	68	AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
	69	AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
cdca7979 JX	70	AMDGPU_RING_TYPE_KIQ,
cdca7979 JX	71	AMDGPU_RING_TYPE_MES
78023016 CK	72	};
78023016 CK	73
9ecefb19 CK	74	enum amdgpu_ib_pool_type {
	75	/* Normal submissions to the top of the pipeline. */
	76	AMDGPU_IB_POOL_DELAYED,
	77	/* Immediate submissions to the bottom of the pipeline. */
	78	AMDGPU_IB_POOL_IMMEDIATE,
	79	/* Direct submission to the ring buffer during init and reset. */
	80	AMDGPU_IB_POOL_DIRECT,
	81
	82	AMDGPU_IB_POOL_MAX
	83	};
	84
78023016 CK	85	struct amdgpu_device;
	86	struct amdgpu_ring;
	87	struct amdgpu_ib;
	88	struct amdgpu_cs_parser;
b2ff0e8a	89	struct amdgpu_job;
78023016	90
1c6d567b ND	91	struct amdgpu_sched {
	92	u32 num_scheds;
	93	struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
	94	};
	95
78023016 CK	96	/*
	97	* Fences.
	98	*/
	99	struct amdgpu_fence_driver {
	100	uint64_t gpu_addr;
	101	volatile uint32_t *cpu_addr;
	102	/* sync_seq is protected by ring emission lock */
	103	uint32_t sync_seq;
	104	atomic_t last_seq;
	105	bool initialized;
	106	struct amdgpu_irq_src *irq_src;
	107	unsigned irq_type;
8c5e13ec	108	struct timer_list fallback_timer;
78023016 CK	109	unsigned num_fences_mask;
78023016 CK	110	spinlock_t lock;
220196b3	111	struct dma_fence **fences;
78023016 CK	112	};
78023016 CK	113
bf67014d	114	void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
2f9d4084	115	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
78023016	116
5fd8518d	117	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
78023016 CK	118	int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
	119	struct amdgpu_irq_src *irq_src,
	120	unsigned irq_type);
067f44c8	121	void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
8d35a259	122	void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
067f44c8	123	int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
8d35a259	124	void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
c530b02f	125	int amdgpu_fence_emit(struct amdgpu_ring ring, struct dma_fence fence, struct amdgpu_job job,
d240cd9e	126	unsigned flags);
04e4e2e9 YT	127	int amdgpu_fence_emit_polling(struct amdgpu_ring ring, uint32_t s,
04e4e2e9 YT	128	uint32_t timeout);
95d7fc4a	129	bool amdgpu_fence_process(struct amdgpu_ring *ring);
78023016	130	int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
43ca8efa	131	signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
	132	uint32_t wait_seq,
	133	signed long timeout);
78023016 CK	134	unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
	135
	136	/*
	137	* Rings.
	138	*/
	139
	140	/* provided by hw blocks that expose a ring buffer for commands */
	141	struct amdgpu_ring_funcs {
21cd942e	142	enum amdgpu_ring_type type;
79887142 CK	143	uint32_t align_mask;
79887142 CK	144	u32 nop;
536fbf94	145	bool support_64bit_ptrs;
120c2125	146	bool no_user_fence;
0eeb68b3	147	unsigned vmhub;
c8c1a1d2	148	unsigned extra_dw;
21cd942e	149
78023016	150	/* ring read/write ptr handling */
536fbf94 KW	151	u64 (get_rptr)(struct amdgpu_ring ring);
536fbf94 KW	152	u64 (get_wptr)(struct amdgpu_ring ring);
78023016 CK	153	void (set_wptr)(struct amdgpu_ring ring);
	154	/* validating and patching of IBs */
	155	int (parse_cs)(struct amdgpu_cs_parser p, uint32_t ib_idx);
9d248517	156	int (patch_cs_in_place)(struct amdgpu_cs_parser p, uint32_t ib_idx);
e12f3d7a CK	157	/* constants to calculate how many DW are needed for an emit */
	158	unsigned emit_frame_size;
	159	unsigned emit_ib_size;
78023016 CK	160	/* command emit functions */
78023016 CK	161	void (emit_ib)(struct amdgpu_ring ring,
34955e03	162	struct amdgpu_job *job,
78023016	163	struct amdgpu_ib *ib,
c4c905ec	164	uint32_t flags);
78023016 CK	165	void (emit_fence)(struct amdgpu_ring ring, uint64_t addr,
	166	uint64_t seq, unsigned flags);
	167	void (emit_pipeline_sync)(struct amdgpu_ring ring);
c4f46f22	168	void (emit_vm_flush)(struct amdgpu_ring ring, unsigned vmid,
c633c00b	169	uint64_t pd_addr);
78023016	170	void (emit_hdp_flush)(struct amdgpu_ring ring);
78023016 CK	171	void (emit_gds_switch)(struct amdgpu_ring ring, uint32_t vmid,
	172	uint32_t gds_base, uint32_t gds_size,
	173	uint32_t gws_base, uint32_t gws_size,
	174	uint32_t oa_base, uint32_t oa_size);
	175	/* testing functions */
	176	int (test_ring)(struct amdgpu_ring ring);
	177	int (test_ib)(struct amdgpu_ring ring, long timeout);
	178	/* insert NOP packets */
	179	void (insert_nop)(struct amdgpu_ring ring, uint32_t count);
ef44f854	180	void (insert_start)(struct amdgpu_ring ring);
135d4735	181	void (insert_end)(struct amdgpu_ring ring);
78023016 CK	182	/* pad the indirect buffer to the necessary number of dw */
	183	void (pad_ib)(struct amdgpu_ring ring, struct amdgpu_ib *ib);
	184	unsigned (init_cond_exec)(struct amdgpu_ring ring);
	185	void (patch_cond_exec)(struct amdgpu_ring ring, unsigned offset);
	186	/* note usage for clock and power gating */
	187	void (begin_use)(struct amdgpu_ring ring);
	188	void (end_use)(struct amdgpu_ring ring);
	189	void (emit_switch_buffer) (struct amdgpu_ring ring);
0bb5d5b0	190	void (emit_cntxcntl) (struct amdgpu_ring ring, uint32_t flags);
54208194 YT	191	void (emit_rreg)(struct amdgpu_ring ring, uint32_t reg,
54208194 YT	192	uint32_t reg_val_offs);
b6091c12	193	void (emit_wreg)(struct amdgpu_ring ring, uint32_t reg, uint32_t val);
c1e877da CK	194	void (emit_reg_wait)(struct amdgpu_ring ring, uint32_t reg,
c1e877da CK	195	uint32_t val, uint32_t mask);
82853638 AD	196	void (emit_reg_write_reg_wait)(struct amdgpu_ring ring,
	197	uint32_t reg0, uint32_t reg1,
	198	uint32_t ref, uint32_t mask);
f77c9aff HR	199	void (emit_frame_cntl)(struct amdgpu_ring ring, bool start,
f77c9aff HR	200	bool secure);
7876fa4f CK	201	/* Try to soft recover the ring to make the fence signal */
7876fa4f CK	202	void (soft_recovery)(struct amdgpu_ring ring, unsigned vmid);
692441f2	203	int (preempt_ib)(struct amdgpu_ring ring);
22301177	204	void (emit_mem_sync)(struct amdgpu_ring ring);
0a52a6ca	205	void (emit_wave_limit)(struct amdgpu_ring ring, bool enable);
78023016 CK	206	};
	207
	208	struct amdgpu_ring {
	209	struct amdgpu_device *adev;
	210	const struct amdgpu_ring_funcs *funcs;
	211	struct amdgpu_fence_driver fence_drv;
1b1f42d8	212	struct drm_gpu_scheduler sched;
78023016 CK	213
	214	struct amdgpu_bo *ring_obj;
	215	volatile uint32_t *ring;
	216	unsigned rptr_offs;
536fbf94 KW	217	u64 wptr;
536fbf94 KW	218	u64 wptr_old;
78023016 CK	219	unsigned ring_size;
	220	unsigned max_dw;
	221	int count_dw;
	222	uint64_t gpu_addr;
536fbf94 KW	223	uint64_t ptr_mask;
536fbf94 KW	224	uint32_t buf_mask;
78023016 CK	225	u32 idx;
	226	u32 me;
	227	u32 pipe;
	228	u32 queue;
	229	struct amdgpu_bo *mqd_obj;
f3972b53	230	uint64_t mqd_gpu_addr;
59a82d7d	231	void *mqd_ptr;
34534610	232	uint64_t eop_gpu_addr;
78023016 CK	233	u32 doorbell_index;
78023016 CK	234	bool use_doorbell;
2ffe31de	235	bool use_pollmem;
78023016 CK	236	unsigned wptr_offs;
	237	unsigned fence_offs;
	238	uint64_t current_ctx;
78023016	239	char name[16];
ef3e1323 JX	240	u32 trail_seq;
	241	unsigned trail_fence_offs;
	242	u64 trail_fence_gpu_addr;
	243	volatile u32 *trail_fence_cpu_addr;
78023016 CK	244	unsigned cond_exe_offs;
	245	u64 cond_exe_gpu_addr;
	246	volatile u32 *cond_exe_cpu_addr;
4789c463	247	unsigned vm_inv_eng;
3af81440	248	struct dma_fence *vmid_wait;
dd684d31	249	bool has_compute_vm_bug;
cb3d1085	250	bool no_scheduler;
ebdd2e9d	251	int hw_prio;
5fd8518d AG	252	unsigned num_hw_submission;
5fd8518d AG	253	atomic_t *sched_score;
78023016 CK	254	};
78023016 CK	255
0a7845db HR	256	#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
	257	#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
	258	#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
	259	#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
	260	#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
	261	#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
	262	#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
c4c905ec	263	#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
0a7845db HR	264	#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
	265	#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
	266	#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
	267	#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
	268	#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
	269	#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
0bb5d5b0	270	#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
54208194	271	#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
0a7845db HR	272	#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
	273	#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
	274	#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
f77c9aff	275	#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
0a7845db HR	276	#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
	277	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
	278	#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
692441f2	279	#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
0a7845db	280
78023016 CK	281	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
	282	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
	283	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);
	284	void amdgpu_ring_commit(struct amdgpu_ring *ring);
	285	void amdgpu_ring_undo(struct amdgpu_ring *ring);
	286	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
1c6d567b	287	unsigned int ring_size, struct amdgpu_irq_src *irq_src,
c107171b CK	288	unsigned int irq_type, unsigned int prio,
c107171b CK	289	atomic_t *sched_score);
78023016	290	void amdgpu_ring_fini(struct amdgpu_ring *ring);
82853638 AD	291	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
	292	uint32_t reg0, uint32_t val0,
	293	uint32_t reg1, uint32_t val1);
7876fa4f CK	294	bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
7876fa4f CK	295	struct dma_fence *fence);
82853638	296
dfc98479 RZ	297	static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
	298	bool cond_exec)
	299	{
	300	*ring->cond_exe_cpu_addr = cond_exec;
	301	}
	302
c79ecfbf ML	303	static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
	304	{
	305	int i = 0;
e09706f4	306	while (i <= ring->buf_mask)
c79ecfbf ML	307	ring->ring[i++] = ring->funcs->nop;
	308
	309	}
78023016	310
e8110b1c CK	311	static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
	312	{
	313	if (ring->count_dw <= 0)
	314	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	315	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	316	ring->wptr &= ring->ptr_mask;
	317	ring->count_dw--;
	318	}
	319
	320	static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
	321	void *src, int count_dw)
	322	{
	323	unsigned occupied, chunk1, chunk2;
	324	void *dst;
	325
369421cb	326	if (unlikely(ring->count_dw < count_dw))
e8110b1c	327	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
e8110b1c CK	328
	329	occupied = ring->wptr & ring->buf_mask;
	330	dst = (void *)&ring->ring[occupied];
	331	chunk1 = ring->buf_mask + 1 - occupied;
	332	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	333	chunk2 = count_dw - chunk1;
	334	chunk1 <<= 2;
	335	chunk2 <<= 2;
	336
	337	if (chunk1)
	338	memcpy(dst, src, chunk1);
	339
	340	if (chunk2) {
	341	src += chunk1;
	342	dst = (void *)ring->ring;
	343	memcpy(dst, src, chunk2);
	344	}
	345
	346	ring->wptr += count_dw;
	347	ring->wptr &= ring->ptr_mask;
	348	ring->count_dw -= count_dw;
	349	}
	350
c66ed765 AG	351	int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
c66ed765 AG	352
62d266b2 ND	353	void amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
62d266b2 ND	354	struct amdgpu_ring *ring);
78023016	355	#endif