[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ring.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Christian König
 */
#ifndef __AMDGPU_RING_H__
#define __AMDGPU_RING_H__

#include <drm/amdgpu_drm.h>
#include <drm/gpu_scheduler.h>
#include <drm/drm_print.h>

/* max number of rings */
#define AMDGPU_MAX_RINGS		28
#define AMDGPU_MAX_HWIP_RINGS		8
#define AMDGPU_MAX_GFX_RINGS		2
#define AMDGPU_MAX_COMPUTE_RINGS	8
#define AMDGPU_MAX_VCE_RINGS		3
#define AMDGPU_MAX_UVD_ENC_RINGS	2

#define AMDGPU_RING_PRIO_DEFAULT	1
#define AMDGPU_RING_PRIO_MAX		AMDGPU_GFX_PIPE_PRIO_MAX

/* some special values for the owner field */
#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)
#define AMDGPU_FENCE_OWNER_VM		((void *)1ul)
#define AMDGPU_FENCE_OWNER_KFD		((void *)2ul)

#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
#define AMDGPU_FENCE_FLAG_INT           (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY    (1 << 2)

/* fence flag bit to indicate the face is embedded in job*/
#define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT		(DMA_FENCE_FLAG_USER_BITS + 1)

#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)

#define AMDGPU_IB_POOL_SIZE	(1024 * 1024)

enum amdgpu_ring_type {
	AMDGPU_RING_TYPE_GFX		= AMDGPU_HW_IP_GFX,
	AMDGPU_RING_TYPE_COMPUTE	= AMDGPU_HW_IP_COMPUTE,
	AMDGPU_RING_TYPE_SDMA		= AMDGPU_HW_IP_DMA,
	AMDGPU_RING_TYPE_UVD		= AMDGPU_HW_IP_UVD,
	AMDGPU_RING_TYPE_VCE		= AMDGPU_HW_IP_VCE,
	AMDGPU_RING_TYPE_UVD_ENC	= AMDGPU_HW_IP_UVD_ENC,
	AMDGPU_RING_TYPE_VCN_DEC	= AMDGPU_HW_IP_VCN_DEC,
	AMDGPU_RING_TYPE_VCN_ENC	= AMDGPU_HW_IP_VCN_ENC,
	AMDGPU_RING_TYPE_VCN_JPEG	= AMDGPU_HW_IP_VCN_JPEG,
	AMDGPU_RING_TYPE_KIQ,
	AMDGPU_RING_TYPE_MES
};

enum amdgpu_ib_pool_type {
	/* Normal submissions to the top of the pipeline. */
	AMDGPU_IB_POOL_DELAYED,
	/* Immediate submissions to the bottom of the pipeline. */
	AMDGPU_IB_POOL_IMMEDIATE,
	/* Direct submission to the ring buffer during init and reset. */
	AMDGPU_IB_POOL_DIRECT,

	AMDGPU_IB_POOL_MAX
};

struct amdgpu_device;
struct amdgpu_ring;
struct amdgpu_ib;
struct amdgpu_cs_parser;
struct amdgpu_job;

struct amdgpu_sched {
	u32				num_scheds;
	struct drm_gpu_scheduler	*sched[AMDGPU_MAX_HWIP_RINGS];
};

/*
 * Fences.
 */
struct amdgpu_fence_driver {
	uint64_t			gpu_addr;
	volatile uint32_t		*cpu_addr;
	/* sync_seq is protected by ring emission lock */
	uint32_t			sync_seq;
	atomic_t			last_seq;
	bool				initialized;
	struct amdgpu_irq_src		*irq_src;
	unsigned			irq_type;
	struct timer_list		fallback_timer;
	unsigned			num_fences_mask;
	spinlock_t			lock;
	struct dma_fence		**fences;
};

void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);

int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
				  unsigned num_hw_submission,
				  atomic_t *sched_score);
int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
				   struct amdgpu_irq_src *irq_src,
				   unsigned irq_type);
void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job,
		      unsigned flags);
int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
			      uint32_t timeout);
bool amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
				      uint32_t wait_seq,
				      signed long timeout);
unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);

/*
 * Rings.
 */

/* provided by hw blocks that expose a ring buffer for commands */
struct amdgpu_ring_funcs {
	enum amdgpu_ring_type	type;
	uint32_t		align_mask;
	u32			nop;
	bool			support_64bit_ptrs;
	bool			no_user_fence;
	unsigned		vmhub;
	unsigned		extra_dw;

	/* ring read/write ptr handling */
	u64 (*get_rptr)(struct amdgpu_ring *ring);
	u64 (*get_wptr)(struct amdgpu_ring *ring);
	void (*set_wptr)(struct amdgpu_ring *ring);
	/* validating and patching of IBs */
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
	/* constants to calculate how many DW are needed for an emit */
	unsigned emit_frame_size;
	unsigned emit_ib_size;
	/* command emit functions */
	void (*emit_ib)(struct amdgpu_ring *ring,
			struct amdgpu_job *job,
			struct amdgpu_ib *ib,
			uint32_t flags);
	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
			   uint64_t seq, unsigned flags);
	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
	void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
			      uint64_t pd_addr);
	void (*emit_hdp_flush)(struct amdgpu_ring *ring);
	void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
				uint32_t gds_base, uint32_t gds_size,
				uint32_t gws_base, uint32_t gws_size,
				uint32_t oa_base, uint32_t oa_size);
	/* testing functions */
	int (*test_ring)(struct amdgpu_ring *ring);
	int (*test_ib)(struct amdgpu_ring *ring, long timeout);
	/* insert NOP packets */
	void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
	void (*insert_start)(struct amdgpu_ring *ring);
	void (*insert_end)(struct amdgpu_ring *ring);
	/* pad the indirect buffer to the necessary number of dw */
	void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
	unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
	void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
	/* note usage for clock and power gating */
	void (*begin_use)(struct amdgpu_ring *ring);
	void (*end_use)(struct amdgpu_ring *ring);
	void (*emit_switch_buffer) (struct amdgpu_ring *ring);
	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
			  uint32_t reg_val_offs);
	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
	void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
			      uint32_t val, uint32_t mask);
	void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
					uint32_t reg0, uint32_t reg1,
					uint32_t ref, uint32_t mask);
	void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
				bool secure);
	/* Try to soft recover the ring to make the fence signal */
	void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
	int (*preempt_ib)(struct amdgpu_ring *ring);
	void (*emit_mem_sync)(struct amdgpu_ring *ring);
	void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
};

struct amdgpu_ring {
	struct amdgpu_device		*adev;
	const struct amdgpu_ring_funcs	*funcs;
	struct amdgpu_fence_driver	fence_drv;
	struct drm_gpu_scheduler	sched;

	struct amdgpu_bo	*ring_obj;
	volatile uint32_t	*ring;
	unsigned		rptr_offs;
	u64			wptr;
	u64			wptr_old;
	unsigned		ring_size;
	unsigned		max_dw;
	int			count_dw;
	uint64_t		gpu_addr;
	uint64_t		ptr_mask;
	uint32_t		buf_mask;
	u32			idx;
	u32			me;
	u32			pipe;
	u32			queue;
	struct amdgpu_bo	*mqd_obj;
	uint64_t                mqd_gpu_addr;
	void                    *mqd_ptr;
	uint64_t                eop_gpu_addr;
	u32			doorbell_index;
	bool			use_doorbell;
	bool			use_pollmem;
	unsigned		wptr_offs;
	unsigned		fence_offs;
	uint64_t		current_ctx;
	char			name[16];
	u32                     trail_seq;
	unsigned		trail_fence_offs;
	u64			trail_fence_gpu_addr;
	volatile u32		*trail_fence_cpu_addr;
	unsigned		cond_exe_offs;
	u64			cond_exe_gpu_addr;
	volatile u32		*cond_exe_cpu_addr;
	unsigned		vm_inv_eng;
	struct dma_fence	*vmid_wait;
	bool			has_compute_vm_bug;
	bool			no_scheduler;
	int			hw_prio;

#if defined(CONFIG_DEBUG_FS)
	struct dentry *ent;
#endif
};

#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)

int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
void amdgpu_ring_commit(struct amdgpu_ring *ring);
void amdgpu_ring_undo(struct amdgpu_ring *ring);
int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
		     unsigned int ring_size, struct amdgpu_irq_src *irq_src,
		     unsigned int irq_type, unsigned int prio,
		     atomic_t *sched_score);
void amdgpu_ring_fini(struct amdgpu_ring *ring);
void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
						uint32_t reg0, uint32_t val0,
						uint32_t reg1, uint32_t val1);
bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
			       struct dma_fence *fence);

static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
							bool cond_exec)
{
	*ring->cond_exe_cpu_addr = cond_exec;
}

static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
{
	int i = 0;
	while (i <= ring->buf_mask)
		ring->ring[i++] = ring->funcs->nop;

}

static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
{
	if (ring->count_dw <= 0)
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw--;
}

static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
					      void *src, int count_dw)
{
	unsigned occupied, chunk1, chunk2;
	void *dst;

	if (unlikely(ring->count_dw < count_dw))
		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	occupied = ring->wptr & ring->buf_mask;
	dst = (void *)&ring->ring[occupied];
	chunk1 = ring->buf_mask + 1 - occupied;
	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	chunk2 = count_dw - chunk1;
	chunk1 <<= 2;
	chunk2 <<= 2;

	if (chunk1)
		memcpy(dst, src, chunk1);

	if (chunk2) {
		src += chunk1;
		dst = (void *)ring->ring;
		memcpy(dst, src, chunk2);
	}

	ring->wptr += count_dw;
	ring->wptr &= ring->ptr_mask;
	ring->count_dw -= count_dw;
}

int amdgpu_ring_test_helper(struct amdgpu_ring *ring);

int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
			     struct amdgpu_ring *ring);
void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);

#endif
Commit	Line	Data
78023016 CK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Christian König
	23	*/
	24	#ifndef __AMDGPU_RING_H__
	25	#define __AMDGPU_RING_H__
	26
b2ff0e8a	27	#include <drm/amdgpu_drm.h>
1b1f42d8	28	#include <drm/gpu_scheduler.h>
61b100e9	29	#include <drm/drm_print.h>
78023016 CK	30
78023016 CK	31	/* max number of rings */
8b75a521	32	#define AMDGPU_MAX_RINGS 28
1c6d567b	33	#define AMDGPU_MAX_HWIP_RINGS 8
a644d85a	34	#define AMDGPU_MAX_GFX_RINGS 2
78023016 CK	35	#define AMDGPU_MAX_COMPUTE_RINGS 8
78023016 CK	36	#define AMDGPU_MAX_VCE_RINGS 3
f7243053	37	#define AMDGPU_MAX_UVD_ENC_RINGS 2
78023016	38
1c6d567b ND	39	#define AMDGPU_RING_PRIO_DEFAULT 1
	40	#define AMDGPU_RING_PRIO_MAX AMDGPU_GFX_PIPE_PRIO_MAX
	41
78023016	42	/* some special values for the owner field */
d8d019cc FK	43	#define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul)
	44	#define AMDGPU_FENCE_OWNER_VM ((void *)1ul)
	45	#define AMDGPU_FENCE_OWNER_KFD ((void *)2ul)
78023016 CK	46
	47	#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
	48	#define AMDGPU_FENCE_FLAG_INT (1 << 1)
d240cd9e	49	#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
78023016	50
c530b02f JZ	51	/* fence flag bit to indicate the face is embedded in job*/
	52	#define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT (DMA_FENCE_FLAG_USER_BITS + 1)
	53
0e28b10f CK	54	#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
0e28b10f CK	55
9ecefb19 CK	56	#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
9ecefb19 CK	57
78023016	58	enum amdgpu_ring_type {
07e14845 ND	59	AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX,
	60	AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE,
	61	AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA,
	62	AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD,
	63	AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE,
	64	AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC,
	65	AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC,
	66	AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC,
	67	AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG,
cdca7979 JX	68	AMDGPU_RING_TYPE_KIQ,
cdca7979 JX	69	AMDGPU_RING_TYPE_MES
78023016 CK	70	};
78023016 CK	71
9ecefb19 CK	72	enum amdgpu_ib_pool_type {
	73	/* Normal submissions to the top of the pipeline. */
	74	AMDGPU_IB_POOL_DELAYED,
	75	/* Immediate submissions to the bottom of the pipeline. */
	76	AMDGPU_IB_POOL_IMMEDIATE,
	77	/* Direct submission to the ring buffer during init and reset. */
	78	AMDGPU_IB_POOL_DIRECT,
	79
	80	AMDGPU_IB_POOL_MAX
	81	};
	82
78023016 CK	83	struct amdgpu_device;
	84	struct amdgpu_ring;
	85	struct amdgpu_ib;
	86	struct amdgpu_cs_parser;
b2ff0e8a	87	struct amdgpu_job;
78023016	88
1c6d567b ND	89	struct amdgpu_sched {
	90	u32 num_scheds;
	91	struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS];
	92	};
	93
78023016 CK	94	/*
	95	* Fences.
	96	*/
	97	struct amdgpu_fence_driver {
	98	uint64_t gpu_addr;
	99	volatile uint32_t *cpu_addr;
	100	/* sync_seq is protected by ring emission lock */
	101	uint32_t sync_seq;
	102	atomic_t last_seq;
	103	bool initialized;
	104	struct amdgpu_irq_src *irq_src;
	105	unsigned irq_type;
8c5e13ec	106	struct timer_list fallback_timer;
78023016 CK	107	unsigned num_fences_mask;
78023016 CK	108	spinlock_t lock;
220196b3	109	struct dma_fence **fences;
78023016 CK	110	};
78023016 CK	111
2f9d4084	112	void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
78023016 CK	113
78023016 CK	114	int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
c107171b CK	115	unsigned num_hw_submission,
c107171b CK	116	atomic_t *sched_score);
78023016 CK	117	int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
	118	struct amdgpu_irq_src *irq_src,
	119	unsigned irq_type);
067f44c8	120	void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev);
8d35a259	121	void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev);
067f44c8	122	int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev);
8d35a259	123	void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev);
c530b02f	124	int amdgpu_fence_emit(struct amdgpu_ring ring, struct dma_fence fence, struct amdgpu_job job,
d240cd9e	125	unsigned flags);
04e4e2e9 YT	126	int amdgpu_fence_emit_polling(struct amdgpu_ring ring, uint32_t s,
04e4e2e9 YT	127	uint32_t timeout);
95d7fc4a	128	bool amdgpu_fence_process(struct amdgpu_ring *ring);
78023016	129	int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
43ca8efa	130	signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
	131	uint32_t wait_seq,
	132	signed long timeout);
78023016 CK	133	unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
	134
	135	/*
	136	* Rings.
	137	*/
	138
	139	/* provided by hw blocks that expose a ring buffer for commands */
	140	struct amdgpu_ring_funcs {
21cd942e	141	enum amdgpu_ring_type type;
79887142 CK	142	uint32_t align_mask;
79887142 CK	143	u32 nop;
536fbf94	144	bool support_64bit_ptrs;
120c2125	145	bool no_user_fence;
0eeb68b3	146	unsigned vmhub;
c8c1a1d2	147	unsigned extra_dw;
21cd942e	148
78023016	149	/* ring read/write ptr handling */
536fbf94 KW	150	u64 (get_rptr)(struct amdgpu_ring ring);
536fbf94 KW	151	u64 (get_wptr)(struct amdgpu_ring ring);
78023016 CK	152	void (set_wptr)(struct amdgpu_ring ring);
	153	/* validating and patching of IBs */
	154	int (parse_cs)(struct amdgpu_cs_parser p, uint32_t ib_idx);
9d248517	155	int (patch_cs_in_place)(struct amdgpu_cs_parser p, uint32_t ib_idx);
e12f3d7a CK	156	/* constants to calculate how many DW are needed for an emit */
	157	unsigned emit_frame_size;
	158	unsigned emit_ib_size;
78023016 CK	159	/* command emit functions */
78023016 CK	160	void (emit_ib)(struct amdgpu_ring ring,
34955e03	161	struct amdgpu_job *job,
78023016	162	struct amdgpu_ib *ib,
c4c905ec	163	uint32_t flags);
78023016 CK	164	void (emit_fence)(struct amdgpu_ring ring, uint64_t addr,
	165	uint64_t seq, unsigned flags);
	166	void (emit_pipeline_sync)(struct amdgpu_ring ring);
c4f46f22	167	void (emit_vm_flush)(struct amdgpu_ring ring, unsigned vmid,
c633c00b	168	uint64_t pd_addr);
78023016	169	void (emit_hdp_flush)(struct amdgpu_ring ring);
78023016 CK	170	void (emit_gds_switch)(struct amdgpu_ring ring, uint32_t vmid,
	171	uint32_t gds_base, uint32_t gds_size,
	172	uint32_t gws_base, uint32_t gws_size,
	173	uint32_t oa_base, uint32_t oa_size);
	174	/* testing functions */
	175	int (test_ring)(struct amdgpu_ring ring);
	176	int (test_ib)(struct amdgpu_ring ring, long timeout);
	177	/* insert NOP packets */
	178	void (insert_nop)(struct amdgpu_ring ring, uint32_t count);
ef44f854	179	void (insert_start)(struct amdgpu_ring ring);
135d4735	180	void (insert_end)(struct amdgpu_ring ring);
78023016 CK	181	/* pad the indirect buffer to the necessary number of dw */
	182	void (pad_ib)(struct amdgpu_ring ring, struct amdgpu_ib *ib);
	183	unsigned (init_cond_exec)(struct amdgpu_ring ring);
	184	void (patch_cond_exec)(struct amdgpu_ring ring, unsigned offset);
	185	/* note usage for clock and power gating */
	186	void (begin_use)(struct amdgpu_ring ring);
	187	void (end_use)(struct amdgpu_ring ring);
	188	void (emit_switch_buffer) (struct amdgpu_ring ring);
0bb5d5b0	189	void (emit_cntxcntl) (struct amdgpu_ring ring, uint32_t flags);
54208194 YT	190	void (emit_rreg)(struct amdgpu_ring ring, uint32_t reg,
54208194 YT	191	uint32_t reg_val_offs);
b6091c12	192	void (emit_wreg)(struct amdgpu_ring ring, uint32_t reg, uint32_t val);
c1e877da CK	193	void (emit_reg_wait)(struct amdgpu_ring ring, uint32_t reg,
c1e877da CK	194	uint32_t val, uint32_t mask);
82853638 AD	195	void (emit_reg_write_reg_wait)(struct amdgpu_ring ring,
	196	uint32_t reg0, uint32_t reg1,
	197	uint32_t ref, uint32_t mask);
f77c9aff HR	198	void (emit_frame_cntl)(struct amdgpu_ring ring, bool start,
f77c9aff HR	199	bool secure);
7876fa4f CK	200	/* Try to soft recover the ring to make the fence signal */
7876fa4f CK	201	void (soft_recovery)(struct amdgpu_ring ring, unsigned vmid);
692441f2	202	int (preempt_ib)(struct amdgpu_ring ring);
22301177	203	void (emit_mem_sync)(struct amdgpu_ring ring);
0a52a6ca	204	void (emit_wave_limit)(struct amdgpu_ring ring, bool enable);
78023016 CK	205	};
	206
	207	struct amdgpu_ring {
	208	struct amdgpu_device *adev;
	209	const struct amdgpu_ring_funcs *funcs;
	210	struct amdgpu_fence_driver fence_drv;
1b1f42d8	211	struct drm_gpu_scheduler sched;
78023016 CK	212
	213	struct amdgpu_bo *ring_obj;
	214	volatile uint32_t *ring;
	215	unsigned rptr_offs;
536fbf94 KW	216	u64 wptr;
536fbf94 KW	217	u64 wptr_old;
78023016 CK	218	unsigned ring_size;
	219	unsigned max_dw;
	220	int count_dw;
	221	uint64_t gpu_addr;
536fbf94 KW	222	uint64_t ptr_mask;
536fbf94 KW	223	uint32_t buf_mask;
78023016 CK	224	u32 idx;
	225	u32 me;
	226	u32 pipe;
	227	u32 queue;
	228	struct amdgpu_bo *mqd_obj;
f3972b53	229	uint64_t mqd_gpu_addr;
59a82d7d	230	void *mqd_ptr;
34534610	231	uint64_t eop_gpu_addr;
78023016 CK	232	u32 doorbell_index;
78023016 CK	233	bool use_doorbell;
2ffe31de	234	bool use_pollmem;
78023016 CK	235	unsigned wptr_offs;
	236	unsigned fence_offs;
	237	uint64_t current_ctx;
78023016	238	char name[16];
ef3e1323 JX	239	u32 trail_seq;
	240	unsigned trail_fence_offs;
	241	u64 trail_fence_gpu_addr;
	242	volatile u32 *trail_fence_cpu_addr;
78023016 CK	243	unsigned cond_exe_offs;
	244	u64 cond_exe_gpu_addr;
	245	volatile u32 *cond_exe_cpu_addr;
4789c463	246	unsigned vm_inv_eng;
3af81440	247	struct dma_fence *vmid_wait;
dd684d31	248	bool has_compute_vm_bug;
cb3d1085	249	bool no_scheduler;
ebdd2e9d	250	int hw_prio;
b2ff0e8a	251
78023016 CK	252	#if defined(CONFIG_DEBUG_FS)
	253	struct dentry *ent;
	254	#endif
	255	};
	256
0a7845db HR	257	#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
	258	#define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib)))
	259	#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
	260	#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
	261	#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
	262	#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
	263	#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
c4c905ec	264	#define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags)))
0a7845db HR	265	#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
	266	#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
	267	#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
	268	#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
	269	#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
	270	#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
0bb5d5b0	271	#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
54208194	272	#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
0a7845db HR	273	#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
	274	#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
	275	#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
f77c9aff	276	#define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s))
0a7845db HR	277	#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
	278	#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
	279	#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
692441f2	280	#define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r)
0a7845db	281
78023016 CK	282	int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
	283	void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
	284	void amdgpu_ring_generic_pad_ib(struct amdgpu_ring ring, struct amdgpu_ib ib);
	285	void amdgpu_ring_commit(struct amdgpu_ring *ring);
	286	void amdgpu_ring_undo(struct amdgpu_ring *ring);
	287	int amdgpu_ring_init(struct amdgpu_device adev, struct amdgpu_ring ring,
1c6d567b	288	unsigned int ring_size, struct amdgpu_irq_src *irq_src,
c107171b CK	289	unsigned int irq_type, unsigned int prio,
c107171b CK	290	atomic_t *sched_score);
78023016	291	void amdgpu_ring_fini(struct amdgpu_ring *ring);
82853638 AD	292	void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
	293	uint32_t reg0, uint32_t val0,
	294	uint32_t reg1, uint32_t val1);
7876fa4f CK	295	bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
7876fa4f CK	296	struct dma_fence *fence);
82853638	297
dfc98479 RZ	298	static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring,
	299	bool cond_exec)
	300	{
	301	*ring->cond_exe_cpu_addr = cond_exec;
	302	}
	303
c79ecfbf ML	304	static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
	305	{
	306	int i = 0;
e09706f4	307	while (i <= ring->buf_mask)
c79ecfbf ML	308	ring->ring[i++] = ring->funcs->nop;
	309
	310	}
78023016	311
e8110b1c CK	312	static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
	313	{
	314	if (ring->count_dw <= 0)
	315	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
	316	ring->ring[ring->wptr++ & ring->buf_mask] = v;
	317	ring->wptr &= ring->ptr_mask;
	318	ring->count_dw--;
	319	}
	320
	321	static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
	322	void *src, int count_dw)
	323	{
	324	unsigned occupied, chunk1, chunk2;
	325	void *dst;
	326
369421cb	327	if (unlikely(ring->count_dw < count_dw))
e8110b1c	328	DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
e8110b1c CK	329
	330	occupied = ring->wptr & ring->buf_mask;
	331	dst = (void *)&ring->ring[occupied];
	332	chunk1 = ring->buf_mask + 1 - occupied;
	333	chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
	334	chunk2 = count_dw - chunk1;
	335	chunk1 <<= 2;
	336	chunk2 <<= 2;
	337
	338	if (chunk1)
	339	memcpy(dst, src, chunk1);
	340
	341	if (chunk2) {
	342	src += chunk1;
	343	dst = (void *)ring->ring;
	344	memcpy(dst, src, chunk2);
	345	}
	346
	347	ring->wptr += count_dw;
	348	ring->wptr &= ring->ptr_mask;
	349	ring->count_dw -= count_dw;
	350	}
	351
c66ed765 AG	352	int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
c66ed765 AG	353
fd23cfcc AD	354	int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
	355	struct amdgpu_ring *ring);
	356	void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
	357
78023016	358	#endif