Commit | Line | Data |
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78023016 CK |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_RING_H__ | |
25 | #define __AMDGPU_RING_H__ | |
26 | ||
b2ff0e8a | 27 | #include <drm/amdgpu_drm.h> |
1b1f42d8 | 28 | #include <drm/gpu_scheduler.h> |
61b100e9 | 29 | #include <drm/drm_print.h> |
78023016 | 30 | |
a190f8dc CK |
31 | struct amdgpu_device; |
32 | struct amdgpu_ring; | |
33 | struct amdgpu_ib; | |
34 | struct amdgpu_cs_parser; | |
35 | struct amdgpu_job; | |
36 | struct amdgpu_vm; | |
37 | ||
78023016 | 38 | /* max number of rings */ |
8b75a521 | 39 | #define AMDGPU_MAX_RINGS 28 |
1c6d567b | 40 | #define AMDGPU_MAX_HWIP_RINGS 8 |
a644d85a | 41 | #define AMDGPU_MAX_GFX_RINGS 2 |
78023016 CK |
42 | #define AMDGPU_MAX_COMPUTE_RINGS 8 |
43 | #define AMDGPU_MAX_VCE_RINGS 3 | |
f7243053 | 44 | #define AMDGPU_MAX_UVD_ENC_RINGS 2 |
78023016 | 45 | |
34eaf30f ND |
46 | enum amdgpu_ring_priority_level { |
47 | AMDGPU_RING_PRIO_0, | |
48 | AMDGPU_RING_PRIO_1, | |
49 | AMDGPU_RING_PRIO_DEFAULT = 1, | |
50 | AMDGPU_RING_PRIO_2, | |
51 | AMDGPU_RING_PRIO_MAX | |
52 | }; | |
1c6d567b | 53 | |
78023016 | 54 | /* some special values for the owner field */ |
d8d019cc FK |
55 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) |
56 | #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) | |
57 | #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) | |
78023016 CK |
58 | |
59 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) | |
60 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
d240cd9e | 61 | #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) |
78023016 | 62 | |
0e28b10f CK |
63 | #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) |
64 | ||
9ecefb19 CK |
65 | #define AMDGPU_IB_POOL_SIZE (1024 * 1024) |
66 | ||
78023016 | 67 | enum amdgpu_ring_type { |
07e14845 ND |
68 | AMDGPU_RING_TYPE_GFX = AMDGPU_HW_IP_GFX, |
69 | AMDGPU_RING_TYPE_COMPUTE = AMDGPU_HW_IP_COMPUTE, | |
70 | AMDGPU_RING_TYPE_SDMA = AMDGPU_HW_IP_DMA, | |
71 | AMDGPU_RING_TYPE_UVD = AMDGPU_HW_IP_UVD, | |
72 | AMDGPU_RING_TYPE_VCE = AMDGPU_HW_IP_VCE, | |
73 | AMDGPU_RING_TYPE_UVD_ENC = AMDGPU_HW_IP_UVD_ENC, | |
74 | AMDGPU_RING_TYPE_VCN_DEC = AMDGPU_HW_IP_VCN_DEC, | |
75 | AMDGPU_RING_TYPE_VCN_ENC = AMDGPU_HW_IP_VCN_ENC, | |
76 | AMDGPU_RING_TYPE_VCN_JPEG = AMDGPU_HW_IP_VCN_JPEG, | |
cdca7979 JX |
77 | AMDGPU_RING_TYPE_KIQ, |
78 | AMDGPU_RING_TYPE_MES | |
78023016 CK |
79 | }; |
80 | ||
9ecefb19 CK |
81 | enum amdgpu_ib_pool_type { |
82 | /* Normal submissions to the top of the pipeline. */ | |
83 | AMDGPU_IB_POOL_DELAYED, | |
84 | /* Immediate submissions to the bottom of the pipeline. */ | |
85 | AMDGPU_IB_POOL_IMMEDIATE, | |
86 | /* Direct submission to the ring buffer during init and reset. */ | |
87 | AMDGPU_IB_POOL_DIRECT, | |
88 | ||
89 | AMDGPU_IB_POOL_MAX | |
90 | }; | |
91 | ||
a190f8dc CK |
92 | struct amdgpu_ib { |
93 | struct amdgpu_sa_bo *sa_bo; | |
94 | uint32_t length_dw; | |
95 | uint64_t gpu_addr; | |
96 | uint32_t *ptr; | |
97 | uint32_t flags; | |
98 | }; | |
78023016 | 99 | |
1c6d567b ND |
100 | struct amdgpu_sched { |
101 | u32 num_scheds; | |
102 | struct drm_gpu_scheduler *sched[AMDGPU_MAX_HWIP_RINGS]; | |
103 | }; | |
104 | ||
78023016 CK |
105 | /* |
106 | * Fences. | |
107 | */ | |
108 | struct amdgpu_fence_driver { | |
109 | uint64_t gpu_addr; | |
110 | volatile uint32_t *cpu_addr; | |
111 | /* sync_seq is protected by ring emission lock */ | |
112 | uint32_t sync_seq; | |
113 | atomic_t last_seq; | |
114 | bool initialized; | |
115 | struct amdgpu_irq_src *irq_src; | |
116 | unsigned irq_type; | |
8c5e13ec | 117 | struct timer_list fallback_timer; |
78023016 CK |
118 | unsigned num_fences_mask; |
119 | spinlock_t lock; | |
220196b3 | 120 | struct dma_fence **fences; |
78023016 CK |
121 | }; |
122 | ||
a190f8dc CK |
123 | extern const struct drm_sched_backend_ops amdgpu_sched_ops; |
124 | ||
bf67014d | 125 | void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); |
2f9d4084 | 126 | void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); |
78023016 | 127 | |
5fd8518d | 128 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); |
78023016 CK |
129 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, |
130 | struct amdgpu_irq_src *irq_src, | |
131 | unsigned irq_type); | |
067f44c8 | 132 | void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev); |
8d35a259 | 133 | void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev); |
067f44c8 | 134 | int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev); |
8d35a259 | 135 | void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev); |
c530b02f | 136 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, struct amdgpu_job *job, |
d240cd9e | 137 | unsigned flags); |
04e4e2e9 YT |
138 | int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s, |
139 | uint32_t timeout); | |
95d7fc4a | 140 | bool amdgpu_fence_process(struct amdgpu_ring *ring); |
78023016 | 141 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); |
43ca8efa | 142 | signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, |
143 | uint32_t wait_seq, | |
144 | signed long timeout); | |
78023016 CK |
145 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); |
146 | ||
147 | /* | |
148 | * Rings. | |
149 | */ | |
150 | ||
151 | /* provided by hw blocks that expose a ring buffer for commands */ | |
152 | struct amdgpu_ring_funcs { | |
21cd942e | 153 | enum amdgpu_ring_type type; |
79887142 CK |
154 | uint32_t align_mask; |
155 | u32 nop; | |
536fbf94 | 156 | bool support_64bit_ptrs; |
120c2125 | 157 | bool no_user_fence; |
8c0f11ff | 158 | bool secure_submission_supported; |
0eeb68b3 | 159 | unsigned vmhub; |
c8c1a1d2 | 160 | unsigned extra_dw; |
21cd942e | 161 | |
78023016 | 162 | /* ring read/write ptr handling */ |
536fbf94 KW |
163 | u64 (*get_rptr)(struct amdgpu_ring *ring); |
164 | u64 (*get_wptr)(struct amdgpu_ring *ring); | |
78023016 CK |
165 | void (*set_wptr)(struct amdgpu_ring *ring); |
166 | /* validating and patching of IBs */ | |
cdc7893f CK |
167 | int (*parse_cs)(struct amdgpu_cs_parser *p, |
168 | struct amdgpu_job *job, | |
169 | struct amdgpu_ib *ib); | |
170 | int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, | |
171 | struct amdgpu_job *job, | |
172 | struct amdgpu_ib *ib); | |
e12f3d7a CK |
173 | /* constants to calculate how many DW are needed for an emit */ |
174 | unsigned emit_frame_size; | |
175 | unsigned emit_ib_size; | |
78023016 CK |
176 | /* command emit functions */ |
177 | void (*emit_ib)(struct amdgpu_ring *ring, | |
34955e03 | 178 | struct amdgpu_job *job, |
78023016 | 179 | struct amdgpu_ib *ib, |
c4c905ec | 180 | uint32_t flags); |
78023016 CK |
181 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, |
182 | uint64_t seq, unsigned flags); | |
183 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); | |
c4f46f22 | 184 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, |
c633c00b | 185 | uint64_t pd_addr); |
78023016 | 186 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); |
78023016 CK |
187 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, |
188 | uint32_t gds_base, uint32_t gds_size, | |
189 | uint32_t gws_base, uint32_t gws_size, | |
190 | uint32_t oa_base, uint32_t oa_size); | |
191 | /* testing functions */ | |
192 | int (*test_ring)(struct amdgpu_ring *ring); | |
193 | int (*test_ib)(struct amdgpu_ring *ring, long timeout); | |
194 | /* insert NOP packets */ | |
195 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
ef44f854 | 196 | void (*insert_start)(struct amdgpu_ring *ring); |
135d4735 | 197 | void (*insert_end)(struct amdgpu_ring *ring); |
78023016 CK |
198 | /* pad the indirect buffer to the necessary number of dw */ |
199 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
200 | unsigned (*init_cond_exec)(struct amdgpu_ring *ring); | |
201 | void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); | |
202 | /* note usage for clock and power gating */ | |
203 | void (*begin_use)(struct amdgpu_ring *ring); | |
204 | void (*end_use)(struct amdgpu_ring *ring); | |
205 | void (*emit_switch_buffer) (struct amdgpu_ring *ring); | |
0bb5d5b0 | 206 | void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); |
54208194 YT |
207 | void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg, |
208 | uint32_t reg_val_offs); | |
b6091c12 | 209 | void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); |
c1e877da CK |
210 | void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, |
211 | uint32_t val, uint32_t mask); | |
82853638 AD |
212 | void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, |
213 | uint32_t reg0, uint32_t reg1, | |
214 | uint32_t ref, uint32_t mask); | |
f77c9aff HR |
215 | void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start, |
216 | bool secure); | |
7876fa4f CK |
217 | /* Try to soft recover the ring to make the fence signal */ |
218 | void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); | |
692441f2 | 219 | int (*preempt_ib)(struct amdgpu_ring *ring); |
22301177 | 220 | void (*emit_mem_sync)(struct amdgpu_ring *ring); |
0a52a6ca | 221 | void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable); |
78023016 CK |
222 | }; |
223 | ||
224 | struct amdgpu_ring { | |
225 | struct amdgpu_device *adev; | |
226 | const struct amdgpu_ring_funcs *funcs; | |
227 | struct amdgpu_fence_driver fence_drv; | |
1b1f42d8 | 228 | struct drm_gpu_scheduler sched; |
78023016 CK |
229 | |
230 | struct amdgpu_bo *ring_obj; | |
231 | volatile uint32_t *ring; | |
232 | unsigned rptr_offs; | |
536fbf94 KW |
233 | u64 wptr; |
234 | u64 wptr_old; | |
78023016 CK |
235 | unsigned ring_size; |
236 | unsigned max_dw; | |
237 | int count_dw; | |
238 | uint64_t gpu_addr; | |
536fbf94 KW |
239 | uint64_t ptr_mask; |
240 | uint32_t buf_mask; | |
78023016 CK |
241 | u32 idx; |
242 | u32 me; | |
243 | u32 pipe; | |
244 | u32 queue; | |
245 | struct amdgpu_bo *mqd_obj; | |
f3972b53 | 246 | uint64_t mqd_gpu_addr; |
59a82d7d | 247 | void *mqd_ptr; |
34534610 | 248 | uint64_t eop_gpu_addr; |
78023016 CK |
249 | u32 doorbell_index; |
250 | bool use_doorbell; | |
2ffe31de | 251 | bool use_pollmem; |
78023016 CK |
252 | unsigned wptr_offs; |
253 | unsigned fence_offs; | |
254 | uint64_t current_ctx; | |
78023016 | 255 | char name[16]; |
ef3e1323 JX |
256 | u32 trail_seq; |
257 | unsigned trail_fence_offs; | |
258 | u64 trail_fence_gpu_addr; | |
259 | volatile u32 *trail_fence_cpu_addr; | |
78023016 CK |
260 | unsigned cond_exe_offs; |
261 | u64 cond_exe_gpu_addr; | |
262 | volatile u32 *cond_exe_cpu_addr; | |
4789c463 | 263 | unsigned vm_inv_eng; |
3af81440 | 264 | struct dma_fence *vmid_wait; |
dd684d31 | 265 | bool has_compute_vm_bug; |
cb3d1085 | 266 | bool no_scheduler; |
ebdd2e9d | 267 | int hw_prio; |
5fd8518d AG |
268 | unsigned num_hw_submission; |
269 | atomic_t *sched_score; | |
78023016 CK |
270 | }; |
271 | ||
cdc7893f CK |
272 | #define amdgpu_ring_parse_cs(r, p, job, ib) ((r)->funcs->parse_cs((p), (job), (ib))) |
273 | #define amdgpu_ring_patch_cs_in_place(r, p, job, ib) ((r)->funcs->patch_cs_in_place((p), (job), (ib))) | |
0a7845db HR |
274 | #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) |
275 | #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) | |
276 | #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) | |
277 | #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) | |
278 | #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) | |
c4c905ec | 279 | #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) |
0a7845db HR |
280 | #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) |
281 | #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) | |
282 | #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) | |
283 | #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) | |
284 | #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) | |
285 | #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) | |
0bb5d5b0 | 286 | #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) |
54208194 | 287 | #define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o)) |
0a7845db HR |
288 | #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) |
289 | #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) | |
290 | #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) | |
f77c9aff | 291 | #define amdgpu_ring_emit_frame_cntl(r, b, s) (r)->funcs->emit_frame_cntl((r), (b), (s)) |
0a7845db HR |
292 | #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) |
293 | #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) | |
294 | #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) | |
692441f2 | 295 | #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) |
0a7845db | 296 | |
78023016 CK |
297 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); |
298 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); | |
299 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
300 | void amdgpu_ring_commit(struct amdgpu_ring *ring); | |
301 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | |
302 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
cf8cc382 MJ |
303 | unsigned int max_dw, struct amdgpu_irq_src *irq_src, |
304 | unsigned int irq_type, unsigned int hw_prio, | |
c107171b | 305 | atomic_t *sched_score); |
78023016 | 306 | void amdgpu_ring_fini(struct amdgpu_ring *ring); |
82853638 AD |
307 | void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, |
308 | uint32_t reg0, uint32_t val0, | |
309 | uint32_t reg1, uint32_t val1); | |
7876fa4f CK |
310 | bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, |
311 | struct dma_fence *fence); | |
82853638 | 312 | |
dfc98479 RZ |
313 | static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, |
314 | bool cond_exec) | |
315 | { | |
316 | *ring->cond_exe_cpu_addr = cond_exec; | |
317 | } | |
318 | ||
c79ecfbf ML |
319 | static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) |
320 | { | |
321 | int i = 0; | |
e09706f4 | 322 | while (i <= ring->buf_mask) |
c79ecfbf ML |
323 | ring->ring[i++] = ring->funcs->nop; |
324 | ||
325 | } | |
78023016 | 326 | |
e8110b1c CK |
327 | static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) |
328 | { | |
329 | if (ring->count_dw <= 0) | |
330 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); | |
331 | ring->ring[ring->wptr++ & ring->buf_mask] = v; | |
332 | ring->wptr &= ring->ptr_mask; | |
333 | ring->count_dw--; | |
334 | } | |
335 | ||
336 | static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, | |
337 | void *src, int count_dw) | |
338 | { | |
339 | unsigned occupied, chunk1, chunk2; | |
340 | void *dst; | |
341 | ||
369421cb | 342 | if (unlikely(ring->count_dw < count_dw)) |
e8110b1c | 343 | DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); |
e8110b1c CK |
344 | |
345 | occupied = ring->wptr & ring->buf_mask; | |
346 | dst = (void *)&ring->ring[occupied]; | |
347 | chunk1 = ring->buf_mask + 1 - occupied; | |
348 | chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; | |
349 | chunk2 = count_dw - chunk1; | |
350 | chunk1 <<= 2; | |
351 | chunk2 <<= 2; | |
352 | ||
353 | if (chunk1) | |
354 | memcpy(dst, src, chunk1); | |
355 | ||
356 | if (chunk2) { | |
357 | src += chunk1; | |
358 | dst = (void *)ring->ring; | |
359 | memcpy(dst, src, chunk2); | |
360 | } | |
361 | ||
362 | ring->wptr += count_dw; | |
363 | ring->wptr &= ring->ptr_mask; | |
364 | ring->count_dw -= count_dw; | |
365 | } | |
366 | ||
2bc956ef JX |
367 | #define amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset) \ |
368 | (ring->is_mes_queue && ring->mes_ctx ? \ | |
369 | (ring->mes_ctx->meta_data_gpu_addr + offset) : 0) | |
370 | ||
371 | #define amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset) \ | |
372 | (ring->is_mes_queue && ring->mes_ctx ? \ | |
373 | (void *)((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : \ | |
374 | NULL) | |
375 | ||
c66ed765 AG |
376 | int amdgpu_ring_test_helper(struct amdgpu_ring *ring); |
377 | ||
62d266b2 ND |
378 | void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
379 | struct amdgpu_ring *ring); | |
a190f8dc | 380 | |
80af9daa JX |
381 | int amdgpu_ring_init_mqd(struct amdgpu_ring *ring); |
382 | ||
cdc7893f CK |
383 | static inline u32 amdgpu_ib_get_value(struct amdgpu_ib *ib, int idx) |
384 | { | |
385 | return ib->ptr[idx]; | |
386 | } | |
387 | ||
388 | static inline void amdgpu_ib_set_value(struct amdgpu_ib *ib, int idx, | |
389 | uint32_t value) | |
390 | { | |
391 | ib->ptr[idx] = value; | |
392 | } | |
393 | ||
a190f8dc CK |
394 | int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, |
395 | unsigned size, | |
396 | enum amdgpu_ib_pool_type pool, | |
397 | struct amdgpu_ib *ib); | |
398 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, | |
399 | struct dma_fence *f); | |
400 | int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, | |
401 | struct amdgpu_ib *ibs, struct amdgpu_job *job, | |
402 | struct dma_fence **f); | |
403 | int amdgpu_ib_pool_init(struct amdgpu_device *adev); | |
404 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev); | |
405 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev); | |
406 | ||
78023016 | 407 | #endif |