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1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Christian König | |
23 | */ | |
24 | #ifndef __AMDGPU_RING_H__ | |
25 | #define __AMDGPU_RING_H__ | |
26 | ||
27 | #include "gpu_scheduler.h" | |
28 | ||
29 | /* max number of rings */ | |
f7243053 | 30 | #define AMDGPU_MAX_RINGS 18 |
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31 | #define AMDGPU_MAX_GFX_RINGS 1 |
32 | #define AMDGPU_MAX_COMPUTE_RINGS 8 | |
33 | #define AMDGPU_MAX_VCE_RINGS 3 | |
f7243053 | 34 | #define AMDGPU_MAX_UVD_ENC_RINGS 2 |
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35 | |
36 | /* some special values for the owner field */ | |
37 | #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) | |
38 | #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) | |
39 | ||
40 | #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) | |
41 | #define AMDGPU_FENCE_FLAG_INT (1 << 1) | |
42 | ||
43 | enum amdgpu_ring_type { | |
44 | AMDGPU_RING_TYPE_GFX, | |
45 | AMDGPU_RING_TYPE_COMPUTE, | |
46 | AMDGPU_RING_TYPE_SDMA, | |
47 | AMDGPU_RING_TYPE_UVD, | |
2068751d | 48 | AMDGPU_RING_TYPE_VCE, |
50c3e232 LL |
49 | AMDGPU_RING_TYPE_KIQ, |
50 | AMDGPU_RING_TYPE_UVD_ENC | |
78023016 CK |
51 | }; |
52 | ||
53 | struct amdgpu_device; | |
54 | struct amdgpu_ring; | |
55 | struct amdgpu_ib; | |
56 | struct amdgpu_cs_parser; | |
57 | ||
58 | /* | |
59 | * Fences. | |
60 | */ | |
61 | struct amdgpu_fence_driver { | |
62 | uint64_t gpu_addr; | |
63 | volatile uint32_t *cpu_addr; | |
64 | /* sync_seq is protected by ring emission lock */ | |
65 | uint32_t sync_seq; | |
66 | atomic_t last_seq; | |
67 | bool initialized; | |
68 | struct amdgpu_irq_src *irq_src; | |
69 | unsigned irq_type; | |
70 | struct timer_list fallback_timer; | |
71 | unsigned num_fences_mask; | |
72 | spinlock_t lock; | |
220196b3 | 73 | struct dma_fence **fences; |
78023016 CK |
74 | }; |
75 | ||
76 | int amdgpu_fence_driver_init(struct amdgpu_device *adev); | |
77 | void amdgpu_fence_driver_fini(struct amdgpu_device *adev); | |
78 | void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); | |
79 | ||
80 | int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, | |
81 | unsigned num_hw_submission); | |
82 | int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, | |
83 | struct amdgpu_irq_src *irq_src, | |
84 | unsigned irq_type); | |
85 | void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); | |
86 | void amdgpu_fence_driver_resume(struct amdgpu_device *adev); | |
220196b3 | 87 | int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence); |
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88 | void amdgpu_fence_process(struct amdgpu_ring *ring); |
89 | int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); | |
90 | unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); | |
91 | ||
92 | /* | |
93 | * Rings. | |
94 | */ | |
95 | ||
96 | /* provided by hw blocks that expose a ring buffer for commands */ | |
97 | struct amdgpu_ring_funcs { | |
21cd942e | 98 | enum amdgpu_ring_type type; |
79887142 CK |
99 | uint32_t align_mask; |
100 | u32 nop; | |
536fbf94 | 101 | bool support_64bit_ptrs; |
21cd942e | 102 | |
78023016 | 103 | /* ring read/write ptr handling */ |
536fbf94 KW |
104 | u64 (*get_rptr)(struct amdgpu_ring *ring); |
105 | u64 (*get_wptr)(struct amdgpu_ring *ring); | |
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106 | void (*set_wptr)(struct amdgpu_ring *ring); |
107 | /* validating and patching of IBs */ | |
108 | int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); | |
e12f3d7a CK |
109 | /* constants to calculate how many DW are needed for an emit */ |
110 | unsigned emit_frame_size; | |
111 | unsigned emit_ib_size; | |
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112 | /* command emit functions */ |
113 | void (*emit_ib)(struct amdgpu_ring *ring, | |
114 | struct amdgpu_ib *ib, | |
115 | unsigned vm_id, bool ctx_switch); | |
116 | void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, | |
117 | uint64_t seq, unsigned flags); | |
118 | void (*emit_pipeline_sync)(struct amdgpu_ring *ring); | |
119 | void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, | |
120 | uint64_t pd_addr); | |
121 | void (*emit_hdp_flush)(struct amdgpu_ring *ring); | |
122 | void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); | |
123 | void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, | |
124 | uint32_t gds_base, uint32_t gds_size, | |
125 | uint32_t gws_base, uint32_t gws_size, | |
126 | uint32_t oa_base, uint32_t oa_size); | |
127 | /* testing functions */ | |
128 | int (*test_ring)(struct amdgpu_ring *ring); | |
129 | int (*test_ib)(struct amdgpu_ring *ring, long timeout); | |
130 | /* insert NOP packets */ | |
131 | void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); | |
135d4735 | 132 | void (*insert_end)(struct amdgpu_ring *ring); |
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133 | /* pad the indirect buffer to the necessary number of dw */ |
134 | void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
135 | unsigned (*init_cond_exec)(struct amdgpu_ring *ring); | |
136 | void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); | |
137 | /* note usage for clock and power gating */ | |
138 | void (*begin_use)(struct amdgpu_ring *ring); | |
139 | void (*end_use)(struct amdgpu_ring *ring); | |
140 | void (*emit_switch_buffer) (struct amdgpu_ring *ring); | |
141 | void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); | |
b6091c12 XY |
142 | void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); |
143 | void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); | |
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144 | }; |
145 | ||
146 | struct amdgpu_ring { | |
147 | struct amdgpu_device *adev; | |
148 | const struct amdgpu_ring_funcs *funcs; | |
149 | struct amdgpu_fence_driver fence_drv; | |
150 | struct amd_gpu_scheduler sched; | |
151 | ||
152 | struct amdgpu_bo *ring_obj; | |
153 | volatile uint32_t *ring; | |
154 | unsigned rptr_offs; | |
536fbf94 KW |
155 | u64 wptr; |
156 | u64 wptr_old; | |
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157 | unsigned ring_size; |
158 | unsigned max_dw; | |
159 | int count_dw; | |
160 | uint64_t gpu_addr; | |
536fbf94 KW |
161 | uint64_t ptr_mask; |
162 | uint32_t buf_mask; | |
78023016 | 163 | bool ready; |
78023016 CK |
164 | u32 idx; |
165 | u32 me; | |
166 | u32 pipe; | |
167 | u32 queue; | |
168 | struct amdgpu_bo *mqd_obj; | |
f3972b53 | 169 | uint64_t mqd_gpu_addr; |
59a82d7d | 170 | void *mqd_ptr; |
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171 | u32 doorbell_index; |
172 | bool use_doorbell; | |
173 | unsigned wptr_offs; | |
174 | unsigned fence_offs; | |
175 | uint64_t current_ctx; | |
78023016 CK |
176 | char name[16]; |
177 | unsigned cond_exe_offs; | |
178 | u64 cond_exe_gpu_addr; | |
179 | volatile u32 *cond_exe_cpu_addr; | |
180 | #if defined(CONFIG_DEBUG_FS) | |
181 | struct dentry *ent; | |
182 | #endif | |
183 | }; | |
184 | ||
185 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); | |
186 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); | |
187 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | |
188 | void amdgpu_ring_commit(struct amdgpu_ring *ring); | |
189 | void amdgpu_ring_undo(struct amdgpu_ring *ring); | |
190 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
79887142 CK |
191 | unsigned ring_size, struct amdgpu_irq_src *irq_src, |
192 | unsigned irq_type); | |
78023016 | 193 | void amdgpu_ring_fini(struct amdgpu_ring *ring); |
c79ecfbf ML |
194 | static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) |
195 | { | |
196 | int i = 0; | |
197 | while (i <= ring->ptr_mask) | |
198 | ring->ring[i++] = ring->funcs->nop; | |
199 | ||
200 | } | |
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201 | |
202 | #endif |