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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | * Christian König | |
28 | */ | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/slab.h> | |
4f4824b5 | 31 | #include <linux/debugfs.h> |
d38ceaf9 AD |
32 | #include <drm/drmP.h> |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include "amdgpu.h" | |
35 | #include "atom.h" | |
36 | ||
37 | /* | |
38 | * Rings | |
39 | * Most engines on the GPU are fed via ring buffers. Ring | |
40 | * buffers are areas of GPU accessible memory that the host | |
41 | * writes commands into and the GPU reads commands out of. | |
42 | * There is a rptr (read pointer) that determines where the | |
43 | * GPU is currently reading, and a wptr (write pointer) | |
44 | * which determines where the host has written. When the | |
45 | * pointers are equal, the ring is idle. When the host | |
46 | * writes commands to the ring buffer, it increments the | |
47 | * wptr. The GPU then starts fetching commands and executes | |
48 | * them until the pointers are equal again. | |
49 | */ | |
eb430969 CK |
50 | static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
51 | struct amdgpu_ring *ring); | |
d38ceaf9 | 52 | |
d38ceaf9 AD |
53 | /** |
54 | * amdgpu_ring_alloc - allocate space on the ring buffer | |
55 | * | |
56 | * @adev: amdgpu_device pointer | |
57 | * @ring: amdgpu_ring structure holding ring information | |
58 | * @ndw: number of dwords to allocate in the ring buffer | |
59 | * | |
60 | * Allocate @ndw dwords in the ring buffer (all asics). | |
61 | * Returns 0 on success, error on failure. | |
62 | */ | |
63 | int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) | |
64 | { | |
d38ceaf9 AD |
65 | /* Align requested size with padding so unlock_commit can |
66 | * pad safely */ | |
d38ceaf9 | 67 | ndw = (ndw + ring->align_mask) & ~ring->align_mask; |
c7e6be23 CK |
68 | |
69 | /* Make sure we aren't trying to allocate more space | |
70 | * than the maximum for one submission | |
71 | */ | |
72 | if (WARN_ON_ONCE(ndw > ring->max_dw)) | |
73 | return -ENOMEM; | |
74 | ||
d38ceaf9 AD |
75 | ring->count_dw = ndw; |
76 | ring->wptr_old = ring->wptr; | |
77 | return 0; | |
78 | } | |
79 | ||
edff0e28 JZ |
80 | /** amdgpu_ring_insert_nop - insert NOP packets |
81 | * | |
82 | * @ring: amdgpu_ring structure holding ring information | |
83 | * @count: the number of NOP packets to insert | |
84 | * | |
85 | * This is the generic insert_nop function for rings except SDMA | |
86 | */ | |
87 | void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) | |
88 | { | |
89 | int i; | |
90 | ||
91 | for (i = 0; i < count; i++) | |
92 | amdgpu_ring_write(ring, ring->nop); | |
93 | } | |
94 | ||
9e5d5309 CK |
95 | /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets |
96 | * | |
97 | * @ring: amdgpu_ring structure holding ring information | |
98 | * @ib: IB to add NOP packets to | |
99 | * | |
100 | * This is the generic pad_ib function for rings except SDMA | |
101 | */ | |
102 | void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) | |
103 | { | |
104 | while (ib->length_dw & ring->align_mask) | |
105 | ib->ptr[ib->length_dw++] = ring->nop; | |
106 | } | |
107 | ||
d38ceaf9 AD |
108 | /** |
109 | * amdgpu_ring_commit - tell the GPU to execute the new | |
110 | * commands on the ring buffer | |
111 | * | |
112 | * @adev: amdgpu_device pointer | |
113 | * @ring: amdgpu_ring structure holding ring information | |
114 | * | |
115 | * Update the wptr (write pointer) to tell the GPU to | |
116 | * execute new commands on the ring buffer (all asics). | |
117 | */ | |
118 | void amdgpu_ring_commit(struct amdgpu_ring *ring) | |
119 | { | |
edff0e28 JZ |
120 | uint32_t count; |
121 | ||
d38ceaf9 | 122 | /* We pad to match fetch size */ |
edff0e28 JZ |
123 | count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); |
124 | count %= ring->align_mask + 1; | |
125 | ring->funcs->insert_nop(ring, count); | |
126 | ||
d38ceaf9 AD |
127 | mb(); |
128 | amdgpu_ring_set_wptr(ring); | |
129 | } | |
130 | ||
d38ceaf9 AD |
131 | /** |
132 | * amdgpu_ring_undo - reset the wptr | |
133 | * | |
134 | * @ring: amdgpu_ring structure holding ring information | |
135 | * | |
136 | * Reset the driver's copy of the wptr (all asics). | |
137 | */ | |
138 | void amdgpu_ring_undo(struct amdgpu_ring *ring) | |
139 | { | |
140 | ring->wptr = ring->wptr_old; | |
141 | } | |
142 | ||
d38ceaf9 AD |
143 | /** |
144 | * amdgpu_ring_backup - Back up the content of a ring | |
145 | * | |
146 | * @ring: the ring we want to back up | |
147 | * | |
148 | * Saves all unprocessed commits from a ring, returns the number of dwords saved. | |
149 | */ | |
150 | unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, | |
151 | uint32_t **data) | |
152 | { | |
153 | unsigned size, ptr, i; | |
154 | ||
d38ceaf9 AD |
155 | *data = NULL; |
156 | ||
a27de35c | 157 | if (ring->ring_obj == NULL) |
d38ceaf9 | 158 | return 0; |
d38ceaf9 AD |
159 | |
160 | /* it doesn't make sense to save anything if all fences are signaled */ | |
a27de35c | 161 | if (!amdgpu_fence_count_emitted(ring)) |
d38ceaf9 | 162 | return 0; |
d38ceaf9 AD |
163 | |
164 | ptr = le32_to_cpu(*ring->next_rptr_cpu_addr); | |
165 | ||
166 | size = ring->wptr + (ring->ring_size / 4); | |
167 | size -= ptr; | |
168 | size &= ring->ptr_mask; | |
a27de35c | 169 | if (size == 0) |
d38ceaf9 | 170 | return 0; |
d38ceaf9 AD |
171 | |
172 | /* and then save the content of the ring */ | |
173 | *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL); | |
a27de35c | 174 | if (!*data) |
d38ceaf9 | 175 | return 0; |
d38ceaf9 AD |
176 | for (i = 0; i < size; ++i) { |
177 | (*data)[i] = ring->ring[ptr++]; | |
178 | ptr &= ring->ptr_mask; | |
179 | } | |
180 | ||
d38ceaf9 AD |
181 | return size; |
182 | } | |
183 | ||
184 | /** | |
185 | * amdgpu_ring_restore - append saved commands to the ring again | |
186 | * | |
187 | * @ring: ring to append commands to | |
188 | * @size: number of dwords we want to write | |
189 | * @data: saved commands | |
190 | * | |
191 | * Allocates space on the ring and restore the previously saved commands. | |
192 | */ | |
193 | int amdgpu_ring_restore(struct amdgpu_ring *ring, | |
194 | unsigned size, uint32_t *data) | |
195 | { | |
196 | int i, r; | |
197 | ||
198 | if (!size || !data) | |
199 | return 0; | |
200 | ||
201 | /* restore the saved ring content */ | |
a27de35c | 202 | r = amdgpu_ring_alloc(ring, size); |
d38ceaf9 AD |
203 | if (r) |
204 | return r; | |
205 | ||
206 | for (i = 0; i < size; ++i) { | |
207 | amdgpu_ring_write(ring, data[i]); | |
208 | } | |
209 | ||
a27de35c | 210 | amdgpu_ring_commit(ring); |
d38ceaf9 AD |
211 | kfree(data); |
212 | return 0; | |
213 | } | |
214 | ||
215 | /** | |
216 | * amdgpu_ring_init - init driver ring struct. | |
217 | * | |
218 | * @adev: amdgpu_device pointer | |
219 | * @ring: amdgpu_ring structure holding ring information | |
a3f1cf35 | 220 | * @max_ndw: maximum number of dw for ring alloc |
d38ceaf9 AD |
221 | * @nop: nop packet for this ring |
222 | * | |
223 | * Initialize the driver information for the selected ring (all asics). | |
224 | * Returns 0 on success, error on failure. | |
225 | */ | |
226 | int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, | |
a3f1cf35 | 227 | unsigned max_dw, u32 nop, u32 align_mask, |
d38ceaf9 AD |
228 | struct amdgpu_irq_src *irq_src, unsigned irq_type, |
229 | enum amdgpu_ring_type ring_type) | |
230 | { | |
d38ceaf9 AD |
231 | int r; |
232 | ||
233 | if (ring->adev == NULL) { | |
234 | if (adev->num_rings >= AMDGPU_MAX_RINGS) | |
235 | return -EINVAL; | |
236 | ||
237 | ring->adev = adev; | |
238 | ring->idx = adev->num_rings++; | |
239 | adev->rings[ring->idx] = ring; | |
e6151a08 CK |
240 | r = amdgpu_fence_driver_init_ring(ring, |
241 | amdgpu_sched_hw_submission); | |
4f839a24 CK |
242 | if (r) |
243 | return r; | |
d38ceaf9 AD |
244 | } |
245 | ||
246 | r = amdgpu_wb_get(adev, &ring->rptr_offs); | |
247 | if (r) { | |
248 | dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r); | |
249 | return r; | |
250 | } | |
251 | ||
252 | r = amdgpu_wb_get(adev, &ring->wptr_offs); | |
253 | if (r) { | |
254 | dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r); | |
255 | return r; | |
256 | } | |
257 | ||
258 | r = amdgpu_wb_get(adev, &ring->fence_offs); | |
259 | if (r) { | |
260 | dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r); | |
261 | return r; | |
262 | } | |
263 | ||
264 | r = amdgpu_wb_get(adev, &ring->next_rptr_offs); | |
265 | if (r) { | |
266 | dev_err(adev->dev, "(%d) ring next_rptr wb alloc failed\n", r); | |
267 | return r; | |
268 | } | |
eb430969 | 269 | ring->next_rptr_gpu_addr = adev->wb.gpu_addr + ring->next_rptr_offs * 4; |
d38ceaf9 | 270 | ring->next_rptr_cpu_addr = &adev->wb.wb[ring->next_rptr_offs]; |
128cff1a ML |
271 | |
272 | r = amdgpu_wb_get(adev, &ring->cond_exe_offs); | |
273 | if (r) { | |
274 | dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r); | |
275 | return r; | |
276 | } | |
277 | ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4); | |
278 | ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs]; | |
279 | ||
176e1ab1 | 280 | spin_lock_init(&ring->fence_lock); |
d38ceaf9 AD |
281 | r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type); |
282 | if (r) { | |
283 | dev_err(adev->dev, "failed initializing fences (%d).\n", r); | |
284 | return r; | |
285 | } | |
286 | ||
a3f1cf35 CK |
287 | ring->ring_size = roundup_pow_of_two(max_dw * 4 * |
288 | amdgpu_sched_hw_submission); | |
d38ceaf9 AD |
289 | ring->align_mask = align_mask; |
290 | ring->nop = nop; | |
291 | ring->type = ring_type; | |
292 | ||
293 | /* Allocate ring buffer */ | |
294 | if (ring->ring_obj == NULL) { | |
295 | r = amdgpu_bo_create(adev, ring->ring_size, PAGE_SIZE, true, | |
296 | AMDGPU_GEM_DOMAIN_GTT, 0, | |
72d7668b | 297 | NULL, NULL, &ring->ring_obj); |
d38ceaf9 AD |
298 | if (r) { |
299 | dev_err(adev->dev, "(%d) ring create failed\n", r); | |
300 | return r; | |
301 | } | |
302 | r = amdgpu_bo_reserve(ring->ring_obj, false); | |
303 | if (unlikely(r != 0)) | |
304 | return r; | |
305 | r = amdgpu_bo_pin(ring->ring_obj, AMDGPU_GEM_DOMAIN_GTT, | |
306 | &ring->gpu_addr); | |
307 | if (r) { | |
308 | amdgpu_bo_unreserve(ring->ring_obj); | |
309 | dev_err(adev->dev, "(%d) ring pin failed\n", r); | |
310 | return r; | |
311 | } | |
312 | r = amdgpu_bo_kmap(ring->ring_obj, | |
313 | (void **)&ring->ring); | |
cc7d8c79 ML |
314 | |
315 | memset((void *)ring->ring, 0, ring->ring_size); | |
316 | ||
d38ceaf9 AD |
317 | amdgpu_bo_unreserve(ring->ring_obj); |
318 | if (r) { | |
319 | dev_err(adev->dev, "(%d) ring map failed\n", r); | |
320 | return r; | |
321 | } | |
322 | } | |
323 | ring->ptr_mask = (ring->ring_size / 4) - 1; | |
a3f1cf35 | 324 | ring->max_dw = max_dw; |
d38ceaf9 AD |
325 | |
326 | if (amdgpu_debugfs_ring_init(adev, ring)) { | |
327 | DRM_ERROR("Failed to register debugfs file for rings !\n"); | |
328 | } | |
d38ceaf9 AD |
329 | return 0; |
330 | } | |
331 | ||
332 | /** | |
333 | * amdgpu_ring_fini - tear down the driver ring struct. | |
334 | * | |
335 | * @adev: amdgpu_device pointer | |
336 | * @ring: amdgpu_ring structure holding ring information | |
337 | * | |
338 | * Tear down the driver information for the selected ring (all asics). | |
339 | */ | |
340 | void amdgpu_ring_fini(struct amdgpu_ring *ring) | |
341 | { | |
342 | int r; | |
343 | struct amdgpu_bo *ring_obj; | |
344 | ||
d38ceaf9 AD |
345 | ring_obj = ring->ring_obj; |
346 | ring->ready = false; | |
347 | ring->ring = NULL; | |
348 | ring->ring_obj = NULL; | |
d38ceaf9 | 349 | |
67a6a504 | 350 | amdgpu_wb_free(ring->adev, ring->cond_exe_offs); |
d38ceaf9 AD |
351 | amdgpu_wb_free(ring->adev, ring->fence_offs); |
352 | amdgpu_wb_free(ring->adev, ring->rptr_offs); | |
353 | amdgpu_wb_free(ring->adev, ring->wptr_offs); | |
354 | amdgpu_wb_free(ring->adev, ring->next_rptr_offs); | |
355 | ||
356 | if (ring_obj) { | |
357 | r = amdgpu_bo_reserve(ring_obj, false); | |
358 | if (likely(r == 0)) { | |
359 | amdgpu_bo_kunmap(ring_obj); | |
360 | amdgpu_bo_unpin(ring_obj); | |
361 | amdgpu_bo_unreserve(ring_obj); | |
362 | } | |
363 | amdgpu_bo_unref(&ring_obj); | |
364 | } | |
365 | } | |
366 | ||
367 | /* | |
368 | * Debugfs info | |
369 | */ | |
370 | #if defined(CONFIG_DEBUG_FS) | |
371 | ||
4f4824b5 TSD |
372 | /* Layout of file is 12 bytes consisting of |
373 | * - rptr | |
374 | * - wptr | |
375 | * - driver's copy of wptr | |
376 | * | |
377 | * followed by n-words of ring data | |
378 | */ | |
379 | static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf, | |
380 | size_t size, loff_t *pos) | |
d38ceaf9 | 381 | { |
4f4824b5 TSD |
382 | struct amdgpu_ring *ring = (struct amdgpu_ring*)f->f_inode->i_private; |
383 | int r, i; | |
384 | uint32_t value, result, early[3]; | |
385 | ||
386 | if (*pos & 3) | |
387 | return -EINVAL; | |
388 | ||
389 | result = 0; | |
390 | ||
391 | if (*pos < 12) { | |
392 | early[0] = amdgpu_ring_get_rptr(ring); | |
393 | early[1] = amdgpu_ring_get_wptr(ring); | |
394 | early[2] = ring->wptr; | |
395 | for (i = *pos / 4; i < 3 && size; i++) { | |
396 | r = put_user(early[i], (uint32_t *)buf); | |
397 | if (r) | |
398 | return r; | |
399 | buf += 4; | |
400 | result += 4; | |
401 | size -= 4; | |
402 | *pos += 4; | |
403 | } | |
c7e6be23 | 404 | } |
4f4824b5 TSD |
405 | |
406 | while (size) { | |
407 | if (*pos >= (ring->ring_size + 12)) | |
408 | return result; | |
409 | ||
410 | value = ring->ring[(*pos - 12)/4]; | |
411 | r = put_user(value, (uint32_t*)buf); | |
412 | if (r) | |
413 | return r; | |
414 | buf += 4; | |
415 | result += 4; | |
416 | size -= 4; | |
417 | *pos += 4; | |
d38ceaf9 | 418 | } |
4f4824b5 TSD |
419 | |
420 | return result; | |
d38ceaf9 AD |
421 | } |
422 | ||
4f4824b5 TSD |
423 | static const struct file_operations amdgpu_debugfs_ring_fops = { |
424 | .owner = THIS_MODULE, | |
425 | .read = amdgpu_debugfs_ring_read, | |
426 | .llseek = default_llseek | |
427 | }; | |
d38ceaf9 AD |
428 | |
429 | #endif | |
430 | ||
771c8ec1 CK |
431 | static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev, |
432 | struct amdgpu_ring *ring) | |
d38ceaf9 AD |
433 | { |
434 | #if defined(CONFIG_DEBUG_FS) | |
4f4824b5 TSD |
435 | struct drm_minor *minor = adev->ddev->primary; |
436 | struct dentry *ent, *root = minor->debugfs_root; | |
437 | char name[32]; | |
d38ceaf9 | 438 | |
771c8ec1 | 439 | sprintf(name, "amdgpu_ring_%s", ring->name); |
771c8ec1 | 440 | |
4f4824b5 TSD |
441 | ent = debugfs_create_file(name, |
442 | S_IFREG | S_IRUGO, root, | |
443 | ring, &amdgpu_debugfs_ring_fops); | |
444 | if (IS_ERR(ent)) | |
445 | return PTR_ERR(ent); | |
446 | ||
447 | i_size_write(ent->d_inode, ring->ring_size + 12); | |
d38ceaf9 AD |
448 | #endif |
449 | return 0; | |
450 | } |