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[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c
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c030f2e4 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
f867723b 27#include <linux/uaccess.h>
7c6e68c7
AG		 28#include <linux/reboot.h>
29#include <linux/syscalls.h>
05adfd80 30#include <linux/pm_runtime.h>
dbf3850d 31#include <linux/list_sort.h>
f867723b 32
c030f2e4 33#include "amdgpu.h"
34#include "amdgpu_ras.h"
b404ae82 35#include "amdgpu_atomfirmware.h"
19744f5f 36#include "amdgpu_xgmi.h"
4e644fff 37#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
9af357bc 38#include "nbio_v4_3.h"
7692e1ee 39#include "nbio_v7_9.h"
f50160cf 40#include "atom.h"
25a2b22e 41#include "amdgpu_reset.h"
4e2965bd 42#include "amdgpu_psp.h"
25a2b22e 43
12b2cab7
MJ		 44#ifdef CONFIG_X86_MCE_AMD
45#include <asm/mce.h>
c030f2e4 46
12b2cab7
MJ		 47static bool notifier_registered;
48#endif
eb0c3cd4
GC		 49static const char *RAS_FS_NAME = "ras";
50
c030f2e4 51const char *ras_error_string[] = {
52 "none",
53 "parity",
54 "single_correctable",
55 "multi_uncorrectable",
56 "poison",
57};
58
59const char *ras_block_string[] = {
60 "umc",
61 "sdma",
62 "gfx",
63 "mmhub",
64 "athub",
65 "pcie_bif",
66 "hdp",
67 "xgmi_wafl",
68 "df",
69 "smn",
70 "sem",
71 "mp0",
72 "mp1",
73 "fuse",
640ae42e 74 "mca",
a3d63c62
MZZ		 75 "vcn",
76 "jpeg",
7ed97155
YW		 77 "ih",
78 "mpio",
c030f2e4 79};
80
640ae42e
JC		 81const char *ras_mca_block_string[] = {
82 "mca_mp0",
83 "mca_mp1",
84 "mca_mpio",
85 "mca_iohc",
86};
87
d5e8ff5f 88struct amdgpu_ras_block_list {
89 /* ras block link */
90 struct list_head node;
91
92 struct amdgpu_ras_block_object *ras_obj;
93};
94
640ae42e
JC		 95const char *get_ras_block_str(struct ras_common_if *ras_block)
96{
97 if (!ras_block)
98 return "NULL";
99
7ed97155
YW		 100 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT ||
101 ras_block->block >= ARRAY_SIZE(ras_block_string))
640ae42e
JC		 102 return "OUT OF RANGE";
103
104 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
105 return ras_mca_block_string[ras_block->sub_block_index];
106
107 return ras_block_string[ras_block->block];
108}
109
954ea6aa 110#define ras_block_str(_BLOCK_) \
111 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
8b0fb0e9 112
c030f2e4 113#define ras_err_str(i) (ras_error_string[ffs(i)])
c030f2e4 114
108c6a63 115#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
116
7cdc2ee3
TZ		 117/* inject address is 52 bits */
118#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
119
e4e6a589
LT		 120/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
121#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
c84d4670 122
6c23f3d1
YC		 123#define MAX_UMC_POISON_POLLING_TIME_ASYNC 100 //ms
124
2cf8e50e
YC		 125#define AMDGPU_RAS_RETIRE_PAGE_INTERVAL 100 //ms
126
52dd95f2
GC		 127enum amdgpu_ras_retire_page_reservation {
128 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
129 AMDGPU_RAS_RETIRE_PAGE_PENDING,
130 AMDGPU_RAS_RETIRE_PAGE_FAULT,
131};
7c6e68c7
AG		 132
133atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
134
676deb38
DL		 135static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
136 uint64_t addr);
6e4be987
TZ		 137static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
138 uint64_t addr);
12b2cab7 139#ifdef CONFIG_X86_MCE_AMD
91a1a52d
MJ		 140static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
141struct mce_notifier_adev_list {
142 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
143 int num_gpu;
144};
145static struct mce_notifier_adev_list mce_adev_list;
12b2cab7 146#endif
6e4be987 147
61380faa
JC		 148void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
149{
a9d82d2f 150 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 151 amdgpu_ras_get_context(adev)->error_query_ready = ready;
152}
153
f3167919 154static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
61380faa 155{
a9d82d2f 156 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 157 return amdgpu_ras_get_context(adev)->error_query_ready;
158
159 return false;
160}
161
cbb8f989
JC		 162static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
163{
5b1270be 164 struct ras_err_data err_data;
cbb8f989 165 struct eeprom_table_record err_rec;
5b1270be 166 int ret;
cbb8f989
JC		 167
168 if ((address >= adev->gmc.mc_vram_size) ||
169 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
170 dev_warn(adev->dev,
171 "RAS WARN: input address 0x%llx is invalid.\n",
172 address);
173 return -EINVAL;
174 }
175
176 if (amdgpu_ras_check_bad_page(adev, address)) {
177 dev_warn(adev->dev,
80b0cd0f 178 "RAS WARN: 0x%llx has already been marked as bad page!\n",
cbb8f989
JC		 179 address);
180 return 0;
181 }
182
5b1270be
YW		 183 ret = amdgpu_ras_error_data_init(&err_data);
184 if (ret)
185 return ret;
186
cbb8f989 187 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
cbb8f989 188 err_data.err_addr = &err_rec;
71344a71 189 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
cbb8f989
JC		 190
191 if (amdgpu_bad_page_threshold != 0) {
192 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
193 err_data.err_addr_cnt);
4d33e0f1 194 amdgpu_ras_save_bad_pages(adev, NULL);
cbb8f989
JC		 195 }
196
5b1270be
YW		 197 amdgpu_ras_error_data_fini(&err_data);
198
cbb8f989
JC		 199 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
200 dev_warn(adev->dev, "Clear EEPROM:\n");
201 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
202
203 return 0;
204}
205
c030f2e4 206static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
207 size_t size, loff_t *pos)
208{
209 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
210 struct ras_query_if info = {
211 .head = obj->head,
212 };
213 ssize_t s;
214 char val[128];
215
761d86d3 216 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 217 return -EINVAL;
218
2a460963 219 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
4e8303cf
LL		 220 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
221 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
2a460963
CL		 222 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
223 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
224 }
225
c030f2e4 226 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
227 "ue", info.ue_count,
228 "ce", info.ce_count);
229 if (*pos >= s)
230 return 0;
231
232 s -= *pos;
233 s = min_t(u64, s, size);
234
235
236 if (copy_to_user(buf, &val[*pos], s))
237 return -EINVAL;
238
239 *pos += s;
240
241 return s;
242}
243
c030f2e4 244static const struct file_operations amdgpu_ras_debugfs_ops = {
245 .owner = THIS_MODULE,
246 .read = amdgpu_ras_debugfs_read,
190211ab 247 .write = NULL,
c030f2e4 248 .llseek = default_llseek
249};
250
96ebb307 251static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
252{
253 int i;
254
255 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
256 *block_id = i;
640ae42e 257 if (strcmp(name, ras_block_string[i]) == 0)
96ebb307 258 return 0;
259 }
260 return -EINVAL;
261}
262
263static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
264 const char __user *buf, size_t size,
265 loff_t *pos, struct ras_debug_if *data)
266{
267 ssize_t s = min_t(u64, 64, size);
268 char str[65];
269 char block_name[33];
270 char err[9] = "ue";
271 int op = -1;
272 int block_id;
44494f96 273 uint32_t sub_block;
96ebb307 274 u64 address, value;
2c22ed0b
TZ		 275 /* default value is 0 if the mask is not set by user */
276 u32 instance_mask = 0;
96ebb307 277
278 if (*pos)
279 return -EINVAL;
280 *pos = size;
281
282 memset(str, 0, sizeof(str));
283 memset(data, 0, sizeof(*data));
284
285 if (copy_from_user(str, buf, s))
286 return -EINVAL;
287
288 if (sscanf(str, "disable %32s", block_name) == 1)
289 op = 0;
290 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
291 op = 1;
292 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
293 op = 2;
6df23f4c 294 else if (strstr(str, "retire_page") != NULL)
cbb8f989 295 op = 3;
b076296b 296 else if (str[0] && str[1] && str[2] && str[3])
96ebb307 297 /* ascii string, but commands are not matched. */
298 return -EINVAL;
299
300 if (op != -1) {
cbb8f989 301 if (op == 3) {
546aa546
LT		 302 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
303 sscanf(str, "%*s %llu", &address) != 1)
6cb7a1d4 304 return -EINVAL;
cbb8f989
JC		 305
306 data->op = op;
307 data->inject.address = address;
308
309 return 0;
310 }
311
96ebb307 312 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
313 return -EINVAL;
314
315 data->head.block = block_id;
fb1e9171 316 /* only ue, ce and poison errors are supported */
e1063493
TZ		 317 if (!memcmp("ue", err, 2))
318 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
319 else if (!memcmp("ce", err, 2))
320 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
fb1e9171
CL		 321 else if (!memcmp("poison", err, 6))
322 data->head.type = AMDGPU_RAS_ERROR__POISON;
e1063493
TZ		 323 else
324 return -EINVAL;
325
96ebb307 326 data->op = op;
327
328 if (op == 2) {
2c22ed0b
TZ		 329 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
330 &sub_block, &address, &value, &instance_mask) != 4 &&
331 sscanf(str, "%*s %*s %*s %u %llu %llu %u",
332 &sub_block, &address, &value, &instance_mask) != 4 &&
333 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
546aa546
LT		 334 &sub_block, &address, &value) != 3 &&
335 sscanf(str, "%*s %*s %*s %u %llu %llu",
6cb7a1d4
LT		 336 &sub_block, &address, &value) != 3)
337 return -EINVAL;
44494f96 338 data->head.sub_block_index = sub_block;
96ebb307 339 data->inject.address = address;
340 data->inject.value = value;
2c22ed0b 341 data->inject.instance_mask = instance_mask;
96ebb307 342 }
343 } else {
73aa8e1a 344 if (size < sizeof(*data))
96ebb307 345 return -EINVAL;
346
347 if (copy_from_user(data, buf, sizeof(*data)))
348 return -EINVAL;
349 }
350
351 return 0;
352}
7c6e68c7 353
f464c5dd
TZ		 354static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
355 struct ras_debug_if *data)
356{
357 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
358 uint32_t mask, inst_mask = data->inject.instance_mask;
359
360 /* no need to set instance mask if there is only one instance */
361 if (num_xcc <= 1 && inst_mask) {
362 data->inject.instance_mask = 0;
363 dev_dbg(adev->dev,
364 "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
365 inst_mask);
366
367 return;
368 }
369
370 switch (data->head.block) {
371 case AMDGPU_RAS_BLOCK__GFX:
372 mask = GENMASK(num_xcc - 1, 0);
373 break;
374 case AMDGPU_RAS_BLOCK__SDMA:
375 mask = GENMASK(adev->sdma.num_instances - 1, 0);
376 break;
e3959cb5
SY		 377 case AMDGPU_RAS_BLOCK__VCN:
378 case AMDGPU_RAS_BLOCK__JPEG:
379 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
380 break;
f464c5dd 381 default:
e3959cb5 382 mask = inst_mask;
f464c5dd
TZ		 383 break;
384 }
385
386 /* remove invalid bits in instance mask */
387 data->inject.instance_mask &= mask;
388 if (inst_mask != data->inject.instance_mask)
389 dev_dbg(adev->dev,
390 "Adjust RAS inject mask 0x%x to 0x%x\n",
391 inst_mask, data->inject.instance_mask);
392}
393
74abc221
TSD		 394/**
395 * DOC: AMDGPU RAS debugfs control interface
36ea1bd2 396 *
737c375b 397 * The control interface accepts struct ras_debug_if which has two members.
36ea1bd2 398 *
399 * First member: ras_debug_if::head or ras_debug_if::inject.
96ebb307 400 *
401 * head is used to indicate which IP block will be under control.
36ea1bd2 402 *
403 * head has four members, they are block, type, sub_block_index, name.
404 * block: which IP will be under control.
405 * type: what kind of error will be enabled/disabled/injected.
406 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
407 * name: the name of IP.
408 *
2c22ed0b 409 * inject has three more members than head, they are address, value and mask.
36ea1bd2 410 * As their names indicate, inject operation will write the
411 * value to the address.
412 *
ef177d11 413 * The second member: struct ras_debug_if::op.
c688a06b 414 * It has three kinds of operations.
879e723d
AZ		 415 *
416 * - 0: disable RAS on the block. Take ::head as its data.
417 * - 1: enable RAS on the block. Take ::head as its data.
418 * - 2: inject errors on the block. Take ::inject as its data.
36ea1bd2 419 *
96ebb307 420 * How to use the interface?
ef177d11 421 *
737c375b 422 * In a program
ef177d11 423 *
737c375b
LT		 424 * Copy the struct ras_debug_if in your code and initialize it.
425 * Write the struct to the control interface.
ef177d11 426 *
737c375b 427 * From shell
96ebb307 428 *
879e723d
AZ		 429 * .. code-block:: bash
430 *
737c375b
LT		 431 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
432 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
2c22ed0b 433 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
879e723d 434 *
737c375b 435 * Where N, is the card which you want to affect.
ef177d11 436 *
737c375b
LT		 437 * "disable" requires only the block.
438 * "enable" requires the block and error type.
439 * "inject" requires the block, error type, address, and value.
c666bbf0 440 *
737c375b 441 * The block is one of: umc, sdma, gfx, etc.
879e723d 442 * see ras_block_string[] for details
c666bbf0 443 *
fb1e9171 444 * The error type is one of: ue, ce and poison where,
737c375b
LT		 445 * ue is multi-uncorrectable
446 * ce is single-correctable
fb1e9171 447 * poison is poison
c666bbf0 448 *
737c375b
LT		 449 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
450 * The address and value are hexadecimal numbers, leading 0x is optional.
2c22ed0b 451 * The mask means instance mask, is optional, default value is 0x1.
879e723d 452 *
737c375b 453 * For instance,
879e723d
AZ		 454 *
455 * .. code-block:: bash
96ebb307 456 *
44494f96 457 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
2c22ed0b 458 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
96ebb307 459 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
460 *
737c375b 461 * How to check the result of the operation?
36ea1bd2 462 *
737c375b 463 * To check disable/enable, see "ras" features at,
36ea1bd2 464 * /sys/class/drm/card[0/1/2...]/device/ras/features
465 *
737c375b
LT		 466 * To check inject, see the corresponding error count at,
467 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
36ea1bd2 468 *
879e723d 469 * .. note::
ef177d11 470 * Operations are only allowed on blocks which are supported.
737c375b 471 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
ef177d11
AD		 472 * to see which blocks support RAS on a particular asic.
473 *
36ea1bd2 474 */
cf696091
LT		 475static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
476 const char __user *buf,
477 size_t size, loff_t *pos)
36ea1bd2 478{
479 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
480 struct ras_debug_if data;
481 int ret = 0;
482
61380faa 483 if (!amdgpu_ras_get_error_query_ready(adev)) {
6952e99c
GC		 484 dev_warn(adev->dev, "RAS WARN: error injection "
485 "currently inaccessible\n");
43c4d576
JC		 486 return size;
487 }
488
96ebb307 489 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
490 if (ret)
cf696091 491 return ret;
36ea1bd2 492
80b0cd0f 493 if (data.op == 3) {
cbb8f989 494 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
80b0cd0f 495 if (!ret)
cbb8f989
JC		 496 return size;
497 else
498 return ret;
499 }
500
36ea1bd2 501 if (!amdgpu_ras_is_supported(adev, data.head.block))
502 return -EINVAL;
503
504 switch (data.op) {
505 case 0:
506 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
507 break;
508 case 1:
509 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
510 break;
511 case 2:
43aedbf4
SY		 512 if ((data.inject.address >= adev->gmc.mc_vram_size &&
513 adev->gmc.mc_vram_size) ||
7cdc2ee3 514 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
b0d4783a
GC		 515 dev_warn(adev->dev, "RAS WARN: input address "
516 "0x%llx is invalid.",
517 data.inject.address);
7cdc2ee3
TZ		 518 ret = -EINVAL;
519 break;
520 }
521
6e4be987
TZ		 522 /* umc ce/ue error injection for a bad page is not allowed */
523 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
524 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
c65b0805
LT		 525 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
526 "already been marked as bad!\n",
527 data.inject.address);
6e4be987
TZ		 528 break;
529 }
530
f464c5dd
TZ		 531 amdgpu_ras_instance_mask_check(adev, &data);
532
7cdc2ee3 533 /* data.inject.address is offset instead of absolute gpu address */
36ea1bd2 534 ret = amdgpu_ras_error_inject(adev, &data.inject);
535 break;
96ebb307 536 default:
537 ret = -EINVAL;
538 break;
374bf7bd 539 }
36ea1bd2 540
541 if (ret)
79c04621 542 return ret;
36ea1bd2 543
544 return size;
545}
546
084fe13b
AG		 547/**
548 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
549 *
f77c7109 550 * Some boards contain an EEPROM which is used to persistently store a list of
ef177d11 551 * bad pages which experiences ECC errors in vram. This interface provides
f77c7109
AD		 552 * a way to reset the EEPROM, e.g., after testing error injection.
553 *
554 * Usage:
555 *
556 * .. code-block:: bash
557 *
558 * echo 1 > ../ras/ras_eeprom_reset
559 *
560 * will reset EEPROM table to 0 entries.
561 *
084fe13b 562 */
cf696091
LT		 563static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
564 const char __user *buf,
565 size_t size, loff_t *pos)
084fe13b 566{
bf0b91b7
GC		 567 struct amdgpu_device *adev =
568 (struct amdgpu_device *)file_inode(f)->i_private;
084fe13b
AG		 569 int ret;
570
bf0b91b7 571 ret = amdgpu_ras_eeprom_reset_table(
cf696091 572 &(amdgpu_ras_get_context(adev)->eeprom_control));
084fe13b 573
63d4c081 574 if (!ret) {
cf696091
LT		 575 /* Something was written to EEPROM.
576 */
bf0b91b7
GC		 577 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
578 return size;
579 } else {
cf696091 580 return ret;
bf0b91b7 581 }
084fe13b
AG		 582}
583
36ea1bd2 584static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
585 .owner = THIS_MODULE,
586 .read = NULL,
587 .write = amdgpu_ras_debugfs_ctrl_write,
588 .llseek = default_llseek
589};
590
084fe13b
AG		 591static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
592 .owner = THIS_MODULE,
593 .read = NULL,
594 .write = amdgpu_ras_debugfs_eeprom_write,
595 .llseek = default_llseek
596};
597
f77c7109
AD		 598/**
599 * DOC: AMDGPU RAS sysfs Error Count Interface
600 *
ef177d11 601 * It allows the user to read the error count for each IP block on the gpu through
f77c7109
AD		 602 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
603 *
604 * It outputs the multiple lines which report the uncorrected (ue) and corrected
605 * (ce) error counts.
606 *
607 * The format of one line is below,
608 *
609 * [ce|ue]: count
610 *
611 * Example:
612 *
613 * .. code-block:: bash
614 *
615 * ue: 0
616 * ce: 1
617 *
618 */
c030f2e4 619static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
620 struct device_attribute *attr, char *buf)
621{
622 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
623 struct ras_query_if info = {
624 .head = obj->head,
625 };
626
61380faa 627 if (!amdgpu_ras_get_error_query_ready(obj->adev))
36000c7a 628 return sysfs_emit(buf, "Query currently inaccessible\n");
43c4d576 629
761d86d3 630 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 631 return -EINVAL;
632
4e8303cf
LL		 633 if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
634 amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
1f0d8e37 635 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
2a460963 636 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
1f0d8e37
MJ		 637 }
638
2c7a1560
SY		 639 if (info.head.block == AMDGPU_RAS_BLOCK__UMC)
640 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,
641 "ce", info.ce_count, "de", info.de_count);
642 else
643 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
644 "ce", info.ce_count);
c030f2e4 645}
646
647/* obj begin */
648
649#define get_obj(obj) do { (obj)->use++; } while (0)
650#define alive_obj(obj) ((obj)->use)
651
652static inline void put_obj(struct ras_manager *obj)
653{
ec3e0a91 654 if (obj && (--obj->use == 0)) {
c030f2e4 655 list_del(&obj->node);
ec3e0a91
YW		 656 amdgpu_ras_error_data_fini(&obj->err_data);
657 }
658
f0872686 659 if (obj && (obj->use < 0))
640ae42e 660 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
c030f2e4 661}
662
663/* make one obj and return it. */
664static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
665 struct ras_common_if *head)
666{
667 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
668 struct ras_manager *obj;
669
8ab0d6f0 670 if (!adev->ras_enabled || !con)
c030f2e4 671 return NULL;
672
673 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
674 return NULL;
675
640ae42e
JC		 676 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
677 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
678 return NULL;
679
680 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
681 } else
682 obj = &con->objs[head->block];
683
c030f2e4 684 /* already exist. return obj? */
685 if (alive_obj(obj))
686 return NULL;
687
ec3e0a91
YW		 688 if (amdgpu_ras_error_data_init(&obj->err_data))
689 return NULL;
690
c030f2e4 691 obj->head = *head;
692 obj->adev = adev;
693 list_add(&obj->node, &con->head);
694 get_obj(obj);
695
696 return obj;
697}
698
699/* return an obj equal to head, or the first when head is NULL */
f2a79be1 700struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
c030f2e4 701 struct ras_common_if *head)
702{
703 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
704 struct ras_manager *obj;
705 int i;
706
8ab0d6f0 707 if (!adev->ras_enabled || !con)
c030f2e4 708 return NULL;
709
710 if (head) {
711 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
712 return NULL;
713
640ae42e
JC		 714 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
715 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
716 return NULL;
717
718 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
719 } else
720 obj = &con->objs[head->block];
c030f2e4 721
640ae42e 722 if (alive_obj(obj))
c030f2e4 723 return obj;
c030f2e4 724 } else {
640ae42e 725 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
c030f2e4 726 obj = &con->objs[i];
640ae42e 727 if (alive_obj(obj))
c030f2e4 728 return obj;
c030f2e4 729 }
730 }
731
732 return NULL;
733}
734/* obj end */
735
736/* feature ctl begin */
737static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
e509965e 738 struct ras_common_if *head)
c030f2e4 739{
8ab0d6f0 740 return adev->ras_hw_enabled & BIT(head->block);
c030f2e4 741}
742
743static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
744 struct ras_common_if *head)
745{
746 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
747
748 return con->features & BIT(head->block);
749}
750
751/*
752 * if obj is not created, then create one.
753 * set feature enable flag.
754 */
755static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
756 struct ras_common_if *head, int enable)
757{
758 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
759 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
760
5caf466a 761 /* If hardware does not support ras, then do not create obj.
762 * But if hardware support ras, we can create the obj.
763 * Ras framework checks con->hw_supported to see if it need do
764 * corresponding initialization.
765 * IP checks con->support to see if it need disable ras.
766 */
c030f2e4 767 if (!amdgpu_ras_is_feature_allowed(adev, head))
768 return 0;
c030f2e4 769
770 if (enable) {
771 if (!obj) {
772 obj = amdgpu_ras_create_obj(adev, head);
773 if (!obj)
774 return -EINVAL;
775 } else {
776 /* In case we create obj somewhere else */
777 get_obj(obj);
778 }
779 con->features |= BIT(head->block);
780 } else {
781 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
19d0dfda 782 con->features &= ~BIT(head->block);
c030f2e4 783 put_obj(obj);
784 }
785 }
786
787 return 0;
788}
789
790/* wrapper of psp_ras_enable_features */
791int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
792 struct ras_common_if *head, bool enable)
793{
794 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
7fcffecf 795 union ta_ras_cmd_input *info;
bf7aa8be 796 int ret;
c030f2e4 797
798 if (!con)
799 return -EINVAL;
800
ec70578c
HZ		 801 /* For non-gfx ip, do not enable ras feature if it is not allowed */
802 /* For gfx ip, regardless of feature support status, */
803 /* Force issue enable or disable ras feature commands */
804 if (head->block != AMDGPU_RAS_BLOCK__GFX &&
6fc9d92c 805 !amdgpu_ras_is_feature_allowed(adev, head))
bf7aa8be 806 return 0;
6fc9d92c
HZ		 807
808 /* Only enable gfx ras feature from host side */
809 if (head->block == AMDGPU_RAS_BLOCK__GFX &&
810 !amdgpu_sriov_vf(adev) &&
811 !amdgpu_ras_intr_triggered()) {
26093ce1
SY		 812 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
813 if (!info)
814 return -ENOMEM;
815
816 if (!enable) {
817 info->disable_features = (struct ta_ras_disable_features_input) {
818 .block_id = amdgpu_ras_block_to_ta(head->block),
819 .error_type = amdgpu_ras_error_to_ta(head->type),
820 };
821 } else {
822 info->enable_features = (struct ta_ras_enable_features_input) {
823 .block_id = amdgpu_ras_block_to_ta(head->block),
824 .error_type = amdgpu_ras_error_to_ta(head->type),
825 };
826 }
c030f2e4 827
7fcffecf 828 ret = psp_ras_enable_features(&adev->psp, info, enable);
bff77e86 829 if (ret) {
e4348849 830 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
011907fd 831 enable ? "enable":"disable",
640ae42e 832 get_ras_block_str(head),
e4348849 833 amdgpu_ras_is_poison_mode_supported(adev), ret);
5838f74c 834 kfree(info);
bf7aa8be 835 return ret;
bff77e86 836 }
bf7aa8be
HZ		 837
838 kfree(info);
c030f2e4 839 }
840
841 /* setup the obj */
842 __amdgpu_ras_feature_enable(adev, head, enable);
bf7aa8be
HZ		 843
844 return 0;
c030f2e4 845}
846
77de502b 847/* Only used in device probe stage and called only once. */
848int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
849 struct ras_common_if *head, bool enable)
850{
851 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
852 int ret;
853
854 if (!con)
855 return -EINVAL;
856
857 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
7af23ebe 858 if (enable) {
859 /* There is no harm to issue a ras TA cmd regardless of
860 * the currecnt ras state.
861 * If current state == target state, it will do nothing
862 * But sometimes it requests driver to reset and repost
863 * with error code -EAGAIN.
864 */
865 ret = amdgpu_ras_feature_enable(adev, head, 1);
866 /* With old ras TA, we might fail to enable ras.
867 * Log it and just setup the object.
868 * TODO need remove this WA in the future.
869 */
870 if (ret == -EINVAL) {
871 ret = __amdgpu_ras_feature_enable(adev, head, 1);
872 if (!ret)
6952e99c
GC		 873 dev_info(adev->dev,
874 "RAS INFO: %s setup object\n",
640ae42e 875 get_ras_block_str(head));
7af23ebe 876 }
877 } else {
878 /* setup the object then issue a ras TA disable cmd.*/
879 ret = __amdgpu_ras_feature_enable(adev, head, 1);
880 if (ret)
881 return ret;
77de502b 882
970fd197
SY		 883 /* gfx block ras dsiable cmd must send to ras-ta */
884 if (head->block == AMDGPU_RAS_BLOCK__GFX)
885 con->features |= BIT(head->block);
886
77de502b 887 ret = amdgpu_ras_feature_enable(adev, head, 0);
19d0dfda
SY		 888
889 /* clean gfx block ras features flag */
8ab0d6f0 890 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
19d0dfda 891 con->features &= ~BIT(head->block);
7af23ebe 892 }
77de502b 893 } else
894 ret = amdgpu_ras_feature_enable(adev, head, enable);
895
896 return ret;
897}
898
c030f2e4 899static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
900 bool bypass)
901{
902 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
903 struct ras_manager *obj, *tmp;
904
905 list_for_each_entry_safe(obj, tmp, &con->head, node) {
906 /* bypass psp.
907 * aka just release the obj and corresponding flags
908 */
909 if (bypass) {
910 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
911 break;
912 } else {
913 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
914 break;
915 }
289d513b 916 }
c030f2e4 917
918 return con->features;
919}
920
921static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
922 bool bypass)
923{
924 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c030f2e4 925 int i;
640ae42e 926 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
c030f2e4 927
640ae42e 928 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
c030f2e4 929 struct ras_common_if head = {
930 .block = i,
191051a1 931 .type = default_ras_type,
c030f2e4 932 .sub_block_index = 0,
933 };
640ae42e
JC		 934
935 if (i == AMDGPU_RAS_BLOCK__MCA)
936 continue;
937
938 if (bypass) {
939 /*
940 * bypass psp. vbios enable ras for us.
941 * so just create the obj
942 */
943 if (__amdgpu_ras_feature_enable(adev, &head, 1))
944 break;
945 } else {
946 if (amdgpu_ras_feature_enable(adev, &head, 1))
947 break;
948 }
949 }
950
951 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
952 struct ras_common_if head = {
953 .block = AMDGPU_RAS_BLOCK__MCA,
954 .type = default_ras_type,
955 .sub_block_index = i,
956 };
957
c030f2e4 958 if (bypass) {
959 /*
960 * bypass psp. vbios enable ras for us.
961 * so just create the obj
962 */
963 if (__amdgpu_ras_feature_enable(adev, &head, 1))
964 break;
965 } else {
966 if (amdgpu_ras_feature_enable(adev, &head, 1))
967 break;
968 }
289d513b 969 }
c030f2e4 970
971 return con->features;
972}
973/* feature ctl end */
974
e3d833f4 975static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
976 enum amdgpu_ras_block block)
6492e1b0 977{
b6efdb02 978 if (!block_obj)
6492e1b0 979 return -EINVAL;
980
bdb3489c 981 if (block_obj->ras_comm.block == block)
6492e1b0 982 return 0;
640ae42e 983
6492e1b0 984 return -EINVAL;
985}
986
b6efdb02 987static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
6492e1b0 988 enum amdgpu_ras_block block, uint32_t sub_block_index)
640ae42e 989{
d5e8ff5f 990 struct amdgpu_ras_block_list *node, *tmp;
991 struct amdgpu_ras_block_object *obj;
6492e1b0 992
993 if (block >= AMDGPU_RAS_BLOCK__LAST)
994 return NULL;
995
d5e8ff5f 996 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
997 if (!node->ras_obj) {
998 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
999 continue;
1000 }
1001
1002 obj = node->ras_obj;
6492e1b0 1003 if (obj->ras_block_match) {
1004 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
1005 return obj;
1006 } else {
1007 if (amdgpu_ras_block_match_default(obj, block) == 0)
1008 return obj;
1009 }
640ae42e 1010 }
6492e1b0 1011
1012 return NULL;
640ae42e
JC		 1013}
1014
fdcb279d
SY		 1015static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
1016{
1017 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1018 int ret = 0;
1019
1020 /*
1021 * choosing right query method according to
1022 * whether smu support query error information
1023 */
bc143d8b 1024 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
fdcb279d 1025 if (ret == -EOPNOTSUPP) {
efe17d5a 1026 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1027 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1028 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
fdcb279d
SY		 1029
1030 /* umc query_ras_error_address is also responsible for clearing
1031 * error status
1032 */
efe17d5a 1033 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1034 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1035 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
fdcb279d 1036 } else if (!ret) {
efe17d5a 1037 if (adev->umc.ras &&
1038 adev->umc.ras->ecc_info_query_ras_error_count)
1039 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
fdcb279d 1040
efe17d5a 1041 if (adev->umc.ras &&
1042 adev->umc.ras->ecc_info_query_ras_error_address)
1043 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
fdcb279d
SY		 1044 }
1045}
1046
5b1270be 1047static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev,
ec3e0a91 1048 struct ras_manager *ras_mgr,
5b1270be 1049 struct ras_err_data *err_data,
9dc57c2a 1050 struct ras_query_context *qctx,
ec3e0a91 1051 const char *blk_name,
46e2231c
CL		 1052 bool is_ue,
1053 bool is_de)
5b1270be 1054{
5b1270be
YW		 1055 struct amdgpu_smuio_mcm_config_info *mcm_info;
1056 struct ras_err_node *err_node;
1057 struct ras_err_info *err_info;
9dc57c2a 1058 u64 event_id = qctx->event_id;
5b1270be 1059
ec3e0a91
YW		 1060 if (is_ue) {
1061 for_each_ras_error(err_node, err_data) {
1062 err_info = &err_node->err_info;
1063 mcm_info = &err_info->mcm_info;
1064 if (err_info->ue_count) {
9dc57c2a
YW		 1065 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1066 "%lld new uncorrectable hardware errors detected in %s block\n",
1067 mcm_info->socket_id,
1068 mcm_info->die_id,
1069 err_info->ue_count,
1070 blk_name);
ec3e0a91
YW		 1071 }
1072 }
1073
1074 for_each_ras_error(err_node, &ras_mgr->err_data) {
1075 err_info = &err_node->err_info;
1076 mcm_info = &err_info->mcm_info;
9dc57c2a
YW		 1077 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1078 "%lld uncorrectable hardware errors detected in total in %s block\n",
1079 mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name);
ec3e0a91
YW		 1080 }
1081
1082 } else {
46e2231c
CL		 1083 if (is_de) {
1084 for_each_ras_error(err_node, err_data) {
1085 err_info = &err_node->err_info;
1086 mcm_info = &err_info->mcm_info;
1087 if (err_info->de_count) {
9dc57c2a
YW		 1088 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1089 "%lld new deferred hardware errors detected in %s block\n",
1090 mcm_info->socket_id,
1091 mcm_info->die_id,
1092 err_info->de_count,
1093 blk_name);
46e2231c
CL		 1094 }
1095 }
1096
1097 for_each_ras_error(err_node, &ras_mgr->err_data) {
1098 err_info = &err_node->err_info;
1099 mcm_info = &err_info->mcm_info;
9dc57c2a
YW		 1100 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1101 "%lld deferred hardware errors detected in total in %s block\n",
1102 mcm_info->socket_id, mcm_info->die_id,
1103 err_info->de_count, blk_name);
46e2231c
CL		 1104 }
1105 } else {
1106 for_each_ras_error(err_node, err_data) {
1107 err_info = &err_node->err_info;
1108 mcm_info = &err_info->mcm_info;
1109 if (err_info->ce_count) {
9dc57c2a
YW		 1110 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1111 "%lld new correctable hardware errors detected in %s block\n",
1112 mcm_info->socket_id,
1113 mcm_info->die_id,
1114 err_info->ce_count,
1115 blk_name);
46e2231c 1116 }
ec3e0a91 1117 }
ec3e0a91 1118
46e2231c
CL		 1119 for_each_ras_error(err_node, &ras_mgr->err_data) {
1120 err_info = &err_node->err_info;
1121 mcm_info = &err_info->mcm_info;
9dc57c2a
YW		 1122 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d, "
1123 "%lld correctable hardware errors detected in total in %s block\n",
1124 mcm_info->socket_id, mcm_info->die_id,
1125 err_info->ce_count, blk_name);
46e2231c 1126 }
5b1270be
YW		 1127 }
1128 }
1129}
1130
ec3e0a91
YW		 1131static inline bool err_data_has_source_info(struct ras_err_data *data)
1132{
1133 return !list_empty(&data->err_node_list);
1134}
1135
5b1270be
YW		 1136static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev,
1137 struct ras_query_if *query_if,
9dc57c2a
YW		 1138 struct ras_err_data *err_data,
1139 struct ras_query_context *qctx)
5b1270be
YW		 1140{
1141 struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head);
1142 const char *blk_name = get_ras_block_str(&query_if->head);
9dc57c2a 1143 u64 event_id = qctx->event_id;
5b1270be
YW		 1144
1145 if (err_data->ce_count) {
ec3e0a91 1146 if (err_data_has_source_info(err_data)) {
9dc57c2a 1147 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,
46e2231c 1148 blk_name, false, false);
5b1270be
YW		 1149 } else if (!adev->aid_mask &&
1150 adev->smuio.funcs &&
1151 adev->smuio.funcs->get_socket_id &&
1152 adev->smuio.funcs->get_die_id) {
9dc57c2a
YW		 1153 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "
1154 "%ld correctable hardware errors "
1155 "detected in %s block\n",
1156 adev->smuio.funcs->get_socket_id(adev),
1157 adev->smuio.funcs->get_die_id(adev),
1158 ras_mgr->err_data.ce_count,
1159 blk_name);
5b1270be 1160 } else {
9dc57c2a
YW		 1161 RAS_EVENT_LOG(adev, event_id, "%ld correctable hardware errors "
1162 "detected in %s block\n",
1163 ras_mgr->err_data.ce_count,
1164 blk_name);
5b1270be
YW		 1165 }
1166 }
1167
1168 if (err_data->ue_count) {
ec3e0a91 1169 if (err_data_has_source_info(err_data)) {
9dc57c2a 1170 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,
46e2231c 1171 blk_name, true, false);
5b1270be
YW		 1172 } else if (!adev->aid_mask &&
1173 adev->smuio.funcs &&
1174 adev->smuio.funcs->get_socket_id &&
1175 adev->smuio.funcs->get_die_id) {
9dc57c2a
YW		 1176 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "
1177 "%ld uncorrectable hardware errors "
1178 "detected in %s block\n",
1179 adev->smuio.funcs->get_socket_id(adev),
1180 adev->smuio.funcs->get_die_id(adev),
1181 ras_mgr->err_data.ue_count,
1182 blk_name);
5b1270be 1183 } else {
9dc57c2a
YW		 1184 RAS_EVENT_LOG(adev, event_id, "%ld uncorrectable hardware errors "
1185 "detected in %s block\n",
1186 ras_mgr->err_data.ue_count,
1187 blk_name);
5b1270be
YW		 1188 }
1189 }
1190
46e2231c
CL		 1191 if (err_data->de_count) {
1192 if (err_data_has_source_info(err_data)) {
9dc57c2a 1193 amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, qctx,
46e2231c
CL		 1194 blk_name, false, true);
1195 } else if (!adev->aid_mask &&
1196 adev->smuio.funcs &&
1197 adev->smuio.funcs->get_socket_id &&
1198 adev->smuio.funcs->get_die_id) {
9dc57c2a
YW		 1199 RAS_EVENT_LOG(adev, event_id, "socket: %d, die: %d "
1200 "%ld deferred hardware errors "
1201 "detected in %s block\n",
1202 adev->smuio.funcs->get_socket_id(adev),
1203 adev->smuio.funcs->get_die_id(adev),
1204 ras_mgr->err_data.de_count,
1205 blk_name);
46e2231c 1206 } else {
9dc57c2a
YW		 1207 RAS_EVENT_LOG(adev, event_id, "%ld deferred hardware errors "
1208 "detected in %s block\n",
1209 ras_mgr->err_data.de_count,
1210 blk_name);
46e2231c
CL		 1211 }
1212 }
5b1270be
YW		 1213}
1214
ec3e0a91
YW		 1215static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data)
1216{
1217 struct ras_err_node *err_node;
1218 struct ras_err_info *err_info;
1219
1220 if (err_data_has_source_info(err_data)) {
1221 for_each_ras_error(err_node, err_data) {
1222 err_info = &err_node->err_info;
46e2231c
CL		 1223 amdgpu_ras_error_statistic_de_count(&obj->err_data,
1224 &err_info->mcm_info, NULL, err_info->de_count);
9f91e983
YC		 1225 amdgpu_ras_error_statistic_ce_count(&obj->err_data,
1226 &err_info->mcm_info, NULL, err_info->ce_count);
1227 amdgpu_ras_error_statistic_ue_count(&obj->err_data,
1228 &err_info->mcm_info, NULL, err_info->ue_count);
ec3e0a91
YW		 1229 }
1230 } else {
1231 /* for legacy asic path which doesn't has error source info */
1232 obj->err_data.ue_count += err_data->ue_count;
1233 obj->err_data.ce_count += err_data->ce_count;
46e2231c 1234 obj->err_data.de_count += err_data->de_count;
ec3e0a91
YW		 1235 }
1236}
1237
04c4fcd2
YW		 1238static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk)
1239{
1240 struct ras_common_if head;
1241
1242 memset(&head, 0, sizeof(head));
1243 head.block = blk;
1244
1245 return amdgpu_ras_find_obj(adev, &head);
1246}
1247
1248int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
1249 const struct aca_info *aca_info, void *data)
1250{
1251 struct ras_manager *obj;
1252
6f3b6913
YC		 1253 /* in resume phase, no need to create aca fs node */
1254 if (adev->in_suspend || amdgpu_in_reset(adev))
1255 return 0;
1256
04c4fcd2
YW		 1257 obj = get_ras_manager(adev, blk);
1258 if (!obj)
1259 return -EINVAL;
1260
1261 return amdgpu_aca_add_handle(adev, &obj->aca_handle, ras_block_str(blk), aca_info, data);
1262}
1263
1264int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk)
1265{
1266 struct ras_manager *obj;
1267
1268 obj = get_ras_manager(adev, blk);
1269 if (!obj)
1270 return -EINVAL;
1271
1272 amdgpu_aca_remove_handle(&obj->aca_handle);
1273
1274 return 0;
1275}
1276
1277static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
31fd330b
YW		 1278 enum aca_error_type type, struct ras_err_data *err_data,
1279 struct ras_query_context *qctx)
04c4fcd2
YW		 1280{
1281 struct ras_manager *obj;
1282
1283 obj = get_ras_manager(adev, blk);
1284 if (!obj)
1285 return -EINVAL;
1286
31fd330b 1287 return amdgpu_aca_get_error_data(adev, &obj->aca_handle, type, err_data, qctx);
04c4fcd2
YW		 1288}
1289
37973b69
YW		 1290ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr,
1291 struct aca_handle *handle, char *buf, void *data)
1292{
1293 struct ras_manager *obj = container_of(handle, struct ras_manager, aca_handle);
1294 struct ras_query_if info = {
1295 .head = obj->head,
1296 };
1297
1298 if (amdgpu_ras_query_error_status(obj->adev, &info))
1299 return -EINVAL;
1300
865d3397
YW		 1301 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count,
1302 "ce", info.ce_count, "de", info.ue_count);
37973b69
YW		 1303}
1304
8cc0f566
HZ		 1305static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev,
1306 struct ras_query_if *info,
1307 struct ras_err_data *err_data,
9dc57c2a 1308 struct ras_query_context *qctx,
8cc0f566 1309 unsigned int error_query_mode)
c030f2e4 1310{
8cc0f566 1311 enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT;
b6efdb02 1312 struct amdgpu_ras_block_object *block_obj = NULL;
04c4fcd2 1313 int ret;
8cc0f566 1314
b8d55a90
SS		 1315 if (blk == AMDGPU_RAS_BLOCK_COUNT)
1316 return -EINVAL;
1317
8cc0f566
HZ		 1318 if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY)
1319 return -EINVAL;
1320
1321 if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) {
1322 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
1323 amdgpu_ras_get_ecc_info(adev, err_data);
1324 } else {
1325 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
1326 if (!block_obj || !block_obj->hw_ops) {
1327 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1328 get_ras_block_str(&info->head));
1329 return -EINVAL;
1330 }
1331
1332 if (block_obj->hw_ops->query_ras_error_count)
07ee43fa 1333 block_obj->hw_ops->query_ras_error_count(adev, err_data);
8cc0f566
HZ		 1334
1335 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1336 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1337 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1338 if (block_obj->hw_ops->query_ras_error_status)
1339 block_obj->hw_ops->query_ras_error_status(adev);
1340 }
1341 }
1342 } else {
04c4fcd2 1343 if (amdgpu_aca_is_enabled(adev)) {
31fd330b 1344 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data, qctx);
04c4fcd2
YW		 1345 if (ret)
1346 return ret;
1347
31fd330b 1348 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data, qctx);
04c4fcd2
YW		 1349 if (ret)
1350 return ret;
865d3397 1351
31fd330b 1352 ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_DEFERRED, err_data, qctx);
865d3397
YW		 1353 if (ret)
1354 return ret;
04c4fcd2
YW		 1355 } else {
1356 /* FIXME: add code to check return value later */
9dc57c2a
YW		 1357 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data, qctx);
1358 amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data, qctx);
04c4fcd2 1359 }
8cc0f566
HZ		 1360 }
1361
1362 return 0;
1363}
1364
1365/* query/inject/cure begin */
1366int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info)
1367{
c030f2e4 1368 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
5b1270be 1369 struct ras_err_data err_data;
9dc57c2a 1370 struct ras_query_context qctx;
8cc0f566 1371 unsigned int error_query_mode;
5b1270be 1372 int ret;
c030f2e4 1373
1374 if (!obj)
1375 return -EINVAL;
c030f2e4 1376
5b1270be
YW		 1377 ret = amdgpu_ras_error_data_init(&err_data);
1378 if (ret)
1379 return ret;
1380
8cc0f566
HZ		 1381 if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode))
1382 return -EINVAL;
7389a5b8 1383
9dc57c2a
YW		 1384 memset(&qctx, 0, sizeof(qctx));
1385 qctx.event_id = amdgpu_ras_acquire_event_id(adev, amdgpu_ras_intr_triggered() ?
1386 RAS_EVENT_TYPE_ISR : RAS_EVENT_TYPE_INVALID);
8cc0f566
HZ		 1387 ret = amdgpu_ras_query_error_status_helper(adev, info,
1388 &err_data,
9dc57c2a 1389 &qctx,
8cc0f566
HZ		 1390 error_query_mode);
1391 if (ret)
1392 goto out_fini_err_data;
05a58345 1393
ec3e0a91 1394 amdgpu_rasmgr_error_data_statistic_update(obj, &err_data);
05a58345 1395
c030f2e4 1396 info->ue_count = obj->err_data.ue_count;
1397 info->ce_count = obj->err_data.ce_count;
46e2231c 1398 info->de_count = obj->err_data.de_count;
c030f2e4 1399
9dc57c2a 1400 amdgpu_ras_error_generate_report(adev, info, &err_data, &qctx);
05a58345 1401
5b1270be
YW		 1402out_fini_err_data:
1403 amdgpu_ras_error_data_fini(&err_data);
1404
1405 return ret;
c030f2e4 1406}
1407
472c5fb2 1408int amdgpu_ras_reset_error_count(struct amdgpu_device *adev,
761d86d3
DL		 1409 enum amdgpu_ras_block block)
1410{
b6efdb02 1411 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
73582be1
TZ		 1412 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1413 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
04c4fcd2 1414 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs;
18eae367
TZ		 1415 struct amdgpu_hive_info *hive;
1416 int hive_ras_recovery = 0;
8b0fb0e9 1417
a83f2bf1 1418 if (!block_obj || !block_obj->hw_ops) {
afa37315 1419 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
472c5fb2
TZ		 1420 ras_block_str(block));
1421 return -EOPNOTSUPP;
761d86d3
DL		 1422 }
1423
d1d4c0b7 1424 if (!amdgpu_ras_is_supported(adev, block) ||
04c4fcd2 1425 !amdgpu_ras_get_aca_debug_mode(adev))
d1d4c0b7
TZ		 1426 return -EOPNOTSUPP;
1427
18eae367
TZ		 1428 hive = amdgpu_get_xgmi_hive(adev);
1429 if (hive) {
1430 hive_ras_recovery = atomic_read(&hive->ras_recovery);
1431 amdgpu_put_xgmi_hive(hive);
1432 }
1433
73582be1 1434 /* skip ras error reset in gpu reset */
18eae367
TZ		 1435 if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) ||
1436 hive_ras_recovery) &&
04c4fcd2
YW		 1437 ((smu_funcs && smu_funcs->set_debug_mode) ||
1438 (mca_funcs && mca_funcs->mca_set_debug_mode)))
73582be1
TZ		 1439 return -EOPNOTSUPP;
1440
7389a5b8 1441 if (block_obj->hw_ops->reset_ras_error_count)
1442 block_obj->hw_ops->reset_ras_error_count(adev);
5c23e9e0 1443
472c5fb2
TZ		 1444 return 0;
1445}
1446
1447int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1448 enum amdgpu_ras_block block)
1449{
1450 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
1451
1452 if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP)
1453 return 0;
1454
7389a5b8 1455 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1456 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
8b0fb0e9 1457 if (block_obj->hw_ops->reset_ras_error_status)
1458 block_obj->hw_ops->reset_ras_error_status(adev);
761d86d3 1459 }
5c23e9e0 1460
761d86d3 1461 return 0;
5c23e9e0
JC		 1462}
1463
c030f2e4 1464/* wrapper of psp_ras_trigger_error */
1465int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1466 struct ras_inject_if *info)
1467{
1468 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1469 struct ta_ras_trigger_error_input block_info = {
828cfa29 1470 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1471 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
c030f2e4 1472 .sub_block_index = info->head.sub_block_index,
1473 .address = info->address,
1474 .value = info->value,
1475 };
ab3b9de6
YL		 1476 int ret = -EINVAL;
1477 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1478 info->head.block,
1479 info->head.sub_block_index);
c030f2e4 1480
248c9635
TZ		 1481 /* inject on guest isn't allowed, return success directly */
1482 if (amdgpu_sriov_vf(adev))
1483 return 0;
1484
c030f2e4 1485 if (!obj)
1486 return -EINVAL;
1487
22d4ba53 1488 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1489 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1490 get_ras_block_str(&info->head));
22d4ba53 1491 return -EINVAL;
1492 }
1493
a6c44d25 1494 /* Calculate XGMI relative offset */
a80fe1a6
TZ		 1495 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1496 info->head.block != AMDGPU_RAS_BLOCK__GFX) {
19744f5f
HZ		 1497 block_info.address =
1498 amdgpu_xgmi_get_relative_phy_addr(adev,
1499 block_info.address);
a6c44d25
JC		 1500 }
1501
27c5f295
TZ		 1502 if (block_obj->hw_ops->ras_error_inject) {
1503 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
2c22ed0b 1504 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
27c5f295 1505 else /* Special ras_error_inject is defined (e.g: xgmi) */
2c22ed0b
TZ		 1506 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1507 info->instance_mask);
27c5f295
TZ		 1508 } else {
1509 /* default path */
1510 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
a5dd40ca
HZ		 1511 }
1512
011907fd
DL		 1513 if (ret)
1514 dev_err(adev->dev, "ras inject %s failed %d\n",
640ae42e 1515 get_ras_block_str(&info->head), ret);
c030f2e4 1516
1517 return ret;
1518}
1519
4d9f771e 1520/**
4a1c9a44
HZ		 1521 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1522 * @adev: pointer to AMD GPU device
1523 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1524 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1525 * @query_info: pointer to ras_query_if
1526 *
1527 * Return 0 for query success or do nothing, otherwise return an error
1528 * on failures
1529 */
1530static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1531 unsigned long *ce_count,
1532 unsigned long *ue_count,
1533 struct ras_query_if *query_info)
1534{
1535 int ret;
1536
1537 if (!query_info)
1538 /* do nothing if query_info is not specified */
1539 return 0;
1540
1541 ret = amdgpu_ras_query_error_status(adev, query_info);
1542 if (ret)
1543 return ret;
1544
1545 *ce_count += query_info->ce_count;
1546 *ue_count += query_info->ue_count;
1547
1548 /* some hardware/IP supports read to clear
1549 * no need to explictly reset the err status after the query call */
4e8303cf
LL		 1550 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) &&
1551 amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) {
4a1c9a44
HZ		 1552 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1553 dev_warn(adev->dev,
1554 "Failed to reset error counter and error status\n");
1555 }
1556
1557 return 0;
1558}
1559
1560/**
1561 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
bbe04dec
IB		 1562 * @adev: pointer to AMD GPU device
1563 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1564 * @ue_count: pointer to an integer to be set to the count of uncorrectible
4d9f771e 1565 * errors.
4a1c9a44
HZ		 1566 * @query_info: pointer to ras_query_if if the query request is only for
1567 * specific ip block; if info is NULL, then the qurey request is for
1568 * all the ip blocks that support query ras error counters/status
4d9f771e
LT		 1569 *
1570 * If set, @ce_count or @ue_count, count and return the corresponding
1571 * error counts in those integer pointers. Return 0 if the device
1572 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1573 */
1574int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1575 unsigned long *ce_count,
4a1c9a44
HZ		 1576 unsigned long *ue_count,
1577 struct ras_query_if *query_info)
c030f2e4 1578{
1579 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1580 struct ras_manager *obj;
a46751fb 1581 unsigned long ce, ue;
4a1c9a44 1582 int ret;
c030f2e4 1583
8ab0d6f0 1584 if (!adev->ras_enabled || !con)
4d9f771e
LT		 1585 return -EOPNOTSUPP;
1586
1587 /* Don't count since no reporting.
1588 */
1589 if (!ce_count && !ue_count)
1590 return 0;
c030f2e4 1591
a46751fb
LT		 1592 ce = 0;
1593 ue = 0;
4a1c9a44
HZ		 1594 if (!query_info) {
1595 /* query all the ip blocks that support ras query interface */
1596 list_for_each_entry(obj, &con->head, node) {
1597 struct ras_query_if info = {
1598 .head = obj->head,
1599 };
c030f2e4 1600
4a1c9a44 1601 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
2a460963 1602 }
4a1c9a44
HZ		 1603 } else {
1604 /* query specific ip block */
1605 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
c030f2e4 1606 }
1607
4a1c9a44
HZ		 1608 if (ret)
1609 return ret;
1610
a46751fb
LT		 1611 if (ce_count)
1612 *ce_count = ce;
1613
1614 if (ue_count)
1615 *ue_count = ue;
4d9f771e
LT		 1616
1617 return 0;
c030f2e4 1618}
1619/* query/inject/cure end */
1620
1621
1622/* sysfs begin */
1623
466b1793 1624static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1625 struct ras_badpage **bps, unsigned int *count);
1626
1627static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1628{
1629 switch (flags) {
52dd95f2 1630 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
466b1793 1631 return "R";
52dd95f2 1632 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
466b1793 1633 return "P";
52dd95f2 1634 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
466b1793 1635 default:
1636 return "F";
aec576f9 1637 }
466b1793 1638}
1639
f77c7109
AD		 1640/**
1641 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
466b1793 1642 *
1643 * It allows user to read the bad pages of vram on the gpu through
1644 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1645 *
1646 * It outputs multiple lines, and each line stands for one gpu page.
1647 *
1648 * The format of one line is below,
1649 * gpu pfn : gpu page size : flags
1650 *
1651 * gpu pfn and gpu page size are printed in hex format.
1652 * flags can be one of below character,
f77c7109 1653 *
466b1793 1654 * R: reserved, this gpu page is reserved and not able to use.
f77c7109 1655 *
466b1793 1656 * P: pending for reserve, this gpu page is marked as bad, will be reserved
f77c7109
AD		 1657 * in next window of page_reserve.
1658 *
466b1793 1659 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1660 *
f77c7109
AD		 1661 * Examples:
1662 *
1663 * .. code-block:: bash
1664 *
1665 * 0x00000001 : 0x00001000 : R
1666 * 0x00000002 : 0x00001000 : P
1667 *
466b1793 1668 */
1669
1670static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1671 struct kobject *kobj, struct bin_attribute *attr,
1672 char *buf, loff_t ppos, size_t count)
1673{
1674 struct amdgpu_ras *con =
1675 container_of(attr, struct amdgpu_ras, badpages_attr);
1676 struct amdgpu_device *adev = con->adev;
1677 const unsigned int element_size =
1678 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
d6ee400e
SA		 1679 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1680 unsigned int end = div64_ul(ppos + count - 1, element_size);
466b1793 1681 ssize_t s = 0;
1682 struct ras_badpage *bps = NULL;
1683 unsigned int bps_count = 0;
1684
1685 memset(buf, 0, count);
1686
1687 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1688 return 0;
1689
1690 for (; start < end && start < bps_count; start++)
1691 s += scnprintf(&buf[s], element_size + 1,
1692 "0x%08x : 0x%08x : %1s\n",
1693 bps[start].bp,
1694 bps[start].size,
1695 amdgpu_ras_badpage_flags_str(bps[start].flags));
1696
1697 kfree(bps);
1698
1699 return s;
1700}
1701
c030f2e4 1702static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1703 struct device_attribute *attr, char *buf)
1704{
1705 struct amdgpu_ras *con =
1706 container_of(attr, struct amdgpu_ras, features_attr);
c030f2e4 1707
2cffcb66 1708 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
c030f2e4 1709}
1710
625e5f38
AK		 1711static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev,
1712 struct device_attribute *attr, char *buf)
1713{
1714 struct amdgpu_ras *con =
1715 container_of(attr, struct amdgpu_ras, version_attr);
1716 return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version);
1717}
1718
1719static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev,
1720 struct device_attribute *attr, char *buf)
1721{
1722 struct amdgpu_ras *con =
1723 container_of(attr, struct amdgpu_ras, schema_attr);
1724 return sysfs_emit(buf, "schema: 0x%x\n", con->schema);
1725}
1726
f848159b
GC		 1727static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1728{
1729 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1730
4638e0c2
VP		 1731 if (adev->dev->kobj.sd)
1732 sysfs_remove_file_from_group(&adev->dev->kobj,
f848159b
GC		 1733 &con->badpages_attr.attr,
1734 RAS_FS_NAME);
1735}
1736
625e5f38 1737static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev)
c030f2e4 1738{
1739 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1740 struct attribute *attrs[] = {
1741 &con->features_attr.attr,
625e5f38
AK		 1742 &con->version_attr.attr,
1743 &con->schema_attr.attr,
c030f2e4 1744 NULL
1745 };
1746 struct attribute_group group = {
eb0c3cd4 1747 .name = RAS_FS_NAME,
c030f2e4 1748 .attrs = attrs,
1749 };
1750
4638e0c2
VP		 1751 if (adev->dev->kobj.sd)
1752 sysfs_remove_group(&adev->dev->kobj, &group);
c030f2e4 1753
1754 return 0;
1755}
1756
1757int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
9252d33d 1758 struct ras_common_if *head)
c030f2e4 1759{
9252d33d 1760 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1761
1762 if (!obj || obj->attr_inuse)
1763 return -EINVAL;
1764
1765 get_obj(obj);
1766
9252d33d 1767 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1768 "%s_err_count", head->name);
c030f2e4 1769
1770 obj->sysfs_attr = (struct device_attribute){
1771 .attr = {
1772 .name = obj->fs_data.sysfs_name,
1773 .mode = S_IRUGO,
1774 },
1775 .show = amdgpu_ras_sysfs_read,
1776 };
163def43 1777 sysfs_attr_init(&obj->sysfs_attr.attr);
c030f2e4 1778
1779 if (sysfs_add_file_to_group(&adev->dev->kobj,
1780 &obj->sysfs_attr.attr,
eb0c3cd4 1781 RAS_FS_NAME)) {
c030f2e4 1782 put_obj(obj);
1783 return -EINVAL;
1784 }
1785
1786 obj->attr_inuse = 1;
1787
1788 return 0;
1789}
1790
1791int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1792 struct ras_common_if *head)
1793{
1794 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1795
1796 if (!obj || !obj->attr_inuse)
1797 return -EINVAL;
1798
4638e0c2
VP		 1799 if (adev->dev->kobj.sd)
1800 sysfs_remove_file_from_group(&adev->dev->kobj,
c030f2e4 1801 &obj->sysfs_attr.attr,
eb0c3cd4 1802 RAS_FS_NAME);
c030f2e4 1803 obj->attr_inuse = 0;
1804 put_obj(obj);
1805
1806 return 0;
1807}
1808
1809static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1810{
1811 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1812 struct ras_manager *obj, *tmp;
1813
1814 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1815 amdgpu_ras_sysfs_remove(adev, &obj->head);
1816 }
1817
f848159b
GC		 1818 if (amdgpu_bad_page_threshold != 0)
1819 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1820
625e5f38 1821 amdgpu_ras_sysfs_remove_dev_attr_node(adev);
c030f2e4 1822
1823 return 0;
1824}
1825/* sysfs end */
1826
ef177d11
AD		 1827/**
1828 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1829 *
1830 * Normally when there is an uncorrectable error, the driver will reset
1831 * the GPU to recover. However, in the event of an unrecoverable error,
1832 * the driver provides an interface to reboot the system automatically
1833 * in that event.
1834 *
1835 * The following file in debugfs provides that interface:
1836 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1837 *
1838 * Usage:
1839 *
1840 * .. code-block:: bash
1841 *
1842 * echo true > .../ras/auto_reboot
1843 *
1844 */
c030f2e4 1845/* debugfs begin */
ea1b8c9b 1846static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
36ea1bd2 1847{
1848 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
740f42a2 1849 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
ef0d7d20
LT		 1850 struct drm_minor *minor = adev_to_drm(adev)->primary;
1851 struct dentry *dir;
36ea1bd2 1852
88293c03
ND		 1853 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1854 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1855 &amdgpu_ras_debugfs_ctrl_ops);
1856 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1857 &amdgpu_ras_debugfs_eeprom_ops);
7fb64071
LT		 1858 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1859 &con->bad_page_cnt_threshold);
740f42a2 1860 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
ef0d7d20
LT		 1861 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1862 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
c65b0805
LT		 1863 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1864 &amdgpu_ras_debugfs_eeprom_size_ops);
1865 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1866 S_IRUGO, dir, adev,
1867 &amdgpu_ras_debugfs_eeprom_table_ops);
1868 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
c688a06b
GC		 1869
1870 /*
1871 * After one uncorrectable error happens, usually GPU recovery will
1872 * be scheduled. But due to the known problem in GPU recovery failing
1873 * to bring GPU back, below interface provides one direct way to
1874 * user to reboot system automatically in such case within
1875 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1876 * will never be called.
1877 */
88293c03 1878 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
66459e1d
GC		 1879
1880 /*
1881 * User could set this not to clean up hardware's error count register
1882 * of RAS IPs during ras recovery.
1883 */
88293c03
ND		 1884 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1885 &con->disable_ras_err_cnt_harvest);
1886 return dir;
36ea1bd2 1887}
1888
cedf7884 1889static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
88293c03
ND		 1890 struct ras_fs_if *head,
1891 struct dentry *dir)
c030f2e4 1892{
c030f2e4 1893 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
c030f2e4 1894
88293c03 1895 if (!obj || !dir)
450f30ea 1896 return;
c030f2e4 1897
1898 get_obj(obj);
1899
1900 memcpy(obj->fs_data.debugfs_name,
1901 head->debugfs_name,
1902 sizeof(obj->fs_data.debugfs_name));
1903
88293c03
ND		 1904 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1905 obj, &amdgpu_ras_debugfs_ops);
c030f2e4 1906}
1907
f9317014
TZ		 1908void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1909{
1910 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
88293c03 1911 struct dentry *dir;
c1509f3f 1912 struct ras_manager *obj;
f9317014
TZ		 1913 struct ras_fs_if fs_info;
1914
1915 /*
1916 * it won't be called in resume path, no need to check
1917 * suspend and gpu reset status
1918 */
cedf7884 1919 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
f9317014
TZ		 1920 return;
1921
88293c03 1922 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
f9317014 1923
c1509f3f 1924 list_for_each_entry(obj, &con->head, node) {
f9317014
TZ		 1925 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1926 (obj->attr_inuse == 1)) {
1927 sprintf(fs_info.debugfs_name, "%s_err_inject",
640ae42e 1928 get_ras_block_str(&obj->head));
f9317014 1929 fs_info.head = obj->head;
88293c03 1930 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
f9317014
TZ		 1931 }
1932 }
4051844c 1933
04c4fcd2
YW		 1934 if (amdgpu_aca_is_enabled(adev))
1935 amdgpu_aca_smu_debugfs_init(adev, dir);
1936 else
1937 amdgpu_mca_smu_debugfs_init(adev, dir);
f9317014
TZ		 1938}
1939
c030f2e4 1940/* debugfs end */
1941
1942/* ras fs */
c3d4d45d
GC		 1943static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1944 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1945static DEVICE_ATTR(features, S_IRUGO,
1946 amdgpu_ras_sysfs_features_read, NULL);
625e5f38
AK		 1947static DEVICE_ATTR(version, 0444,
1948 amdgpu_ras_sysfs_version_show, NULL);
1949static DEVICE_ATTR(schema, 0444,
1950 amdgpu_ras_sysfs_schema_show, NULL);
c030f2e4 1951static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1952{
c3d4d45d
GC		 1953 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1954 struct attribute_group group = {
1955 .name = RAS_FS_NAME,
1956 };
1957 struct attribute *attrs[] = {
1958 &con->features_attr.attr,
625e5f38
AK		 1959 &con->version_attr.attr,
1960 &con->schema_attr.attr,
c3d4d45d
GC		 1961 NULL
1962 };
1963 struct bin_attribute *bin_attrs[] = {
1964 NULL,
1965 NULL,
1966 };
a069a9eb 1967 int r;
c030f2e4 1968
625e5f38
AK		 1969 group.attrs = attrs;
1970
c3d4d45d
GC		 1971 /* add features entry */
1972 con->features_attr = dev_attr_features;
c3d4d45d
GC		 1973 sysfs_attr_init(attrs[0]);
1974
625e5f38
AK		 1975 /* add version entry */
1976 con->version_attr = dev_attr_version;
1977 sysfs_attr_init(attrs[1]);
1978
1979 /* add schema entry */
1980 con->schema_attr = dev_attr_schema;
1981 sysfs_attr_init(attrs[2]);
1982
c3d4d45d
GC		 1983 if (amdgpu_bad_page_threshold != 0) {
1984 /* add bad_page_features entry */
1985 bin_attr_gpu_vram_bad_pages.private = NULL;
1986 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1987 bin_attrs[0] = &con->badpages_attr;
1988 group.bin_attrs = bin_attrs;
1989 sysfs_bin_attr_init(bin_attrs[0]);
1990 }
1991
a069a9eb
AD		 1992 r = sysfs_create_group(&adev->dev->kobj, &group);
1993 if (r)
1994 dev_err(adev->dev, "Failed to create RAS sysfs group!");
f848159b 1995
c030f2e4 1996 return 0;
1997}
1998
1999static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
2000{
88293c03
ND		 2001 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2002 struct ras_manager *con_obj, *ip_obj, *tmp;
2003
2004 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2005 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
2006 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
2007 if (ip_obj)
2008 put_obj(ip_obj);
2009 }
2010 }
2011
c030f2e4 2012 amdgpu_ras_sysfs_remove_all(adev);
2013 return 0;
2014}
2015/* ras fs end */
2016
2017/* ih begin */
b3c76814
TZ		 2018
2019/* For the hardware that cannot enable bif ring for both ras_controller_irq
2020 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
2021 * register to check whether the interrupt is triggered or not, and properly
2022 * ack the interrupt if it is there
2023 */
2024void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
2025{
950d6425 2026 /* Fatal error events are handled on host side */
8eba7205 2027 if (amdgpu_sriov_vf(adev))
b3c76814
TZ		 2028 return;
2029
2030 if (adev->nbio.ras &&
2031 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
2032 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
2033
2034 if (adev->nbio.ras &&
2035 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
2036 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
2037}
2038
66f87949
TZ		 2039static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
2040 struct amdgpu_iv_entry *entry)
2041{
b63ac5d3 2042 bool poison_stat = false;
66f87949 2043 struct amdgpu_device *adev = obj->adev;
66f87949
TZ		 2044 struct amdgpu_ras_block_object *block_obj =
2045 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
2046
ac7b25d9 2047 if (!block_obj)
b63ac5d3 2048 return;
66f87949 2049
b63ac5d3
TZ		 2050 /* both query_poison_status and handle_poison_consumption are optional,
2051 * but at least one of them should be implemented if we need poison
2052 * consumption handler
2053 */
ac7b25d9 2054 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
b63ac5d3
TZ		 2055 poison_stat = block_obj->hw_ops->query_poison_status(adev);
2056 if (!poison_stat) {
2057 /* Not poison consumption interrupt, no need to handle it */
2058 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
2059 block_obj->ras_comm.name);
2060
2061 return;
66f87949
TZ		 2062 }
2063 }
2064
2fc46e0b 2065 amdgpu_umc_poison_handler(adev, obj->head.block, 0);
b63ac5d3 2066
ac7b25d9 2067 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
b63ac5d3
TZ		 2068 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
2069
2070 /* gpu reset is fallback for failed and default cases */
2071 if (poison_stat) {
2072 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
2073 block_obj->ras_comm.name);
66f87949 2074 amdgpu_ras_reset_gpu(adev);
ac7b25d9
YC		 2075 } else {
2076 amdgpu_gfx_poison_consumption_handler(adev, entry);
b63ac5d3 2077 }
66f87949
TZ		 2078}
2079
50a7d025
TZ		 2080static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
2081 struct amdgpu_iv_entry *entry)
2082{
2083 dev_info(obj->adev->dev,
90bd0147 2084 "Poison is created\n");
a734adfb
YC		 2085
2086 if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
2087 struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev);
2088
2089 amdgpu_ras_put_poison_req(obj->adev,
2090 AMDGPU_RAS_BLOCK__UMC, 0, NULL, NULL, false);
2091
2092 atomic_inc(&con->page_retirement_req_cnt);
2093
2094 wake_up(&con->page_retirement_wq);
2095 }
50a7d025
TZ		 2096}
2097
2098static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
2099 struct amdgpu_iv_entry *entry)
2100{
2101 struct ras_ih_data *data = &obj->ih_data;
5b1270be 2102 struct ras_err_data err_data;
50a7d025
TZ		 2103 int ret;
2104
2105 if (!data->cb)
2106 return;
2107
5b1270be
YW		 2108 ret = amdgpu_ras_error_data_init(&err_data);
2109 if (ret)
2110 return;
2111
50a7d025
TZ		 2112 /* Let IP handle its data, maybe we need get the output
2113 * from the callback to update the error type/count, etc
2114 */
2115 ret = data->cb(obj->adev, &err_data, entry);
2116 /* ue will trigger an interrupt, and in that case
2117 * we need do a reset to recovery the whole system.
2118 * But leave IP do that recovery, here we just dispatch
2119 * the error.
2120 */
2121 if (ret == AMDGPU_RAS_SUCCESS) {
2122 /* these counts could be left as 0 if
2123 * some blocks do not count error number
2124 */
2125 obj->err_data.ue_count += err_data.ue_count;
2126 obj->err_data.ce_count += err_data.ce_count;
46e2231c 2127 obj->err_data.de_count += err_data.de_count;
50a7d025 2128 }
5b1270be
YW		 2129
2130 amdgpu_ras_error_data_fini(&err_data);
50a7d025
TZ		 2131}
2132
c030f2e4 2133static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
2134{
2135 struct ras_ih_data *data = &obj->ih_data;
2136 struct amdgpu_iv_entry entry;
c030f2e4 2137
2138 while (data->rptr != data->wptr) {
2139 rmb();
2140 memcpy(&entry, &data->ring[data->rptr],
2141 data->element_size);
2142
2143 wmb();
2144 data->rptr = (data->aligned_element_size +
2145 data->rptr) % data->ring_size;
2146
50a7d025
TZ		 2147 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
2148 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2149 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
66f87949
TZ		 2150 else
2151 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
50a7d025
TZ		 2152 } else {
2153 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
2154 amdgpu_ras_interrupt_umc_handler(obj, &entry);
2155 else
2156 dev_warn(obj->adev->dev,
2157 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
c030f2e4 2158 }
2159 }
2160}
2161
2162static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
2163{
2164 struct ras_ih_data *data =
2165 container_of(work, struct ras_ih_data, ih_work);
2166 struct ras_manager *obj =
2167 container_of(data, struct ras_manager, ih_data);
2168
2169 amdgpu_ras_interrupt_handler(obj);
2170}
2171
2172int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
2173 struct ras_dispatch_if *info)
2174{
2175 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
2176 struct ras_ih_data *data = &obj->ih_data;
2177
2178 if (!obj)
2179 return -EINVAL;
2180
2181 if (data->inuse == 0)
2182 return 0;
2183
2184 /* Might be overflow... */
2185 memcpy(&data->ring[data->wptr], info->entry,
2186 data->element_size);
2187
2188 wmb();
2189 data->wptr = (data->aligned_element_size +
2190 data->wptr) % data->ring_size;
2191
2192 schedule_work(&data->ih_work);
2193
2194 return 0;
2195}
2196
2197int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
9252d33d 2198 struct ras_common_if *head)
c030f2e4 2199{
9252d33d 2200 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 2201 struct ras_ih_data *data;
2202
2203 if (!obj)
2204 return -EINVAL;
2205
2206 data = &obj->ih_data;
2207 if (data->inuse == 0)
2208 return 0;
2209
2210 cancel_work_sync(&data->ih_work);
2211
2212 kfree(data->ring);
2213 memset(data, 0, sizeof(*data));
2214 put_obj(obj);
2215
2216 return 0;
2217}
2218
2219int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
9252d33d 2220 struct ras_common_if *head)
c030f2e4 2221{
9252d33d 2222 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 2223 struct ras_ih_data *data;
9252d33d 2224 struct amdgpu_ras_block_object *ras_obj;
c030f2e4 2225
2226 if (!obj) {
2227 /* in case we registe the IH before enable ras feature */
9252d33d 2228 obj = amdgpu_ras_create_obj(adev, head);
c030f2e4 2229 if (!obj)
2230 return -EINVAL;
2231 } else
2232 get_obj(obj);
2233
9252d33d 2234 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
2235
c030f2e4 2236 data = &obj->ih_data;
2237 /* add the callback.etc */
2238 *data = (struct ras_ih_data) {
2239 .inuse = 0,
9252d33d 2240 .cb = ras_obj->ras_cb,
c030f2e4 2241 .element_size = sizeof(struct amdgpu_iv_entry),
2242 .rptr = 0,
2243 .wptr = 0,
2244 };
2245
2246 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
2247
2248 data->aligned_element_size = ALIGN(data->element_size, 8);
2249 /* the ring can store 64 iv entries. */
2250 data->ring_size = 64 * data->aligned_element_size;
2251 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
2252 if (!data->ring) {
2253 put_obj(obj);
2254 return -ENOMEM;
2255 }
2256
2257 /* IH is ready */
2258 data->inuse = 1;
2259
2260 return 0;
2261}
2262
2263static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
2264{
2265 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2266 struct ras_manager *obj, *tmp;
2267
2268 list_for_each_entry_safe(obj, tmp, &con->head, node) {
9252d33d 2269 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
c030f2e4 2270 }
2271
2272 return 0;
2273}
2274/* ih end */
2275
313c8fd3
GC		 2276/* traversal all IPs except NBIO to query error counter */
2277static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
2278{
2279 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2280 struct ras_manager *obj;
2281
8ab0d6f0 2282 if (!adev->ras_enabled || !con)
313c8fd3
GC		 2283 return;
2284
2285 list_for_each_entry(obj, &con->head, node) {
2286 struct ras_query_if info = {
2287 .head = obj->head,
2288 };
2289
2290 /*
2291 * PCIE_BIF IP has one different isr by ras controller
2292 * interrupt, the specific ras counter query will be
2293 * done in that isr. So skip such block from common
2294 * sync flood interrupt isr calling.
2295 */
2296 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
2297 continue;
2298
cf63b702
SY		 2299 /*
2300 * this is a workaround for aldebaran, skip send msg to
2301 * smu to get ecc_info table due to smu handle get ecc
2302 * info table failed temporarily.
2303 * should be removed until smu fix handle ecc_info table.
2304 */
2305 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
4e8303cf
LL		 2306 (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2307 IP_VERSION(13, 0, 2)))
cf63b702
SY		 2308 continue;
2309
761d86d3 2310 amdgpu_ras_query_error_status(adev, &info);
2a460963 2311
4e8303cf
LL		 2312 if (amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2313 IP_VERSION(11, 0, 2) &&
2314 amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2315 IP_VERSION(11, 0, 4) &&
2316 amdgpu_ip_version(adev, MP0_HWIP, 0) !=
2317 IP_VERSION(13, 0, 0)) {
2a460963
CL		 2318 if (amdgpu_ras_reset_error_status(adev, info.head.block))
2319 dev_warn(adev->dev, "Failed to reset error counter and error status");
2320 }
313c8fd3
GC		 2321 }
2322}
2323
3f975d0f 2324/* Parse RdRspStatus and WrRspStatus */
cd92df93
LJ		 2325static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
2326 struct ras_query_if *info)
3f975d0f 2327{
8eb53bb2 2328 struct amdgpu_ras_block_object *block_obj;
3f975d0f
SY		 2329 /*
2330 * Only two block need to query read/write
2331 * RspStatus at current state
2332 */
5e67bba3 2333 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
2334 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
b6efdb02 2335 return;
2336
2337 block_obj = amdgpu_ras_get_ras_block(adev,
2338 info->head.block,
2339 info->head.sub_block_index);
5e67bba3 2340
5e67bba3 2341 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 2342 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
2343 get_ras_block_str(&info->head));
b6efdb02 2344 return;
3f975d0f 2345 }
5e67bba3 2346
2347 if (block_obj->hw_ops->query_ras_error_status)
ab3b9de6 2348 block_obj->hw_ops->query_ras_error_status(adev);
5e67bba3 2349
3f975d0f
SY		 2350}
2351
2352static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
2353{
2354 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2355 struct ras_manager *obj;
2356
8ab0d6f0 2357 if (!adev->ras_enabled || !con)
3f975d0f
SY		 2358 return;
2359
2360 list_for_each_entry(obj, &con->head, node) {
2361 struct ras_query_if info = {
2362 .head = obj->head,
2363 };
2364
2365 amdgpu_ras_error_status_query(adev, &info);
2366 }
2367}
2368
c030f2e4 2369/* recovery begin */
466b1793 2370
2371/* return 0 on success.
2372 * caller need free bps.
2373 */
2374static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
2375 struct ras_badpage **bps, unsigned int *count)
2376{
2377 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2378 struct ras_err_handler_data *data;
2379 int i = 0;
732f2a30 2380 int ret = 0, status;
466b1793 2381
2382 if (!con || !con->eh_data || !bps || !count)
2383 return -EINVAL;
2384
2385 mutex_lock(&con->recovery_lock);
2386 data = con->eh_data;
2387 if (!data || data->count == 0) {
2388 *bps = NULL;
46cf2fec 2389 ret = -EINVAL;
466b1793 2390 goto out;
2391 }
2392
2393 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
2394 if (!*bps) {
2395 ret = -ENOMEM;
2396 goto out;
2397 }
2398
2399 for (; i < data->count; i++) {
2400 (*bps)[i] = (struct ras_badpage){
9dc23a63 2401 .bp = data->bps[i].retired_page,
466b1793 2402 .size = AMDGPU_GPU_PAGE_SIZE,
52dd95f2 2403 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
466b1793 2404 };
ec6aae97 2405 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
bcc09348 2406 data->bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT);
732f2a30 2407 if (status == -EBUSY)
52dd95f2 2408 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
732f2a30 2409 else if (status == -ENOENT)
52dd95f2 2410 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
466b1793 2411 }
2412
2413 *count = data->count;
2414out:
2415 mutex_unlock(&con->recovery_lock);
2416 return ret;
2417}
2418
b41f742d
LL		 2419static void amdgpu_ras_set_fed_all(struct amdgpu_device *adev,
2420 struct amdgpu_hive_info *hive, bool status)
2421{
2422 struct amdgpu_device *tmp_adev;
2423
2424 if (hive) {
2425 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head)
2426 amdgpu_ras_set_fed(tmp_adev, status);
2427 } else {
2428 amdgpu_ras_set_fed(adev, status);
2429 }
2430}
2431
c030f2e4 2432static void amdgpu_ras_do_recovery(struct work_struct *work)
2433{
2434 struct amdgpu_ras *ras =
2435 container_of(work, struct amdgpu_ras, recovery_work);
b3dbd6d3
JC		 2436 struct amdgpu_device *remote_adev = NULL;
2437 struct amdgpu_device *adev = ras->adev;
2438 struct list_head device_list, *device_list_handle = NULL;
53dd920c 2439 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
b3dbd6d3 2440
b41f742d 2441 if (hive) {
53dd920c 2442 atomic_set(&hive->ras_recovery, 1);
b41f742d
LL		 2443
2444 /* If any device which is part of the hive received RAS fatal
2445 * error interrupt, set fatal error status on all. This
2446 * condition will need a recovery, and flag will be cleared
2447 * as part of recovery.
2448 */
2449 list_for_each_entry(remote_adev, &hive->device_list,
2450 gmc.xgmi.head)
2451 if (amdgpu_ras_get_fed_status(remote_adev)) {
2452 amdgpu_ras_set_fed_all(adev, hive, true);
2453 break;
2454 }
2455 }
f75e94d8 2456 if (!ras->disable_ras_err_cnt_harvest) {
d95e8e97 2457
f75e94d8
GC		 2458 /* Build list of devices to query RAS related errors */
2459 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2460 device_list_handle = &hive->device_list;
2461 } else {
2462 INIT_LIST_HEAD(&device_list);
2463 list_add_tail(&adev->gmc.xgmi.head, &device_list);
2464 device_list_handle = &device_list;
2465 }
c030f2e4 2466
f75e94d8 2467 list_for_each_entry(remote_adev,
3f975d0f
SY		 2468 device_list_handle, gmc.xgmi.head) {
2469 amdgpu_ras_query_err_status(remote_adev);
f75e94d8 2470 amdgpu_ras_log_on_err_counter(remote_adev);
3f975d0f 2471 }
d95e8e97 2472
b3dbd6d3 2473 }
313c8fd3 2474
f1549c09
LG		 2475 if (amdgpu_device_should_recover_gpu(ras->adev)) {
2476 struct amdgpu_reset_context reset_context;
2477 memset(&reset_context, 0, sizeof(reset_context));
2478
2479 reset_context.method = AMD_RESET_METHOD_NONE;
2480 reset_context.reset_req_dev = adev;
1a11a65d
YC		 2481
2482 /* Perform full reset in fatal error mode */
2483 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2484 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6c47a79b 2485 else {
1a11a65d 2486 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
f1549c09 2487
6c47a79b
YC		 2488 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2489 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2490 reset_context.method = AMD_RESET_METHOD_MODE2;
2491 }
2c7cd280
YC		 2492
2493 /* Fatal error occurs in poison mode, mode1 reset is used to
2494 * recover gpu.
2495 */
2496 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2497 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2498 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
1b98a5f8
YC		 2499
2500 psp_fatal_error_recovery_quirk(&adev->psp);
2c7cd280 2501 }
6c47a79b
YC		 2502 }
2503
f1549c09
LG		 2504 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2505 }
c030f2e4 2506 atomic_set(&ras->in_recovery, 0);
53dd920c
AK		 2507 if (hive) {
2508 atomic_set(&hive->ras_recovery, 0);
2509 amdgpu_put_xgmi_hive(hive);
2510 }
c030f2e4 2511}
2512
c030f2e4 2513/* alloc/realloc bps array */
2514static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2515 struct ras_err_handler_data *data, int pages)
2516{
2517 unsigned int old_space = data->count + data->space_left;
2518 unsigned int new_space = old_space + pages;
9dc23a63
TZ		 2519 unsigned int align_space = ALIGN(new_space, 512);
2520 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
9dc23a63 2521
676deb38 2522 if (!bps) {
c030f2e4 2523 return -ENOMEM;
9dc23a63 2524 }
c030f2e4 2525
2526 if (data->bps) {
9dc23a63 2527 memcpy(bps, data->bps,
c030f2e4 2528 data->count * sizeof(*data->bps));
2529 kfree(data->bps);
2530 }
2531
9dc23a63 2532 data->bps = bps;
c030f2e4 2533 data->space_left += align_space - old_space;
2534 return 0;
2535}
2536
2537/* it deal with vram only. */
2538int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
9dc23a63 2539 struct eeprom_table_record *bps, int pages)
c030f2e4 2540{
2541 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
73aa8e1a 2542 struct ras_err_handler_data *data;
c030f2e4 2543 int ret = 0;
676deb38 2544 uint32_t i;
c030f2e4 2545
73aa8e1a 2546 if (!con || !con->eh_data || !bps || pages <= 0)
c030f2e4 2547 return 0;
2548
2549 mutex_lock(&con->recovery_lock);
73aa8e1a 2550 data = con->eh_data;
c030f2e4 2551 if (!data)
2552 goto out;
2553
676deb38
DL		 2554 for (i = 0; i < pages; i++) {
2555 if (amdgpu_ras_check_bad_page_unlock(con,
2556 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2557 continue;
2558
2559 if (!data->space_left &&
2560 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
c030f2e4 2561 ret = -ENOMEM;
2562 goto out;
2563 }
2564
48fa9071 2565 amdgpu_ras_reserve_page(adev, bps[i].retired_page);
9dc23a63 2566
676deb38
DL		 2567 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2568 data->count++;
2569 data->space_left--;
2570 }
c030f2e4 2571out:
2572 mutex_unlock(&con->recovery_lock);
2573
2574 return ret;
2575}
2576
78ad00c9
TZ		 2577/*
2578 * write error record array to eeprom, the function should be
2579 * protected by recovery_lock
4d33e0f1 2580 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
78ad00c9 2581 */
4d33e0f1
TZ		 2582int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2583 unsigned long *new_cnt)
78ad00c9
TZ		 2584{
2585 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2586 struct ras_err_handler_data *data;
8a3e801f 2587 struct amdgpu_ras_eeprom_control *control;
78ad00c9
TZ		 2588 int save_count;
2589
4d33e0f1
TZ		 2590 if (!con || !con->eh_data) {
2591 if (new_cnt)
2592 *new_cnt = 0;
2593
78ad00c9 2594 return 0;
4d33e0f1 2595 }
78ad00c9 2596
d9a69fe5 2597 mutex_lock(&con->recovery_lock);
8a3e801f 2598 control = &con->eeprom_control;
78ad00c9 2599 data = con->eh_data;
0686627b 2600 save_count = data->count - control->ras_num_recs;
d9a69fe5 2601 mutex_unlock(&con->recovery_lock);
4d33e0f1
TZ		 2602
2603 if (new_cnt)
2604 *new_cnt = save_count / adev->umc.retire_unit;
2605
78ad00c9 2606 /* only new entries are saved */
b1628425 2607 if (save_count > 0) {
63d4c081
LT		 2608 if (amdgpu_ras_eeprom_append(control,
2609 &data->bps[control->ras_num_recs],
2610 save_count)) {
6952e99c 2611 dev_err(adev->dev, "Failed to save EEPROM table data!");
78ad00c9
TZ		 2612 return -EIO;
2613 }
2614
b1628425
GC		 2615 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2616 }
2617
78ad00c9
TZ		 2618 return 0;
2619}
2620
2621/*
2622 * read error record array in eeprom and reserve enough space for
2623 * storing new bad pages
2624 */
2625static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2626{
2627 struct amdgpu_ras_eeprom_control *control =
6457205c 2628 &adev->psp.ras_context.ras->eeprom_control;
e4e6a589
LT		 2629 struct eeprom_table_record *bps;
2630 int ret;
78ad00c9
TZ		 2631
2632 /* no bad page record, skip eeprom access */
0686627b 2633 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
e4e6a589 2634 return 0;
78ad00c9 2635
0686627b 2636 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
78ad00c9
TZ		 2637 if (!bps)
2638 return -ENOMEM;
2639
0686627b 2640 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
e4e6a589 2641 if (ret)
6952e99c 2642 dev_err(adev->dev, "Failed to load EEPROM table records!");
e4e6a589 2643 else
0686627b 2644 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
78ad00c9 2645
78ad00c9
TZ		 2646 kfree(bps);
2647 return ret;
2648}
2649
676deb38
DL		 2650static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2651 uint64_t addr)
2652{
2653 struct ras_err_handler_data *data = con->eh_data;
2654 int i;
2655
2656 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2657 for (i = 0; i < data->count; i++)
2658 if (addr == data->bps[i].retired_page)
2659 return true;
2660
2661 return false;
2662}
2663
6e4be987
TZ		 2664/*
2665 * check if an address belongs to bad page
2666 *
2667 * Note: this check is only for umc block
2668 */
2669static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2670 uint64_t addr)
2671{
2672 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
6e4be987
TZ		 2673 bool ret = false;
2674
2675 if (!con || !con->eh_data)
2676 return ret;
2677
2678 mutex_lock(&con->recovery_lock);
676deb38 2679 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
6e4be987
TZ		 2680 mutex_unlock(&con->recovery_lock);
2681 return ret;
2682}
2683
e5c04edf 2684static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
e4e6a589 2685 uint32_t max_count)
c84d4670 2686{
e5c04edf 2687 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c84d4670
GC		 2688
2689 /*
2690 * Justification of value bad_page_cnt_threshold in ras structure
2691 *
f3cbe70e
TZ		 2692 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2693 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2694 * scenarios accordingly.
c84d4670
GC		 2695 *
2696 * Bad page retirement enablement:
f3cbe70e 2697 * - If amdgpu_bad_page_threshold = -2,
c84d4670
GC		 2698 * bad_page_cnt_threshold = typical value by formula.
2699 *
2700 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2701 * max record length in eeprom, use it directly.
2702 *
2703 * Bad page retirement disablement:
2704 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2705 * functionality is disabled, and bad_page_cnt_threshold will
2706 * take no effect.
2707 */
2708
e4e6a589
LT		 2709 if (amdgpu_bad_page_threshold < 0) {
2710 u64 val = adev->gmc.mc_vram_size;
c84d4670 2711
e4e6a589 2712 do_div(val, RAS_BAD_PAGE_COVER);
e5c04edf 2713 con->bad_page_cnt_threshold = min(lower_32_bits(val),
e4e6a589 2714 max_count);
e5c04edf 2715 } else {
e4e6a589
LT		 2716 con->bad_page_cnt_threshold = min_t(int, max_count,
2717 amdgpu_bad_page_threshold);
c84d4670
GC		 2718 }
2719}
2720
98b5bc87
YC		 2721int amdgpu_ras_put_poison_req(struct amdgpu_device *adev,
2722 enum amdgpu_ras_block block, uint16_t pasid,
2723 pasid_notify pasid_fn, void *data, uint32_t reset)
2724{
2725 int ret = 0;
2726 struct ras_poison_msg poison_msg;
2727 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2728
2729 memset(&poison_msg, 0, sizeof(poison_msg));
2730 poison_msg.block = block;
2731 poison_msg.pasid = pasid;
2732 poison_msg.reset = reset;
2733 poison_msg.pasid_fn = pasid_fn;
2734 poison_msg.data = data;
2735
2736 ret = kfifo_put(&con->poison_fifo, poison_msg);
2737 if (!ret) {
2738 dev_err(adev->dev, "Poison message fifo is full!\n");
2739 return -ENOSPC;
2740 }
2741
2742 return 0;
2743}
2744
98b5bc87
YC		 2745static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev,
2746 struct ras_poison_msg *poison_msg)
2747{
2748 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2749
2750 return kfifo_get(&con->poison_fifo, poison_msg);
2751}
98b5bc87 2752
f493dd64
YC		 2753static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log)
2754{
2755 mutex_init(&ecc_log->lock);
2756
2757 /* Set any value as siphash key */
2758 memset(&ecc_log->ecc_key, 0xad, sizeof(ecc_log->ecc_key));
2759
2760 INIT_RADIX_TREE(&ecc_log->de_page_tree, GFP_KERNEL);
2761 ecc_log->de_updated = false;
2762}
2763
2764static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log)
2765{
2766 struct radix_tree_iter iter;
2767 void __rcu **slot;
2768 struct ras_ecc_err *ecc_err;
2769
2770 mutex_lock(&ecc_log->lock);
2771 radix_tree_for_each_slot(slot, &ecc_log->de_page_tree, &iter, 0) {
2772 ecc_err = radix_tree_deref_slot(slot);
2773 kfree(ecc_err->err_pages.pfn);
2774 kfree(ecc_err);
2775 radix_tree_iter_delete(&ecc_log->de_page_tree, &iter, slot);
2776 }
2777 mutex_unlock(&ecc_log->lock);
2778
2779 mutex_destroy(&ecc_log->lock);
2780 ecc_log->de_updated = false;
2781}
a734adfb 2782
2cf8e50e
YC		 2783static void amdgpu_ras_do_page_retirement(struct work_struct *work)
2784{
2785 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2786 page_retirement_dwork.work);
2787 struct amdgpu_device *adev = con->adev;
2788 struct ras_err_data err_data;
2789
2790 if (amdgpu_in_reset(adev) || atomic_read(&con->in_recovery))
2791 return;
2792
2793 amdgpu_ras_error_data_init(&err_data);
2794
2795 amdgpu_umc_handle_bad_pages(adev, &err_data);
2796
2797 amdgpu_ras_error_data_fini(&err_data);
2798
2799 mutex_lock(&con->umc_ecc_log.lock);
2800 if (radix_tree_tagged(&con->umc_ecc_log.de_page_tree,
2801 UMC_ECC_NEW_DETECTED_TAG))
2802 schedule_delayed_work(&con->page_retirement_dwork,
2803 msecs_to_jiffies(AMDGPU_RAS_RETIRE_PAGE_INTERVAL));
2804 mutex_unlock(&con->umc_ecc_log.lock);
2805}
2806
a734adfb
YC		 2807static int amdgpu_ras_query_ecc_status(struct amdgpu_device *adev,
2808 enum amdgpu_ras_block ras_block, uint32_t timeout_ms)
2809{
2810 int ret = 0;
2811 struct ras_ecc_log_info *ecc_log;
2812 struct ras_query_if info;
2813 uint32_t timeout = timeout_ms;
2814 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2815
2816 memset(&info, 0, sizeof(info));
2817 info.head.block = ras_block;
2818
2819 ecc_log = &ras->umc_ecc_log;
2820 ecc_log->de_updated = false;
2821 do {
2822 ret = amdgpu_ras_query_error_status(adev, &info);
2823 if (ret) {
2824 dev_err(adev->dev, "Failed to query ras error! ret:%d\n", ret);
2825 return ret;
2826 }
2827
2828 if (timeout && !ecc_log->de_updated) {
2829 msleep(1);
2830 timeout--;
2831 }
2832 } while (timeout && !ecc_log->de_updated);
2833
2834 if (timeout_ms && !timeout) {
2835 dev_warn(adev->dev, "Can't find deferred error\n");
2836 return -ETIMEDOUT;
2837 }
2838
2839 return 0;
2840}
2841
2842static void amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev,
2843 uint32_t timeout)
2844{
2cf8e50e
YC		 2845 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2846 int ret;
2847
2848 ret = amdgpu_ras_query_ecc_status(adev, AMDGPU_RAS_BLOCK__UMC, timeout);
2849 if (!ret)
2850 schedule_delayed_work(&con->page_retirement_dwork, 0);
a734adfb
YC		 2851}
2852
370fbff4
YC		 2853static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev,
2854 struct ras_poison_msg *poison_msg)
2855{
2856 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2857 uint32_t reset = poison_msg->reset;
2858 uint16_t pasid = poison_msg->pasid;
2859
2860 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
2861
2862 if (poison_msg->pasid_fn)
2863 poison_msg->pasid_fn(adev, pasid, poison_msg->data);
2864
2865 if (reset) {
2866 flush_delayed_work(&con->page_retirement_dwork);
2867
2868 con->gpu_reset_flags |= reset;
2869 amdgpu_ras_reset_gpu(adev);
2870 }
2871
2872 return 0;
2873}
2874
3fdcd0a3
YC		 2875static int amdgpu_ras_page_retirement_thread(void *param)
2876{
2877 struct amdgpu_device *adev = (struct amdgpu_device *)param;
2878 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
a734adfb
YC		 2879 struct ras_poison_msg poison_msg;
2880 enum amdgpu_ras_block ras_block;
370fbff4 2881 bool poison_creation_is_handled = false;
3fdcd0a3
YC		 2882
2883 while (!kthread_should_stop()) {
2884
2885 wait_event_interruptible(con->page_retirement_wq,
c84a7e21 2886 kthread_should_stop() ||
3fdcd0a3
YC		 2887 atomic_read(&con->page_retirement_req_cnt));
2888
c84a7e21
MJ		 2889 if (kthread_should_stop())
2890 break;
2891
3fdcd0a3 2892 atomic_dec(&con->page_retirement_req_cnt);
6c23f3d1 2893
a734adfb
YC		 2894 if (!amdgpu_ras_get_poison_req(adev, &poison_msg))
2895 continue;
2896
2897 ras_block = poison_msg.block;
2898
2899 dev_info(adev->dev, "Start processing ras block %s(%d)\n",
2900 ras_block_str(ras_block), ras_block);
2901
370fbff4 2902 if (ras_block == AMDGPU_RAS_BLOCK__UMC) {
a734adfb
YC		 2903 amdgpu_ras_poison_creation_handler(adev,
2904 MAX_UMC_POISON_POLLING_TIME_ASYNC);
370fbff4
YC		 2905 poison_creation_is_handled = true;
2906 } else {
2907 /* poison_creation_is_handled:
2908 * false: no poison creation interrupt, but it has poison
2909 * consumption interrupt.
2910 * true: It has poison creation interrupt at the beginning,
2911 * but it has no poison creation interrupt later.
2912 */
2913 amdgpu_ras_poison_creation_handler(adev,
2914 poison_creation_is_handled ?
2915 0 : MAX_UMC_POISON_POLLING_TIME_ASYNC);
2916
2917 amdgpu_ras_poison_consumption_handler(adev, &poison_msg);
2918 poison_creation_is_handled = false;
2919 }
3fdcd0a3
YC		 2920 }
2921
2922 return 0;
2923}
2924
1a6fc071 2925int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
c030f2e4 2926{
2927 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4d1337d2 2928 struct ras_err_handler_data **data;
e4e6a589 2929 u32 max_eeprom_records_count = 0;
b82e65a9 2930 bool exc_err_limit = false;
78ad00c9 2931 int ret;
c030f2e4 2932
e0e146d5 2933 if (!con || amdgpu_sriov_vf(adev))
1d9d2ca8
LT		 2934 return 0;
2935
2936 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2937 * supports RAS and debugfs is enabled, but when
2938 * adev->ras_enabled is unset, i.e. when "ras_enable"
2939 * module parameter is set to 0.
2940 */
2941 con->adev = adev;
2942
2943 if (!adev->ras_enabled)
4d1337d2
AG		 2944 return 0;
2945
1d9d2ca8 2946 data = &con->eh_data;
091411be 2947 *data = kzalloc(sizeof(**data), GFP_KERNEL);
1a6fc071
TZ		 2948 if (!*data) {
2949 ret = -ENOMEM;
2950 goto out;
2951 }
c030f2e4 2952
2953 mutex_init(&con->recovery_lock);
2954 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2955 atomic_set(&con->in_recovery, 0);
69691c82 2956 con->eeprom_control.bad_channel_bitmap = 0;
c030f2e4 2957
7f599fed 2958 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
e4e6a589 2959 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
c84d4670 2960
e5086659 2961 /* Todo: During test the SMU might fail to read the eeprom through I2C
2962 * when the GPU is pending on XGMI reset during probe time
2963 * (Mostly after second bus reset), skip it now
2964 */
2965 if (adev->gmc.xgmi.pending_reset)
2966 return 0;
b82e65a9
GC		 2967 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2968 /*
2969 * This calling fails when exc_err_limit is true or
2970 * ret != 0.
2971 */
2972 if (exc_err_limit || ret)
1a6fc071 2973 goto free;
78ad00c9 2974
0686627b 2975 if (con->eeprom_control.ras_num_recs) {
78ad00c9
TZ		 2976 ret = amdgpu_ras_load_bad_pages(adev);
2977 if (ret)
1a6fc071 2978 goto free;
513befa6 2979
bc143d8b 2980 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
69691c82
SY		 2981
2982 if (con->update_channel_flag == true) {
2983 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2984 con->update_channel_flag = false;
2985 }
78ad00c9 2986 }
c030f2e4 2987
af730e08 2988 mutex_init(&con->page_rsv_lock);
98b5bc87 2989 INIT_KFIFO(con->poison_fifo);
3fdcd0a3
YC		 2990 mutex_init(&con->page_retirement_lock);
2991 init_waitqueue_head(&con->page_retirement_wq);
2992 atomic_set(&con->page_retirement_req_cnt, 0);
2993 con->page_retirement_thread =
2994 kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement");
2995 if (IS_ERR(con->page_retirement_thread)) {
2996 con->page_retirement_thread = NULL;
2997 dev_warn(adev->dev, "Failed to create umc_page_retirement thread!!!\n");
2998 }
2999
2cf8e50e 3000 INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement);
f493dd64 3001 amdgpu_ras_ecc_log_init(&con->umc_ecc_log);
12b2cab7
MJ		 3002#ifdef CONFIG_X86_MCE_AMD
3003 if ((adev->asic_type == CHIP_ALDEBARAN) &&
3004 (adev->gmc.xgmi.connected_to_cpu))
91a1a52d 3005 amdgpu_register_bad_pages_mca_notifier(adev);
12b2cab7 3006#endif
c030f2e4 3007 return 0;
1a6fc071 3008
1a6fc071 3009free:
1a6fc071 3010 kfree((*data)->bps);
1a6fc071 3011 kfree(*data);
1995b3a3 3012 con->eh_data = NULL;
1a6fc071 3013out:
cf696091 3014 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
1a6fc071 3015
b82e65a9
GC		 3016 /*
3017 * Except error threshold exceeding case, other failure cases in this
3018 * function would not fail amdgpu driver init.
3019 */
3020 if (!exc_err_limit)
3021 ret = 0;
3022 else
3023 ret = -EINVAL;
3024
1a6fc071 3025 return ret;
c030f2e4 3026}
3027
3028static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
3029{
3030 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3031 struct ras_err_handler_data *data = con->eh_data;
3032
1a6fc071
TZ		 3033 /* recovery_init failed to init it, fini is useless */
3034 if (!data)
3035 return 0;
3036
3fdcd0a3
YC		 3037 if (con->page_retirement_thread)
3038 kthread_stop(con->page_retirement_thread);
3039
3040 atomic_set(&con->page_retirement_req_cnt, 0);
3041
af730e08
YC		 3042 mutex_destroy(&con->page_rsv_lock);
3043
c030f2e4 3044 cancel_work_sync(&con->recovery_work);
c030f2e4 3045
2cf8e50e
YC		 3046 cancel_delayed_work_sync(&con->page_retirement_dwork);
3047
f493dd64
YC		 3048 amdgpu_ras_ecc_log_fini(&con->umc_ecc_log);
3049
c030f2e4 3050 mutex_lock(&con->recovery_lock);
3051 con->eh_data = NULL;
3052 kfree(data->bps);
3053 kfree(data);
3054 mutex_unlock(&con->recovery_lock);
3055
3056 return 0;
3057}
3058/* recovery end */
3059
084e2640 3060static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
5436ab94 3061{
82835055 3062 if (amdgpu_sriov_vf(adev)) {
4e8303cf 3063 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
82835055 3064 case IP_VERSION(13, 0, 2):
80578f16 3065 case IP_VERSION(13, 0, 6):
82835055
YC		 3066 return true;
3067 default:
3068 return false;
3069 }
3070 }
3071
073285ef 3072 if (adev->asic_type == CHIP_IP_DISCOVERY) {
4e8303cf 3073 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
073285ef 3074 case IP_VERSION(13, 0, 0):
cb906ce3 3075 case IP_VERSION(13, 0, 6):
073285ef
YC		 3076 case IP_VERSION(13, 0, 10):
3077 return true;
3078 default:
3079 return false;
3080 }
3081 }
3082
084e2640
LT		 3083 return adev->asic_type == CHIP_VEGA10 ||
3084 adev->asic_type == CHIP_VEGA20 ||
3085 adev->asic_type == CHIP_ARCTURUS ||
75f06251 3086 adev->asic_type == CHIP_ALDEBARAN ||
084e2640 3087 adev->asic_type == CHIP_SIENNA_CICHLID;
5436ab94
SY		 3088}
3089
f50160cf
SY		 3090/*
3091 * this is workaround for vega20 workstation sku,
3092 * force enable gfx ras, ignore vbios gfx ras flag
3093 * due to GC EDC can not write
3094 */
e509965e 3095static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
f50160cf
SY		 3096{
3097 struct atom_context *ctx = adev->mode_info.atom_context;
3098
3099 if (!ctx)
3100 return;
3101
adf64e21
ML		 3102 if (strnstr(ctx->vbios_pn, "D16406",
3103 sizeof(ctx->vbios_pn)) ||
3104 strnstr(ctx->vbios_pn, "D36002",
3105 sizeof(ctx->vbios_pn)))
8ab0d6f0 3106 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
f50160cf
SY		 3107}
3108
4e2965bd
HZ		 3109/* Query ras capablity via atomfirmware interface */
3110static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev)
3111{
3112 /* mem_ecc cap */
3113 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
3114 dev_info(adev->dev, "MEM ECC is active.\n");
3115 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
3116 1 << AMDGPU_RAS_BLOCK__DF);
3117 } else {
3118 dev_info(adev->dev, "MEM ECC is not presented.\n");
3119 }
3120
3121 /* sram_ecc cap */
3122 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
3123 dev_info(adev->dev, "SRAM ECC is active.\n");
3124 if (!amdgpu_sriov_vf(adev))
3125 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
3126 1 << AMDGPU_RAS_BLOCK__DF);
3127 else
3128 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
3129 1 << AMDGPU_RAS_BLOCK__SDMA |
3130 1 << AMDGPU_RAS_BLOCK__GFX);
3131
3132 /*
3133 * VCN/JPEG RAS can be supported on both bare metal and
3134 * SRIOV environment
3135 */
3136 if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) ||
3137 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) ||
3138 amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3))
3139 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
3140 1 << AMDGPU_RAS_BLOCK__JPEG);
3141 else
3142 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
3143 1 << AMDGPU_RAS_BLOCK__JPEG);
3144
3145 /*
3146 * XGMI RAS is not supported if xgmi num physical nodes
3147 * is zero
3148 */
3149 if (!adev->gmc.xgmi.num_physical_nodes)
3150 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
3151 } else {
3152 dev_info(adev->dev, "SRAM ECC is not presented.\n");
3153 }
3154}
3155
3156/* Query poison mode from umc/df IP callbacks */
3157static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
3158{
3159 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3160 bool df_poison, umc_poison;
3161
3162 /* poison setting is useless on SRIOV guest */
3163 if (amdgpu_sriov_vf(adev) || !con)
3164 return;
3165
3166 /* Init poison supported flag, the default value is false */
3167 if (adev->gmc.xgmi.connected_to_cpu ||
3168 adev->gmc.is_app_apu) {
3169 /* enabled by default when GPU is connected to CPU */
3170 con->poison_supported = true;
3171 } else if (adev->df.funcs &&
3172 adev->df.funcs->query_ras_poison_mode &&
3173 adev->umc.ras &&
3174 adev->umc.ras->query_ras_poison_mode) {
3175 df_poison =
3176 adev->df.funcs->query_ras_poison_mode(adev);
3177 umc_poison =
3178 adev->umc.ras->query_ras_poison_mode(adev);
3179
3180 /* Only poison is set in both DF and UMC, we can support it */
3181 if (df_poison && umc_poison)
3182 con->poison_supported = true;
3183 else if (df_poison != umc_poison)
3184 dev_warn(adev->dev,
3185 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
3186 df_poison, umc_poison);
3187 }
3188}
3189
5caf466a 3190/*
3191 * check hardware's ras ability which will be saved in hw_supported.
3192 * if hardware does not support ras, we can skip some ras initializtion and
3193 * forbid some ras operations from IP.
3194 * if software itself, say boot parameter, limit the ras ability. We still
3195 * need allow IP do some limited operations, like disable. In such case,
3196 * we have to initialize ras as normal. but need check if operation is
3197 * allowed or not in each function.
3198 */
e509965e 3199static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
c030f2e4 3200{
8ab0d6f0 3201 adev->ras_hw_enabled = adev->ras_enabled = 0;
c030f2e4 3202
38298ce6 3203 if (!amdgpu_ras_asic_supported(adev))
5caf466a 3204 return;
b404ae82 3205
4e2965bd
HZ		 3206 /* query ras capability from psp */
3207 if (amdgpu_psp_get_ras_capability(&adev->psp))
3208 goto init_ras_enabled_flag;
58bc2a9c 3209
4e2965bd
HZ		 3210 /* query ras capablity from bios */
3211 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
3212 amdgpu_ras_query_ras_capablity_from_vbios(adev);
75f06251
HZ		 3213 } else {
3214 /* driver only manages a few IP blocks RAS feature
3215 * when GPU is connected cpu through XGMI */
8ab0d6f0 3216 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
e509965e
LT		 3217 1 << AMDGPU_RAS_BLOCK__SDMA |
3218 1 << AMDGPU_RAS_BLOCK__MMHUB);
75f06251 3219 }
88474cca 3220
4e2965bd 3221 /* apply asic specific settings (vega20 only for now) */
e509965e 3222 amdgpu_ras_get_quirks(adev);
f50160cf 3223
4e2965bd
HZ		 3224 /* query poison mode from umc/df ip callback */
3225 amdgpu_ras_query_poison_mode(adev);
3226
3227init_ras_enabled_flag:
88474cca 3228 /* hw_supported needs to be aligned with RAS block mask. */
8ab0d6f0 3229 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
b404ae82 3230
66d64e4e
SY		 3231 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
3232 adev->ras_hw_enabled & amdgpu_ras_mask;
04c4fcd2
YW		 3233
3234 /* aca is disabled by default */
3235 adev->aca.is_enabled = false;
c030f2e4 3236}
3237
05adfd80
LT		 3238static void amdgpu_ras_counte_dw(struct work_struct *work)
3239{
3240 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
3241 ras_counte_delay_work.work);
3242 struct amdgpu_device *adev = con->adev;
a3fbb0d8 3243 struct drm_device *dev = adev_to_drm(adev);
05adfd80
LT		 3244 unsigned long ce_count, ue_count;
3245 int res;
3246
3247 res = pm_runtime_get_sync(dev->dev);
3248 if (res < 0)
3249 goto Out;
3250
3251 /* Cache new values.
3252 */
4a1c9a44 3253 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
4d9f771e
LT		 3254 atomic_set(&con->ras_ce_count, ce_count);
3255 atomic_set(&con->ras_ue_count, ue_count);
3256 }
05adfd80
LT		 3257
3258 pm_runtime_mark_last_busy(dev->dev);
3259Out:
3260 pm_runtime_put_autosuspend(dev->dev);
3261}
3262
625e5f38
AK		 3263static int amdgpu_get_ras_schema(struct amdgpu_device *adev)
3264{
3265 return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 |
3266 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE |
3267 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE |
3268 AMDGPU_RAS_ERROR__PARITY;
3269}
3270
9dc57c2a
YW		 3271static void ras_event_mgr_init(struct ras_event_manager *mgr)
3272{
3273 int i;
3274
3275 for (i = 0; i < ARRAY_SIZE(mgr->seqnos); i++)
3276 atomic64_set(&mgr->seqnos[i], 0);
3277}
3278
3279static void amdgpu_ras_event_mgr_init(struct amdgpu_device *adev)
3280{
3281 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3282 struct amdgpu_hive_info *hive;
3283
3284 if (!ras)
3285 return;
3286
3287 hive = amdgpu_get_xgmi_hive(adev);
3288 ras->event_mgr = hive ? &hive->event_mgr : &ras->__event_mgr;
3289
3290 /* init event manager with node 0 on xgmi system */
3291 if (!amdgpu_in_reset(adev)) {
3292 if (!hive || adev->gmc.xgmi.node_id == 0)
3293 ras_event_mgr_init(ras->event_mgr);
3294 }
3295
3296 if (hive)
3297 amdgpu_put_xgmi_hive(hive);
3298}
3299
c030f2e4 3300int amdgpu_ras_init(struct amdgpu_device *adev)
3301{
3302 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4e644fff 3303 int r;
c030f2e4 3304
b404ae82 3305 if (con)
c030f2e4 3306 return 0;
3307
091411be 3308 con = kzalloc(sizeof(*con) +
640ae42e
JC		 3309 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
3310 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
091411be 3311 GFP_KERNEL);
c030f2e4 3312 if (!con)
3313 return -ENOMEM;
3314
05adfd80
LT		 3315 con->adev = adev;
3316 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
3317 atomic_set(&con->ras_ce_count, 0);
3318 atomic_set(&con->ras_ue_count, 0);
3319
c030f2e4 3320 con->objs = (struct ras_manager *)(con + 1);
3321
3322 amdgpu_ras_set_context(adev, con);
3323
e509965e
LT		 3324 amdgpu_ras_check_supported(adev);
3325
7ddd9770 3326 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
970fd197
SY		 3327 /* set gfx block ras context feature for VEGA20 Gaming
3328 * send ras disable cmd to ras ta during ras late init.
3329 */
8ab0d6f0 3330 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
970fd197
SY		 3331 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
3332
3333 return 0;
3334 }
3335
5e91160a 3336 r = 0;
5436ab94 3337 goto release_con;
fb2a3607
HZ		 3338 }
3339
69691c82 3340 con->update_channel_flag = false;
c030f2e4 3341 con->features = 0;
625e5f38 3342 con->schema = 0;
c030f2e4 3343 INIT_LIST_HEAD(&con->head);
108c6a63 3344 /* Might need get this flag from vbios. */
3345 con->flags = RAS_DEFAULT_FLAGS;
c030f2e4 3346
6e36f231
HZ		 3347 /* initialize nbio ras function ahead of any other
3348 * ras functions so hardware fatal error interrupt
3349 * can be enabled as early as possible */
4e8303cf 3350 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
fdc94d3a
HZ		 3351 case IP_VERSION(7, 4, 0):
3352 case IP_VERSION(7, 4, 1):
3353 case IP_VERSION(7, 4, 4):
3354 if (!adev->gmc.xgmi.connected_to_cpu)
2e54fe5d 3355 adev->nbio.ras = &nbio_v7_4_ras;
6e36f231 3356 break;
9af357bc
HZ		 3357 case IP_VERSION(4, 3, 0):
3358 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
3359 /* unlike other generation of nbio ras,
3360 * nbio v4_3 only support fatal error interrupt
3361 * to inform software that DF is freezed due to
3362 * system fatal error event. driver should not
3363 * enable nbio ras in such case. Instead,
3364 * check DF RAS */
3365 adev->nbio.ras = &nbio_v4_3_ras;
3366 break;
7692e1ee
TZ		 3367 case IP_VERSION(7, 9, 0):
3368 if (!adev->gmc.is_app_apu)
3369 adev->nbio.ras = &nbio_v7_9_ras;
3370 break;
6e36f231
HZ		 3371 default:
3372 /* nbio ras is not available */
3373 break;
3374 }
3375
fdc94d3a
HZ		 3376 /* nbio ras block needs to be enabled ahead of other ras blocks
3377 * to handle fatal error */
3378 r = amdgpu_nbio_ras_sw_init(adev);
3379 if (r)
3380 return r;
3381
2e54fe5d 3382 if (adev->nbio.ras &&
3383 adev->nbio.ras->init_ras_controller_interrupt) {
3384 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
4e644fff 3385 if (r)
5436ab94 3386 goto release_con;
4e644fff
HZ		 3387 }
3388
2e54fe5d 3389 if (adev->nbio.ras &&
3390 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
3391 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
4e644fff 3392 if (r)
5436ab94 3393 goto release_con;
4e644fff
HZ		 3394 }
3395
73cb81dc
HZ		 3396 /* Packed socket_id to ras feature mask bits[31:29] */
3397 if (adev->smuio.funcs &&
3398 adev->smuio.funcs->get_socket_id)
ee9c3031
SY		 3399 con->features |= ((adev->smuio.funcs->get_socket_id(adev)) <<
3400 AMDGPU_RAS_FEATURES_SOCKETID_SHIFT);
73cb81dc 3401
625e5f38
AK		 3402 /* Get RAS schema for particular SOC */
3403 con->schema = amdgpu_get_ras_schema(adev);
3404
5e91160a
GC		 3405 if (amdgpu_ras_fs_init(adev)) {
3406 r = -EINVAL;
5436ab94 3407 goto release_con;
5e91160a 3408 }
c030f2e4 3409
6952e99c 3410 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
e509965e 3411 "hardware ability[%x] ras_mask[%x]\n",
8ab0d6f0 3412 adev->ras_hw_enabled, adev->ras_enabled);
e509965e 3413
c030f2e4 3414 return 0;
5436ab94 3415release_con:
c030f2e4 3416 amdgpu_ras_set_context(adev, NULL);
3417 kfree(con);
3418
5e91160a 3419 return r;
c030f2e4 3420}
3421
8f6368a9 3422int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
134d16d5 3423{
8107e499
HZ		 3424 if (adev->gmc.xgmi.connected_to_cpu ||
3425 adev->gmc.is_app_apu)
134d16d5
JC		 3426 return 1;
3427 return 0;
3428}
3429
3430static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
3431 struct ras_common_if *ras_block)
3432{
3433 struct ras_query_if info = {
3434 .head = *ras_block,
3435 };
3436
3437 if (!amdgpu_persistent_edc_harvesting_supported(adev))
3438 return 0;
3439
3440 if (amdgpu_ras_query_error_status(adev, &info) != 0)
3441 DRM_WARN("RAS init harvest failure");
3442
3443 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
3444 DRM_WARN("RAS init harvest reset failure");
3445
3446 return 0;
3447}
3448
e4348849
TZ		 3449bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
3450{
3451 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3452
3453 if (!con)
3454 return false;
3455
3456 return con->poison_supported;
3457}
3458
b293e891 3459/* helper function to handle common stuff in ip late init phase */
563285c8 3460int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
3461 struct ras_common_if *ras_block)
b293e891 3462{
29c9b6cd 3463 struct amdgpu_ras_block_object *ras_obj = NULL;
05adfd80 3464 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4a1c9a44 3465 struct ras_query_if *query_info;
05adfd80 3466 unsigned long ue_count, ce_count;
b293e891
HZ		 3467 int r;
3468
3469 /* disable RAS feature per IP block if it is not supported */
3470 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
3471 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
3472 return 0;
3473 }
3474
3475 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
3476 if (r) {
9080a18f 3477 if (adev->in_suspend || amdgpu_in_reset(adev)) {
b293e891
HZ		 3478 /* in resume phase, if fail to enable ras,
3479 * clean up all ras fs nodes, and disable ras */
3480 goto cleanup;
3481 } else
3482 return r;
3483 }
3484
134d16d5
JC		 3485 /* check for errors on warm reset edc persisant supported ASIC */
3486 amdgpu_persistent_edc_harvesting(adev, ras_block);
3487
b293e891 3488 /* in resume phase, no need to create ras fs node */
53b3f8f4 3489 if (adev->in_suspend || amdgpu_in_reset(adev))
b293e891
HZ		 3490 return 0;
3491
563285c8 3492 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
36780606
TZ		 3493 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
3494 (ras_obj->hw_ops->query_poison_status ||
3495 ras_obj->hw_ops->handle_poison_consumption))) {
9252d33d 3496 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
b293e891 3497 if (r)
779596ce 3498 goto cleanup;
b293e891
HZ		 3499 }
3500
f957138c
HZ		 3501 if (ras_obj->hw_ops &&
3502 (ras_obj->hw_ops->query_ras_error_count ||
3503 ras_obj->hw_ops->query_ras_error_status)) {
3504 r = amdgpu_ras_sysfs_create(adev, ras_block);
3505 if (r)
3506 goto interrupt;
b293e891 3507
f957138c
HZ		 3508 /* Those are the cached values at init.
3509 */
3510 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
3511 if (!query_info)
3512 return -ENOMEM;
3513 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
4a1c9a44 3514
f957138c
HZ		 3515 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
3516 atomic_set(&con->ras_ce_count, ce_count);
3517 atomic_set(&con->ras_ue_count, ue_count);
3518 }
3519
3520 kfree(query_info);
4d9f771e 3521 }
05adfd80 3522
b293e891 3523 return 0;
779596ce
TR		 3524
3525interrupt:
563285c8 3526 if (ras_obj->ras_cb)
9252d33d 3527 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
779596ce 3528cleanup:
b293e891
HZ		 3529 amdgpu_ras_feature_enable(adev, ras_block, 0);
3530 return r;
3531}
3532
d41ff22a 3533static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
418abce2 3534 struct ras_common_if *ras_block)
3535{
3536 return amdgpu_ras_block_late_init(adev, ras_block);
3537}
3538
b293e891 3539/* helper function to remove ras fs node and interrupt handler */
bdb3489c 3540void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
3541 struct ras_common_if *ras_block)
3542{
563285c8 3543 struct amdgpu_ras_block_object *ras_obj;
bdb3489c 3544 if (!ras_block)
3545 return;
3546
563285c8 3547 amdgpu_ras_sysfs_remove(adev, ras_block);
bdb3489c 3548
563285c8 3549 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
3550 if (ras_obj->ras_cb)
3551 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
bdb3489c 3552}
3553
80e0c2cb 3554static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
3555 struct ras_common_if *ras_block)
3556{
3557 return amdgpu_ras_block_late_fini(adev, ras_block);
3558}
3559
a564808e 3560/* do some init work after IP late init as dependence.
511fdbc3 3561 * and it runs in resume/gpu reset/booting up cases.
a564808e 3562 */
511fdbc3 3563void amdgpu_ras_resume(struct amdgpu_device *adev)
108c6a63 3564{
3565 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3566 struct ras_manager *obj, *tmp;
3567
8ab0d6f0 3568 if (!adev->ras_enabled || !con) {
970fd197
SY		 3569 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
3570 amdgpu_release_ras_context(adev);
3571
108c6a63 3572 return;
970fd197 3573 }
108c6a63 3574
108c6a63 3575 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
191051a1 3576 /* Set up all other IPs which are not implemented. There is a
3577 * tricky thing that IP's actual ras error type should be
3578 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
3579 * ERROR_NONE make sense anyway.
3580 */
3581 amdgpu_ras_enable_all_features(adev, 1);
3582
3583 /* We enable ras on all hw_supported block, but as boot
3584 * parameter might disable some of them and one or more IP has
3585 * not implemented yet. So we disable them on behalf.
3586 */
108c6a63 3587 list_for_each_entry_safe(obj, tmp, &con->head, node) {
3588 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
3589 amdgpu_ras_feature_enable(adev, &obj->head, 0);
3590 /* there should be no any reference. */
3591 WARN_ON(alive_obj(obj));
3592 }
191051a1 3593 }
108c6a63 3594 }
3595}
3596
511fdbc3 3597void amdgpu_ras_suspend(struct amdgpu_device *adev)
3598{
3599 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3600
8ab0d6f0 3601 if (!adev->ras_enabled || !con)
511fdbc3 3602 return;
3603
3604 amdgpu_ras_disable_all_features(adev, 0);
3605 /* Make sure all ras objects are disabled. */
ee9c3031 3606 if (AMDGPU_RAS_GET_FEATURES(con->features))
511fdbc3 3607 amdgpu_ras_disable_all_features(adev, 1);
3608}
3609
867e24ca 3610int amdgpu_ras_late_init(struct amdgpu_device *adev)
3611{
3612 struct amdgpu_ras_block_list *node, *tmp;
3613 struct amdgpu_ras_block_object *obj;
3614 int r;
3615
950d6425
SY		 3616 /* Guest side doesn't need init ras feature */
3617 if (amdgpu_sriov_vf(adev))
3618 return 0;
3619
9dc57c2a
YW		 3620 amdgpu_ras_event_mgr_init(adev);
3621
c0c48f0d
YW		 3622 if (amdgpu_aca_is_enabled(adev)) {
3623 if (amdgpu_in_reset(adev))
3624 r = amdgpu_aca_reset(adev);
3625 else
3626 r = amdgpu_aca_init(adev);
3627 if (r)
3628 return r;
3629
04c4fcd2 3630 amdgpu_ras_set_aca_debug_mode(adev, false);
c0c48f0d 3631 } else {
04c4fcd2 3632 amdgpu_ras_set_mca_debug_mode(adev, false);
c0c48f0d 3633 }
201761b5 3634
867e24ca 3635 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2866a454
YW		 3636 obj = node->ras_obj;
3637 if (!obj) {
867e24ca 3638 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
3639 continue;
3640 }
418abce2 3641
2866a454
YW		 3642 if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block))
3643 continue;
3644
867e24ca 3645 if (obj->ras_late_init) {
3646 r = obj->ras_late_init(adev, &obj->ras_comm);
3647 if (r) {
3648 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
3649 obj->ras_comm.name, r);
3650 return r;
3651 }
418abce2 3652 } else
3653 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
867e24ca 3654 }
3655
3656 return 0;
3657}
3658
c030f2e4 3659/* do some fini work before IP fini as dependence */
3660int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
3661{
3662 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3663
8ab0d6f0 3664 if (!adev->ras_enabled || !con)
c030f2e4 3665 return 0;
3666
72c8c97b 3667
c030f2e4 3668 /* Need disable ras on all IPs here before ip [hw/sw]fini */
ee9c3031 3669 if (AMDGPU_RAS_GET_FEATURES(con->features))
642c0401 3670 amdgpu_ras_disable_all_features(adev, 0);
c030f2e4 3671 amdgpu_ras_recovery_fini(adev);
3672 return 0;
3673}
3674
3675int amdgpu_ras_fini(struct amdgpu_device *adev)
3676{
d5e8ff5f 3677 struct amdgpu_ras_block_list *ras_node, *tmp;
1f211a82 3678 struct amdgpu_ras_block_object *obj = NULL;
c030f2e4 3679 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3680
8ab0d6f0 3681 if (!adev->ras_enabled || !con)
c030f2e4 3682 return 0;
3683
1f211a82 3684 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
3685 if (ras_node->ras_obj) {
3686 obj = ras_node->ras_obj;
3687 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
3688 obj->ras_fini)
3689 obj->ras_fini(adev, &obj->ras_comm);
80e0c2cb 3690 else
3691 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
1f211a82 3692 }
3693
3694 /* Clear ras blocks from ras_list and free ras block list node */
3695 list_del(&ras_node->node);
3696 kfree(ras_node);
3697 }
3698
c030f2e4 3699 amdgpu_ras_fs_fini(adev);
3700 amdgpu_ras_interrupt_remove_all(adev);
3701
c0c48f0d
YW		 3702 if (amdgpu_aca_is_enabled(adev))
3703 amdgpu_aca_fini(adev);
3704
ee9c3031 3705 WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not cleared");
c030f2e4 3706
ee9c3031 3707 if (AMDGPU_RAS_GET_FEATURES(con->features))
edfdde90 3708 amdgpu_ras_disable_all_features(adev, 0);
c030f2e4 3709
05adfd80
LT		 3710 cancel_delayed_work_sync(&con->ras_counte_delay_work);
3711
c030f2e4 3712 amdgpu_ras_set_context(adev, NULL);
3713 kfree(con);
3714
3715 return 0;
3716}
7c6e68c7 3717
1b6ef74b
LL		 3718bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev)
3719{
3720 struct amdgpu_ras *ras;
3721
3722 ras = amdgpu_ras_get_context(adev);
3723 if (!ras)
3724 return false;
3725
3726 return atomic_read(&ras->fed);
3727}
3728
3729void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status)
3730{
3731 struct amdgpu_ras *ras;
3732
3733 ras = amdgpu_ras_get_context(adev);
3734 if (ras)
3735 atomic_set(&ras->fed, !!status);
3736}
3737
9dc57c2a
YW		 3738bool amdgpu_ras_event_id_is_valid(struct amdgpu_device *adev, u64 id)
3739{
3740 return !(id & BIT_ULL(63));
3741}
3742
3743u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type)
3744{
3745 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3746 u64 id;
3747
3748 switch (type) {
3749 case RAS_EVENT_TYPE_ISR:
3750 id = (u64)atomic64_read(&ras->event_mgr->seqnos[type]);
3751 break;
3752 case RAS_EVENT_TYPE_INVALID:
3753 default:
3754 id = BIT_ULL(63) | 0ULL;
3755 break;
3756 }
3757
3758 return id;
3759}
3760
7c6e68c7
AG		 3761void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
3762{
3763 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2c7cd280 3764 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
9dc57c2a 3765 u64 event_id = (u64)atomic64_inc_return(&ras->event_mgr->seqnos[RAS_EVENT_TYPE_ISR]);
2c7cd280 3766
9dc57c2a
YW		 3767 RAS_EVENT_LOG(adev, event_id, "uncorrectable hardware error"
3768 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
d5ea093e 3769
b41f742d 3770 amdgpu_ras_set_fed(adev, true);
2c7cd280 3771 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
61934624 3772 amdgpu_ras_reset_gpu(adev);
7c6e68c7
AG		 3773 }
3774}
bb5c7235
WS		 3775
3776bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
3777{
3778 if (adev->asic_type == CHIP_VEGA20 &&
3779 adev->pm.fw_version <= 0x283400) {
3780 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
3781 amdgpu_ras_intr_triggered();
3782 }
3783
3784 return false;
3785}
970fd197
SY		 3786
3787void amdgpu_release_ras_context(struct amdgpu_device *adev)
3788{
3789 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3790
3791 if (!con)
3792 return;
3793
8ab0d6f0 3794 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
970fd197
SY		 3795 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3796 amdgpu_ras_set_context(adev, NULL);
3797 kfree(con);
3798 }
3799}
12b2cab7
MJ		 3800
3801#ifdef CONFIG_X86_MCE_AMD
3802static struct amdgpu_device *find_adev(uint32_t node_id)
3803{
12b2cab7
MJ		 3804 int i;
3805 struct amdgpu_device *adev = NULL;
3806
91a1a52d
MJ		 3807 for (i = 0; i < mce_adev_list.num_gpu; i++) {
3808 adev = mce_adev_list.devs[i];
12b2cab7 3809
91a1a52d 3810 if (adev && adev->gmc.xgmi.connected_to_cpu &&
12b2cab7
MJ		 3811 adev->gmc.xgmi.physical_node_id == node_id)
3812 break;
3813 adev = NULL;
3814 }
3815
12b2cab7
MJ		 3816 return adev;
3817}
3818
3819#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
3820#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
3821#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3822#define GPU_ID_OFFSET 8
3823
3824static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3825 unsigned long val, void *data)
3826{
3827 struct mce *m = (struct mce *)data;
3828 struct amdgpu_device *adev = NULL;
3829 uint32_t gpu_id = 0;
cd4c99f1 3830 uint32_t umc_inst = 0, ch_inst = 0;
12b2cab7
MJ		 3831
3832 /*
3833 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3834 * and error occurred in DramECC (Extended error code = 0) then only
3835 * process the error, else bail out.
3836 */
91f75eb4 3837 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
12b2cab7
MJ		 3838 (XEC(m->status, 0x3f) == 0x0)))
3839 return NOTIFY_DONE;
3840
3841 /*
3842 * If it is correctable error, return.
3843 */
3844 if (mce_is_correctable(m))
3845 return NOTIFY_OK;
3846
3847 /*
3848 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3849 */
3850 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3851
3852 adev = find_adev(gpu_id);
3853 if (!adev) {
3854 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3855 gpu_id);
3856 return NOTIFY_DONE;
3857 }
3858
3859 /*
3860 * If it is uncorrectable error, then find out UMC instance and
3861 * channel index.
3862 */
3863 umc_inst = GET_UMC_INST(m->ipid);
3864 ch_inst = GET_CHAN_INDEX(m->ipid);
3865
3866 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3867 umc_inst, ch_inst);
3868
24b82292
TZ		 3869 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3870 return NOTIFY_OK;
3871 else
6c0ca748 3872 return NOTIFY_DONE;
12b2cab7
MJ		 3873}
3874
3875static struct notifier_block amdgpu_bad_page_nb = {
3876 .notifier_call = amdgpu_bad_page_notifier,
3877 .priority = MCE_PRIO_UC,
3878};
3879
91a1a52d 3880static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
12b2cab7 3881{
91a1a52d
MJ		 3882 /*
3883 * Add the adev to the mce_adev_list.
3884 * During mode2 reset, amdgpu device is temporarily
3885 * removed from the mgpu_info list which can cause
3886 * page retirement to fail.
3887 * Use this list instead of mgpu_info to find the amdgpu
3888 * device on which the UMC error was reported.
3889 */
3890 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3891
12b2cab7
MJ		 3892 /*
3893 * Register the x86 notifier only once
3894 * with MCE subsystem.
3895 */
3896 if (notifier_registered == false) {
3897 mce_register_decode_chain(&amdgpu_bad_page_nb);
3898 notifier_registered = true;
3899 }
3900}
3901#endif
7cab2124 3902
b6efdb02 3903struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
7cab2124 3904{
3905 if (!adev)
3906 return NULL;
3907
3908 return adev->psp.ras_context.ras;
3909}
3910
b6efdb02 3911int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
7cab2124 3912{
3913 if (!adev)
69f91d32 3914 return -EINVAL;
7cab2124 3915
3916 adev->psp.ras_context.ras = ras_con;
3917 return 0;
3918}
3919
3920/* check if ras is supported on block, say, sdma, gfx */
3921int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3922 unsigned int block)
3923{
8f453c51 3924 int ret = 0;
7cab2124 3925 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3926
3927 if (block >= AMDGPU_RAS_BLOCK_COUNT)
3928 return 0;
8f453c51
YC		 3929
3930 ret = ras && (adev->ras_enabled & (1 << block));
3931
3932 /* For the special asic with mem ecc enabled but sram ecc
3933 * not enabled, even if the ras block is not supported on
3934 * .ras_enabled, if the asic supports poison mode and the
3935 * ras block has ras configuration, it can be considered
3936 * that the ras block supports ras function.
3937 */
3938 if (!ret &&
bc0f8080
CL		 3939 (block == AMDGPU_RAS_BLOCK__GFX ||
3940 block == AMDGPU_RAS_BLOCK__SDMA ||
3941 block == AMDGPU_RAS_BLOCK__VCN ||
3942 block == AMDGPU_RAS_BLOCK__JPEG) &&
7ec11c2f 3943 (amdgpu_ras_mask & (1 << block)) &&
8f453c51
YC		 3944 amdgpu_ras_is_poison_mode_supported(adev) &&
3945 amdgpu_ras_get_ras_block(adev, block, 0))
3946 ret = 1;
3947
3948 return ret;
7cab2124 3949}
3950
3951int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3952{
3953 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3954
3955 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
25a2b22e 3956 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
7cab2124 3957 return 0;
3958}
3959
201761b5 3960int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable)
8096df76
TZ		 3961{
3962 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
201761b5 3963 int ret = 0;
8096df76 3964
201761b5
LL		 3965 if (con) {
3966 ret = amdgpu_mca_smu_set_debug_mode(adev, enable);
3967 if (!ret)
04c4fcd2 3968 con->is_aca_debug_mode = enable;
201761b5
LL		 3969 }
3970
3971 return ret;
8096df76
TZ		 3972}
3973
33dcda51
YW		 3974int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable)
3975{
3976 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3977 int ret = 0;
3978
3979 if (con) {
04c4fcd2
YW		 3980 if (amdgpu_aca_is_enabled(adev))
3981 ret = amdgpu_aca_smu_set_debug_mode(adev, enable);
3982 else
3983 ret = amdgpu_mca_smu_set_debug_mode(adev, enable);
33dcda51 3984 if (!ret)
04c4fcd2 3985 con->is_aca_debug_mode = enable;
33dcda51
YW		 3986 }
3987
3988 return ret;
3989}
3990
04c4fcd2 3991bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev)
8096df76
TZ		 3992{
3993 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
04c4fcd2 3994 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs;
8096df76
TZ		 3995 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
3996
3997 if (!con)
3998 return false;
3999
04c4fcd2
YW		 4000 if ((amdgpu_aca_is_enabled(adev) && smu_funcs && smu_funcs->set_debug_mode) ||
4001 (!amdgpu_aca_is_enabled(adev) && mca_funcs && mca_funcs->mca_set_debug_mode))
4002 return con->is_aca_debug_mode;
8096df76
TZ		 4003 else
4004 return true;
4005}
7cab2124 4006
8cc0f566
HZ		 4007bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev,
4008 unsigned int *error_query_mode)
4009{
4010 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4011 const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
04c4fcd2 4012 const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs;
8cc0f566
HZ		 4013
4014 if (!con) {
4015 *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY;
4016 return false;
4017 }
4018
04c4fcd2 4019 if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode))
8cc0f566 4020 *error_query_mode =
04c4fcd2 4021 (con->is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY;
8cc0f566
HZ		 4022 else
4023 *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY;
4024
4025 return true;
4026}
4027
6492e1b0 4028/* Register each ip ras block into amdgpu ras */
4029int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
b6efdb02 4030 struct amdgpu_ras_block_object *ras_block_obj)
6492e1b0 4031{
d5e8ff5f 4032 struct amdgpu_ras_block_list *ras_node;
6492e1b0 4033 if (!adev || !ras_block_obj)
4034 return -EINVAL;
4035
d5e8ff5f 4036 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
4037 if (!ras_node)
4038 return -ENOMEM;
4039
4040 INIT_LIST_HEAD(&ras_node->node);
4041 ras_node->ras_obj = ras_block_obj;
4042 list_add_tail(&ras_node->node, &adev->ras_list);
6492e1b0 4043
4044 return 0;
4045}
322a7e00
HZ		 4046
4047void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
4048{
4049 if (!err_type_name)
4050 return;
4051
4052 switch (err_type) {
4053 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
4054 sprintf(err_type_name, "correctable");
4055 break;
4056 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
4057 sprintf(err_type_name, "uncorrectable");
4058 break;
4059 default:
4060 sprintf(err_type_name, "unknown");
4061 break;
4062 }
4063}
4064
4065bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
4066 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
4067 uint32_t instance,
4068 uint32_t *memory_id)
4069{
4070 uint32_t err_status_lo_data, err_status_lo_offset;
4071
4072 if (!reg_entry)
4073 return false;
4074
4075 err_status_lo_offset =
4076 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4077 reg_entry->seg_lo, reg_entry->reg_lo);
4078 err_status_lo_data = RREG32(err_status_lo_offset);
4079
4080 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
4081 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
4082 return false;
4083
4084 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
4085
4086 return true;
4087}
4088
4089bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
4090 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
4091 uint32_t instance,
4092 unsigned long *err_cnt)
4093{
4094 uint32_t err_status_hi_data, err_status_hi_offset;
4095
4096 if (!reg_entry)
4097 return false;
4098
4099 err_status_hi_offset =
4100 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
4101 reg_entry->seg_hi, reg_entry->reg_hi);
4102 err_status_hi_data = RREG32(err_status_hi_offset);
4103
4104 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
4105 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
9b337b7d
HZ		 4106 /* keep the check here in case we need to refer to the result later */
4107 dev_dbg(adev->dev, "Invalid err_info field\n");
322a7e00
HZ		 4108
4109 /* read err count */
4110 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
4111
4112 return true;
4113}
4114
4115void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
4116 const struct amdgpu_ras_err_status_reg_entry *reg_list,
4117 uint32_t reg_list_size,
4118 const struct amdgpu_ras_memory_id_entry *mem_list,
4119 uint32_t mem_list_size,
4120 uint32_t instance,
4121 uint32_t err_type,
4122 unsigned long *err_count)
4123{
4124 uint32_t memory_id;
4125 unsigned long err_cnt;
4126 char err_type_name[16];
4127 uint32_t i, j;
4128
4129 for (i = 0; i < reg_list_size; i++) {
9b337b7d
HZ		 4130 /* query memory_id from err_status_lo */
4131 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
4132 instance, &memory_id))
4133 continue;
4134
322a7e00
HZ		 4135 /* query err_cnt from err_status_hi */
4136 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
4137 instance, &err_cnt) ||
4138 !err_cnt)
4139 continue;
4140
322a7e00
HZ		 4141 *err_count += err_cnt;
4142
4143 /* log the errors */
4144 amdgpu_ras_get_error_type_name(err_type, err_type_name);
4145 if (!mem_list) {
4146 /* memory_list is not supported */
4147 dev_info(adev->dev,
4148 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
4149 err_cnt, err_type_name,
4150 reg_list[i].block_name,
4151 instance, memory_id);
4152 } else {
4153 for (j = 0; j < mem_list_size; j++) {
4154 if (memory_id == mem_list[j].memory_id) {
4155 dev_info(adev->dev,
4156 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
4157 err_cnt, err_type_name,
4158 reg_list[i].block_name,
4159 instance, mem_list[j].name);
4160 break;
4161 }
4162 }
4163 }
4164 }
4165}
e53a3250
HZ		 4166
4167void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
4168 const struct amdgpu_ras_err_status_reg_entry *reg_list,
4169 uint32_t reg_list_size,
4170 uint32_t instance)
4171{
4172 uint32_t err_status_lo_offset, err_status_hi_offset;
4173 uint32_t i;
4174
4175 for (i = 0; i < reg_list_size; i++) {
4176 err_status_lo_offset =
4177 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
4178 reg_list[i].seg_lo, reg_list[i].reg_lo);
4179 err_status_hi_offset =
4180 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
4181 reg_list[i].seg_hi, reg_list[i].reg_hi);
4182 WREG32(err_status_lo_offset, 0);
4183 WREG32(err_status_hi_offset, 0);
4184 }
4185}
5b1270be
YW		 4186
4187int amdgpu_ras_error_data_init(struct ras_err_data *err_data)
4188{
4189 memset(err_data, 0, sizeof(*err_data));
4190
4191 INIT_LIST_HEAD(&err_data->err_node_list);
4192
4193 return 0;
4194}
4195
4196static void amdgpu_ras_error_node_release(struct ras_err_node *err_node)
4197{
4198 if (!err_node)
4199 return;
4200
4201 list_del(&err_node->node);
4202 kvfree(err_node);
4203}
4204
4205void amdgpu_ras_error_data_fini(struct ras_err_data *err_data)
4206{
4207 struct ras_err_node *err_node, *tmp;
4208
8a656611 4209 list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node)
5b1270be 4210 amdgpu_ras_error_node_release(err_node);
5b1270be
YW		 4211}
4212
4213static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data,
4214 struct amdgpu_smuio_mcm_config_info *mcm_info)
4215{
4216 struct ras_err_node *err_node;
4217 struct amdgpu_smuio_mcm_config_info *ref_id;
4218
4219 if (!err_data || !mcm_info)
4220 return NULL;
4221
4222 for_each_ras_error(err_node, err_data) {
4223 ref_id = &err_node->err_info.mcm_info;
5b1270be 4224
53d4d779
YW		 4225 if (mcm_info->socket_id == ref_id->socket_id &&
4226 mcm_info->die_id == ref_id->die_id)
4227 return err_node;
5b1270be
YW		 4228 }
4229
4230 return NULL;
4231}
4232
4233static struct ras_err_node *amdgpu_ras_error_node_new(void)
4234{
4235 struct ras_err_node *err_node;
4236
4237 err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL);
4238 if (!err_node)
4239 return NULL;
4240
4241 INIT_LIST_HEAD(&err_node->node);
4242
4243 return err_node;
4244}
4245
dbf3850d
YW		 4246static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b)
4247{
4248 struct ras_err_node *nodea = container_of(a, struct ras_err_node, node);
4249 struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node);
4250 struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info;
4251 struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info;
4252
4253 if (unlikely(infoa->socket_id != infob->socket_id))
4254 return infoa->socket_id - infob->socket_id;
4255 else
4256 return infoa->die_id - infob->die_id;
4257
4258 return 0;
4259}
4260
5b1270be 4261static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data,
0795b5d2 4262 struct amdgpu_smuio_mcm_config_info *mcm_info)
5b1270be
YW		 4263{
4264 struct ras_err_node *err_node;
4265
4266 err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info);
4267 if (err_node)
4268 return &err_node->err_info;
4269
4270 err_node = amdgpu_ras_error_node_new();
4271 if (!err_node)
4272 return NULL;
4273
0795b5d2 4274 INIT_LIST_HEAD(&err_node->err_info.err_addr_list);
5b1270be 4275
0795b5d2 4276 memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info));
9f91e983 4277
5b1270be
YW		 4278 err_data->err_list_count++;
4279 list_add_tail(&err_node->node, &err_data->err_node_list);
dbf3850d 4280 list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp);
5b1270be
YW		 4281
4282 return &err_node->err_info;
4283}
4284
0795b5d2
YC		 4285void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *err_addr)
4286{
4287 struct ras_err_addr *mca_err_addr;
4288
95b4063d
YC		 4289 /* This function will be retired. */
4290 return;
0795b5d2
YC		 4291 mca_err_addr = kzalloc(sizeof(*mca_err_addr), GFP_KERNEL);
4292 if (!mca_err_addr)
4293 return;
4294
4295 INIT_LIST_HEAD(&mca_err_addr->node);
4296
4297 mca_err_addr->err_status = err_addr->err_status;
4298 mca_err_addr->err_ipid = err_addr->err_ipid;
4299 mca_err_addr->err_addr = err_addr->err_addr;
4300
4301 list_add_tail(&mca_err_addr->node, &err_info->err_addr_list);
4302}
4303
4304void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *mca_err_addr)
4305{
4306 list_del(&mca_err_addr->node);
4307 kfree(mca_err_addr);
4308}
4309
5b1270be 4310int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data,
9f91e983
YC		 4311 struct amdgpu_smuio_mcm_config_info *mcm_info,
4312 struct ras_err_addr *err_addr, u64 count)
5b1270be
YW		 4313{
4314 struct ras_err_info *err_info;
4315
4316 if (!err_data || !mcm_info)
4317 return -EINVAL;
4318
4319 if (!count)
4320 return 0;
4321
0795b5d2 4322 err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
5b1270be
YW		 4323 if (!err_info)
4324 return -EINVAL;
4325
0795b5d2
YC		 4326 if (err_addr && err_addr->err_status)
4327 amdgpu_ras_add_mca_err_addr(err_info, err_addr);
4328
5b1270be
YW		 4329 err_info->ue_count += count;
4330 err_data->ue_count += count;
4331
4332 return 0;
4333}
4334
4335int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data,
9f91e983
YC		 4336 struct amdgpu_smuio_mcm_config_info *mcm_info,
4337 struct ras_err_addr *err_addr, u64 count)
5b1270be
YW		 4338{
4339 struct ras_err_info *err_info;
4340
4341 if (!err_data || !mcm_info)
4342 return -EINVAL;
4343
4344 if (!count)
4345 return 0;
4346
0795b5d2 4347 err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
5b1270be
YW		 4348 if (!err_info)
4349 return -EINVAL;
4350
4351 err_info->ce_count += count;
4352 err_data->ce_count += count;
4353
4354 return 0;
4355}
cce4febb 4356
46e2231c
CL		 4357int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data,
4358 struct amdgpu_smuio_mcm_config_info *mcm_info,
4359 struct ras_err_addr *err_addr, u64 count)
4360{
4361 struct ras_err_info *err_info;
4362
4363 if (!err_data || !mcm_info)
4364 return -EINVAL;
4365
4366 if (!count)
4367 return 0;
4368
0795b5d2 4369 err_info = amdgpu_ras_error_get_info(err_data, mcm_info);
46e2231c
CL		 4370 if (!err_info)
4371 return -EINVAL;
4372
0795b5d2
YC		 4373 if (err_addr && err_addr->err_status)
4374 amdgpu_ras_add_mca_err_addr(err_info, err_addr);
4375
46e2231c
CL		 4376 err_info->de_count += count;
4377 err_data->de_count += count;
4378
4379 return 0;
4380}
4381
cce4febb
HZ		 4382#define mmMP0_SMN_C2PMSG_92 0x1609C
4383#define mmMP0_SMN_C2PMSG_126 0x160BE
4384static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev,
4385 u32 instance, u32 boot_error)
4386{
4387 u32 socket_id, aid_id, hbm_id;
4388 u32 reg_data;
4389 u64 reg_addr;
4390
4391 socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
4392 aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
4393 hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);
4394
4395 /* The pattern for smn addressing in other SOC could be different from
4396 * the one for aqua_vanjaram. We should revisit the code if the pattern
4397 * is changed. In such case, replace the aqua_vanjaram implementation
4398 * with more common helper */
4399 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
4400 aqua_vanjaram_encode_ext_smn_addressing(instance);
4401
4402 reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4403 dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n",
4404 socket_id, aid_id, reg_data);
4405
4406 if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
4407 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n",
4408 socket_id, aid_id, hbm_id);
4409
4410 if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error))
4411 dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n",
4412 socket_id, aid_id);
4413
4414 if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error))
4415 dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n",
4416 socket_id, aid_id);
4417
4418 if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error))
4419 dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n",
4420 socket_id, aid_id);
4421
4422 if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error))
4423 dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n",
4424 socket_id, aid_id);
4425
4426 if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error))
4427 dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n",
4428 socket_id, aid_id);
4429
4430 if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error))
4431 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n",
4432 socket_id, aid_id, hbm_id);
4433
4434 if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error))
4435 dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n",
4436 socket_id, aid_id, hbm_id);
4437}
4438
4439static int amdgpu_ras_wait_for_boot_complete(struct amdgpu_device *adev,
4440 u32 instance, u32 *boot_error)
4441{
4442 u32 reg_addr;
4443 u32 reg_data;
4444 int retry_loop;
4445
1731ba9b
HZ		 4446 reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) +
4447 aqua_vanjaram_encode_ext_smn_addressing(instance);
4448
4449 for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {
4450 reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4451 if ((reg_data & AMDGPU_RAS_BOOT_STATUS_MASK) == AMDGPU_RAS_BOOT_STEADY_STATUS) {
4452 *boot_error = AMDGPU_RAS_BOOT_SUCEESS;
4453 return 0;
4454 }
4455 msleep(1);
4456 }
4457
cce4febb
HZ		 4458 /* The pattern for smn addressing in other SOC could be different from
4459 * the one for aqua_vanjaram. We should revisit the code if the pattern
4460 * is changed. In such case, replace the aqua_vanjaram implementation
4461 * with more common helper */
4462 reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) +
4463 aqua_vanjaram_encode_ext_smn_addressing(instance);
4464
1731ba9b 4465 for (retry_loop = 0; retry_loop < AMDGPU_RAS_BOOT_STATUS_POLLING_LIMIT; retry_loop++) {
cce4febb
HZ		 4466 reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr);
4467 if (AMDGPU_RAS_GPU_ERR_BOOT_STATUS(reg_data)) {
4468 *boot_error = reg_data;
4469 return 0;
4470 }
4471 msleep(1);
4472 }
4473
4474 *boot_error = reg_data;
4475 return -ETIME;
4476}
4477
4478void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances)
4479{
4480 u32 boot_error = 0;
4481 u32 i;
4482
4483 for (i = 0; i < num_instances; i++) {
4484 if (amdgpu_ras_wait_for_boot_complete(adev, i, &boot_error))
4485 amdgpu_ras_boot_time_error_reporting(adev, i, boot_error);
4486 }
4487}
af730e08
YC		 4488
4489int amdgpu_ras_reserve_page(struct amdgpu_device *adev, uint64_t pfn)
4490{
4491 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4492 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr;
4493 uint64_t start = pfn << AMDGPU_GPU_PAGE_SHIFT;
4494 int ret = 0;
4495
4496 mutex_lock(&con->page_rsv_lock);
4497 ret = amdgpu_vram_mgr_query_page_status(mgr, start);
4498 if (ret == -ENOENT)
4499 ret = amdgpu_vram_mgr_reserve_range(mgr, start, AMDGPU_GPU_PAGE_SIZE);
4500 mutex_unlock(&con->page_rsv_lock);
4501
4502 return ret;
4503}
Linux 6.x block layer and io_uring tree(s)