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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
4e644fff | 34 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 35 | |
c030f2e4 | 36 | const char *ras_error_string[] = { |
37 | "none", | |
38 | "parity", | |
39 | "single_correctable", | |
40 | "multi_uncorrectable", | |
41 | "poison", | |
42 | }; | |
43 | ||
44 | const char *ras_block_string[] = { | |
45 | "umc", | |
46 | "sdma", | |
47 | "gfx", | |
48 | "mmhub", | |
49 | "athub", | |
50 | "pcie_bif", | |
51 | "hdp", | |
52 | "xgmi_wafl", | |
53 | "df", | |
54 | "smn", | |
55 | "sem", | |
56 | "mp0", | |
57 | "mp1", | |
58 | "fuse", | |
59 | }; | |
60 | ||
61 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
62 | #define ras_block_str(i) (ras_block_string[i]) | |
63 | ||
a564808e | 64 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 |
65 | #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 | |
108c6a63 | 66 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
67 | ||
7cdc2ee3 TZ |
68 | /* inject address is 52 bits */ |
69 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
70 | ||
7c6e68c7 AG |
71 | |
72 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
73 | ||
c030f2e4 | 74 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
75 | size_t size, loff_t *pos) | |
76 | { | |
77 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
78 | struct ras_query_if info = { | |
79 | .head = obj->head, | |
80 | }; | |
81 | ssize_t s; | |
82 | char val[128]; | |
83 | ||
84 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
85 | return -EINVAL; | |
86 | ||
87 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
88 | "ue", info.ue_count, | |
89 | "ce", info.ce_count); | |
90 | if (*pos >= s) | |
91 | return 0; | |
92 | ||
93 | s -= *pos; | |
94 | s = min_t(u64, s, size); | |
95 | ||
96 | ||
97 | if (copy_to_user(buf, &val[*pos], s)) | |
98 | return -EINVAL; | |
99 | ||
100 | *pos += s; | |
101 | ||
102 | return s; | |
103 | } | |
104 | ||
c030f2e4 | 105 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
106 | .owner = THIS_MODULE, | |
107 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 108 | .write = NULL, |
c030f2e4 | 109 | .llseek = default_llseek |
110 | }; | |
111 | ||
96ebb307 | 112 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
113 | { | |
114 | int i; | |
115 | ||
116 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
117 | *block_id = i; | |
118 | if (strcmp(name, ras_block_str(i)) == 0) | |
119 | return 0; | |
120 | } | |
121 | return -EINVAL; | |
122 | } | |
123 | ||
124 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
125 | const char __user *buf, size_t size, | |
126 | loff_t *pos, struct ras_debug_if *data) | |
127 | { | |
128 | ssize_t s = min_t(u64, 64, size); | |
129 | char str[65]; | |
130 | char block_name[33]; | |
131 | char err[9] = "ue"; | |
132 | int op = -1; | |
133 | int block_id; | |
44494f96 | 134 | uint32_t sub_block; |
96ebb307 | 135 | u64 address, value; |
136 | ||
137 | if (*pos) | |
138 | return -EINVAL; | |
139 | *pos = size; | |
140 | ||
141 | memset(str, 0, sizeof(str)); | |
142 | memset(data, 0, sizeof(*data)); | |
143 | ||
144 | if (copy_from_user(str, buf, s)) | |
145 | return -EINVAL; | |
146 | ||
147 | if (sscanf(str, "disable %32s", block_name) == 1) | |
148 | op = 0; | |
149 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
150 | op = 1; | |
151 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
152 | op = 2; | |
d5ea093e AG |
153 | else if (sscanf(str, "reboot %32s", block_name) == 1) |
154 | op = 3; | |
b076296b | 155 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 156 | /* ascii string, but commands are not matched. */ |
157 | return -EINVAL; | |
158 | ||
159 | if (op != -1) { | |
160 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
161 | return -EINVAL; | |
162 | ||
163 | data->head.block = block_id; | |
e1063493 TZ |
164 | /* only ue and ce errors are supported */ |
165 | if (!memcmp("ue", err, 2)) | |
166 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
167 | else if (!memcmp("ce", err, 2)) | |
168 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
169 | else | |
170 | return -EINVAL; | |
171 | ||
96ebb307 | 172 | data->op = op; |
173 | ||
174 | if (op == 2) { | |
44494f96 TZ |
175 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
176 | &sub_block, &address, &value) != 3) | |
177 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
178 | &sub_block, &address, &value) != 3) | |
96ebb307 | 179 | return -EINVAL; |
44494f96 | 180 | data->head.sub_block_index = sub_block; |
96ebb307 | 181 | data->inject.address = address; |
182 | data->inject.value = value; | |
183 | } | |
184 | } else { | |
73aa8e1a | 185 | if (size < sizeof(*data)) |
96ebb307 | 186 | return -EINVAL; |
187 | ||
188 | if (copy_from_user(data, buf, sizeof(*data))) | |
189 | return -EINVAL; | |
190 | } | |
191 | ||
192 | return 0; | |
193 | } | |
7c6e68c7 AG |
194 | |
195 | static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, | |
196 | struct ras_common_if *head); | |
197 | ||
74abc221 TSD |
198 | /** |
199 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 200 | * |
201 | * It accepts struct ras_debug_if who has two members. | |
202 | * | |
203 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 204 | * |
205 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 206 | * |
207 | * head has four members, they are block, type, sub_block_index, name. | |
208 | * block: which IP will be under control. | |
209 | * type: what kind of error will be enabled/disabled/injected. | |
210 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
211 | * name: the name of IP. | |
212 | * | |
213 | * inject has two more members than head, they are address, value. | |
214 | * As their names indicate, inject operation will write the | |
215 | * value to the address. | |
216 | * | |
217 | * Second member: struct ras_debug_if::op. | |
218 | * It has three kinds of operations. | |
879e723d AZ |
219 | * |
220 | * - 0: disable RAS on the block. Take ::head as its data. | |
221 | * - 1: enable RAS on the block. Take ::head as its data. | |
222 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 223 | * |
96ebb307 | 224 | * How to use the interface? |
225 | * programs: | |
226 | * copy the struct ras_debug_if in your codes and initialize it. | |
227 | * write the struct to the control node. | |
228 | * | |
879e723d AZ |
229 | * .. code-block:: bash |
230 | * | |
231 | * echo op block [error [sub_blcok address value]] > .../ras/ras_ctrl | |
232 | * | |
233 | * op: disable, enable, inject | |
234 | * disable: only block is needed | |
235 | * enable: block and error are needed | |
236 | * inject: error, address, value are needed | |
237 | * block: umc, smda, gfx, ......... | |
238 | * see ras_block_string[] for details | |
239 | * error: ue, ce | |
240 | * ue: multi_uncorrectable | |
241 | * ce: single_correctable | |
242 | * sub_block: | |
243 | * sub block index, pass 0 if there is no sub block | |
244 | * | |
245 | * here are some examples for bash commands: | |
246 | * | |
247 | * .. code-block:: bash | |
96ebb307 | 248 | * |
44494f96 TZ |
249 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
250 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 251 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
252 | * | |
36ea1bd2 | 253 | * How to check the result? |
254 | * | |
255 | * For disable/enable, please check ras features at | |
256 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
257 | * | |
258 | * For inject, please check corresponding err count at | |
259 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
260 | * | |
879e723d AZ |
261 | * .. note:: |
262 | * Operation is only allowed on blocks which are supported. | |
263 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask | |
36ea1bd2 | 264 | */ |
265 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
266 | size_t size, loff_t *pos) | |
267 | { | |
268 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
269 | struct ras_debug_if data; | |
270 | int ret = 0; | |
271 | ||
96ebb307 | 272 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
273 | if (ret) | |
36ea1bd2 | 274 | return -EINVAL; |
275 | ||
36ea1bd2 | 276 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
277 | return -EINVAL; | |
278 | ||
279 | switch (data.op) { | |
280 | case 0: | |
281 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
282 | break; | |
283 | case 1: | |
284 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
285 | break; | |
286 | case 2: | |
7cdc2ee3 TZ |
287 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
288 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
289 | ret = -EINVAL; | |
290 | break; | |
291 | } | |
292 | ||
293 | /* data.inject.address is offset instead of absolute gpu address */ | |
36ea1bd2 | 294 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
295 | break; | |
d5ea093e AG |
296 | case 3: |
297 | amdgpu_ras_get_context(adev)->reboot = true; | |
298 | break; | |
96ebb307 | 299 | default: |
300 | ret = -EINVAL; | |
301 | break; | |
36ea1bd2 | 302 | }; |
303 | ||
304 | if (ret) | |
305 | return -EINVAL; | |
306 | ||
307 | return size; | |
308 | } | |
309 | ||
084fe13b AG |
310 | /** |
311 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
312 | * | |
313 | * Usage: echo 1 > ../ras/ras_eeprom_reset will reset EEPROM table to 0 entries. | |
314 | */ | |
315 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
316 | size_t size, loff_t *pos) | |
317 | { | |
318 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
319 | int ret; | |
320 | ||
321 | ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); | |
322 | ||
323 | return ret == 1 ? size : -EIO; | |
324 | } | |
325 | ||
36ea1bd2 | 326 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
327 | .owner = THIS_MODULE, | |
328 | .read = NULL, | |
329 | .write = amdgpu_ras_debugfs_ctrl_write, | |
330 | .llseek = default_llseek | |
331 | }; | |
332 | ||
084fe13b AG |
333 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
334 | .owner = THIS_MODULE, | |
335 | .read = NULL, | |
336 | .write = amdgpu_ras_debugfs_eeprom_write, | |
337 | .llseek = default_llseek | |
338 | }; | |
339 | ||
c030f2e4 | 340 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
341 | struct device_attribute *attr, char *buf) | |
342 | { | |
343 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
344 | struct ras_query_if info = { | |
345 | .head = obj->head, | |
346 | }; | |
347 | ||
348 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
349 | return -EINVAL; | |
350 | ||
351 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
352 | "ue", info.ue_count, | |
353 | "ce", info.ce_count); | |
354 | } | |
355 | ||
356 | /* obj begin */ | |
357 | ||
358 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
359 | #define alive_obj(obj) ((obj)->use) | |
360 | ||
361 | static inline void put_obj(struct ras_manager *obj) | |
362 | { | |
363 | if (obj && --obj->use == 0) | |
364 | list_del(&obj->node); | |
365 | if (obj && obj->use < 0) { | |
366 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
367 | } | |
368 | } | |
369 | ||
370 | /* make one obj and return it. */ | |
371 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
372 | struct ras_common_if *head) | |
373 | { | |
374 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
375 | struct ras_manager *obj; | |
376 | ||
377 | if (!con) | |
378 | return NULL; | |
379 | ||
380 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
381 | return NULL; | |
382 | ||
383 | obj = &con->objs[head->block]; | |
384 | /* already exist. return obj? */ | |
385 | if (alive_obj(obj)) | |
386 | return NULL; | |
387 | ||
388 | obj->head = *head; | |
389 | obj->adev = adev; | |
390 | list_add(&obj->node, &con->head); | |
391 | get_obj(obj); | |
392 | ||
393 | return obj; | |
394 | } | |
395 | ||
396 | /* return an obj equal to head, or the first when head is NULL */ | |
397 | static struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, | |
398 | struct ras_common_if *head) | |
399 | { | |
400 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
401 | struct ras_manager *obj; | |
402 | int i; | |
403 | ||
404 | if (!con) | |
405 | return NULL; | |
406 | ||
407 | if (head) { | |
408 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
409 | return NULL; | |
410 | ||
411 | obj = &con->objs[head->block]; | |
412 | ||
413 | if (alive_obj(obj)) { | |
414 | WARN_ON(head->block != obj->head.block); | |
415 | return obj; | |
416 | } | |
417 | } else { | |
418 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
419 | obj = &con->objs[i]; | |
420 | if (alive_obj(obj)) { | |
421 | WARN_ON(i != obj->head.block); | |
422 | return obj; | |
423 | } | |
424 | } | |
425 | } | |
426 | ||
427 | return NULL; | |
428 | } | |
429 | /* obj end */ | |
430 | ||
431 | /* feature ctl begin */ | |
432 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
433 | struct ras_common_if *head) | |
434 | { | |
5caf466a | 435 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
436 | ||
437 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 438 | } |
439 | ||
440 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
441 | struct ras_common_if *head) | |
442 | { | |
443 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
444 | ||
445 | return con->features & BIT(head->block); | |
446 | } | |
447 | ||
448 | /* | |
449 | * if obj is not created, then create one. | |
450 | * set feature enable flag. | |
451 | */ | |
452 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
453 | struct ras_common_if *head, int enable) | |
454 | { | |
455 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
456 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
457 | ||
5caf466a | 458 | /* If hardware does not support ras, then do not create obj. |
459 | * But if hardware support ras, we can create the obj. | |
460 | * Ras framework checks con->hw_supported to see if it need do | |
461 | * corresponding initialization. | |
462 | * IP checks con->support to see if it need disable ras. | |
463 | */ | |
c030f2e4 | 464 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
465 | return 0; | |
466 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
467 | return 0; | |
468 | ||
469 | if (enable) { | |
470 | if (!obj) { | |
471 | obj = amdgpu_ras_create_obj(adev, head); | |
472 | if (!obj) | |
473 | return -EINVAL; | |
474 | } else { | |
475 | /* In case we create obj somewhere else */ | |
476 | get_obj(obj); | |
477 | } | |
478 | con->features |= BIT(head->block); | |
479 | } else { | |
480 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
481 | con->features &= ~BIT(head->block); | |
482 | put_obj(obj); | |
483 | } | |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | /* wrapper of psp_ras_enable_features */ | |
490 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
491 | struct ras_common_if *head, bool enable) | |
492 | { | |
493 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
494 | union ta_ras_cmd_input info; | |
495 | int ret; | |
496 | ||
497 | if (!con) | |
498 | return -EINVAL; | |
499 | ||
500 | if (!enable) { | |
501 | info.disable_features = (struct ta_ras_disable_features_input) { | |
828cfa29 | 502 | .block_id = amdgpu_ras_block_to_ta(head->block), |
503 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 504 | }; |
505 | } else { | |
506 | info.enable_features = (struct ta_ras_enable_features_input) { | |
828cfa29 | 507 | .block_id = amdgpu_ras_block_to_ta(head->block), |
508 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 509 | }; |
510 | } | |
511 | ||
512 | /* Do not enable if it is not allowed. */ | |
513 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
514 | /* Are we alerady in that state we are going to set? */ | |
515 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
516 | return 0; | |
517 | ||
518 | ret = psp_ras_enable_features(&adev->psp, &info, enable); | |
519 | if (ret) { | |
520 | DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n", | |
521 | enable ? "enable":"disable", | |
522 | ras_block_str(head->block), | |
523 | ret); | |
7af23ebe | 524 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
525 | return -EAGAIN; | |
c030f2e4 | 526 | return -EINVAL; |
527 | } | |
528 | ||
529 | /* setup the obj */ | |
530 | __amdgpu_ras_feature_enable(adev, head, enable); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
77de502b | 535 | /* Only used in device probe stage and called only once. */ |
536 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
537 | struct ras_common_if *head, bool enable) | |
538 | { | |
539 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
540 | int ret; | |
541 | ||
542 | if (!con) | |
543 | return -EINVAL; | |
544 | ||
545 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 546 | if (enable) { |
547 | /* There is no harm to issue a ras TA cmd regardless of | |
548 | * the currecnt ras state. | |
549 | * If current state == target state, it will do nothing | |
550 | * But sometimes it requests driver to reset and repost | |
551 | * with error code -EAGAIN. | |
552 | */ | |
553 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
554 | /* With old ras TA, we might fail to enable ras. | |
555 | * Log it and just setup the object. | |
556 | * TODO need remove this WA in the future. | |
557 | */ | |
558 | if (ret == -EINVAL) { | |
559 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
560 | if (!ret) | |
561 | DRM_INFO("RAS INFO: %s setup object\n", | |
562 | ras_block_str(head->block)); | |
563 | } | |
564 | } else { | |
565 | /* setup the object then issue a ras TA disable cmd.*/ | |
566 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
567 | if (ret) | |
568 | return ret; | |
77de502b | 569 | |
77de502b | 570 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 571 | } |
77de502b | 572 | } else |
573 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
574 | ||
575 | return ret; | |
576 | } | |
577 | ||
c030f2e4 | 578 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
579 | bool bypass) | |
580 | { | |
581 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
582 | struct ras_manager *obj, *tmp; | |
583 | ||
584 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
585 | /* bypass psp. | |
586 | * aka just release the obj and corresponding flags | |
587 | */ | |
588 | if (bypass) { | |
589 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
590 | break; | |
591 | } else { | |
592 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
593 | break; | |
594 | } | |
289d513b | 595 | } |
c030f2e4 | 596 | |
597 | return con->features; | |
598 | } | |
599 | ||
600 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
601 | bool bypass) | |
602 | { | |
603 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
604 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
605 | int i; | |
191051a1 | 606 | const enum amdgpu_ras_error_type default_ras_type = |
607 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 608 | |
609 | for (i = 0; i < ras_block_count; i++) { | |
610 | struct ras_common_if head = { | |
611 | .block = i, | |
191051a1 | 612 | .type = default_ras_type, |
c030f2e4 | 613 | .sub_block_index = 0, |
614 | }; | |
615 | strcpy(head.name, ras_block_str(i)); | |
616 | if (bypass) { | |
617 | /* | |
618 | * bypass psp. vbios enable ras for us. | |
619 | * so just create the obj | |
620 | */ | |
621 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
622 | break; | |
623 | } else { | |
624 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
625 | break; | |
626 | } | |
289d513b | 627 | } |
c030f2e4 | 628 | |
629 | return con->features; | |
630 | } | |
631 | /* feature ctl end */ | |
632 | ||
633 | /* query/inject/cure begin */ | |
634 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
635 | struct ras_query_if *info) | |
636 | { | |
637 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 638 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 639 | |
640 | if (!obj) | |
641 | return -EINVAL; | |
c030f2e4 | 642 | |
939e2258 HZ |
643 | switch (info->head.block) { |
644 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
645 | if (adev->umc.funcs->query_ras_error_count) |
646 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
647 | /* umc query_ras_error_address is also responsible for clearing |
648 | * error status | |
649 | */ | |
650 | if (adev->umc.funcs->query_ras_error_address) | |
651 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 652 | break; |
83b0582c DL |
653 | case AMDGPU_RAS_BLOCK__GFX: |
654 | if (adev->gfx.funcs->query_ras_error_count) | |
655 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
656 | break; | |
9fb2d8de TZ |
657 | case AMDGPU_RAS_BLOCK__MMHUB: |
658 | if (adev->mmhub_funcs->query_ras_error_count) | |
659 | adev->mmhub_funcs->query_ras_error_count(adev, &err_data); | |
660 | break; | |
d7bd680d GC |
661 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
662 | if (adev->nbio.funcs->query_ras_error_count) | |
663 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
664 | break; | |
939e2258 HZ |
665 | default: |
666 | break; | |
667 | } | |
05a58345 TZ |
668 | |
669 | obj->err_data.ue_count += err_data.ue_count; | |
670 | obj->err_data.ce_count += err_data.ce_count; | |
671 | ||
c030f2e4 | 672 | info->ue_count = obj->err_data.ue_count; |
673 | info->ce_count = obj->err_data.ce_count; | |
674 | ||
7c6e68c7 | 675 | if (err_data.ce_count) { |
05a58345 TZ |
676 | dev_info(adev->dev, "%ld correctable errors detected in %s block\n", |
677 | obj->err_data.ce_count, ras_block_str(info->head.block)); | |
7c6e68c7 AG |
678 | } |
679 | if (err_data.ue_count) { | |
05a58345 TZ |
680 | dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n", |
681 | obj->err_data.ue_count, ras_block_str(info->head.block)); | |
7c6e68c7 | 682 | } |
05a58345 | 683 | |
c030f2e4 | 684 | return 0; |
685 | } | |
686 | ||
687 | /* wrapper of psp_ras_trigger_error */ | |
688 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
689 | struct ras_inject_if *info) | |
690 | { | |
691 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
692 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 693 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
694 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 695 | .sub_block_index = info->head.sub_block_index, |
696 | .address = info->address, | |
697 | .value = info->value, | |
698 | }; | |
699 | int ret = 0; | |
700 | ||
701 | if (!obj) | |
702 | return -EINVAL; | |
703 | ||
83b0582c DL |
704 | switch (info->head.block) { |
705 | case AMDGPU_RAS_BLOCK__GFX: | |
706 | if (adev->gfx.funcs->ras_error_inject) | |
707 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
708 | else | |
709 | ret = -EINVAL; | |
710 | break; | |
711 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 712 | case AMDGPU_RAS_BLOCK__MMHUB: |
f3170352 | 713 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
d7bd680d | 714 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
715 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
716 | break; | |
717 | default: | |
a5dd40ca HZ |
718 | DRM_INFO("%s error injection is not supported yet\n", |
719 | ras_block_str(info->head.block)); | |
83b0582c | 720 | ret = -EINVAL; |
a5dd40ca HZ |
721 | } |
722 | ||
c030f2e4 | 723 | if (ret) |
724 | DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", | |
725 | ras_block_str(info->head.block), | |
726 | ret); | |
727 | ||
728 | return ret; | |
729 | } | |
730 | ||
731 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
732 | struct ras_cure_if *info) | |
733 | { | |
734 | /* psp fw has no cure interface for now. */ | |
735 | return 0; | |
736 | } | |
737 | ||
738 | /* get the total error counts on all IPs */ | |
64cc5414 | 739 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 740 | bool is_ce) |
741 | { | |
742 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
743 | struct ras_manager *obj; | |
744 | struct ras_err_data data = {0, 0}; | |
745 | ||
746 | if (!con) | |
64cc5414 | 747 | return 0; |
c030f2e4 | 748 | |
749 | list_for_each_entry(obj, &con->head, node) { | |
750 | struct ras_query_if info = { | |
751 | .head = obj->head, | |
752 | }; | |
753 | ||
754 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 755 | return 0; |
c030f2e4 | 756 | |
757 | data.ce_count += info.ce_count; | |
758 | data.ue_count += info.ue_count; | |
759 | } | |
760 | ||
761 | return is_ce ? data.ce_count : data.ue_count; | |
762 | } | |
763 | /* query/inject/cure end */ | |
764 | ||
765 | ||
766 | /* sysfs begin */ | |
767 | ||
466b1793 | 768 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
769 | struct ras_badpage **bps, unsigned int *count); | |
770 | ||
771 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
772 | { | |
773 | switch (flags) { | |
774 | case 0: | |
775 | return "R"; | |
776 | case 1: | |
777 | return "P"; | |
778 | case 2: | |
779 | default: | |
780 | return "F"; | |
781 | }; | |
782 | } | |
783 | ||
784 | /* | |
785 | * DOC: ras sysfs gpu_vram_bad_pages interface | |
786 | * | |
787 | * It allows user to read the bad pages of vram on the gpu through | |
788 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
789 | * | |
790 | * It outputs multiple lines, and each line stands for one gpu page. | |
791 | * | |
792 | * The format of one line is below, | |
793 | * gpu pfn : gpu page size : flags | |
794 | * | |
795 | * gpu pfn and gpu page size are printed in hex format. | |
796 | * flags can be one of below character, | |
797 | * R: reserved, this gpu page is reserved and not able to use. | |
798 | * P: pending for reserve, this gpu page is marked as bad, will be reserved | |
799 | * in next window of page_reserve. | |
800 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. | |
801 | * | |
802 | * examples: | |
803 | * 0x00000001 : 0x00001000 : R | |
804 | * 0x00000002 : 0x00001000 : P | |
805 | */ | |
806 | ||
807 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
808 | struct kobject *kobj, struct bin_attribute *attr, | |
809 | char *buf, loff_t ppos, size_t count) | |
810 | { | |
811 | struct amdgpu_ras *con = | |
812 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
813 | struct amdgpu_device *adev = con->adev; | |
814 | const unsigned int element_size = | |
815 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
816 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
817 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 818 | ssize_t s = 0; |
819 | struct ras_badpage *bps = NULL; | |
820 | unsigned int bps_count = 0; | |
821 | ||
822 | memset(buf, 0, count); | |
823 | ||
824 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
825 | return 0; | |
826 | ||
827 | for (; start < end && start < bps_count; start++) | |
828 | s += scnprintf(&buf[s], element_size + 1, | |
829 | "0x%08x : 0x%08x : %1s\n", | |
830 | bps[start].bp, | |
831 | bps[start].size, | |
832 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
833 | ||
834 | kfree(bps); | |
835 | ||
836 | return s; | |
837 | } | |
838 | ||
c030f2e4 | 839 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
840 | struct device_attribute *attr, char *buf) | |
841 | { | |
842 | struct amdgpu_ras *con = | |
843 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 844 | |
5212a3bd | 845 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 846 | } |
847 | ||
848 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
849 | { | |
850 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
851 | struct attribute *attrs[] = { | |
852 | &con->features_attr.attr, | |
853 | NULL | |
854 | }; | |
466b1793 | 855 | struct bin_attribute *bin_attrs[] = { |
856 | &con->badpages_attr, | |
857 | NULL | |
858 | }; | |
c030f2e4 | 859 | struct attribute_group group = { |
860 | .name = "ras", | |
861 | .attrs = attrs, | |
466b1793 | 862 | .bin_attrs = bin_attrs, |
c030f2e4 | 863 | }; |
864 | ||
865 | con->features_attr = (struct device_attribute) { | |
866 | .attr = { | |
867 | .name = "features", | |
868 | .mode = S_IRUGO, | |
869 | }, | |
870 | .show = amdgpu_ras_sysfs_features_read, | |
871 | }; | |
466b1793 | 872 | |
873 | con->badpages_attr = (struct bin_attribute) { | |
874 | .attr = { | |
875 | .name = "gpu_vram_bad_pages", | |
876 | .mode = S_IRUGO, | |
877 | }, | |
878 | .size = 0, | |
879 | .private = NULL, | |
880 | .read = amdgpu_ras_sysfs_badpages_read, | |
881 | }; | |
882 | ||
163def43 | 883 | sysfs_attr_init(attrs[0]); |
466b1793 | 884 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 885 | |
886 | return sysfs_create_group(&adev->dev->kobj, &group); | |
887 | } | |
888 | ||
889 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
890 | { | |
891 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
892 | struct attribute *attrs[] = { | |
893 | &con->features_attr.attr, | |
894 | NULL | |
895 | }; | |
466b1793 | 896 | struct bin_attribute *bin_attrs[] = { |
897 | &con->badpages_attr, | |
898 | NULL | |
899 | }; | |
c030f2e4 | 900 | struct attribute_group group = { |
901 | .name = "ras", | |
902 | .attrs = attrs, | |
466b1793 | 903 | .bin_attrs = bin_attrs, |
c030f2e4 | 904 | }; |
905 | ||
906 | sysfs_remove_group(&adev->dev->kobj, &group); | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
912 | struct ras_fs_if *head) | |
913 | { | |
914 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
915 | ||
916 | if (!obj || obj->attr_inuse) | |
917 | return -EINVAL; | |
918 | ||
919 | get_obj(obj); | |
920 | ||
921 | memcpy(obj->fs_data.sysfs_name, | |
922 | head->sysfs_name, | |
923 | sizeof(obj->fs_data.sysfs_name)); | |
924 | ||
925 | obj->sysfs_attr = (struct device_attribute){ | |
926 | .attr = { | |
927 | .name = obj->fs_data.sysfs_name, | |
928 | .mode = S_IRUGO, | |
929 | }, | |
930 | .show = amdgpu_ras_sysfs_read, | |
931 | }; | |
163def43 | 932 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 933 | |
934 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
935 | &obj->sysfs_attr.attr, | |
936 | "ras")) { | |
937 | put_obj(obj); | |
938 | return -EINVAL; | |
939 | } | |
940 | ||
941 | obj->attr_inuse = 1; | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
947 | struct ras_common_if *head) | |
948 | { | |
949 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
950 | ||
951 | if (!obj || !obj->attr_inuse) | |
952 | return -EINVAL; | |
953 | ||
954 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
955 | &obj->sysfs_attr.attr, | |
956 | "ras"); | |
957 | obj->attr_inuse = 0; | |
958 | put_obj(obj); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
964 | { | |
965 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
966 | struct ras_manager *obj, *tmp; | |
967 | ||
968 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
969 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
970 | } | |
971 | ||
972 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | /* sysfs end */ | |
977 | ||
978 | /* debugfs begin */ | |
450f30ea | 979 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 980 | { |
981 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
982 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 983 | |
450f30ea | 984 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
012dd14d GC |
985 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
986 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
987 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
988 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
36ea1bd2 | 989 | } |
990 | ||
450f30ea | 991 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 992 | struct ras_fs_if *head) |
993 | { | |
994 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
995 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 996 | |
997 | if (!obj || obj->ent) | |
450f30ea | 998 | return; |
c030f2e4 | 999 | |
1000 | get_obj(obj); | |
1001 | ||
1002 | memcpy(obj->fs_data.debugfs_name, | |
1003 | head->debugfs_name, | |
1004 | sizeof(obj->fs_data.debugfs_name)); | |
1005 | ||
450f30ea GKH |
1006 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1007 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1008 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1009 | } |
1010 | ||
450f30ea | 1011 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1012 | struct ras_common_if *head) |
1013 | { | |
1014 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1015 | ||
1016 | if (!obj || !obj->ent) | |
450f30ea | 1017 | return; |
c030f2e4 | 1018 | |
1019 | debugfs_remove(obj->ent); | |
1020 | obj->ent = NULL; | |
1021 | put_obj(obj); | |
c030f2e4 | 1022 | } |
1023 | ||
450f30ea | 1024 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1025 | { |
1026 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1027 | struct ras_manager *obj, *tmp; | |
1028 | ||
1029 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1030 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1031 | } | |
1032 | ||
012dd14d | 1033 | debugfs_remove_recursive(con->dir); |
c030f2e4 | 1034 | con->dir = NULL; |
c030f2e4 | 1035 | } |
1036 | /* debugfs end */ | |
1037 | ||
1038 | /* ras fs */ | |
1039 | ||
1040 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1041 | { | |
c030f2e4 | 1042 | amdgpu_ras_sysfs_create_feature_node(adev); |
36ea1bd2 | 1043 | amdgpu_ras_debugfs_create_ctrl_node(adev); |
c030f2e4 | 1044 | |
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1049 | { | |
1050 | amdgpu_ras_debugfs_remove_all(adev); | |
1051 | amdgpu_ras_sysfs_remove_all(adev); | |
1052 | return 0; | |
1053 | } | |
1054 | /* ras fs end */ | |
1055 | ||
1056 | /* ih begin */ | |
1057 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1058 | { | |
1059 | struct ras_ih_data *data = &obj->ih_data; | |
1060 | struct amdgpu_iv_entry entry; | |
1061 | int ret; | |
cf04dfd0 | 1062 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1063 | |
1064 | while (data->rptr != data->wptr) { | |
1065 | rmb(); | |
1066 | memcpy(&entry, &data->ring[data->rptr], | |
1067 | data->element_size); | |
1068 | ||
1069 | wmb(); | |
1070 | data->rptr = (data->aligned_element_size + | |
1071 | data->rptr) % data->ring_size; | |
1072 | ||
1073 | /* Let IP handle its data, maybe we need get the output | |
1074 | * from the callback to udpate the error type/count, etc | |
1075 | */ | |
1076 | if (data->cb) { | |
cf04dfd0 | 1077 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1078 | /* ue will trigger an interrupt, and in that case |
1079 | * we need do a reset to recovery the whole system. | |
1080 | * But leave IP do that recovery, here we just dispatch | |
1081 | * the error. | |
1082 | */ | |
bd2280da | 1083 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1084 | /* these counts could be left as 0 if |
1085 | * some blocks do not count error number | |
1086 | */ | |
cf04dfd0 | 1087 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1088 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1089 | } |
c030f2e4 | 1090 | } |
1091 | } | |
1092 | } | |
1093 | ||
1094 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1095 | { | |
1096 | struct ras_ih_data *data = | |
1097 | container_of(work, struct ras_ih_data, ih_work); | |
1098 | struct ras_manager *obj = | |
1099 | container_of(data, struct ras_manager, ih_data); | |
1100 | ||
1101 | amdgpu_ras_interrupt_handler(obj); | |
1102 | } | |
1103 | ||
1104 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1105 | struct ras_dispatch_if *info) | |
1106 | { | |
1107 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1108 | struct ras_ih_data *data = &obj->ih_data; | |
1109 | ||
1110 | if (!obj) | |
1111 | return -EINVAL; | |
1112 | ||
1113 | if (data->inuse == 0) | |
1114 | return 0; | |
1115 | ||
1116 | /* Might be overflow... */ | |
1117 | memcpy(&data->ring[data->wptr], info->entry, | |
1118 | data->element_size); | |
1119 | ||
1120 | wmb(); | |
1121 | data->wptr = (data->aligned_element_size + | |
1122 | data->wptr) % data->ring_size; | |
1123 | ||
1124 | schedule_work(&data->ih_work); | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1130 | struct ras_ih_if *info) | |
1131 | { | |
1132 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1133 | struct ras_ih_data *data; | |
1134 | ||
1135 | if (!obj) | |
1136 | return -EINVAL; | |
1137 | ||
1138 | data = &obj->ih_data; | |
1139 | if (data->inuse == 0) | |
1140 | return 0; | |
1141 | ||
1142 | cancel_work_sync(&data->ih_work); | |
1143 | ||
1144 | kfree(data->ring); | |
1145 | memset(data, 0, sizeof(*data)); | |
1146 | put_obj(obj); | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
1151 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1152 | struct ras_ih_if *info) | |
1153 | { | |
1154 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1155 | struct ras_ih_data *data; | |
1156 | ||
1157 | if (!obj) { | |
1158 | /* in case we registe the IH before enable ras feature */ | |
1159 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1160 | if (!obj) | |
1161 | return -EINVAL; | |
1162 | } else | |
1163 | get_obj(obj); | |
1164 | ||
1165 | data = &obj->ih_data; | |
1166 | /* add the callback.etc */ | |
1167 | *data = (struct ras_ih_data) { | |
1168 | .inuse = 0, | |
1169 | .cb = info->cb, | |
1170 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1171 | .rptr = 0, | |
1172 | .wptr = 0, | |
1173 | }; | |
1174 | ||
1175 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1176 | ||
1177 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1178 | /* the ring can store 64 iv entries. */ | |
1179 | data->ring_size = 64 * data->aligned_element_size; | |
1180 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1181 | if (!data->ring) { | |
1182 | put_obj(obj); | |
1183 | return -ENOMEM; | |
1184 | } | |
1185 | ||
1186 | /* IH is ready */ | |
1187 | data->inuse = 1; | |
1188 | ||
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1193 | { | |
1194 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1195 | struct ras_manager *obj, *tmp; | |
1196 | ||
1197 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1198 | struct ras_ih_if info = { | |
1199 | .head = obj->head, | |
1200 | }; | |
1201 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1202 | } | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | /* ih end */ | |
1207 | ||
1208 | /* recovery begin */ | |
466b1793 | 1209 | |
1210 | /* return 0 on success. | |
1211 | * caller need free bps. | |
1212 | */ | |
1213 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1214 | struct ras_badpage **bps, unsigned int *count) | |
1215 | { | |
1216 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1217 | struct ras_err_handler_data *data; | |
1218 | int i = 0; | |
1219 | int ret = 0; | |
1220 | ||
1221 | if (!con || !con->eh_data || !bps || !count) | |
1222 | return -EINVAL; | |
1223 | ||
1224 | mutex_lock(&con->recovery_lock); | |
1225 | data = con->eh_data; | |
1226 | if (!data || data->count == 0) { | |
1227 | *bps = NULL; | |
1228 | goto out; | |
1229 | } | |
1230 | ||
1231 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1232 | if (!*bps) { | |
1233 | ret = -ENOMEM; | |
1234 | goto out; | |
1235 | } | |
1236 | ||
1237 | for (; i < data->count; i++) { | |
1238 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1239 | .bp = data->bps[i].retired_page, |
466b1793 | 1240 | .size = AMDGPU_GPU_PAGE_SIZE, |
1241 | .flags = 0, | |
1242 | }; | |
1243 | ||
1244 | if (data->last_reserved <= i) | |
1245 | (*bps)[i].flags = 1; | |
9dc23a63 | 1246 | else if (data->bps_bo[i] == NULL) |
466b1793 | 1247 | (*bps)[i].flags = 2; |
1248 | } | |
1249 | ||
1250 | *count = data->count; | |
1251 | out: | |
1252 | mutex_unlock(&con->recovery_lock); | |
1253 | return ret; | |
1254 | } | |
1255 | ||
c030f2e4 | 1256 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1257 | { | |
1258 | struct amdgpu_ras *ras = | |
1259 | container_of(work, struct amdgpu_ras, recovery_work); | |
1260 | ||
1261 | amdgpu_device_gpu_recover(ras->adev, 0); | |
1262 | atomic_set(&ras->in_recovery, 0); | |
1263 | } | |
1264 | ||
c030f2e4 | 1265 | /* alloc/realloc bps array */ |
1266 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1267 | struct ras_err_handler_data *data, int pages) | |
1268 | { | |
1269 | unsigned int old_space = data->count + data->space_left; | |
1270 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1271 | unsigned int align_space = ALIGN(new_space, 512); |
1272 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1273 | struct amdgpu_bo **bps_bo = | |
1274 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1275 | ||
1276 | if (!bps || !bps_bo) { | |
1277 | kfree(bps); | |
1278 | kfree(bps_bo); | |
c030f2e4 | 1279 | return -ENOMEM; |
9dc23a63 | 1280 | } |
c030f2e4 | 1281 | |
1282 | if (data->bps) { | |
9dc23a63 | 1283 | memcpy(bps, data->bps, |
c030f2e4 | 1284 | data->count * sizeof(*data->bps)); |
1285 | kfree(data->bps); | |
1286 | } | |
9dc23a63 TZ |
1287 | if (data->bps_bo) { |
1288 | memcpy(bps_bo, data->bps_bo, | |
1289 | data->count * sizeof(*data->bps_bo)); | |
1290 | kfree(data->bps_bo); | |
1291 | } | |
c030f2e4 | 1292 | |
9dc23a63 TZ |
1293 | data->bps = bps; |
1294 | data->bps_bo = bps_bo; | |
c030f2e4 | 1295 | data->space_left += align_space - old_space; |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | /* it deal with vram only. */ | |
1300 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1301 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1302 | { |
1303 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1304 | struct ras_err_handler_data *data; |
c030f2e4 | 1305 | int ret = 0; |
1306 | ||
73aa8e1a | 1307 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1308 | return 0; |
1309 | ||
1310 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1311 | data = con->eh_data; |
c030f2e4 | 1312 | if (!data) |
1313 | goto out; | |
1314 | ||
1315 | if (data->space_left <= pages) | |
1316 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1317 | ret = -ENOMEM; | |
1318 | goto out; | |
1319 | } | |
1320 | ||
9dc23a63 TZ |
1321 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1322 | data->count += pages; | |
c030f2e4 | 1323 | data->space_left -= pages; |
9dc23a63 | 1324 | |
c030f2e4 | 1325 | out: |
1326 | mutex_unlock(&con->recovery_lock); | |
1327 | ||
1328 | return ret; | |
1329 | } | |
1330 | ||
78ad00c9 TZ |
1331 | /* |
1332 | * write error record array to eeprom, the function should be | |
1333 | * protected by recovery_lock | |
1334 | */ | |
1335 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1336 | { | |
1337 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1338 | struct ras_err_handler_data *data; | |
1339 | struct amdgpu_ras_eeprom_control *control = | |
1340 | &adev->psp.ras.ras->eeprom_control; | |
1341 | int save_count; | |
1342 | ||
1343 | if (!con || !con->eh_data) | |
1344 | return 0; | |
1345 | ||
1346 | data = con->eh_data; | |
1347 | save_count = data->count - control->num_recs; | |
1348 | /* only new entries are saved */ | |
1349 | if (save_count > 0) | |
1350 | if (amdgpu_ras_eeprom_process_recods(&con->eeprom_control, | |
1351 | &data->bps[control->num_recs], | |
1352 | true, | |
1353 | save_count)) { | |
1354 | DRM_ERROR("Failed to save EEPROM table data!"); | |
1355 | return -EIO; | |
1356 | } | |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | /* | |
1362 | * read error record array in eeprom and reserve enough space for | |
1363 | * storing new bad pages | |
1364 | */ | |
1365 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1366 | { | |
1367 | struct amdgpu_ras_eeprom_control *control = | |
1368 | &adev->psp.ras.ras->eeprom_control; | |
1369 | struct eeprom_table_record *bps = NULL; | |
1370 | int ret = 0; | |
1371 | ||
1372 | /* no bad page record, skip eeprom access */ | |
1373 | if (!control->num_recs) | |
1374 | return ret; | |
1375 | ||
1376 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1377 | if (!bps) | |
1378 | return -ENOMEM; | |
1379 | ||
1380 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1381 | control->num_recs)) { | |
1382 | DRM_ERROR("Failed to load EEPROM table records!"); | |
1383 | ret = -EIO; | |
1384 | goto out; | |
1385 | } | |
1386 | ||
1387 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1388 | ||
1389 | out: | |
1390 | kfree(bps); | |
1391 | return ret; | |
1392 | } | |
1393 | ||
c030f2e4 | 1394 | /* called in gpu recovery/init */ |
1395 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1396 | { | |
1397 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1398 | struct ras_err_handler_data *data; |
c030f2e4 | 1399 | uint64_t bp; |
de7b45ba | 1400 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1401 | int i, ret = 0; |
c030f2e4 | 1402 | |
73aa8e1a | 1403 | if (!con || !con->eh_data) |
c030f2e4 | 1404 | return 0; |
1405 | ||
1406 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1407 | data = con->eh_data; |
1408 | if (!data) | |
1409 | goto out; | |
c030f2e4 | 1410 | /* reserve vram at driver post stage. */ |
1411 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1412 | bp = data->bps[i].retired_page; |
c030f2e4 | 1413 | |
ae115c81 TZ |
1414 | /* There are two cases of reserve error should be ignored: |
1415 | * 1) a ras bad page has been allocated (used by someone); | |
1416 | * 2) a ras bad page has been reserved (duplicate error injection | |
1417 | * for one page); | |
1418 | */ | |
de7b45ba CK |
1419 | if (amdgpu_bo_create_kernel_at(adev, bp << PAGE_SHIFT, PAGE_SIZE, |
1420 | AMDGPU_GEM_DOMAIN_VRAM, | |
1421 | &bo, NULL)) | |
ae115c81 | 1422 | DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp); |
c030f2e4 | 1423 | |
9dc23a63 | 1424 | data->bps_bo[i] = bo; |
c030f2e4 | 1425 | data->last_reserved = i + 1; |
de7b45ba | 1426 | bo = NULL; |
c030f2e4 | 1427 | } |
78ad00c9 TZ |
1428 | |
1429 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1430 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1431 | out: |
c030f2e4 | 1432 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1433 | return ret; |
c030f2e4 | 1434 | } |
1435 | ||
1436 | /* called when driver unload */ | |
1437 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1438 | { | |
1439 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1440 | struct ras_err_handler_data *data; |
c030f2e4 | 1441 | struct amdgpu_bo *bo; |
1442 | int i; | |
1443 | ||
73aa8e1a | 1444 | if (!con || !con->eh_data) |
c030f2e4 | 1445 | return 0; |
1446 | ||
1447 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1448 | data = con->eh_data; |
1449 | if (!data) | |
1450 | goto out; | |
1451 | ||
c030f2e4 | 1452 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1453 | bo = data->bps_bo[i]; |
c030f2e4 | 1454 | |
de7b45ba | 1455 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1456 | |
9dc23a63 | 1457 | data->bps_bo[i] = bo; |
c030f2e4 | 1458 | data->last_reserved = i; |
1459 | } | |
73aa8e1a | 1460 | out: |
c030f2e4 | 1461 | mutex_unlock(&con->recovery_lock); |
1462 | return 0; | |
1463 | } | |
1464 | ||
1a6fc071 | 1465 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1466 | { |
1467 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1468 | struct ras_err_handler_data **data; |
78ad00c9 | 1469 | int ret; |
c030f2e4 | 1470 | |
4d1337d2 AG |
1471 | if (con) |
1472 | data = &con->eh_data; | |
1473 | else | |
1474 | return 0; | |
1475 | ||
1a6fc071 TZ |
1476 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1477 | if (!*data) { | |
1478 | ret = -ENOMEM; | |
1479 | goto out; | |
1480 | } | |
c030f2e4 | 1481 | |
1482 | mutex_init(&con->recovery_lock); | |
1483 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1484 | atomic_set(&con->in_recovery, 0); | |
1485 | con->adev = adev; | |
1486 | ||
78ad00c9 TZ |
1487 | ret = amdgpu_ras_eeprom_init(&adev->psp.ras.ras->eeprom_control); |
1488 | if (ret) | |
1a6fc071 | 1489 | goto free; |
78ad00c9 TZ |
1490 | |
1491 | if (adev->psp.ras.ras->eeprom_control.num_recs) { | |
1492 | ret = amdgpu_ras_load_bad_pages(adev); | |
1493 | if (ret) | |
1a6fc071 | 1494 | goto free; |
78ad00c9 TZ |
1495 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1496 | if (ret) | |
1a6fc071 | 1497 | goto release; |
78ad00c9 | 1498 | } |
c030f2e4 | 1499 | |
1500 | return 0; | |
1a6fc071 TZ |
1501 | |
1502 | release: | |
1503 | amdgpu_ras_release_bad_pages(adev); | |
1504 | free: | |
1505 | con->eh_data = NULL; | |
1506 | kfree((*data)->bps); | |
1507 | kfree((*data)->bps_bo); | |
1508 | kfree(*data); | |
1509 | out: | |
1510 | DRM_WARN("Failed to initialize ras recovery!\n"); | |
1511 | ||
1512 | return ret; | |
c030f2e4 | 1513 | } |
1514 | ||
1515 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1516 | { | |
1517 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1518 | struct ras_err_handler_data *data = con->eh_data; | |
1519 | ||
1a6fc071 TZ |
1520 | /* recovery_init failed to init it, fini is useless */ |
1521 | if (!data) | |
1522 | return 0; | |
1523 | ||
c030f2e4 | 1524 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1525 | amdgpu_ras_release_bad_pages(adev); |
1526 | ||
1527 | mutex_lock(&con->recovery_lock); | |
1528 | con->eh_data = NULL; | |
1529 | kfree(data->bps); | |
1a6fc071 | 1530 | kfree(data->bps_bo); |
c030f2e4 | 1531 | kfree(data); |
1532 | mutex_unlock(&con->recovery_lock); | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | /* recovery end */ | |
1537 | ||
a564808e | 1538 | /* return 0 if ras will reset gpu and repost.*/ |
1539 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1540 | unsigned int block) | |
1541 | { | |
1542 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1543 | ||
1544 | if (!ras) | |
1545 | return -EINVAL; | |
1546 | ||
1547 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1548 | return 0; | |
1549 | } | |
1550 | ||
5caf466a | 1551 | /* |
1552 | * check hardware's ras ability which will be saved in hw_supported. | |
1553 | * if hardware does not support ras, we can skip some ras initializtion and | |
1554 | * forbid some ras operations from IP. | |
1555 | * if software itself, say boot parameter, limit the ras ability. We still | |
1556 | * need allow IP do some limited operations, like disable. In such case, | |
1557 | * we have to initialize ras as normal. but need check if operation is | |
1558 | * allowed or not in each function. | |
1559 | */ | |
1560 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1561 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1562 | { |
5caf466a | 1563 | *hw_supported = 0; |
1564 | *supported = 0; | |
c030f2e4 | 1565 | |
5caf466a | 1566 | if (amdgpu_sriov_vf(adev) || |
b404ae82 | 1567 | adev->asic_type != CHIP_VEGA20) |
5caf466a | 1568 | return; |
b404ae82 | 1569 | |
5d0f903f | 1570 | if (adev->is_atom_fw && |
1571 | (amdgpu_atomfirmware_mem_ecc_supported(adev) || | |
1572 | amdgpu_atomfirmware_sram_ecc_supported(adev))) | |
5caf466a | 1573 | *hw_supported = AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 1574 | |
5caf466a | 1575 | *supported = amdgpu_ras_enable == 0 ? |
1576 | 0 : *hw_supported & amdgpu_ras_mask; | |
c030f2e4 | 1577 | } |
1578 | ||
1579 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1580 | { | |
1581 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1582 | int r; |
c030f2e4 | 1583 | |
b404ae82 | 1584 | if (con) |
c030f2e4 | 1585 | return 0; |
1586 | ||
1587 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1588 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1589 | GFP_KERNEL|__GFP_ZERO); | |
1590 | if (!con) | |
1591 | return -ENOMEM; | |
1592 | ||
1593 | con->objs = (struct ras_manager *)(con + 1); | |
1594 | ||
1595 | amdgpu_ras_set_context(adev, con); | |
1596 | ||
5caf466a | 1597 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1598 | &con->supported); | |
fb2a3607 HZ |
1599 | if (!con->hw_supported) { |
1600 | amdgpu_ras_set_context(adev, NULL); | |
1601 | kfree(con); | |
1602 | return 0; | |
1603 | } | |
1604 | ||
c030f2e4 | 1605 | con->features = 0; |
1606 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1607 | /* Might need get this flag from vbios. */ |
1608 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1609 | |
4e644fff HZ |
1610 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1611 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1612 | if (r) | |
1613 | return r; | |
1614 | } | |
1615 | ||
1616 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1617 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
1618 | if (r) | |
1619 | return r; | |
1620 | } | |
1621 | ||
c030f2e4 | 1622 | amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK; |
1623 | ||
c030f2e4 | 1624 | if (amdgpu_ras_fs_init(adev)) |
1625 | goto fs_out; | |
1626 | ||
5d0f903f | 1627 | DRM_INFO("RAS INFO: ras initialized successfully, " |
1628 | "hardware ability[%x] ras_mask[%x]\n", | |
1629 | con->hw_supported, con->supported); | |
c030f2e4 | 1630 | return 0; |
1631 | fs_out: | |
c030f2e4 | 1632 | amdgpu_ras_set_context(adev, NULL); |
1633 | kfree(con); | |
1634 | ||
1635 | return -EINVAL; | |
1636 | } | |
1637 | ||
b293e891 HZ |
1638 | /* helper function to handle common stuff in ip late init phase */ |
1639 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
1640 | struct ras_common_if *ras_block, | |
1641 | struct ras_fs_if *fs_info, | |
1642 | struct ras_ih_if *ih_info) | |
1643 | { | |
1644 | int r; | |
1645 | ||
1646 | /* disable RAS feature per IP block if it is not supported */ | |
1647 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
1648 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
1649 | return 0; | |
1650 | } | |
1651 | ||
1652 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
1653 | if (r) { | |
1654 | if (r == -EAGAIN) { | |
1655 | /* request gpu reset. will run again */ | |
1656 | amdgpu_ras_request_reset_on_boot(adev, | |
1657 | ras_block->block); | |
1658 | return 0; | |
1659 | } else if (adev->in_suspend || adev->in_gpu_reset) { | |
1660 | /* in resume phase, if fail to enable ras, | |
1661 | * clean up all ras fs nodes, and disable ras */ | |
1662 | goto cleanup; | |
1663 | } else | |
1664 | return r; | |
1665 | } | |
1666 | ||
1667 | /* in resume phase, no need to create ras fs node */ | |
1668 | if (adev->in_suspend || adev->in_gpu_reset) | |
1669 | return 0; | |
1670 | ||
1671 | if (ih_info->cb) { | |
1672 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
1673 | if (r) | |
1674 | goto interrupt; | |
1675 | } | |
1676 | ||
1677 | amdgpu_ras_debugfs_create(adev, fs_info); | |
1678 | ||
1679 | r = amdgpu_ras_sysfs_create(adev, fs_info); | |
1680 | if (r) | |
1681 | goto sysfs; | |
1682 | ||
1683 | return 0; | |
1684 | cleanup: | |
1685 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
1686 | sysfs: | |
1687 | amdgpu_ras_debugfs_remove(adev, ras_block); | |
1688 | if (ih_info->cb) | |
1689 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1690 | interrupt: | |
1691 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1692 | return r; | |
1693 | } | |
1694 | ||
1695 | /* helper function to remove ras fs node and interrupt handler */ | |
1696 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
1697 | struct ras_common_if *ras_block, | |
1698 | struct ras_ih_if *ih_info) | |
1699 | { | |
1700 | if (!ras_block || !ih_info) | |
1701 | return; | |
1702 | ||
1703 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
1704 | amdgpu_ras_debugfs_remove(adev, ras_block); | |
1705 | if (ih_info->cb) | |
1706 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1707 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1708 | } | |
1709 | ||
a564808e | 1710 | /* do some init work after IP late init as dependence. |
511fdbc3 | 1711 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 1712 | */ |
511fdbc3 | 1713 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 1714 | { |
1715 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1716 | struct ras_manager *obj, *tmp; | |
1717 | ||
1718 | if (!con) | |
1719 | return; | |
1720 | ||
108c6a63 | 1721 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 1722 | /* Set up all other IPs which are not implemented. There is a |
1723 | * tricky thing that IP's actual ras error type should be | |
1724 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
1725 | * ERROR_NONE make sense anyway. | |
1726 | */ | |
1727 | amdgpu_ras_enable_all_features(adev, 1); | |
1728 | ||
1729 | /* We enable ras on all hw_supported block, but as boot | |
1730 | * parameter might disable some of them and one or more IP has | |
1731 | * not implemented yet. So we disable them on behalf. | |
1732 | */ | |
108c6a63 | 1733 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
1734 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
1735 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
1736 | /* there should be no any reference. */ | |
1737 | WARN_ON(alive_obj(obj)); | |
1738 | } | |
191051a1 | 1739 | } |
108c6a63 | 1740 | } |
a564808e | 1741 | |
1742 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
1743 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1744 | /* setup ras obj state as disabled. | |
1745 | * for init_by_vbios case. | |
1746 | * if we want to enable ras, just enable it in a normal way. | |
1747 | * If we want do disable it, need setup ras obj as enabled, | |
1748 | * then issue another TA disable cmd. | |
1749 | * See feature_enable_on_boot | |
1750 | */ | |
1751 | amdgpu_ras_disable_all_features(adev, 1); | |
1752 | amdgpu_ras_reset_gpu(adev, 0); | |
1753 | } | |
108c6a63 | 1754 | } |
1755 | ||
511fdbc3 | 1756 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
1757 | { | |
1758 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1759 | ||
1760 | if (!con) | |
1761 | return; | |
1762 | ||
1763 | amdgpu_ras_disable_all_features(adev, 0); | |
1764 | /* Make sure all ras objects are disabled. */ | |
1765 | if (con->features) | |
1766 | amdgpu_ras_disable_all_features(adev, 1); | |
1767 | } | |
1768 | ||
c030f2e4 | 1769 | /* do some fini work before IP fini as dependence */ |
1770 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
1771 | { | |
1772 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1773 | ||
1774 | if (!con) | |
1775 | return 0; | |
1776 | ||
1777 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
1778 | amdgpu_ras_disable_all_features(adev, 0); | |
1779 | amdgpu_ras_recovery_fini(adev); | |
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
1784 | { | |
1785 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1786 | ||
1787 | if (!con) | |
1788 | return 0; | |
1789 | ||
1790 | amdgpu_ras_fs_fini(adev); | |
1791 | amdgpu_ras_interrupt_remove_all(adev); | |
1792 | ||
1793 | WARN(con->features, "Feature mask is not cleared"); | |
1794 | ||
1795 | if (con->features) | |
1796 | amdgpu_ras_disable_all_features(adev, 1); | |
1797 | ||
1798 | amdgpu_ras_set_context(adev, NULL); | |
1799 | kfree(con); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
7c6e68c7 AG |
1803 | |
1804 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
1805 | { | |
1806 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { | |
d5ea093e AG |
1807 | DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n"); |
1808 | ||
1809 | amdgpu_ras_reset_gpu(adev, false); | |
7c6e68c7 AG |
1810 | } |
1811 | } |