Commit | Line | Data |
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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
c030f2e4 | 37 | const char *ras_error_string[] = { |
38 | "none", | |
39 | "parity", | |
40 | "single_correctable", | |
41 | "multi_uncorrectable", | |
42 | "poison", | |
43 | }; | |
44 | ||
45 | const char *ras_block_string[] = { | |
46 | "umc", | |
47 | "sdma", | |
48 | "gfx", | |
49 | "mmhub", | |
50 | "athub", | |
51 | "pcie_bif", | |
52 | "hdp", | |
53 | "xgmi_wafl", | |
54 | "df", | |
55 | "smn", | |
56 | "sem", | |
57 | "mp0", | |
58 | "mp1", | |
59 | "fuse", | |
60 | }; | |
61 | ||
62 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
63 | #define ras_block_str(i) (ras_block_string[i]) | |
64 | ||
a564808e | 65 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 |
66 | #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 | |
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
52dd95f2 GC |
72 | enum amdgpu_ras_retire_page_reservation { |
73 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
74 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
75 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
76 | }; | |
7c6e68c7 AG |
77 | |
78 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
79 | ||
6e4be987 TZ |
80 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
81 | uint64_t addr); | |
82 | ||
61380faa JC |
83 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
84 | { | |
a9d82d2f | 85 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
86 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
87 | } | |
88 | ||
f3167919 | 89 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 90 | { |
a9d82d2f | 91 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
92 | return amdgpu_ras_get_context(adev)->error_query_ready; |
93 | ||
94 | return false; | |
95 | } | |
96 | ||
c030f2e4 | 97 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
98 | size_t size, loff_t *pos) | |
99 | { | |
100 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
101 | struct ras_query_if info = { | |
102 | .head = obj->head, | |
103 | }; | |
104 | ssize_t s; | |
105 | char val[128]; | |
106 | ||
107 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
108 | return -EINVAL; | |
109 | ||
110 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
111 | "ue", info.ue_count, | |
112 | "ce", info.ce_count); | |
113 | if (*pos >= s) | |
114 | return 0; | |
115 | ||
116 | s -= *pos; | |
117 | s = min_t(u64, s, size); | |
118 | ||
119 | ||
120 | if (copy_to_user(buf, &val[*pos], s)) | |
121 | return -EINVAL; | |
122 | ||
123 | *pos += s; | |
124 | ||
125 | return s; | |
126 | } | |
127 | ||
c030f2e4 | 128 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
129 | .owner = THIS_MODULE, | |
130 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 131 | .write = NULL, |
c030f2e4 | 132 | .llseek = default_llseek |
133 | }; | |
134 | ||
96ebb307 | 135 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
136 | { | |
137 | int i; | |
138 | ||
139 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
140 | *block_id = i; | |
141 | if (strcmp(name, ras_block_str(i)) == 0) | |
142 | return 0; | |
143 | } | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
147 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
148 | const char __user *buf, size_t size, | |
149 | loff_t *pos, struct ras_debug_if *data) | |
150 | { | |
151 | ssize_t s = min_t(u64, 64, size); | |
152 | char str[65]; | |
153 | char block_name[33]; | |
154 | char err[9] = "ue"; | |
155 | int op = -1; | |
156 | int block_id; | |
44494f96 | 157 | uint32_t sub_block; |
96ebb307 | 158 | u64 address, value; |
159 | ||
160 | if (*pos) | |
161 | return -EINVAL; | |
162 | *pos = size; | |
163 | ||
164 | memset(str, 0, sizeof(str)); | |
165 | memset(data, 0, sizeof(*data)); | |
166 | ||
167 | if (copy_from_user(str, buf, s)) | |
168 | return -EINVAL; | |
169 | ||
170 | if (sscanf(str, "disable %32s", block_name) == 1) | |
171 | op = 0; | |
172 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
173 | op = 1; | |
174 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
175 | op = 2; | |
b076296b | 176 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 177 | /* ascii string, but commands are not matched. */ |
178 | return -EINVAL; | |
179 | ||
180 | if (op != -1) { | |
181 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
182 | return -EINVAL; | |
183 | ||
184 | data->head.block = block_id; | |
e1063493 TZ |
185 | /* only ue and ce errors are supported */ |
186 | if (!memcmp("ue", err, 2)) | |
187 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
188 | else if (!memcmp("ce", err, 2)) | |
189 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
190 | else | |
191 | return -EINVAL; | |
192 | ||
96ebb307 | 193 | data->op = op; |
194 | ||
195 | if (op == 2) { | |
44494f96 TZ |
196 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
197 | &sub_block, &address, &value) != 3) | |
198 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
199 | &sub_block, &address, &value) != 3) | |
96ebb307 | 200 | return -EINVAL; |
44494f96 | 201 | data->head.sub_block_index = sub_block; |
96ebb307 | 202 | data->inject.address = address; |
203 | data->inject.value = value; | |
204 | } | |
205 | } else { | |
73aa8e1a | 206 | if (size < sizeof(*data)) |
96ebb307 | 207 | return -EINVAL; |
208 | ||
209 | if (copy_from_user(data, buf, sizeof(*data))) | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
7c6e68c7 | 215 | |
74abc221 TSD |
216 | /** |
217 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 218 | * |
219 | * It accepts struct ras_debug_if who has two members. | |
220 | * | |
221 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 222 | * |
223 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 224 | * |
225 | * head has four members, they are block, type, sub_block_index, name. | |
226 | * block: which IP will be under control. | |
227 | * type: what kind of error will be enabled/disabled/injected. | |
228 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
229 | * name: the name of IP. | |
230 | * | |
231 | * inject has two more members than head, they are address, value. | |
232 | * As their names indicate, inject operation will write the | |
233 | * value to the address. | |
234 | * | |
ef177d11 | 235 | * The second member: struct ras_debug_if::op. |
c688a06b | 236 | * It has three kinds of operations. |
879e723d AZ |
237 | * |
238 | * - 0: disable RAS on the block. Take ::head as its data. | |
239 | * - 1: enable RAS on the block. Take ::head as its data. | |
240 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 241 | * |
96ebb307 | 242 | * How to use the interface? |
ef177d11 AD |
243 | * |
244 | * Programs | |
245 | * | |
246 | * Copy the struct ras_debug_if in your codes and initialize it. | |
247 | * Write the struct to the control node. | |
248 | * | |
249 | * Shells | |
96ebb307 | 250 | * |
879e723d AZ |
251 | * .. code-block:: bash |
252 | * | |
a20bfd0f | 253 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 254 | * |
ef177d11 AD |
255 | * Parameters: |
256 | * | |
879e723d AZ |
257 | * op: disable, enable, inject |
258 | * disable: only block is needed | |
259 | * enable: block and error are needed | |
260 | * inject: error, address, value are needed | |
a20bfd0f | 261 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
262 | * see ras_block_string[] for details |
263 | * error: ue, ce | |
264 | * ue: multi_uncorrectable | |
265 | * ce: single_correctable | |
266 | * sub_block: | |
267 | * sub block index, pass 0 if there is no sub block | |
268 | * | |
269 | * here are some examples for bash commands: | |
270 | * | |
271 | * .. code-block:: bash | |
96ebb307 | 272 | * |
44494f96 TZ |
273 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
274 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 275 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
276 | * | |
36ea1bd2 | 277 | * How to check the result? |
278 | * | |
279 | * For disable/enable, please check ras features at | |
280 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
281 | * | |
282 | * For inject, please check corresponding err count at | |
283 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
284 | * | |
879e723d | 285 | * .. note:: |
ef177d11 | 286 | * Operations are only allowed on blocks which are supported. |
879e723d | 287 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
288 | * to see which blocks support RAS on a particular asic. |
289 | * | |
36ea1bd2 | 290 | */ |
291 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
292 | size_t size, loff_t *pos) | |
293 | { | |
294 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
295 | struct ras_debug_if data; | |
296 | int ret = 0; | |
297 | ||
61380faa | 298 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
299 | dev_warn(adev->dev, "RAS WARN: error injection " |
300 | "currently inaccessible\n"); | |
43c4d576 JC |
301 | return size; |
302 | } | |
303 | ||
96ebb307 | 304 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
305 | if (ret) | |
36ea1bd2 | 306 | return -EINVAL; |
307 | ||
36ea1bd2 | 308 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
309 | return -EINVAL; | |
310 | ||
311 | switch (data.op) { | |
312 | case 0: | |
313 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
314 | break; | |
315 | case 1: | |
316 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
317 | break; | |
318 | case 2: | |
7cdc2ee3 TZ |
319 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
320 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
321 | dev_warn(adev->dev, "RAS WARN: input address " |
322 | "0x%llx is invalid.", | |
323 | data.inject.address); | |
7cdc2ee3 TZ |
324 | ret = -EINVAL; |
325 | break; | |
326 | } | |
327 | ||
6e4be987 TZ |
328 | /* umc ce/ue error injection for a bad page is not allowed */ |
329 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
330 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
331 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
332 | "as bad before error injection!\n", | |
6e4be987 TZ |
333 | data.inject.address); |
334 | break; | |
335 | } | |
336 | ||
7cdc2ee3 | 337 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 338 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
339 | break; | |
96ebb307 | 340 | default: |
341 | ret = -EINVAL; | |
342 | break; | |
374bf7bd | 343 | } |
36ea1bd2 | 344 | |
345 | if (ret) | |
346 | return -EINVAL; | |
347 | ||
348 | return size; | |
349 | } | |
350 | ||
084fe13b AG |
351 | /** |
352 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
353 | * | |
f77c7109 | 354 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 355 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
356 | * a way to reset the EEPROM, e.g., after testing error injection. |
357 | * | |
358 | * Usage: | |
359 | * | |
360 | * .. code-block:: bash | |
361 | * | |
362 | * echo 1 > ../ras/ras_eeprom_reset | |
363 | * | |
364 | * will reset EEPROM table to 0 entries. | |
365 | * | |
084fe13b AG |
366 | */ |
367 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
368 | size_t size, loff_t *pos) | |
369 | { | |
370 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
371 | int ret; | |
372 | ||
373 | ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); | |
374 | ||
375 | return ret == 1 ? size : -EIO; | |
376 | } | |
377 | ||
36ea1bd2 | 378 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
379 | .owner = THIS_MODULE, | |
380 | .read = NULL, | |
381 | .write = amdgpu_ras_debugfs_ctrl_write, | |
382 | .llseek = default_llseek | |
383 | }; | |
384 | ||
084fe13b AG |
385 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
386 | .owner = THIS_MODULE, | |
387 | .read = NULL, | |
388 | .write = amdgpu_ras_debugfs_eeprom_write, | |
389 | .llseek = default_llseek | |
390 | }; | |
391 | ||
f77c7109 AD |
392 | /** |
393 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
394 | * | |
ef177d11 | 395 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
396 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
397 | * | |
398 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
399 | * (ce) error counts. | |
400 | * | |
401 | * The format of one line is below, | |
402 | * | |
403 | * [ce|ue]: count | |
404 | * | |
405 | * Example: | |
406 | * | |
407 | * .. code-block:: bash | |
408 | * | |
409 | * ue: 0 | |
410 | * ce: 1 | |
411 | * | |
412 | */ | |
c030f2e4 | 413 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
414 | struct device_attribute *attr, char *buf) | |
415 | { | |
416 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
417 | struct ras_query_if info = { | |
418 | .head = obj->head, | |
419 | }; | |
420 | ||
61380faa | 421 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
43c4d576 JC |
422 | return snprintf(buf, PAGE_SIZE, |
423 | "Query currently inaccessible\n"); | |
424 | ||
c030f2e4 | 425 | if (amdgpu_ras_error_query(obj->adev, &info)) |
426 | return -EINVAL; | |
427 | ||
428 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
429 | "ue", info.ue_count, | |
430 | "ce", info.ce_count); | |
431 | } | |
432 | ||
433 | /* obj begin */ | |
434 | ||
435 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
436 | #define alive_obj(obj) ((obj)->use) | |
437 | ||
438 | static inline void put_obj(struct ras_manager *obj) | |
439 | { | |
440 | if (obj && --obj->use == 0) | |
441 | list_del(&obj->node); | |
442 | if (obj && obj->use < 0) { | |
443 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
444 | } | |
445 | } | |
446 | ||
447 | /* make one obj and return it. */ | |
448 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
449 | struct ras_common_if *head) | |
450 | { | |
451 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
452 | struct ras_manager *obj; | |
453 | ||
454 | if (!con) | |
455 | return NULL; | |
456 | ||
457 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
458 | return NULL; | |
459 | ||
460 | obj = &con->objs[head->block]; | |
461 | /* already exist. return obj? */ | |
462 | if (alive_obj(obj)) | |
463 | return NULL; | |
464 | ||
465 | obj->head = *head; | |
466 | obj->adev = adev; | |
467 | list_add(&obj->node, &con->head); | |
468 | get_obj(obj); | |
469 | ||
470 | return obj; | |
471 | } | |
472 | ||
473 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 474 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 475 | struct ras_common_if *head) |
476 | { | |
477 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
478 | struct ras_manager *obj; | |
479 | int i; | |
480 | ||
481 | if (!con) | |
482 | return NULL; | |
483 | ||
484 | if (head) { | |
485 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
486 | return NULL; | |
487 | ||
488 | obj = &con->objs[head->block]; | |
489 | ||
490 | if (alive_obj(obj)) { | |
491 | WARN_ON(head->block != obj->head.block); | |
492 | return obj; | |
493 | } | |
494 | } else { | |
495 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
496 | obj = &con->objs[i]; | |
497 | if (alive_obj(obj)) { | |
498 | WARN_ON(i != obj->head.block); | |
499 | return obj; | |
500 | } | |
501 | } | |
502 | } | |
503 | ||
504 | return NULL; | |
505 | } | |
506 | /* obj end */ | |
507 | ||
f3167919 | 508 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
a200034b JC |
509 | const char* invoke_type, |
510 | const char* block_name, | |
511 | enum ta_ras_status ret) | |
512 | { | |
513 | switch (ret) { | |
514 | case TA_RAS_STATUS__SUCCESS: | |
515 | return; | |
516 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
517 | dev_warn(adev->dev, | |
518 | "RAS WARN: %s %s currently unavailable\n", | |
519 | invoke_type, | |
520 | block_name); | |
521 | break; | |
522 | default: | |
523 | dev_err(adev->dev, | |
524 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
525 | invoke_type, | |
526 | block_name, | |
527 | ret); | |
528 | } | |
529 | } | |
530 | ||
c030f2e4 | 531 | /* feature ctl begin */ |
532 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
533 | struct ras_common_if *head) | |
534 | { | |
5caf466a | 535 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
536 | ||
537 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 538 | } |
539 | ||
540 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
541 | struct ras_common_if *head) | |
542 | { | |
543 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
544 | ||
545 | return con->features & BIT(head->block); | |
546 | } | |
547 | ||
548 | /* | |
549 | * if obj is not created, then create one. | |
550 | * set feature enable flag. | |
551 | */ | |
552 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
553 | struct ras_common_if *head, int enable) | |
554 | { | |
555 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
556 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
557 | ||
5caf466a | 558 | /* If hardware does not support ras, then do not create obj. |
559 | * But if hardware support ras, we can create the obj. | |
560 | * Ras framework checks con->hw_supported to see if it need do | |
561 | * corresponding initialization. | |
562 | * IP checks con->support to see if it need disable ras. | |
563 | */ | |
c030f2e4 | 564 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
565 | return 0; | |
566 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
567 | return 0; | |
568 | ||
569 | if (enable) { | |
570 | if (!obj) { | |
571 | obj = amdgpu_ras_create_obj(adev, head); | |
572 | if (!obj) | |
573 | return -EINVAL; | |
574 | } else { | |
575 | /* In case we create obj somewhere else */ | |
576 | get_obj(obj); | |
577 | } | |
578 | con->features |= BIT(head->block); | |
579 | } else { | |
580 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
581 | con->features &= ~BIT(head->block); | |
582 | put_obj(obj); | |
583 | } | |
584 | } | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
589 | /* wrapper of psp_ras_enable_features */ | |
590 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
591 | struct ras_common_if *head, bool enable) | |
592 | { | |
593 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 594 | union ta_ras_cmd_input *info; |
c030f2e4 | 595 | int ret; |
596 | ||
597 | if (!con) | |
598 | return -EINVAL; | |
599 | ||
7fcffecf AB |
600 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
601 | if (!info) | |
602 | return -ENOMEM; | |
603 | ||
c030f2e4 | 604 | if (!enable) { |
7fcffecf | 605 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 606 | .block_id = amdgpu_ras_block_to_ta(head->block), |
607 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 608 | }; |
609 | } else { | |
7fcffecf | 610 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 611 | .block_id = amdgpu_ras_block_to_ta(head->block), |
612 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 613 | }; |
614 | } | |
615 | ||
616 | /* Do not enable if it is not allowed. */ | |
617 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
618 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
619 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
620 | ret = 0; | |
621 | goto out; | |
622 | } | |
c030f2e4 | 623 | |
bff77e86 | 624 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 625 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 626 | if (ret) { |
a200034b JC |
627 | amdgpu_ras_parse_status_code(adev, |
628 | enable ? "enable":"disable", | |
629 | ras_block_str(head->block), | |
630 | (enum ta_ras_status)ret); | |
bff77e86 | 631 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
632 | ret = -EAGAIN; |
633 | else | |
634 | ret = -EINVAL; | |
635 | ||
636 | goto out; | |
bff77e86 | 637 | } |
c030f2e4 | 638 | } |
639 | ||
640 | /* setup the obj */ | |
641 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
642 | ret = 0; |
643 | out: | |
644 | kfree(info); | |
645 | return ret; | |
c030f2e4 | 646 | } |
647 | ||
77de502b | 648 | /* Only used in device probe stage and called only once. */ |
649 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
650 | struct ras_common_if *head, bool enable) | |
651 | { | |
652 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
653 | int ret; | |
654 | ||
655 | if (!con) | |
656 | return -EINVAL; | |
657 | ||
658 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 659 | if (enable) { |
660 | /* There is no harm to issue a ras TA cmd regardless of | |
661 | * the currecnt ras state. | |
662 | * If current state == target state, it will do nothing | |
663 | * But sometimes it requests driver to reset and repost | |
664 | * with error code -EAGAIN. | |
665 | */ | |
666 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
667 | /* With old ras TA, we might fail to enable ras. | |
668 | * Log it and just setup the object. | |
669 | * TODO need remove this WA in the future. | |
670 | */ | |
671 | if (ret == -EINVAL) { | |
672 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
673 | if (!ret) | |
6952e99c GC |
674 | dev_info(adev->dev, |
675 | "RAS INFO: %s setup object\n", | |
7af23ebe | 676 | ras_block_str(head->block)); |
677 | } | |
678 | } else { | |
679 | /* setup the object then issue a ras TA disable cmd.*/ | |
680 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
681 | if (ret) | |
682 | return ret; | |
77de502b | 683 | |
77de502b | 684 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 685 | } |
77de502b | 686 | } else |
687 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
688 | ||
689 | return ret; | |
690 | } | |
691 | ||
c030f2e4 | 692 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
693 | bool bypass) | |
694 | { | |
695 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
696 | struct ras_manager *obj, *tmp; | |
697 | ||
698 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
699 | /* bypass psp. | |
700 | * aka just release the obj and corresponding flags | |
701 | */ | |
702 | if (bypass) { | |
703 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
704 | break; | |
705 | } else { | |
706 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
707 | break; | |
708 | } | |
289d513b | 709 | } |
c030f2e4 | 710 | |
711 | return con->features; | |
712 | } | |
713 | ||
714 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
715 | bool bypass) | |
716 | { | |
717 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
718 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
719 | int i; | |
191051a1 | 720 | const enum amdgpu_ras_error_type default_ras_type = |
721 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 722 | |
723 | for (i = 0; i < ras_block_count; i++) { | |
724 | struct ras_common_if head = { | |
725 | .block = i, | |
191051a1 | 726 | .type = default_ras_type, |
c030f2e4 | 727 | .sub_block_index = 0, |
728 | }; | |
729 | strcpy(head.name, ras_block_str(i)); | |
730 | if (bypass) { | |
731 | /* | |
732 | * bypass psp. vbios enable ras for us. | |
733 | * so just create the obj | |
734 | */ | |
735 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
736 | break; | |
737 | } else { | |
738 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
739 | break; | |
740 | } | |
289d513b | 741 | } |
c030f2e4 | 742 | |
743 | return con->features; | |
744 | } | |
745 | /* feature ctl end */ | |
746 | ||
747 | /* query/inject/cure begin */ | |
748 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
749 | struct ras_query_if *info) | |
750 | { | |
751 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 752 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 753 | int i; |
c030f2e4 | 754 | |
755 | if (!obj) | |
756 | return -EINVAL; | |
c030f2e4 | 757 | |
939e2258 HZ |
758 | switch (info->head.block) { |
759 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
760 | if (adev->umc.funcs->query_ras_error_count) |
761 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
762 | /* umc query_ras_error_address is also responsible for clearing |
763 | * error status | |
764 | */ | |
765 | if (adev->umc.funcs->query_ras_error_address) | |
766 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 767 | break; |
3e81ee9a HZ |
768 | case AMDGPU_RAS_BLOCK__SDMA: |
769 | if (adev->sdma.funcs->query_ras_error_count) { | |
770 | for (i = 0; i < adev->sdma.num_instances; i++) | |
771 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
772 | &err_data); | |
773 | } | |
774 | break; | |
83b0582c DL |
775 | case AMDGPU_RAS_BLOCK__GFX: |
776 | if (adev->gfx.funcs->query_ras_error_count) | |
777 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
778 | break; | |
9fb2d8de | 779 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
780 | if (adev->mmhub.funcs->query_ras_error_count) |
781 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 782 | break; |
d7bd680d GC |
783 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
784 | if (adev->nbio.funcs->query_ras_error_count) | |
785 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
786 | break; | |
ec01fe2d HZ |
787 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
788 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
789 | break; | |
939e2258 HZ |
790 | default: |
791 | break; | |
792 | } | |
05a58345 TZ |
793 | |
794 | obj->err_data.ue_count += err_data.ue_count; | |
795 | obj->err_data.ce_count += err_data.ce_count; | |
796 | ||
c030f2e4 | 797 | info->ue_count = obj->err_data.ue_count; |
798 | info->ce_count = obj->err_data.ce_count; | |
799 | ||
7c6e68c7 | 800 | if (err_data.ce_count) { |
6952e99c GC |
801 | dev_info(adev->dev, "%ld correctable hardware errors " |
802 | "detected in %s block, no user " | |
803 | "action is needed.\n", | |
804 | obj->err_data.ce_count, | |
805 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
806 | } |
807 | if (err_data.ue_count) { | |
6952e99c GC |
808 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
809 | "detected in %s block\n", | |
810 | obj->err_data.ue_count, | |
811 | ras_block_str(info->head.block)); | |
7c6e68c7 | 812 | } |
05a58345 | 813 | |
c030f2e4 | 814 | return 0; |
815 | } | |
816 | ||
5c23e9e0 | 817 | /* Trigger XGMI/WAFL error */ |
f3167919 | 818 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
819 | struct ta_ras_trigger_error_input *block_info) |
820 | { | |
821 | int ret; | |
822 | ||
823 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
824 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
825 | ||
826 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
827 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
828 | ||
829 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
830 | ||
831 | if (amdgpu_ras_intr_triggered()) | |
832 | return ret; | |
833 | ||
834 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
835 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
836 | ||
837 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
838 | dev_warn(adev->dev, "Failed to allow df cstate"); | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
c030f2e4 | 843 | /* wrapper of psp_ras_trigger_error */ |
844 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
845 | struct ras_inject_if *info) | |
846 | { | |
847 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
848 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 849 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
850 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 851 | .sub_block_index = info->head.sub_block_index, |
852 | .address = info->address, | |
853 | .value = info->value, | |
854 | }; | |
855 | int ret = 0; | |
856 | ||
857 | if (!obj) | |
858 | return -EINVAL; | |
859 | ||
a6c44d25 JC |
860 | /* Calculate XGMI relative offset */ |
861 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
862 | block_info.address = |
863 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
864 | block_info.address); | |
a6c44d25 JC |
865 | } |
866 | ||
83b0582c DL |
867 | switch (info->head.block) { |
868 | case AMDGPU_RAS_BLOCK__GFX: | |
869 | if (adev->gfx.funcs->ras_error_inject) | |
870 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
871 | else | |
872 | ret = -EINVAL; | |
873 | break; | |
874 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 875 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 876 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
877 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
878 | break; | |
5c23e9e0 JC |
879 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
880 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
881 | break; | |
83b0582c | 882 | default: |
6952e99c | 883 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 884 | ras_block_str(info->head.block)); |
83b0582c | 885 | ret = -EINVAL; |
a5dd40ca HZ |
886 | } |
887 | ||
a200034b JC |
888 | amdgpu_ras_parse_status_code(adev, |
889 | "inject", | |
890 | ras_block_str(info->head.block), | |
891 | (enum ta_ras_status)ret); | |
c030f2e4 | 892 | |
893 | return ret; | |
894 | } | |
895 | ||
896 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
897 | struct ras_cure_if *info) | |
898 | { | |
899 | /* psp fw has no cure interface for now. */ | |
900 | return 0; | |
901 | } | |
902 | ||
903 | /* get the total error counts on all IPs */ | |
64cc5414 | 904 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 905 | bool is_ce) |
906 | { | |
907 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
908 | struct ras_manager *obj; | |
909 | struct ras_err_data data = {0, 0}; | |
910 | ||
911 | if (!con) | |
64cc5414 | 912 | return 0; |
c030f2e4 | 913 | |
914 | list_for_each_entry(obj, &con->head, node) { | |
915 | struct ras_query_if info = { | |
916 | .head = obj->head, | |
917 | }; | |
918 | ||
919 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 920 | return 0; |
c030f2e4 | 921 | |
922 | data.ce_count += info.ce_count; | |
923 | data.ue_count += info.ue_count; | |
924 | } | |
925 | ||
926 | return is_ce ? data.ce_count : data.ue_count; | |
927 | } | |
928 | /* query/inject/cure end */ | |
929 | ||
930 | ||
931 | /* sysfs begin */ | |
932 | ||
466b1793 | 933 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
934 | struct ras_badpage **bps, unsigned int *count); | |
935 | ||
936 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
937 | { | |
938 | switch (flags) { | |
52dd95f2 | 939 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 940 | return "R"; |
52dd95f2 | 941 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 942 | return "P"; |
52dd95f2 | 943 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 944 | default: |
945 | return "F"; | |
946 | }; | |
947 | } | |
948 | ||
f77c7109 AD |
949 | /** |
950 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 951 | * |
952 | * It allows user to read the bad pages of vram on the gpu through | |
953 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
954 | * | |
955 | * It outputs multiple lines, and each line stands for one gpu page. | |
956 | * | |
957 | * The format of one line is below, | |
958 | * gpu pfn : gpu page size : flags | |
959 | * | |
960 | * gpu pfn and gpu page size are printed in hex format. | |
961 | * flags can be one of below character, | |
f77c7109 | 962 | * |
466b1793 | 963 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 964 | * |
466b1793 | 965 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
966 | * in next window of page_reserve. |
967 | * | |
466b1793 | 968 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
969 | * | |
f77c7109 AD |
970 | * Examples: |
971 | * | |
972 | * .. code-block:: bash | |
973 | * | |
974 | * 0x00000001 : 0x00001000 : R | |
975 | * 0x00000002 : 0x00001000 : P | |
976 | * | |
466b1793 | 977 | */ |
978 | ||
979 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
980 | struct kobject *kobj, struct bin_attribute *attr, | |
981 | char *buf, loff_t ppos, size_t count) | |
982 | { | |
983 | struct amdgpu_ras *con = | |
984 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
985 | struct amdgpu_device *adev = con->adev; | |
986 | const unsigned int element_size = | |
987 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
988 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
989 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 990 | ssize_t s = 0; |
991 | struct ras_badpage *bps = NULL; | |
992 | unsigned int bps_count = 0; | |
993 | ||
994 | memset(buf, 0, count); | |
995 | ||
996 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
997 | return 0; | |
998 | ||
999 | for (; start < end && start < bps_count; start++) | |
1000 | s += scnprintf(&buf[s], element_size + 1, | |
1001 | "0x%08x : 0x%08x : %1s\n", | |
1002 | bps[start].bp, | |
1003 | bps[start].size, | |
1004 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1005 | ||
1006 | kfree(bps); | |
1007 | ||
1008 | return s; | |
1009 | } | |
1010 | ||
c030f2e4 | 1011 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1012 | struct device_attribute *attr, char *buf) | |
1013 | { | |
1014 | struct amdgpu_ras *con = | |
1015 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1016 | |
5212a3bd | 1017 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1018 | } |
1019 | ||
1020 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
1021 | { | |
1022 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1023 | struct attribute *attrs[] = { | |
1024 | &con->features_attr.attr, | |
1025 | NULL | |
1026 | }; | |
466b1793 | 1027 | struct bin_attribute *bin_attrs[] = { |
1028 | &con->badpages_attr, | |
1029 | NULL | |
1030 | }; | |
c030f2e4 | 1031 | struct attribute_group group = { |
1032 | .name = "ras", | |
1033 | .attrs = attrs, | |
466b1793 | 1034 | .bin_attrs = bin_attrs, |
c030f2e4 | 1035 | }; |
1036 | ||
1037 | con->features_attr = (struct device_attribute) { | |
1038 | .attr = { | |
1039 | .name = "features", | |
1040 | .mode = S_IRUGO, | |
1041 | }, | |
1042 | .show = amdgpu_ras_sysfs_features_read, | |
1043 | }; | |
466b1793 | 1044 | |
1045 | con->badpages_attr = (struct bin_attribute) { | |
1046 | .attr = { | |
1047 | .name = "gpu_vram_bad_pages", | |
1048 | .mode = S_IRUGO, | |
1049 | }, | |
1050 | .size = 0, | |
1051 | .private = NULL, | |
1052 | .read = amdgpu_ras_sysfs_badpages_read, | |
1053 | }; | |
1054 | ||
163def43 | 1055 | sysfs_attr_init(attrs[0]); |
466b1793 | 1056 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 1057 | |
1058 | return sysfs_create_group(&adev->dev->kobj, &group); | |
1059 | } | |
1060 | ||
1061 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
1062 | { | |
1063 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1064 | struct attribute *attrs[] = { | |
1065 | &con->features_attr.attr, | |
1066 | NULL | |
1067 | }; | |
466b1793 | 1068 | struct bin_attribute *bin_attrs[] = { |
1069 | &con->badpages_attr, | |
1070 | NULL | |
1071 | }; | |
c030f2e4 | 1072 | struct attribute_group group = { |
1073 | .name = "ras", | |
1074 | .attrs = attrs, | |
466b1793 | 1075 | .bin_attrs = bin_attrs, |
c030f2e4 | 1076 | }; |
1077 | ||
1078 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1084 | struct ras_fs_if *head) | |
1085 | { | |
1086 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1087 | ||
1088 | if (!obj || obj->attr_inuse) | |
1089 | return -EINVAL; | |
1090 | ||
1091 | get_obj(obj); | |
1092 | ||
1093 | memcpy(obj->fs_data.sysfs_name, | |
1094 | head->sysfs_name, | |
1095 | sizeof(obj->fs_data.sysfs_name)); | |
1096 | ||
1097 | obj->sysfs_attr = (struct device_attribute){ | |
1098 | .attr = { | |
1099 | .name = obj->fs_data.sysfs_name, | |
1100 | .mode = S_IRUGO, | |
1101 | }, | |
1102 | .show = amdgpu_ras_sysfs_read, | |
1103 | }; | |
163def43 | 1104 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1105 | |
1106 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1107 | &obj->sysfs_attr.attr, | |
1108 | "ras")) { | |
1109 | put_obj(obj); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | ||
1113 | obj->attr_inuse = 1; | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1119 | struct ras_common_if *head) | |
1120 | { | |
1121 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1122 | ||
1123 | if (!obj || !obj->attr_inuse) | |
1124 | return -EINVAL; | |
1125 | ||
1126 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1127 | &obj->sysfs_attr.attr, | |
1128 | "ras"); | |
1129 | obj->attr_inuse = 0; | |
1130 | put_obj(obj); | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1136 | { | |
1137 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1138 | struct ras_manager *obj, *tmp; | |
1139 | ||
1140 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1141 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1142 | } | |
1143 | ||
1144 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | /* sysfs end */ | |
1149 | ||
ef177d11 AD |
1150 | /** |
1151 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1152 | * | |
1153 | * Normally when there is an uncorrectable error, the driver will reset | |
1154 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1155 | * the driver provides an interface to reboot the system automatically | |
1156 | * in that event. | |
1157 | * | |
1158 | * The following file in debugfs provides that interface: | |
1159 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1160 | * | |
1161 | * Usage: | |
1162 | * | |
1163 | * .. code-block:: bash | |
1164 | * | |
1165 | * echo true > .../ras/auto_reboot | |
1166 | * | |
1167 | */ | |
c030f2e4 | 1168 | /* debugfs begin */ |
450f30ea | 1169 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1170 | { |
1171 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1172 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 1173 | |
450f30ea | 1174 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
012dd14d GC |
1175 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1176 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1177 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1178 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1179 | |
1180 | /* | |
1181 | * After one uncorrectable error happens, usually GPU recovery will | |
1182 | * be scheduled. But due to the known problem in GPU recovery failing | |
1183 | * to bring GPU back, below interface provides one direct way to | |
1184 | * user to reboot system automatically in such case within | |
1185 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1186 | * will never be called. | |
1187 | */ | |
1188 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1189 | &con->reboot); | |
36ea1bd2 | 1190 | } |
1191 | ||
450f30ea | 1192 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1193 | struct ras_fs_if *head) |
1194 | { | |
1195 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1196 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1197 | |
1198 | if (!obj || obj->ent) | |
450f30ea | 1199 | return; |
c030f2e4 | 1200 | |
1201 | get_obj(obj); | |
1202 | ||
1203 | memcpy(obj->fs_data.debugfs_name, | |
1204 | head->debugfs_name, | |
1205 | sizeof(obj->fs_data.debugfs_name)); | |
1206 | ||
450f30ea GKH |
1207 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1208 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1209 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1210 | } |
1211 | ||
f9317014 TZ |
1212 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1213 | { | |
1214 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c1509f3f | 1215 | struct ras_manager *obj; |
f9317014 TZ |
1216 | struct ras_fs_if fs_info; |
1217 | ||
1218 | /* | |
1219 | * it won't be called in resume path, no need to check | |
1220 | * suspend and gpu reset status | |
1221 | */ | |
1222 | if (!con) | |
1223 | return; | |
1224 | ||
1225 | amdgpu_ras_debugfs_create_ctrl_node(adev); | |
1226 | ||
c1509f3f | 1227 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1228 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1229 | (obj->attr_inuse == 1)) { | |
1230 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1231 | ras_block_str(obj->head.block)); | |
1232 | fs_info.head = obj->head; | |
1233 | amdgpu_ras_debugfs_create(adev, &fs_info); | |
1234 | } | |
1235 | } | |
1236 | } | |
1237 | ||
450f30ea | 1238 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1239 | struct ras_common_if *head) |
1240 | { | |
1241 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1242 | ||
1243 | if (!obj || !obj->ent) | |
450f30ea | 1244 | return; |
c030f2e4 | 1245 | |
1246 | debugfs_remove(obj->ent); | |
1247 | obj->ent = NULL; | |
1248 | put_obj(obj); | |
c030f2e4 | 1249 | } |
1250 | ||
450f30ea | 1251 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1252 | { |
1253 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1254 | struct ras_manager *obj, *tmp; | |
1255 | ||
1256 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1257 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1258 | } | |
1259 | ||
012dd14d | 1260 | debugfs_remove_recursive(con->dir); |
c030f2e4 | 1261 | con->dir = NULL; |
c030f2e4 | 1262 | } |
1263 | /* debugfs end */ | |
1264 | ||
1265 | /* ras fs */ | |
1266 | ||
1267 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1268 | { | |
c030f2e4 | 1269 | amdgpu_ras_sysfs_create_feature_node(adev); |
1270 | ||
1271 | return 0; | |
1272 | } | |
1273 | ||
1274 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1275 | { | |
1276 | amdgpu_ras_debugfs_remove_all(adev); | |
1277 | amdgpu_ras_sysfs_remove_all(adev); | |
1278 | return 0; | |
1279 | } | |
1280 | /* ras fs end */ | |
1281 | ||
1282 | /* ih begin */ | |
1283 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1284 | { | |
1285 | struct ras_ih_data *data = &obj->ih_data; | |
1286 | struct amdgpu_iv_entry entry; | |
1287 | int ret; | |
cf04dfd0 | 1288 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1289 | |
1290 | while (data->rptr != data->wptr) { | |
1291 | rmb(); | |
1292 | memcpy(&entry, &data->ring[data->rptr], | |
1293 | data->element_size); | |
1294 | ||
1295 | wmb(); | |
1296 | data->rptr = (data->aligned_element_size + | |
1297 | data->rptr) % data->ring_size; | |
1298 | ||
1299 | /* Let IP handle its data, maybe we need get the output | |
1300 | * from the callback to udpate the error type/count, etc | |
1301 | */ | |
1302 | if (data->cb) { | |
cf04dfd0 | 1303 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1304 | /* ue will trigger an interrupt, and in that case |
1305 | * we need do a reset to recovery the whole system. | |
1306 | * But leave IP do that recovery, here we just dispatch | |
1307 | * the error. | |
1308 | */ | |
bd2280da | 1309 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1310 | /* these counts could be left as 0 if |
1311 | * some blocks do not count error number | |
1312 | */ | |
cf04dfd0 | 1313 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1314 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1315 | } |
c030f2e4 | 1316 | } |
1317 | } | |
1318 | } | |
1319 | ||
1320 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1321 | { | |
1322 | struct ras_ih_data *data = | |
1323 | container_of(work, struct ras_ih_data, ih_work); | |
1324 | struct ras_manager *obj = | |
1325 | container_of(data, struct ras_manager, ih_data); | |
1326 | ||
1327 | amdgpu_ras_interrupt_handler(obj); | |
1328 | } | |
1329 | ||
1330 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1331 | struct ras_dispatch_if *info) | |
1332 | { | |
1333 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1334 | struct ras_ih_data *data = &obj->ih_data; | |
1335 | ||
1336 | if (!obj) | |
1337 | return -EINVAL; | |
1338 | ||
1339 | if (data->inuse == 0) | |
1340 | return 0; | |
1341 | ||
1342 | /* Might be overflow... */ | |
1343 | memcpy(&data->ring[data->wptr], info->entry, | |
1344 | data->element_size); | |
1345 | ||
1346 | wmb(); | |
1347 | data->wptr = (data->aligned_element_size + | |
1348 | data->wptr) % data->ring_size; | |
1349 | ||
1350 | schedule_work(&data->ih_work); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1356 | struct ras_ih_if *info) | |
1357 | { | |
1358 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1359 | struct ras_ih_data *data; | |
1360 | ||
1361 | if (!obj) | |
1362 | return -EINVAL; | |
1363 | ||
1364 | data = &obj->ih_data; | |
1365 | if (data->inuse == 0) | |
1366 | return 0; | |
1367 | ||
1368 | cancel_work_sync(&data->ih_work); | |
1369 | ||
1370 | kfree(data->ring); | |
1371 | memset(data, 0, sizeof(*data)); | |
1372 | put_obj(obj); | |
1373 | ||
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1378 | struct ras_ih_if *info) | |
1379 | { | |
1380 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1381 | struct ras_ih_data *data; | |
1382 | ||
1383 | if (!obj) { | |
1384 | /* in case we registe the IH before enable ras feature */ | |
1385 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1386 | if (!obj) | |
1387 | return -EINVAL; | |
1388 | } else | |
1389 | get_obj(obj); | |
1390 | ||
1391 | data = &obj->ih_data; | |
1392 | /* add the callback.etc */ | |
1393 | *data = (struct ras_ih_data) { | |
1394 | .inuse = 0, | |
1395 | .cb = info->cb, | |
1396 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1397 | .rptr = 0, | |
1398 | .wptr = 0, | |
1399 | }; | |
1400 | ||
1401 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1402 | ||
1403 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1404 | /* the ring can store 64 iv entries. */ | |
1405 | data->ring_size = 64 * data->aligned_element_size; | |
1406 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1407 | if (!data->ring) { | |
1408 | put_obj(obj); | |
1409 | return -ENOMEM; | |
1410 | } | |
1411 | ||
1412 | /* IH is ready */ | |
1413 | data->inuse = 1; | |
1414 | ||
1415 | return 0; | |
1416 | } | |
1417 | ||
1418 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1419 | { | |
1420 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1421 | struct ras_manager *obj, *tmp; | |
1422 | ||
1423 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1424 | struct ras_ih_if info = { | |
1425 | .head = obj->head, | |
1426 | }; | |
1427 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1428 | } | |
1429 | ||
1430 | return 0; | |
1431 | } | |
1432 | /* ih end */ | |
1433 | ||
313c8fd3 GC |
1434 | /* traversal all IPs except NBIO to query error counter */ |
1435 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1436 | { | |
1437 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1438 | struct ras_manager *obj; | |
1439 | ||
1440 | if (!con) | |
1441 | return; | |
1442 | ||
1443 | list_for_each_entry(obj, &con->head, node) { | |
1444 | struct ras_query_if info = { | |
1445 | .head = obj->head, | |
1446 | }; | |
1447 | ||
1448 | /* | |
1449 | * PCIE_BIF IP has one different isr by ras controller | |
1450 | * interrupt, the specific ras counter query will be | |
1451 | * done in that isr. So skip such block from common | |
1452 | * sync flood interrupt isr calling. | |
1453 | */ | |
1454 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1455 | continue; | |
1456 | ||
1457 | amdgpu_ras_error_query(adev, &info); | |
1458 | } | |
1459 | } | |
1460 | ||
c030f2e4 | 1461 | /* recovery begin */ |
466b1793 | 1462 | |
1463 | /* return 0 on success. | |
1464 | * caller need free bps. | |
1465 | */ | |
1466 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1467 | struct ras_badpage **bps, unsigned int *count) | |
1468 | { | |
1469 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1470 | struct ras_err_handler_data *data; | |
1471 | int i = 0; | |
1472 | int ret = 0; | |
1473 | ||
1474 | if (!con || !con->eh_data || !bps || !count) | |
1475 | return -EINVAL; | |
1476 | ||
1477 | mutex_lock(&con->recovery_lock); | |
1478 | data = con->eh_data; | |
1479 | if (!data || data->count == 0) { | |
1480 | *bps = NULL; | |
46cf2fec | 1481 | ret = -EINVAL; |
466b1793 | 1482 | goto out; |
1483 | } | |
1484 | ||
1485 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1486 | if (!*bps) { | |
1487 | ret = -ENOMEM; | |
1488 | goto out; | |
1489 | } | |
1490 | ||
1491 | for (; i < data->count; i++) { | |
1492 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1493 | .bp = data->bps[i].retired_page, |
466b1793 | 1494 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1495 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1496 | }; |
1497 | ||
1498 | if (data->last_reserved <= i) | |
52dd95f2 | 1499 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
9dc23a63 | 1500 | else if (data->bps_bo[i] == NULL) |
52dd95f2 | 1501 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1502 | } |
1503 | ||
1504 | *count = data->count; | |
1505 | out: | |
1506 | mutex_unlock(&con->recovery_lock); | |
1507 | return ret; | |
1508 | } | |
1509 | ||
c030f2e4 | 1510 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1511 | { | |
1512 | struct amdgpu_ras *ras = | |
1513 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1514 | struct amdgpu_device *remote_adev = NULL; |
1515 | struct amdgpu_device *adev = ras->adev; | |
1516 | struct list_head device_list, *device_list_handle = NULL; | |
1517 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false); | |
1518 | ||
1519 | /* Build list of devices to query RAS related errors */ | |
12c17b9d | 1520 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) |
b3dbd6d3 | 1521 | device_list_handle = &hive->device_list; |
12c17b9d GC |
1522 | else { |
1523 | INIT_LIST_HEAD(&device_list); | |
b3dbd6d3 JC |
1524 | list_add_tail(&adev->gmc.xgmi.head, &device_list); |
1525 | device_list_handle = &device_list; | |
1526 | } | |
c030f2e4 | 1527 | |
b3dbd6d3 JC |
1528 | list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) { |
1529 | amdgpu_ras_log_on_err_counter(remote_adev); | |
1530 | } | |
313c8fd3 | 1531 | |
93af20f7 HZ |
1532 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
1533 | amdgpu_device_gpu_recover(ras->adev, 0); | |
c030f2e4 | 1534 | atomic_set(&ras->in_recovery, 0); |
1535 | } | |
1536 | ||
c030f2e4 | 1537 | /* alloc/realloc bps array */ |
1538 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1539 | struct ras_err_handler_data *data, int pages) | |
1540 | { | |
1541 | unsigned int old_space = data->count + data->space_left; | |
1542 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1543 | unsigned int align_space = ALIGN(new_space, 512); |
1544 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1545 | struct amdgpu_bo **bps_bo = | |
1546 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1547 | ||
1548 | if (!bps || !bps_bo) { | |
1549 | kfree(bps); | |
1550 | kfree(bps_bo); | |
c030f2e4 | 1551 | return -ENOMEM; |
9dc23a63 | 1552 | } |
c030f2e4 | 1553 | |
1554 | if (data->bps) { | |
9dc23a63 | 1555 | memcpy(bps, data->bps, |
c030f2e4 | 1556 | data->count * sizeof(*data->bps)); |
1557 | kfree(data->bps); | |
1558 | } | |
9dc23a63 TZ |
1559 | if (data->bps_bo) { |
1560 | memcpy(bps_bo, data->bps_bo, | |
1561 | data->count * sizeof(*data->bps_bo)); | |
1562 | kfree(data->bps_bo); | |
1563 | } | |
c030f2e4 | 1564 | |
9dc23a63 TZ |
1565 | data->bps = bps; |
1566 | data->bps_bo = bps_bo; | |
c030f2e4 | 1567 | data->space_left += align_space - old_space; |
1568 | return 0; | |
1569 | } | |
1570 | ||
1571 | /* it deal with vram only. */ | |
1572 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1573 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1574 | { |
1575 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1576 | struct ras_err_handler_data *data; |
c030f2e4 | 1577 | int ret = 0; |
1578 | ||
73aa8e1a | 1579 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1580 | return 0; |
1581 | ||
1582 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1583 | data = con->eh_data; |
c030f2e4 | 1584 | if (!data) |
1585 | goto out; | |
1586 | ||
1587 | if (data->space_left <= pages) | |
1588 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1589 | ret = -ENOMEM; | |
1590 | goto out; | |
1591 | } | |
1592 | ||
9dc23a63 TZ |
1593 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1594 | data->count += pages; | |
c030f2e4 | 1595 | data->space_left -= pages; |
9dc23a63 | 1596 | |
c030f2e4 | 1597 | out: |
1598 | mutex_unlock(&con->recovery_lock); | |
1599 | ||
1600 | return ret; | |
1601 | } | |
1602 | ||
78ad00c9 TZ |
1603 | /* |
1604 | * write error record array to eeprom, the function should be | |
1605 | * protected by recovery_lock | |
1606 | */ | |
1607 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1608 | { | |
1609 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1610 | struct ras_err_handler_data *data; | |
8a3e801f | 1611 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1612 | int save_count; |
1613 | ||
1614 | if (!con || !con->eh_data) | |
1615 | return 0; | |
1616 | ||
8a3e801f | 1617 | control = &con->eeprom_control; |
78ad00c9 TZ |
1618 | data = con->eh_data; |
1619 | save_count = data->count - control->num_recs; | |
1620 | /* only new entries are saved */ | |
1621 | if (save_count > 0) | |
0771b0bf | 1622 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1623 | &data->bps[control->num_recs], |
1624 | true, | |
1625 | save_count)) { | |
6952e99c | 1626 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1627 | return -EIO; |
1628 | } | |
1629 | ||
1630 | return 0; | |
1631 | } | |
1632 | ||
1633 | /* | |
1634 | * read error record array in eeprom and reserve enough space for | |
1635 | * storing new bad pages | |
1636 | */ | |
1637 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1638 | { | |
1639 | struct amdgpu_ras_eeprom_control *control = | |
1640 | &adev->psp.ras.ras->eeprom_control; | |
1641 | struct eeprom_table_record *bps = NULL; | |
1642 | int ret = 0; | |
1643 | ||
1644 | /* no bad page record, skip eeprom access */ | |
1645 | if (!control->num_recs) | |
1646 | return ret; | |
1647 | ||
1648 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1649 | if (!bps) | |
1650 | return -ENOMEM; | |
1651 | ||
1652 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1653 | control->num_recs)) { | |
6952e99c | 1654 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1655 | ret = -EIO; |
1656 | goto out; | |
1657 | } | |
1658 | ||
1659 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1660 | ||
1661 | out: | |
1662 | kfree(bps); | |
1663 | return ret; | |
1664 | } | |
1665 | ||
6e4be987 TZ |
1666 | /* |
1667 | * check if an address belongs to bad page | |
1668 | * | |
1669 | * Note: this check is only for umc block | |
1670 | */ | |
1671 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1672 | uint64_t addr) | |
1673 | { | |
1674 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1675 | struct ras_err_handler_data *data; | |
1676 | int i; | |
1677 | bool ret = false; | |
1678 | ||
1679 | if (!con || !con->eh_data) | |
1680 | return ret; | |
1681 | ||
1682 | mutex_lock(&con->recovery_lock); | |
1683 | data = con->eh_data; | |
1684 | if (!data) | |
1685 | goto out; | |
1686 | ||
1687 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1688 | for (i = 0; i < data->count; i++) | |
1689 | if (addr == data->bps[i].retired_page) { | |
1690 | ret = true; | |
1691 | goto out; | |
1692 | } | |
1693 | ||
1694 | out: | |
1695 | mutex_unlock(&con->recovery_lock); | |
1696 | return ret; | |
1697 | } | |
1698 | ||
c030f2e4 | 1699 | /* called in gpu recovery/init */ |
1700 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1701 | { | |
1702 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1703 | struct ras_err_handler_data *data; |
c030f2e4 | 1704 | uint64_t bp; |
de7b45ba | 1705 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1706 | int i, ret = 0; |
c030f2e4 | 1707 | |
73aa8e1a | 1708 | if (!con || !con->eh_data) |
c030f2e4 | 1709 | return 0; |
1710 | ||
1711 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1712 | data = con->eh_data; |
1713 | if (!data) | |
1714 | goto out; | |
c030f2e4 | 1715 | /* reserve vram at driver post stage. */ |
1716 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1717 | bp = data->bps[i].retired_page; |
c030f2e4 | 1718 | |
ae115c81 TZ |
1719 | /* There are two cases of reserve error should be ignored: |
1720 | * 1) a ras bad page has been allocated (used by someone); | |
1721 | * 2) a ras bad page has been reserved (duplicate error injection | |
1722 | * for one page); | |
1723 | */ | |
a142ba88 AD |
1724 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, |
1725 | AMDGPU_GPU_PAGE_SIZE, | |
de7b45ba CK |
1726 | AMDGPU_GEM_DOMAIN_VRAM, |
1727 | &bo, NULL)) | |
6952e99c GC |
1728 | dev_warn(adev->dev, "RAS WARN: reserve vram for " |
1729 | "retired page %llx fail\n", bp); | |
c030f2e4 | 1730 | |
9dc23a63 | 1731 | data->bps_bo[i] = bo; |
c030f2e4 | 1732 | data->last_reserved = i + 1; |
de7b45ba | 1733 | bo = NULL; |
c030f2e4 | 1734 | } |
78ad00c9 TZ |
1735 | |
1736 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1737 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1738 | out: |
c030f2e4 | 1739 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1740 | return ret; |
c030f2e4 | 1741 | } |
1742 | ||
1743 | /* called when driver unload */ | |
1744 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1745 | { | |
1746 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1747 | struct ras_err_handler_data *data; |
c030f2e4 | 1748 | struct amdgpu_bo *bo; |
1749 | int i; | |
1750 | ||
73aa8e1a | 1751 | if (!con || !con->eh_data) |
c030f2e4 | 1752 | return 0; |
1753 | ||
1754 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1755 | data = con->eh_data; |
1756 | if (!data) | |
1757 | goto out; | |
1758 | ||
c030f2e4 | 1759 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1760 | bo = data->bps_bo[i]; |
c030f2e4 | 1761 | |
de7b45ba | 1762 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1763 | |
9dc23a63 | 1764 | data->bps_bo[i] = bo; |
c030f2e4 | 1765 | data->last_reserved = i; |
1766 | } | |
73aa8e1a | 1767 | out: |
c030f2e4 | 1768 | mutex_unlock(&con->recovery_lock); |
1769 | return 0; | |
1770 | } | |
1771 | ||
1a6fc071 | 1772 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1773 | { |
1774 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1775 | struct ras_err_handler_data **data; |
78ad00c9 | 1776 | int ret; |
c030f2e4 | 1777 | |
4d1337d2 AG |
1778 | if (con) |
1779 | data = &con->eh_data; | |
1780 | else | |
1781 | return 0; | |
1782 | ||
1a6fc071 TZ |
1783 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1784 | if (!*data) { | |
1785 | ret = -ENOMEM; | |
1786 | goto out; | |
1787 | } | |
c030f2e4 | 1788 | |
1789 | mutex_init(&con->recovery_lock); | |
1790 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1791 | atomic_set(&con->in_recovery, 0); | |
1792 | con->adev = adev; | |
1793 | ||
0771b0bf | 1794 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control); |
78ad00c9 | 1795 | if (ret) |
1a6fc071 | 1796 | goto free; |
78ad00c9 | 1797 | |
0771b0bf | 1798 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1799 | ret = amdgpu_ras_load_bad_pages(adev); |
1800 | if (ret) | |
1a6fc071 | 1801 | goto free; |
78ad00c9 TZ |
1802 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1803 | if (ret) | |
1a6fc071 | 1804 | goto release; |
78ad00c9 | 1805 | } |
c030f2e4 | 1806 | |
1807 | return 0; | |
1a6fc071 TZ |
1808 | |
1809 | release: | |
1810 | amdgpu_ras_release_bad_pages(adev); | |
1811 | free: | |
1a6fc071 TZ |
1812 | kfree((*data)->bps); |
1813 | kfree((*data)->bps_bo); | |
1814 | kfree(*data); | |
1995b3a3 | 1815 | con->eh_data = NULL; |
1a6fc071 | 1816 | out: |
6952e99c | 1817 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 TZ |
1818 | |
1819 | return ret; | |
c030f2e4 | 1820 | } |
1821 | ||
1822 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1823 | { | |
1824 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1825 | struct ras_err_handler_data *data = con->eh_data; | |
1826 | ||
1a6fc071 TZ |
1827 | /* recovery_init failed to init it, fini is useless */ |
1828 | if (!data) | |
1829 | return 0; | |
1830 | ||
c030f2e4 | 1831 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1832 | amdgpu_ras_release_bad_pages(adev); |
1833 | ||
1834 | mutex_lock(&con->recovery_lock); | |
1835 | con->eh_data = NULL; | |
1836 | kfree(data->bps); | |
1a6fc071 | 1837 | kfree(data->bps_bo); |
c030f2e4 | 1838 | kfree(data); |
1839 | mutex_unlock(&con->recovery_lock); | |
1840 | ||
1841 | return 0; | |
1842 | } | |
1843 | /* recovery end */ | |
1844 | ||
a564808e | 1845 | /* return 0 if ras will reset gpu and repost.*/ |
1846 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1847 | unsigned int block) | |
1848 | { | |
1849 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1850 | ||
1851 | if (!ras) | |
1852 | return -EINVAL; | |
1853 | ||
1854 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1855 | return 0; | |
1856 | } | |
1857 | ||
5caf466a | 1858 | /* |
1859 | * check hardware's ras ability which will be saved in hw_supported. | |
1860 | * if hardware does not support ras, we can skip some ras initializtion and | |
1861 | * forbid some ras operations from IP. | |
1862 | * if software itself, say boot parameter, limit the ras ability. We still | |
1863 | * need allow IP do some limited operations, like disable. In such case, | |
1864 | * we have to initialize ras as normal. but need check if operation is | |
1865 | * allowed or not in each function. | |
1866 | */ | |
1867 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1868 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1869 | { |
5caf466a | 1870 | *hw_supported = 0; |
1871 | *supported = 0; | |
c030f2e4 | 1872 | |
88474cca | 1873 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
baaeb610 HZ |
1874 | (adev->asic_type != CHIP_VEGA20 && |
1875 | adev->asic_type != CHIP_ARCTURUS)) | |
5caf466a | 1876 | return; |
b404ae82 | 1877 | |
88474cca | 1878 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
6952e99c | 1879 | dev_info(adev->dev, "HBM ECC is active.\n"); |
88474cca GC |
1880 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | |
1881 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1882 | } else | |
6952e99c | 1883 | dev_info(adev->dev, "HBM ECC is not presented.\n"); |
88474cca GC |
1884 | |
1885 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
6952e99c | 1886 | dev_info(adev->dev, "SRAM ECC is active.\n"); |
88474cca GC |
1887 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
1888 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1889 | } else | |
6952e99c | 1890 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); |
88474cca GC |
1891 | |
1892 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1893 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1894 | |
5caf466a | 1895 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1896 | 0 : *hw_supported & amdgpu_ras_mask; |
c030f2e4 | 1897 | } |
1898 | ||
1899 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1900 | { | |
1901 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1902 | int r; |
c030f2e4 | 1903 | |
b404ae82 | 1904 | if (con) |
c030f2e4 | 1905 | return 0; |
1906 | ||
1907 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1908 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1909 | GFP_KERNEL|__GFP_ZERO); | |
1910 | if (!con) | |
1911 | return -ENOMEM; | |
1912 | ||
1913 | con->objs = (struct ras_manager *)(con + 1); | |
1914 | ||
1915 | amdgpu_ras_set_context(adev, con); | |
1916 | ||
5caf466a | 1917 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1918 | &con->supported); | |
fb2a3607 | 1919 | if (!con->hw_supported) { |
5e91160a GC |
1920 | r = 0; |
1921 | goto err_out; | |
fb2a3607 HZ |
1922 | } |
1923 | ||
c030f2e4 | 1924 | con->features = 0; |
1925 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1926 | /* Might need get this flag from vbios. */ |
1927 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1928 | |
4e644fff HZ |
1929 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1930 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1931 | if (r) | |
5e91160a | 1932 | goto err_out; |
4e644fff HZ |
1933 | } |
1934 | ||
1935 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1936 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
1937 | if (r) | |
5e91160a | 1938 | goto err_out; |
4e644fff HZ |
1939 | } |
1940 | ||
5e91160a GC |
1941 | if (amdgpu_ras_fs_init(adev)) { |
1942 | r = -EINVAL; | |
1943 | goto err_out; | |
1944 | } | |
c030f2e4 | 1945 | |
6952e99c | 1946 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 1947 | "hardware ability[%x] ras_mask[%x]\n", |
1948 | con->hw_supported, con->supported); | |
c030f2e4 | 1949 | return 0; |
5e91160a | 1950 | err_out: |
c030f2e4 | 1951 | amdgpu_ras_set_context(adev, NULL); |
1952 | kfree(con); | |
1953 | ||
5e91160a | 1954 | return r; |
c030f2e4 | 1955 | } |
1956 | ||
b293e891 HZ |
1957 | /* helper function to handle common stuff in ip late init phase */ |
1958 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
1959 | struct ras_common_if *ras_block, | |
1960 | struct ras_fs_if *fs_info, | |
1961 | struct ras_ih_if *ih_info) | |
1962 | { | |
1963 | int r; | |
1964 | ||
1965 | /* disable RAS feature per IP block if it is not supported */ | |
1966 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
1967 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
1972 | if (r) { | |
1973 | if (r == -EAGAIN) { | |
1974 | /* request gpu reset. will run again */ | |
1975 | amdgpu_ras_request_reset_on_boot(adev, | |
1976 | ras_block->block); | |
1977 | return 0; | |
1978 | } else if (adev->in_suspend || adev->in_gpu_reset) { | |
1979 | /* in resume phase, if fail to enable ras, | |
1980 | * clean up all ras fs nodes, and disable ras */ | |
1981 | goto cleanup; | |
1982 | } else | |
1983 | return r; | |
1984 | } | |
1985 | ||
1986 | /* in resume phase, no need to create ras fs node */ | |
a891d239 | 1987 | if (adev->in_suspend || adev->in_gpu_reset) |
b293e891 HZ |
1988 | return 0; |
1989 | ||
1990 | if (ih_info->cb) { | |
1991 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
1992 | if (r) | |
1993 | goto interrupt; | |
1994 | } | |
1995 | ||
b293e891 HZ |
1996 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
1997 | if (r) | |
1998 | goto sysfs; | |
1999 | ||
2000 | return 0; | |
2001 | cleanup: | |
2002 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2003 | sysfs: | |
b293e891 HZ |
2004 | if (ih_info->cb) |
2005 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2006 | interrupt: | |
2007 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2008 | return r; | |
2009 | } | |
2010 | ||
2011 | /* helper function to remove ras fs node and interrupt handler */ | |
2012 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2013 | struct ras_common_if *ras_block, | |
2014 | struct ras_ih_if *ih_info) | |
2015 | { | |
2016 | if (!ras_block || !ih_info) | |
2017 | return; | |
2018 | ||
2019 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 HZ |
2020 | if (ih_info->cb) |
2021 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2022 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2023 | } | |
2024 | ||
a564808e | 2025 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2026 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2027 | */ |
511fdbc3 | 2028 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2029 | { |
2030 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2031 | struct ras_manager *obj, *tmp; | |
2032 | ||
2033 | if (!con) | |
2034 | return; | |
2035 | ||
108c6a63 | 2036 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2037 | /* Set up all other IPs which are not implemented. There is a |
2038 | * tricky thing that IP's actual ras error type should be | |
2039 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2040 | * ERROR_NONE make sense anyway. | |
2041 | */ | |
2042 | amdgpu_ras_enable_all_features(adev, 1); | |
2043 | ||
2044 | /* We enable ras on all hw_supported block, but as boot | |
2045 | * parameter might disable some of them and one or more IP has | |
2046 | * not implemented yet. So we disable them on behalf. | |
2047 | */ | |
108c6a63 | 2048 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2049 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2050 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2051 | /* there should be no any reference. */ | |
2052 | WARN_ON(alive_obj(obj)); | |
2053 | } | |
191051a1 | 2054 | } |
108c6a63 | 2055 | } |
a564808e | 2056 | |
2057 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2058 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2059 | /* setup ras obj state as disabled. | |
2060 | * for init_by_vbios case. | |
2061 | * if we want to enable ras, just enable it in a normal way. | |
2062 | * If we want do disable it, need setup ras obj as enabled, | |
2063 | * then issue another TA disable cmd. | |
2064 | * See feature_enable_on_boot | |
2065 | */ | |
2066 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2067 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2068 | } |
108c6a63 | 2069 | } |
2070 | ||
511fdbc3 | 2071 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2072 | { | |
2073 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2074 | ||
2075 | if (!con) | |
2076 | return; | |
2077 | ||
2078 | amdgpu_ras_disable_all_features(adev, 0); | |
2079 | /* Make sure all ras objects are disabled. */ | |
2080 | if (con->features) | |
2081 | amdgpu_ras_disable_all_features(adev, 1); | |
2082 | } | |
2083 | ||
c030f2e4 | 2084 | /* do some fini work before IP fini as dependence */ |
2085 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2086 | { | |
2087 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2088 | ||
2089 | if (!con) | |
2090 | return 0; | |
2091 | ||
2092 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2093 | amdgpu_ras_disable_all_features(adev, 0); | |
2094 | amdgpu_ras_recovery_fini(adev); | |
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2099 | { | |
2100 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2101 | ||
2102 | if (!con) | |
2103 | return 0; | |
2104 | ||
2105 | amdgpu_ras_fs_fini(adev); | |
2106 | amdgpu_ras_interrupt_remove_all(adev); | |
2107 | ||
2108 | WARN(con->features, "Feature mask is not cleared"); | |
2109 | ||
2110 | if (con->features) | |
2111 | amdgpu_ras_disable_all_features(adev, 1); | |
2112 | ||
2113 | amdgpu_ras_set_context(adev, NULL); | |
2114 | kfree(con); | |
2115 | ||
2116 | return 0; | |
2117 | } | |
7c6e68c7 AG |
2118 | |
2119 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2120 | { | |
ed606f8a AG |
2121 | uint32_t hw_supported, supported; |
2122 | ||
2123 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2124 | if (!hw_supported) | |
2125 | return; | |
2126 | ||
7c6e68c7 | 2127 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2128 | dev_info(adev->dev, "uncorrectable hardware error" |
2129 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2130 | |
61934624 | 2131 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2132 | } |
2133 | } |