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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
c030f2e4 | 37 | const char *ras_error_string[] = { |
38 | "none", | |
39 | "parity", | |
40 | "single_correctable", | |
41 | "multi_uncorrectable", | |
42 | "poison", | |
43 | }; | |
44 | ||
45 | const char *ras_block_string[] = { | |
46 | "umc", | |
47 | "sdma", | |
48 | "gfx", | |
49 | "mmhub", | |
50 | "athub", | |
51 | "pcie_bif", | |
52 | "hdp", | |
53 | "xgmi_wafl", | |
54 | "df", | |
55 | "smn", | |
56 | "sem", | |
57 | "mp0", | |
58 | "mp1", | |
59 | "fuse", | |
60 | }; | |
61 | ||
62 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
63 | #define ras_block_str(i) (ras_block_string[i]) | |
64 | ||
108c6a63 | 65 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
66 | ||
7cdc2ee3 TZ |
67 | /* inject address is 52 bits */ |
68 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
69 | ||
c84d4670 GC |
70 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
71 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
72 | ||
52dd95f2 GC |
73 | enum amdgpu_ras_retire_page_reservation { |
74 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
75 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
76 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
77 | }; | |
7c6e68c7 AG |
78 | |
79 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
80 | ||
6e4be987 TZ |
81 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
82 | uint64_t addr); | |
83 | ||
61380faa JC |
84 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
85 | { | |
a9d82d2f | 86 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
87 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
88 | } | |
89 | ||
f3167919 | 90 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 91 | { |
a9d82d2f | 92 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
93 | return amdgpu_ras_get_context(adev)->error_query_ready; |
94 | ||
95 | return false; | |
96 | } | |
97 | ||
c030f2e4 | 98 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
99 | size_t size, loff_t *pos) | |
100 | { | |
101 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
102 | struct ras_query_if info = { | |
103 | .head = obj->head, | |
104 | }; | |
105 | ssize_t s; | |
106 | char val[128]; | |
107 | ||
108 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
109 | return -EINVAL; | |
110 | ||
111 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
112 | "ue", info.ue_count, | |
113 | "ce", info.ce_count); | |
114 | if (*pos >= s) | |
115 | return 0; | |
116 | ||
117 | s -= *pos; | |
118 | s = min_t(u64, s, size); | |
119 | ||
120 | ||
121 | if (copy_to_user(buf, &val[*pos], s)) | |
122 | return -EINVAL; | |
123 | ||
124 | *pos += s; | |
125 | ||
126 | return s; | |
127 | } | |
128 | ||
c030f2e4 | 129 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
130 | .owner = THIS_MODULE, | |
131 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 132 | .write = NULL, |
c030f2e4 | 133 | .llseek = default_llseek |
134 | }; | |
135 | ||
96ebb307 | 136 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
137 | { | |
138 | int i; | |
139 | ||
140 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
141 | *block_id = i; | |
142 | if (strcmp(name, ras_block_str(i)) == 0) | |
143 | return 0; | |
144 | } | |
145 | return -EINVAL; | |
146 | } | |
147 | ||
148 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
149 | const char __user *buf, size_t size, | |
150 | loff_t *pos, struct ras_debug_if *data) | |
151 | { | |
152 | ssize_t s = min_t(u64, 64, size); | |
153 | char str[65]; | |
154 | char block_name[33]; | |
155 | char err[9] = "ue"; | |
156 | int op = -1; | |
157 | int block_id; | |
44494f96 | 158 | uint32_t sub_block; |
96ebb307 | 159 | u64 address, value; |
160 | ||
161 | if (*pos) | |
162 | return -EINVAL; | |
163 | *pos = size; | |
164 | ||
165 | memset(str, 0, sizeof(str)); | |
166 | memset(data, 0, sizeof(*data)); | |
167 | ||
168 | if (copy_from_user(str, buf, s)) | |
169 | return -EINVAL; | |
170 | ||
171 | if (sscanf(str, "disable %32s", block_name) == 1) | |
172 | op = 0; | |
173 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
174 | op = 1; | |
175 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
176 | op = 2; | |
b076296b | 177 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 178 | /* ascii string, but commands are not matched. */ |
179 | return -EINVAL; | |
180 | ||
181 | if (op != -1) { | |
182 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
183 | return -EINVAL; | |
184 | ||
185 | data->head.block = block_id; | |
e1063493 TZ |
186 | /* only ue and ce errors are supported */ |
187 | if (!memcmp("ue", err, 2)) | |
188 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
189 | else if (!memcmp("ce", err, 2)) | |
190 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
191 | else | |
192 | return -EINVAL; | |
193 | ||
96ebb307 | 194 | data->op = op; |
195 | ||
196 | if (op == 2) { | |
44494f96 TZ |
197 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
198 | &sub_block, &address, &value) != 3) | |
199 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
200 | &sub_block, &address, &value) != 3) | |
96ebb307 | 201 | return -EINVAL; |
44494f96 | 202 | data->head.sub_block_index = sub_block; |
96ebb307 | 203 | data->inject.address = address; |
204 | data->inject.value = value; | |
205 | } | |
206 | } else { | |
73aa8e1a | 207 | if (size < sizeof(*data)) |
96ebb307 | 208 | return -EINVAL; |
209 | ||
210 | if (copy_from_user(data, buf, sizeof(*data))) | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | return 0; | |
215 | } | |
7c6e68c7 | 216 | |
74abc221 TSD |
217 | /** |
218 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 219 | * |
220 | * It accepts struct ras_debug_if who has two members. | |
221 | * | |
222 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 223 | * |
224 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 225 | * |
226 | * head has four members, they are block, type, sub_block_index, name. | |
227 | * block: which IP will be under control. | |
228 | * type: what kind of error will be enabled/disabled/injected. | |
229 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
230 | * name: the name of IP. | |
231 | * | |
232 | * inject has two more members than head, they are address, value. | |
233 | * As their names indicate, inject operation will write the | |
234 | * value to the address. | |
235 | * | |
ef177d11 | 236 | * The second member: struct ras_debug_if::op. |
c688a06b | 237 | * It has three kinds of operations. |
879e723d AZ |
238 | * |
239 | * - 0: disable RAS on the block. Take ::head as its data. | |
240 | * - 1: enable RAS on the block. Take ::head as its data. | |
241 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 242 | * |
96ebb307 | 243 | * How to use the interface? |
ef177d11 AD |
244 | * |
245 | * Programs | |
246 | * | |
247 | * Copy the struct ras_debug_if in your codes and initialize it. | |
248 | * Write the struct to the control node. | |
249 | * | |
250 | * Shells | |
96ebb307 | 251 | * |
879e723d AZ |
252 | * .. code-block:: bash |
253 | * | |
a20bfd0f | 254 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 255 | * |
ef177d11 AD |
256 | * Parameters: |
257 | * | |
879e723d AZ |
258 | * op: disable, enable, inject |
259 | * disable: only block is needed | |
260 | * enable: block and error are needed | |
261 | * inject: error, address, value are needed | |
a20bfd0f | 262 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
263 | * see ras_block_string[] for details |
264 | * error: ue, ce | |
265 | * ue: multi_uncorrectable | |
266 | * ce: single_correctable | |
267 | * sub_block: | |
268 | * sub block index, pass 0 if there is no sub block | |
269 | * | |
270 | * here are some examples for bash commands: | |
271 | * | |
272 | * .. code-block:: bash | |
96ebb307 | 273 | * |
44494f96 TZ |
274 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
275 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 276 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
277 | * | |
36ea1bd2 | 278 | * How to check the result? |
279 | * | |
280 | * For disable/enable, please check ras features at | |
281 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
282 | * | |
283 | * For inject, please check corresponding err count at | |
284 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
285 | * | |
879e723d | 286 | * .. note:: |
ef177d11 | 287 | * Operations are only allowed on blocks which are supported. |
879e723d | 288 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
289 | * to see which blocks support RAS on a particular asic. |
290 | * | |
36ea1bd2 | 291 | */ |
292 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
293 | size_t size, loff_t *pos) | |
294 | { | |
295 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
296 | struct ras_debug_if data; | |
297 | int ret = 0; | |
298 | ||
61380faa | 299 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
300 | dev_warn(adev->dev, "RAS WARN: error injection " |
301 | "currently inaccessible\n"); | |
43c4d576 JC |
302 | return size; |
303 | } | |
304 | ||
96ebb307 | 305 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
306 | if (ret) | |
36ea1bd2 | 307 | return -EINVAL; |
308 | ||
36ea1bd2 | 309 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
310 | return -EINVAL; | |
311 | ||
312 | switch (data.op) { | |
313 | case 0: | |
314 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
315 | break; | |
316 | case 1: | |
317 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
318 | break; | |
319 | case 2: | |
7cdc2ee3 TZ |
320 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
321 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
322 | dev_warn(adev->dev, "RAS WARN: input address " |
323 | "0x%llx is invalid.", | |
324 | data.inject.address); | |
7cdc2ee3 TZ |
325 | ret = -EINVAL; |
326 | break; | |
327 | } | |
328 | ||
6e4be987 TZ |
329 | /* umc ce/ue error injection for a bad page is not allowed */ |
330 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
331 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
332 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
333 | "as bad before error injection!\n", | |
6e4be987 TZ |
334 | data.inject.address); |
335 | break; | |
336 | } | |
337 | ||
7cdc2ee3 | 338 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 339 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
340 | break; | |
96ebb307 | 341 | default: |
342 | ret = -EINVAL; | |
343 | break; | |
374bf7bd | 344 | } |
36ea1bd2 | 345 | |
346 | if (ret) | |
347 | return -EINVAL; | |
348 | ||
349 | return size; | |
350 | } | |
351 | ||
084fe13b AG |
352 | /** |
353 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
354 | * | |
f77c7109 | 355 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 356 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
357 | * a way to reset the EEPROM, e.g., after testing error injection. |
358 | * | |
359 | * Usage: | |
360 | * | |
361 | * .. code-block:: bash | |
362 | * | |
363 | * echo 1 > ../ras/ras_eeprom_reset | |
364 | * | |
365 | * will reset EEPROM table to 0 entries. | |
366 | * | |
084fe13b AG |
367 | */ |
368 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
369 | size_t size, loff_t *pos) | |
370 | { | |
371 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
372 | int ret; | |
373 | ||
374 | ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); | |
375 | ||
376 | return ret == 1 ? size : -EIO; | |
377 | } | |
378 | ||
36ea1bd2 | 379 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
380 | .owner = THIS_MODULE, | |
381 | .read = NULL, | |
382 | .write = amdgpu_ras_debugfs_ctrl_write, | |
383 | .llseek = default_llseek | |
384 | }; | |
385 | ||
084fe13b AG |
386 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
387 | .owner = THIS_MODULE, | |
388 | .read = NULL, | |
389 | .write = amdgpu_ras_debugfs_eeprom_write, | |
390 | .llseek = default_llseek | |
391 | }; | |
392 | ||
f77c7109 AD |
393 | /** |
394 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
395 | * | |
ef177d11 | 396 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
397 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
398 | * | |
399 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
400 | * (ce) error counts. | |
401 | * | |
402 | * The format of one line is below, | |
403 | * | |
404 | * [ce|ue]: count | |
405 | * | |
406 | * Example: | |
407 | * | |
408 | * .. code-block:: bash | |
409 | * | |
410 | * ue: 0 | |
411 | * ce: 1 | |
412 | * | |
413 | */ | |
c030f2e4 | 414 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
415 | struct device_attribute *attr, char *buf) | |
416 | { | |
417 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
418 | struct ras_query_if info = { | |
419 | .head = obj->head, | |
420 | }; | |
421 | ||
61380faa | 422 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
43c4d576 JC |
423 | return snprintf(buf, PAGE_SIZE, |
424 | "Query currently inaccessible\n"); | |
425 | ||
c030f2e4 | 426 | if (amdgpu_ras_error_query(obj->adev, &info)) |
427 | return -EINVAL; | |
428 | ||
429 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
430 | "ue", info.ue_count, | |
431 | "ce", info.ce_count); | |
432 | } | |
433 | ||
434 | /* obj begin */ | |
435 | ||
436 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
437 | #define alive_obj(obj) ((obj)->use) | |
438 | ||
439 | static inline void put_obj(struct ras_manager *obj) | |
440 | { | |
441 | if (obj && --obj->use == 0) | |
442 | list_del(&obj->node); | |
443 | if (obj && obj->use < 0) { | |
444 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
445 | } | |
446 | } | |
447 | ||
448 | /* make one obj and return it. */ | |
449 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
450 | struct ras_common_if *head) | |
451 | { | |
452 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
453 | struct ras_manager *obj; | |
454 | ||
455 | if (!con) | |
456 | return NULL; | |
457 | ||
458 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
459 | return NULL; | |
460 | ||
461 | obj = &con->objs[head->block]; | |
462 | /* already exist. return obj? */ | |
463 | if (alive_obj(obj)) | |
464 | return NULL; | |
465 | ||
466 | obj->head = *head; | |
467 | obj->adev = adev; | |
468 | list_add(&obj->node, &con->head); | |
469 | get_obj(obj); | |
470 | ||
471 | return obj; | |
472 | } | |
473 | ||
474 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 475 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 476 | struct ras_common_if *head) |
477 | { | |
478 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
479 | struct ras_manager *obj; | |
480 | int i; | |
481 | ||
482 | if (!con) | |
483 | return NULL; | |
484 | ||
485 | if (head) { | |
486 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
487 | return NULL; | |
488 | ||
489 | obj = &con->objs[head->block]; | |
490 | ||
491 | if (alive_obj(obj)) { | |
492 | WARN_ON(head->block != obj->head.block); | |
493 | return obj; | |
494 | } | |
495 | } else { | |
496 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
497 | obj = &con->objs[i]; | |
498 | if (alive_obj(obj)) { | |
499 | WARN_ON(i != obj->head.block); | |
500 | return obj; | |
501 | } | |
502 | } | |
503 | } | |
504 | ||
505 | return NULL; | |
506 | } | |
507 | /* obj end */ | |
508 | ||
f3167919 | 509 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
a200034b JC |
510 | const char* invoke_type, |
511 | const char* block_name, | |
512 | enum ta_ras_status ret) | |
513 | { | |
514 | switch (ret) { | |
515 | case TA_RAS_STATUS__SUCCESS: | |
516 | return; | |
517 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
518 | dev_warn(adev->dev, | |
519 | "RAS WARN: %s %s currently unavailable\n", | |
520 | invoke_type, | |
521 | block_name); | |
522 | break; | |
523 | default: | |
524 | dev_err(adev->dev, | |
525 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
526 | invoke_type, | |
527 | block_name, | |
528 | ret); | |
529 | } | |
530 | } | |
531 | ||
c030f2e4 | 532 | /* feature ctl begin */ |
533 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
534 | struct ras_common_if *head) | |
535 | { | |
5caf466a | 536 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
537 | ||
538 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 539 | } |
540 | ||
541 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
542 | struct ras_common_if *head) | |
543 | { | |
544 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
545 | ||
546 | return con->features & BIT(head->block); | |
547 | } | |
548 | ||
549 | /* | |
550 | * if obj is not created, then create one. | |
551 | * set feature enable flag. | |
552 | */ | |
553 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
554 | struct ras_common_if *head, int enable) | |
555 | { | |
556 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
557 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
558 | ||
5caf466a | 559 | /* If hardware does not support ras, then do not create obj. |
560 | * But if hardware support ras, we can create the obj. | |
561 | * Ras framework checks con->hw_supported to see if it need do | |
562 | * corresponding initialization. | |
563 | * IP checks con->support to see if it need disable ras. | |
564 | */ | |
c030f2e4 | 565 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
566 | return 0; | |
567 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
568 | return 0; | |
569 | ||
570 | if (enable) { | |
571 | if (!obj) { | |
572 | obj = amdgpu_ras_create_obj(adev, head); | |
573 | if (!obj) | |
574 | return -EINVAL; | |
575 | } else { | |
576 | /* In case we create obj somewhere else */ | |
577 | get_obj(obj); | |
578 | } | |
579 | con->features |= BIT(head->block); | |
580 | } else { | |
581 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
582 | con->features &= ~BIT(head->block); | |
583 | put_obj(obj); | |
584 | } | |
585 | } | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | /* wrapper of psp_ras_enable_features */ | |
591 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
592 | struct ras_common_if *head, bool enable) | |
593 | { | |
594 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 595 | union ta_ras_cmd_input *info; |
c030f2e4 | 596 | int ret; |
597 | ||
598 | if (!con) | |
599 | return -EINVAL; | |
600 | ||
7fcffecf AB |
601 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
602 | if (!info) | |
603 | return -ENOMEM; | |
604 | ||
c030f2e4 | 605 | if (!enable) { |
7fcffecf | 606 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 607 | .block_id = amdgpu_ras_block_to_ta(head->block), |
608 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 609 | }; |
610 | } else { | |
7fcffecf | 611 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 612 | .block_id = amdgpu_ras_block_to_ta(head->block), |
613 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 614 | }; |
615 | } | |
616 | ||
617 | /* Do not enable if it is not allowed. */ | |
618 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
619 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
620 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
621 | ret = 0; | |
622 | goto out; | |
623 | } | |
c030f2e4 | 624 | |
bff77e86 | 625 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 626 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 627 | if (ret) { |
a200034b JC |
628 | amdgpu_ras_parse_status_code(adev, |
629 | enable ? "enable":"disable", | |
630 | ras_block_str(head->block), | |
631 | (enum ta_ras_status)ret); | |
bff77e86 | 632 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
633 | ret = -EAGAIN; |
634 | else | |
635 | ret = -EINVAL; | |
636 | ||
637 | goto out; | |
bff77e86 | 638 | } |
c030f2e4 | 639 | } |
640 | ||
641 | /* setup the obj */ | |
642 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
643 | ret = 0; |
644 | out: | |
645 | kfree(info); | |
646 | return ret; | |
c030f2e4 | 647 | } |
648 | ||
77de502b | 649 | /* Only used in device probe stage and called only once. */ |
650 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
651 | struct ras_common_if *head, bool enable) | |
652 | { | |
653 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
654 | int ret; | |
655 | ||
656 | if (!con) | |
657 | return -EINVAL; | |
658 | ||
659 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 660 | if (enable) { |
661 | /* There is no harm to issue a ras TA cmd regardless of | |
662 | * the currecnt ras state. | |
663 | * If current state == target state, it will do nothing | |
664 | * But sometimes it requests driver to reset and repost | |
665 | * with error code -EAGAIN. | |
666 | */ | |
667 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
668 | /* With old ras TA, we might fail to enable ras. | |
669 | * Log it and just setup the object. | |
670 | * TODO need remove this WA in the future. | |
671 | */ | |
672 | if (ret == -EINVAL) { | |
673 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
674 | if (!ret) | |
6952e99c GC |
675 | dev_info(adev->dev, |
676 | "RAS INFO: %s setup object\n", | |
7af23ebe | 677 | ras_block_str(head->block)); |
678 | } | |
679 | } else { | |
680 | /* setup the object then issue a ras TA disable cmd.*/ | |
681 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
682 | if (ret) | |
683 | return ret; | |
77de502b | 684 | |
77de502b | 685 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 686 | } |
77de502b | 687 | } else |
688 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
689 | ||
690 | return ret; | |
691 | } | |
692 | ||
c030f2e4 | 693 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
694 | bool bypass) | |
695 | { | |
696 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
697 | struct ras_manager *obj, *tmp; | |
698 | ||
699 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
700 | /* bypass psp. | |
701 | * aka just release the obj and corresponding flags | |
702 | */ | |
703 | if (bypass) { | |
704 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
705 | break; | |
706 | } else { | |
707 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
708 | break; | |
709 | } | |
289d513b | 710 | } |
c030f2e4 | 711 | |
712 | return con->features; | |
713 | } | |
714 | ||
715 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
716 | bool bypass) | |
717 | { | |
718 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
719 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
720 | int i; | |
191051a1 | 721 | const enum amdgpu_ras_error_type default_ras_type = |
722 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 723 | |
724 | for (i = 0; i < ras_block_count; i++) { | |
725 | struct ras_common_if head = { | |
726 | .block = i, | |
191051a1 | 727 | .type = default_ras_type, |
c030f2e4 | 728 | .sub_block_index = 0, |
729 | }; | |
730 | strcpy(head.name, ras_block_str(i)); | |
731 | if (bypass) { | |
732 | /* | |
733 | * bypass psp. vbios enable ras for us. | |
734 | * so just create the obj | |
735 | */ | |
736 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
737 | break; | |
738 | } else { | |
739 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
740 | break; | |
741 | } | |
289d513b | 742 | } |
c030f2e4 | 743 | |
744 | return con->features; | |
745 | } | |
746 | /* feature ctl end */ | |
747 | ||
748 | /* query/inject/cure begin */ | |
749 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
750 | struct ras_query_if *info) | |
751 | { | |
752 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 753 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 754 | int i; |
c030f2e4 | 755 | |
756 | if (!obj) | |
757 | return -EINVAL; | |
c030f2e4 | 758 | |
939e2258 HZ |
759 | switch (info->head.block) { |
760 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
761 | if (adev->umc.funcs->query_ras_error_count) |
762 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
763 | /* umc query_ras_error_address is also responsible for clearing |
764 | * error status | |
765 | */ | |
766 | if (adev->umc.funcs->query_ras_error_address) | |
767 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 768 | break; |
3e81ee9a HZ |
769 | case AMDGPU_RAS_BLOCK__SDMA: |
770 | if (adev->sdma.funcs->query_ras_error_count) { | |
771 | for (i = 0; i < adev->sdma.num_instances; i++) | |
772 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
773 | &err_data); | |
774 | } | |
775 | break; | |
83b0582c DL |
776 | case AMDGPU_RAS_BLOCK__GFX: |
777 | if (adev->gfx.funcs->query_ras_error_count) | |
778 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
779 | break; | |
9fb2d8de | 780 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
781 | if (adev->mmhub.funcs->query_ras_error_count) |
782 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 783 | break; |
d7bd680d GC |
784 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
785 | if (adev->nbio.funcs->query_ras_error_count) | |
786 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
787 | break; | |
ec01fe2d HZ |
788 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
789 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
790 | break; | |
939e2258 HZ |
791 | default: |
792 | break; | |
793 | } | |
05a58345 TZ |
794 | |
795 | obj->err_data.ue_count += err_data.ue_count; | |
796 | obj->err_data.ce_count += err_data.ce_count; | |
797 | ||
c030f2e4 | 798 | info->ue_count = obj->err_data.ue_count; |
799 | info->ce_count = obj->err_data.ce_count; | |
800 | ||
7c6e68c7 | 801 | if (err_data.ce_count) { |
6952e99c GC |
802 | dev_info(adev->dev, "%ld correctable hardware errors " |
803 | "detected in %s block, no user " | |
804 | "action is needed.\n", | |
805 | obj->err_data.ce_count, | |
806 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
807 | } |
808 | if (err_data.ue_count) { | |
6952e99c GC |
809 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
810 | "detected in %s block\n", | |
811 | obj->err_data.ue_count, | |
812 | ras_block_str(info->head.block)); | |
7c6e68c7 | 813 | } |
05a58345 | 814 | |
c030f2e4 | 815 | return 0; |
816 | } | |
817 | ||
5c23e9e0 | 818 | /* Trigger XGMI/WAFL error */ |
f3167919 | 819 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
820 | struct ta_ras_trigger_error_input *block_info) |
821 | { | |
822 | int ret; | |
823 | ||
824 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
825 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
826 | ||
827 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
828 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
829 | ||
830 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
831 | ||
832 | if (amdgpu_ras_intr_triggered()) | |
833 | return ret; | |
834 | ||
835 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
836 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
837 | ||
838 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
839 | dev_warn(adev->dev, "Failed to allow df cstate"); | |
840 | ||
841 | return ret; | |
842 | } | |
843 | ||
c030f2e4 | 844 | /* wrapper of psp_ras_trigger_error */ |
845 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
846 | struct ras_inject_if *info) | |
847 | { | |
848 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
849 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 850 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
851 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 852 | .sub_block_index = info->head.sub_block_index, |
853 | .address = info->address, | |
854 | .value = info->value, | |
855 | }; | |
856 | int ret = 0; | |
857 | ||
858 | if (!obj) | |
859 | return -EINVAL; | |
860 | ||
a6c44d25 JC |
861 | /* Calculate XGMI relative offset */ |
862 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
863 | block_info.address = |
864 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
865 | block_info.address); | |
a6c44d25 JC |
866 | } |
867 | ||
83b0582c DL |
868 | switch (info->head.block) { |
869 | case AMDGPU_RAS_BLOCK__GFX: | |
870 | if (adev->gfx.funcs->ras_error_inject) | |
871 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
872 | else | |
873 | ret = -EINVAL; | |
874 | break; | |
875 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 876 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 877 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
878 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
879 | break; | |
5c23e9e0 JC |
880 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
881 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
882 | break; | |
83b0582c | 883 | default: |
6952e99c | 884 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 885 | ras_block_str(info->head.block)); |
83b0582c | 886 | ret = -EINVAL; |
a5dd40ca HZ |
887 | } |
888 | ||
a200034b JC |
889 | amdgpu_ras_parse_status_code(adev, |
890 | "inject", | |
891 | ras_block_str(info->head.block), | |
892 | (enum ta_ras_status)ret); | |
c030f2e4 | 893 | |
894 | return ret; | |
895 | } | |
896 | ||
897 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
898 | struct ras_cure_if *info) | |
899 | { | |
900 | /* psp fw has no cure interface for now. */ | |
901 | return 0; | |
902 | } | |
903 | ||
904 | /* get the total error counts on all IPs */ | |
64cc5414 | 905 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 906 | bool is_ce) |
907 | { | |
908 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
909 | struct ras_manager *obj; | |
910 | struct ras_err_data data = {0, 0}; | |
911 | ||
912 | if (!con) | |
64cc5414 | 913 | return 0; |
c030f2e4 | 914 | |
915 | list_for_each_entry(obj, &con->head, node) { | |
916 | struct ras_query_if info = { | |
917 | .head = obj->head, | |
918 | }; | |
919 | ||
920 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 921 | return 0; |
c030f2e4 | 922 | |
923 | data.ce_count += info.ce_count; | |
924 | data.ue_count += info.ue_count; | |
925 | } | |
926 | ||
927 | return is_ce ? data.ce_count : data.ue_count; | |
928 | } | |
929 | /* query/inject/cure end */ | |
930 | ||
931 | ||
932 | /* sysfs begin */ | |
933 | ||
466b1793 | 934 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
935 | struct ras_badpage **bps, unsigned int *count); | |
936 | ||
937 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
938 | { | |
939 | switch (flags) { | |
52dd95f2 | 940 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 941 | return "R"; |
52dd95f2 | 942 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 943 | return "P"; |
52dd95f2 | 944 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 945 | default: |
946 | return "F"; | |
947 | }; | |
948 | } | |
949 | ||
f77c7109 AD |
950 | /** |
951 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 952 | * |
953 | * It allows user to read the bad pages of vram on the gpu through | |
954 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
955 | * | |
956 | * It outputs multiple lines, and each line stands for one gpu page. | |
957 | * | |
958 | * The format of one line is below, | |
959 | * gpu pfn : gpu page size : flags | |
960 | * | |
961 | * gpu pfn and gpu page size are printed in hex format. | |
962 | * flags can be one of below character, | |
f77c7109 | 963 | * |
466b1793 | 964 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 965 | * |
466b1793 | 966 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
967 | * in next window of page_reserve. |
968 | * | |
466b1793 | 969 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
970 | * | |
f77c7109 AD |
971 | * Examples: |
972 | * | |
973 | * .. code-block:: bash | |
974 | * | |
975 | * 0x00000001 : 0x00001000 : R | |
976 | * 0x00000002 : 0x00001000 : P | |
977 | * | |
466b1793 | 978 | */ |
979 | ||
980 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
981 | struct kobject *kobj, struct bin_attribute *attr, | |
982 | char *buf, loff_t ppos, size_t count) | |
983 | { | |
984 | struct amdgpu_ras *con = | |
985 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
986 | struct amdgpu_device *adev = con->adev; | |
987 | const unsigned int element_size = | |
988 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
989 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
990 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 991 | ssize_t s = 0; |
992 | struct ras_badpage *bps = NULL; | |
993 | unsigned int bps_count = 0; | |
994 | ||
995 | memset(buf, 0, count); | |
996 | ||
997 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
998 | return 0; | |
999 | ||
1000 | for (; start < end && start < bps_count; start++) | |
1001 | s += scnprintf(&buf[s], element_size + 1, | |
1002 | "0x%08x : 0x%08x : %1s\n", | |
1003 | bps[start].bp, | |
1004 | bps[start].size, | |
1005 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1006 | ||
1007 | kfree(bps); | |
1008 | ||
1009 | return s; | |
1010 | } | |
1011 | ||
c030f2e4 | 1012 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1013 | struct device_attribute *attr, char *buf) | |
1014 | { | |
1015 | struct amdgpu_ras *con = | |
1016 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1017 | |
5212a3bd | 1018 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1019 | } |
1020 | ||
1021 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
1022 | { | |
1023 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1024 | struct attribute *attrs[] = { | |
1025 | &con->features_attr.attr, | |
1026 | NULL | |
1027 | }; | |
466b1793 | 1028 | struct bin_attribute *bin_attrs[] = { |
1029 | &con->badpages_attr, | |
1030 | NULL | |
1031 | }; | |
c030f2e4 | 1032 | struct attribute_group group = { |
1033 | .name = "ras", | |
1034 | .attrs = attrs, | |
466b1793 | 1035 | .bin_attrs = bin_attrs, |
c030f2e4 | 1036 | }; |
1037 | ||
1038 | con->features_attr = (struct device_attribute) { | |
1039 | .attr = { | |
1040 | .name = "features", | |
1041 | .mode = S_IRUGO, | |
1042 | }, | |
1043 | .show = amdgpu_ras_sysfs_features_read, | |
1044 | }; | |
466b1793 | 1045 | |
1046 | con->badpages_attr = (struct bin_attribute) { | |
1047 | .attr = { | |
1048 | .name = "gpu_vram_bad_pages", | |
1049 | .mode = S_IRUGO, | |
1050 | }, | |
1051 | .size = 0, | |
1052 | .private = NULL, | |
1053 | .read = amdgpu_ras_sysfs_badpages_read, | |
1054 | }; | |
1055 | ||
163def43 | 1056 | sysfs_attr_init(attrs[0]); |
466b1793 | 1057 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 1058 | |
1059 | return sysfs_create_group(&adev->dev->kobj, &group); | |
1060 | } | |
1061 | ||
1062 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
1063 | { | |
1064 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1065 | struct attribute *attrs[] = { | |
1066 | &con->features_attr.attr, | |
1067 | NULL | |
1068 | }; | |
466b1793 | 1069 | struct bin_attribute *bin_attrs[] = { |
1070 | &con->badpages_attr, | |
1071 | NULL | |
1072 | }; | |
c030f2e4 | 1073 | struct attribute_group group = { |
1074 | .name = "ras", | |
1075 | .attrs = attrs, | |
466b1793 | 1076 | .bin_attrs = bin_attrs, |
c030f2e4 | 1077 | }; |
1078 | ||
1079 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1085 | struct ras_fs_if *head) | |
1086 | { | |
1087 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1088 | ||
1089 | if (!obj || obj->attr_inuse) | |
1090 | return -EINVAL; | |
1091 | ||
1092 | get_obj(obj); | |
1093 | ||
1094 | memcpy(obj->fs_data.sysfs_name, | |
1095 | head->sysfs_name, | |
1096 | sizeof(obj->fs_data.sysfs_name)); | |
1097 | ||
1098 | obj->sysfs_attr = (struct device_attribute){ | |
1099 | .attr = { | |
1100 | .name = obj->fs_data.sysfs_name, | |
1101 | .mode = S_IRUGO, | |
1102 | }, | |
1103 | .show = amdgpu_ras_sysfs_read, | |
1104 | }; | |
163def43 | 1105 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1106 | |
1107 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1108 | &obj->sysfs_attr.attr, | |
1109 | "ras")) { | |
1110 | put_obj(obj); | |
1111 | return -EINVAL; | |
1112 | } | |
1113 | ||
1114 | obj->attr_inuse = 1; | |
1115 | ||
1116 | return 0; | |
1117 | } | |
1118 | ||
1119 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1120 | struct ras_common_if *head) | |
1121 | { | |
1122 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1123 | ||
1124 | if (!obj || !obj->attr_inuse) | |
1125 | return -EINVAL; | |
1126 | ||
1127 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1128 | &obj->sysfs_attr.attr, | |
1129 | "ras"); | |
1130 | obj->attr_inuse = 0; | |
1131 | put_obj(obj); | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1137 | { | |
1138 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1139 | struct ras_manager *obj, *tmp; | |
1140 | ||
1141 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1142 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1143 | } | |
1144 | ||
1145 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | /* sysfs end */ | |
1150 | ||
ef177d11 AD |
1151 | /** |
1152 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1153 | * | |
1154 | * Normally when there is an uncorrectable error, the driver will reset | |
1155 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1156 | * the driver provides an interface to reboot the system automatically | |
1157 | * in that event. | |
1158 | * | |
1159 | * The following file in debugfs provides that interface: | |
1160 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1161 | * | |
1162 | * Usage: | |
1163 | * | |
1164 | * .. code-block:: bash | |
1165 | * | |
1166 | * echo true > .../ras/auto_reboot | |
1167 | * | |
1168 | */ | |
c030f2e4 | 1169 | /* debugfs begin */ |
450f30ea | 1170 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1171 | { |
1172 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1173 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 1174 | |
450f30ea | 1175 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
012dd14d GC |
1176 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1177 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1178 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1179 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1180 | |
1181 | /* | |
1182 | * After one uncorrectable error happens, usually GPU recovery will | |
1183 | * be scheduled. But due to the known problem in GPU recovery failing | |
1184 | * to bring GPU back, below interface provides one direct way to | |
1185 | * user to reboot system automatically in such case within | |
1186 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1187 | * will never be called. | |
1188 | */ | |
1189 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1190 | &con->reboot); | |
36ea1bd2 | 1191 | } |
1192 | ||
450f30ea | 1193 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1194 | struct ras_fs_if *head) |
1195 | { | |
1196 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1197 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1198 | |
1199 | if (!obj || obj->ent) | |
450f30ea | 1200 | return; |
c030f2e4 | 1201 | |
1202 | get_obj(obj); | |
1203 | ||
1204 | memcpy(obj->fs_data.debugfs_name, | |
1205 | head->debugfs_name, | |
1206 | sizeof(obj->fs_data.debugfs_name)); | |
1207 | ||
450f30ea GKH |
1208 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1209 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1210 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1211 | } |
1212 | ||
f9317014 TZ |
1213 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1214 | { | |
1215 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c1509f3f | 1216 | struct ras_manager *obj; |
f9317014 TZ |
1217 | struct ras_fs_if fs_info; |
1218 | ||
1219 | /* | |
1220 | * it won't be called in resume path, no need to check | |
1221 | * suspend and gpu reset status | |
1222 | */ | |
1223 | if (!con) | |
1224 | return; | |
1225 | ||
1226 | amdgpu_ras_debugfs_create_ctrl_node(adev); | |
1227 | ||
c1509f3f | 1228 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1229 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1230 | (obj->attr_inuse == 1)) { | |
1231 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1232 | ras_block_str(obj->head.block)); | |
1233 | fs_info.head = obj->head; | |
1234 | amdgpu_ras_debugfs_create(adev, &fs_info); | |
1235 | } | |
1236 | } | |
1237 | } | |
1238 | ||
450f30ea | 1239 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1240 | struct ras_common_if *head) |
1241 | { | |
1242 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1243 | ||
1244 | if (!obj || !obj->ent) | |
450f30ea | 1245 | return; |
c030f2e4 | 1246 | |
1247 | debugfs_remove(obj->ent); | |
1248 | obj->ent = NULL; | |
1249 | put_obj(obj); | |
c030f2e4 | 1250 | } |
1251 | ||
450f30ea | 1252 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1253 | { |
1254 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1255 | struct ras_manager *obj, *tmp; | |
1256 | ||
1257 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1258 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1259 | } | |
1260 | ||
012dd14d | 1261 | debugfs_remove_recursive(con->dir); |
c030f2e4 | 1262 | con->dir = NULL; |
c030f2e4 | 1263 | } |
1264 | /* debugfs end */ | |
1265 | ||
1266 | /* ras fs */ | |
1267 | ||
1268 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1269 | { | |
c030f2e4 | 1270 | amdgpu_ras_sysfs_create_feature_node(adev); |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1276 | { | |
1277 | amdgpu_ras_debugfs_remove_all(adev); | |
1278 | amdgpu_ras_sysfs_remove_all(adev); | |
1279 | return 0; | |
1280 | } | |
1281 | /* ras fs end */ | |
1282 | ||
1283 | /* ih begin */ | |
1284 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1285 | { | |
1286 | struct ras_ih_data *data = &obj->ih_data; | |
1287 | struct amdgpu_iv_entry entry; | |
1288 | int ret; | |
cf04dfd0 | 1289 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1290 | |
1291 | while (data->rptr != data->wptr) { | |
1292 | rmb(); | |
1293 | memcpy(&entry, &data->ring[data->rptr], | |
1294 | data->element_size); | |
1295 | ||
1296 | wmb(); | |
1297 | data->rptr = (data->aligned_element_size + | |
1298 | data->rptr) % data->ring_size; | |
1299 | ||
1300 | /* Let IP handle its data, maybe we need get the output | |
1301 | * from the callback to udpate the error type/count, etc | |
1302 | */ | |
1303 | if (data->cb) { | |
cf04dfd0 | 1304 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1305 | /* ue will trigger an interrupt, and in that case |
1306 | * we need do a reset to recovery the whole system. | |
1307 | * But leave IP do that recovery, here we just dispatch | |
1308 | * the error. | |
1309 | */ | |
bd2280da | 1310 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1311 | /* these counts could be left as 0 if |
1312 | * some blocks do not count error number | |
1313 | */ | |
cf04dfd0 | 1314 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1315 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1316 | } |
c030f2e4 | 1317 | } |
1318 | } | |
1319 | } | |
1320 | ||
1321 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1322 | { | |
1323 | struct ras_ih_data *data = | |
1324 | container_of(work, struct ras_ih_data, ih_work); | |
1325 | struct ras_manager *obj = | |
1326 | container_of(data, struct ras_manager, ih_data); | |
1327 | ||
1328 | amdgpu_ras_interrupt_handler(obj); | |
1329 | } | |
1330 | ||
1331 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1332 | struct ras_dispatch_if *info) | |
1333 | { | |
1334 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1335 | struct ras_ih_data *data = &obj->ih_data; | |
1336 | ||
1337 | if (!obj) | |
1338 | return -EINVAL; | |
1339 | ||
1340 | if (data->inuse == 0) | |
1341 | return 0; | |
1342 | ||
1343 | /* Might be overflow... */ | |
1344 | memcpy(&data->ring[data->wptr], info->entry, | |
1345 | data->element_size); | |
1346 | ||
1347 | wmb(); | |
1348 | data->wptr = (data->aligned_element_size + | |
1349 | data->wptr) % data->ring_size; | |
1350 | ||
1351 | schedule_work(&data->ih_work); | |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1357 | struct ras_ih_if *info) | |
1358 | { | |
1359 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1360 | struct ras_ih_data *data; | |
1361 | ||
1362 | if (!obj) | |
1363 | return -EINVAL; | |
1364 | ||
1365 | data = &obj->ih_data; | |
1366 | if (data->inuse == 0) | |
1367 | return 0; | |
1368 | ||
1369 | cancel_work_sync(&data->ih_work); | |
1370 | ||
1371 | kfree(data->ring); | |
1372 | memset(data, 0, sizeof(*data)); | |
1373 | put_obj(obj); | |
1374 | ||
1375 | return 0; | |
1376 | } | |
1377 | ||
1378 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1379 | struct ras_ih_if *info) | |
1380 | { | |
1381 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1382 | struct ras_ih_data *data; | |
1383 | ||
1384 | if (!obj) { | |
1385 | /* in case we registe the IH before enable ras feature */ | |
1386 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1387 | if (!obj) | |
1388 | return -EINVAL; | |
1389 | } else | |
1390 | get_obj(obj); | |
1391 | ||
1392 | data = &obj->ih_data; | |
1393 | /* add the callback.etc */ | |
1394 | *data = (struct ras_ih_data) { | |
1395 | .inuse = 0, | |
1396 | .cb = info->cb, | |
1397 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1398 | .rptr = 0, | |
1399 | .wptr = 0, | |
1400 | }; | |
1401 | ||
1402 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1403 | ||
1404 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1405 | /* the ring can store 64 iv entries. */ | |
1406 | data->ring_size = 64 * data->aligned_element_size; | |
1407 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1408 | if (!data->ring) { | |
1409 | put_obj(obj); | |
1410 | return -ENOMEM; | |
1411 | } | |
1412 | ||
1413 | /* IH is ready */ | |
1414 | data->inuse = 1; | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1420 | { | |
1421 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1422 | struct ras_manager *obj, *tmp; | |
1423 | ||
1424 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1425 | struct ras_ih_if info = { | |
1426 | .head = obj->head, | |
1427 | }; | |
1428 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1429 | } | |
1430 | ||
1431 | return 0; | |
1432 | } | |
1433 | /* ih end */ | |
1434 | ||
313c8fd3 GC |
1435 | /* traversal all IPs except NBIO to query error counter */ |
1436 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1437 | { | |
1438 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1439 | struct ras_manager *obj; | |
1440 | ||
1441 | if (!con) | |
1442 | return; | |
1443 | ||
1444 | list_for_each_entry(obj, &con->head, node) { | |
1445 | struct ras_query_if info = { | |
1446 | .head = obj->head, | |
1447 | }; | |
1448 | ||
1449 | /* | |
1450 | * PCIE_BIF IP has one different isr by ras controller | |
1451 | * interrupt, the specific ras counter query will be | |
1452 | * done in that isr. So skip such block from common | |
1453 | * sync flood interrupt isr calling. | |
1454 | */ | |
1455 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1456 | continue; | |
1457 | ||
1458 | amdgpu_ras_error_query(adev, &info); | |
1459 | } | |
1460 | } | |
1461 | ||
c030f2e4 | 1462 | /* recovery begin */ |
466b1793 | 1463 | |
1464 | /* return 0 on success. | |
1465 | * caller need free bps. | |
1466 | */ | |
1467 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1468 | struct ras_badpage **bps, unsigned int *count) | |
1469 | { | |
1470 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1471 | struct ras_err_handler_data *data; | |
1472 | int i = 0; | |
1473 | int ret = 0; | |
1474 | ||
1475 | if (!con || !con->eh_data || !bps || !count) | |
1476 | return -EINVAL; | |
1477 | ||
1478 | mutex_lock(&con->recovery_lock); | |
1479 | data = con->eh_data; | |
1480 | if (!data || data->count == 0) { | |
1481 | *bps = NULL; | |
46cf2fec | 1482 | ret = -EINVAL; |
466b1793 | 1483 | goto out; |
1484 | } | |
1485 | ||
1486 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1487 | if (!*bps) { | |
1488 | ret = -ENOMEM; | |
1489 | goto out; | |
1490 | } | |
1491 | ||
1492 | for (; i < data->count; i++) { | |
1493 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1494 | .bp = data->bps[i].retired_page, |
466b1793 | 1495 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1496 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1497 | }; |
1498 | ||
1499 | if (data->last_reserved <= i) | |
52dd95f2 | 1500 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
9dc23a63 | 1501 | else if (data->bps_bo[i] == NULL) |
52dd95f2 | 1502 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1503 | } |
1504 | ||
1505 | *count = data->count; | |
1506 | out: | |
1507 | mutex_unlock(&con->recovery_lock); | |
1508 | return ret; | |
1509 | } | |
1510 | ||
c030f2e4 | 1511 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1512 | { | |
1513 | struct amdgpu_ras *ras = | |
1514 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1515 | struct amdgpu_device *remote_adev = NULL; |
1516 | struct amdgpu_device *adev = ras->adev; | |
1517 | struct list_head device_list, *device_list_handle = NULL; | |
1518 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false); | |
1519 | ||
1520 | /* Build list of devices to query RAS related errors */ | |
12c17b9d | 1521 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) |
b3dbd6d3 | 1522 | device_list_handle = &hive->device_list; |
12c17b9d GC |
1523 | else { |
1524 | INIT_LIST_HEAD(&device_list); | |
b3dbd6d3 JC |
1525 | list_add_tail(&adev->gmc.xgmi.head, &device_list); |
1526 | device_list_handle = &device_list; | |
1527 | } | |
c030f2e4 | 1528 | |
b3dbd6d3 JC |
1529 | list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) { |
1530 | amdgpu_ras_log_on_err_counter(remote_adev); | |
1531 | } | |
313c8fd3 | 1532 | |
93af20f7 HZ |
1533 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
1534 | amdgpu_device_gpu_recover(ras->adev, 0); | |
c030f2e4 | 1535 | atomic_set(&ras->in_recovery, 0); |
1536 | } | |
1537 | ||
c030f2e4 | 1538 | /* alloc/realloc bps array */ |
1539 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1540 | struct ras_err_handler_data *data, int pages) | |
1541 | { | |
1542 | unsigned int old_space = data->count + data->space_left; | |
1543 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1544 | unsigned int align_space = ALIGN(new_space, 512); |
1545 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1546 | struct amdgpu_bo **bps_bo = | |
1547 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1548 | ||
1549 | if (!bps || !bps_bo) { | |
1550 | kfree(bps); | |
1551 | kfree(bps_bo); | |
c030f2e4 | 1552 | return -ENOMEM; |
9dc23a63 | 1553 | } |
c030f2e4 | 1554 | |
1555 | if (data->bps) { | |
9dc23a63 | 1556 | memcpy(bps, data->bps, |
c030f2e4 | 1557 | data->count * sizeof(*data->bps)); |
1558 | kfree(data->bps); | |
1559 | } | |
9dc23a63 TZ |
1560 | if (data->bps_bo) { |
1561 | memcpy(bps_bo, data->bps_bo, | |
1562 | data->count * sizeof(*data->bps_bo)); | |
1563 | kfree(data->bps_bo); | |
1564 | } | |
c030f2e4 | 1565 | |
9dc23a63 TZ |
1566 | data->bps = bps; |
1567 | data->bps_bo = bps_bo; | |
c030f2e4 | 1568 | data->space_left += align_space - old_space; |
1569 | return 0; | |
1570 | } | |
1571 | ||
1572 | /* it deal with vram only. */ | |
1573 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1574 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1575 | { |
1576 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1577 | struct ras_err_handler_data *data; |
c030f2e4 | 1578 | int ret = 0; |
1579 | ||
73aa8e1a | 1580 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1581 | return 0; |
1582 | ||
1583 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1584 | data = con->eh_data; |
c030f2e4 | 1585 | if (!data) |
1586 | goto out; | |
1587 | ||
1588 | if (data->space_left <= pages) | |
1589 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1590 | ret = -ENOMEM; | |
1591 | goto out; | |
1592 | } | |
1593 | ||
9dc23a63 TZ |
1594 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1595 | data->count += pages; | |
c030f2e4 | 1596 | data->space_left -= pages; |
9dc23a63 | 1597 | |
c030f2e4 | 1598 | out: |
1599 | mutex_unlock(&con->recovery_lock); | |
1600 | ||
1601 | return ret; | |
1602 | } | |
1603 | ||
78ad00c9 TZ |
1604 | /* |
1605 | * write error record array to eeprom, the function should be | |
1606 | * protected by recovery_lock | |
1607 | */ | |
1608 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1609 | { | |
1610 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1611 | struct ras_err_handler_data *data; | |
8a3e801f | 1612 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1613 | int save_count; |
1614 | ||
1615 | if (!con || !con->eh_data) | |
1616 | return 0; | |
1617 | ||
8a3e801f | 1618 | control = &con->eeprom_control; |
78ad00c9 TZ |
1619 | data = con->eh_data; |
1620 | save_count = data->count - control->num_recs; | |
1621 | /* only new entries are saved */ | |
b1628425 | 1622 | if (save_count > 0) { |
0771b0bf | 1623 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1624 | &data->bps[control->num_recs], |
1625 | true, | |
1626 | save_count)) { | |
6952e99c | 1627 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1628 | return -EIO; |
1629 | } | |
1630 | ||
b1628425 GC |
1631 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1632 | } | |
1633 | ||
78ad00c9 TZ |
1634 | return 0; |
1635 | } | |
1636 | ||
1637 | /* | |
1638 | * read error record array in eeprom and reserve enough space for | |
1639 | * storing new bad pages | |
1640 | */ | |
1641 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1642 | { | |
1643 | struct amdgpu_ras_eeprom_control *control = | |
1644 | &adev->psp.ras.ras->eeprom_control; | |
1645 | struct eeprom_table_record *bps = NULL; | |
1646 | int ret = 0; | |
1647 | ||
1648 | /* no bad page record, skip eeprom access */ | |
1649 | if (!control->num_recs) | |
1650 | return ret; | |
1651 | ||
1652 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1653 | if (!bps) | |
1654 | return -ENOMEM; | |
1655 | ||
1656 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1657 | control->num_recs)) { | |
6952e99c | 1658 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1659 | ret = -EIO; |
1660 | goto out; | |
1661 | } | |
1662 | ||
1663 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1664 | ||
1665 | out: | |
1666 | kfree(bps); | |
1667 | return ret; | |
1668 | } | |
1669 | ||
6e4be987 TZ |
1670 | /* |
1671 | * check if an address belongs to bad page | |
1672 | * | |
1673 | * Note: this check is only for umc block | |
1674 | */ | |
1675 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1676 | uint64_t addr) | |
1677 | { | |
1678 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1679 | struct ras_err_handler_data *data; | |
1680 | int i; | |
1681 | bool ret = false; | |
1682 | ||
1683 | if (!con || !con->eh_data) | |
1684 | return ret; | |
1685 | ||
1686 | mutex_lock(&con->recovery_lock); | |
1687 | data = con->eh_data; | |
1688 | if (!data) | |
1689 | goto out; | |
1690 | ||
1691 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1692 | for (i = 0; i < data->count; i++) | |
1693 | if (addr == data->bps[i].retired_page) { | |
1694 | ret = true; | |
1695 | goto out; | |
1696 | } | |
1697 | ||
1698 | out: | |
1699 | mutex_unlock(&con->recovery_lock); | |
1700 | return ret; | |
1701 | } | |
1702 | ||
c84d4670 GC |
1703 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1704 | uint32_t max_length) | |
1705 | { | |
1706 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1707 | int tmp_threshold = amdgpu_bad_page_threshold; | |
1708 | u64 val; | |
1709 | ||
1710 | /* | |
1711 | * Justification of value bad_page_cnt_threshold in ras structure | |
1712 | * | |
1713 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1714 | * in eeprom, and introduce two scenarios accordingly. | |
1715 | * | |
1716 | * Bad page retirement enablement: | |
1717 | * - If amdgpu_bad_page_threshold = -1, | |
1718 | * bad_page_cnt_threshold = typical value by formula. | |
1719 | * | |
1720 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1721 | * max record length in eeprom, use it directly. | |
1722 | * | |
1723 | * Bad page retirement disablement: | |
1724 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1725 | * functionality is disabled, and bad_page_cnt_threshold will | |
1726 | * take no effect. | |
1727 | */ | |
1728 | ||
1729 | if (tmp_threshold < -1) | |
1730 | tmp_threshold = -1; | |
1731 | else if (tmp_threshold > max_length) | |
1732 | tmp_threshold = max_length; | |
1733 | ||
1734 | if (tmp_threshold == -1) { | |
1735 | val = adev->gmc.mc_vram_size; | |
1736 | do_div(val, RAS_BAD_PAGE_RATE); | |
1737 | con->bad_page_cnt_threshold = min(lower_32_bits(val), | |
1738 | max_length); | |
1739 | } else { | |
1740 | con->bad_page_cnt_threshold = tmp_threshold; | |
1741 | } | |
1742 | } | |
1743 | ||
c030f2e4 | 1744 | /* called in gpu recovery/init */ |
1745 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1746 | { | |
1747 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1748 | struct ras_err_handler_data *data; |
c030f2e4 | 1749 | uint64_t bp; |
de7b45ba | 1750 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1751 | int i, ret = 0; |
c030f2e4 | 1752 | |
73aa8e1a | 1753 | if (!con || !con->eh_data) |
c030f2e4 | 1754 | return 0; |
1755 | ||
1756 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1757 | data = con->eh_data; |
1758 | if (!data) | |
1759 | goto out; | |
c030f2e4 | 1760 | /* reserve vram at driver post stage. */ |
1761 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1762 | bp = data->bps[i].retired_page; |
c030f2e4 | 1763 | |
ae115c81 TZ |
1764 | /* There are two cases of reserve error should be ignored: |
1765 | * 1) a ras bad page has been allocated (used by someone); | |
1766 | * 2) a ras bad page has been reserved (duplicate error injection | |
1767 | * for one page); | |
1768 | */ | |
a142ba88 AD |
1769 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, |
1770 | AMDGPU_GPU_PAGE_SIZE, | |
de7b45ba CK |
1771 | AMDGPU_GEM_DOMAIN_VRAM, |
1772 | &bo, NULL)) | |
6952e99c GC |
1773 | dev_warn(adev->dev, "RAS WARN: reserve vram for " |
1774 | "retired page %llx fail\n", bp); | |
c030f2e4 | 1775 | |
9dc23a63 | 1776 | data->bps_bo[i] = bo; |
c030f2e4 | 1777 | data->last_reserved = i + 1; |
de7b45ba | 1778 | bo = NULL; |
c030f2e4 | 1779 | } |
78ad00c9 TZ |
1780 | |
1781 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1782 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1783 | out: |
c030f2e4 | 1784 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1785 | return ret; |
c030f2e4 | 1786 | } |
1787 | ||
1788 | /* called when driver unload */ | |
1789 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1790 | { | |
1791 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1792 | struct ras_err_handler_data *data; |
c030f2e4 | 1793 | struct amdgpu_bo *bo; |
1794 | int i; | |
1795 | ||
73aa8e1a | 1796 | if (!con || !con->eh_data) |
c030f2e4 | 1797 | return 0; |
1798 | ||
1799 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1800 | data = con->eh_data; |
1801 | if (!data) | |
1802 | goto out; | |
1803 | ||
c030f2e4 | 1804 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1805 | bo = data->bps_bo[i]; |
c030f2e4 | 1806 | |
de7b45ba | 1807 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1808 | |
9dc23a63 | 1809 | data->bps_bo[i] = bo; |
c030f2e4 | 1810 | data->last_reserved = i; |
1811 | } | |
73aa8e1a | 1812 | out: |
c030f2e4 | 1813 | mutex_unlock(&con->recovery_lock); |
1814 | return 0; | |
1815 | } | |
1816 | ||
1a6fc071 | 1817 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1818 | { |
1819 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1820 | struct ras_err_handler_data **data; |
c84d4670 | 1821 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1822 | bool exc_err_limit = false; |
78ad00c9 | 1823 | int ret; |
c030f2e4 | 1824 | |
4d1337d2 AG |
1825 | if (con) |
1826 | data = &con->eh_data; | |
1827 | else | |
1828 | return 0; | |
1829 | ||
1a6fc071 TZ |
1830 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1831 | if (!*data) { | |
1832 | ret = -ENOMEM; | |
1833 | goto out; | |
1834 | } | |
c030f2e4 | 1835 | |
1836 | mutex_init(&con->recovery_lock); | |
1837 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1838 | atomic_set(&con->in_recovery, 0); | |
1839 | con->adev = adev; | |
1840 | ||
c84d4670 GC |
1841 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1842 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
1843 | ||
b82e65a9 GC |
1844 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1845 | /* | |
1846 | * This calling fails when exc_err_limit is true or | |
1847 | * ret != 0. | |
1848 | */ | |
1849 | if (exc_err_limit || ret) | |
1a6fc071 | 1850 | goto free; |
78ad00c9 | 1851 | |
0771b0bf | 1852 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1853 | ret = amdgpu_ras_load_bad_pages(adev); |
1854 | if (ret) | |
1a6fc071 | 1855 | goto free; |
78ad00c9 TZ |
1856 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1857 | if (ret) | |
1a6fc071 | 1858 | goto release; |
78ad00c9 | 1859 | } |
c030f2e4 | 1860 | |
1861 | return 0; | |
1a6fc071 TZ |
1862 | |
1863 | release: | |
1864 | amdgpu_ras_release_bad_pages(adev); | |
1865 | free: | |
1a6fc071 TZ |
1866 | kfree((*data)->bps); |
1867 | kfree((*data)->bps_bo); | |
1868 | kfree(*data); | |
1995b3a3 | 1869 | con->eh_data = NULL; |
1a6fc071 | 1870 | out: |
6952e99c | 1871 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1872 | |
b82e65a9 GC |
1873 | /* |
1874 | * Except error threshold exceeding case, other failure cases in this | |
1875 | * function would not fail amdgpu driver init. | |
1876 | */ | |
1877 | if (!exc_err_limit) | |
1878 | ret = 0; | |
1879 | else | |
1880 | ret = -EINVAL; | |
1881 | ||
1a6fc071 | 1882 | return ret; |
c030f2e4 | 1883 | } |
1884 | ||
1885 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1886 | { | |
1887 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1888 | struct ras_err_handler_data *data = con->eh_data; | |
1889 | ||
1a6fc071 TZ |
1890 | /* recovery_init failed to init it, fini is useless */ |
1891 | if (!data) | |
1892 | return 0; | |
1893 | ||
c030f2e4 | 1894 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1895 | amdgpu_ras_release_bad_pages(adev); |
1896 | ||
1897 | mutex_lock(&con->recovery_lock); | |
1898 | con->eh_data = NULL; | |
1899 | kfree(data->bps); | |
1a6fc071 | 1900 | kfree(data->bps_bo); |
c030f2e4 | 1901 | kfree(data); |
1902 | mutex_unlock(&con->recovery_lock); | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | /* recovery end */ | |
1907 | ||
a564808e | 1908 | /* return 0 if ras will reset gpu and repost.*/ |
1909 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1910 | unsigned int block) | |
1911 | { | |
1912 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1913 | ||
1914 | if (!ras) | |
1915 | return -EINVAL; | |
1916 | ||
1917 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1918 | return 0; | |
1919 | } | |
1920 | ||
5caf466a | 1921 | /* |
1922 | * check hardware's ras ability which will be saved in hw_supported. | |
1923 | * if hardware does not support ras, we can skip some ras initializtion and | |
1924 | * forbid some ras operations from IP. | |
1925 | * if software itself, say boot parameter, limit the ras ability. We still | |
1926 | * need allow IP do some limited operations, like disable. In such case, | |
1927 | * we have to initialize ras as normal. but need check if operation is | |
1928 | * allowed or not in each function. | |
1929 | */ | |
1930 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1931 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1932 | { |
5caf466a | 1933 | *hw_supported = 0; |
1934 | *supported = 0; | |
c030f2e4 | 1935 | |
88474cca | 1936 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
baaeb610 HZ |
1937 | (adev->asic_type != CHIP_VEGA20 && |
1938 | adev->asic_type != CHIP_ARCTURUS)) | |
5caf466a | 1939 | return; |
b404ae82 | 1940 | |
88474cca | 1941 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
6952e99c | 1942 | dev_info(adev->dev, "HBM ECC is active.\n"); |
88474cca GC |
1943 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | |
1944 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1945 | } else | |
6952e99c | 1946 | dev_info(adev->dev, "HBM ECC is not presented.\n"); |
88474cca GC |
1947 | |
1948 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
6952e99c | 1949 | dev_info(adev->dev, "SRAM ECC is active.\n"); |
88474cca GC |
1950 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
1951 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1952 | } else | |
6952e99c | 1953 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); |
88474cca GC |
1954 | |
1955 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1956 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1957 | |
5caf466a | 1958 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1959 | 0 : *hw_supported & amdgpu_ras_mask; |
c030f2e4 | 1960 | } |
1961 | ||
1962 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1963 | { | |
1964 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1965 | int r; |
c030f2e4 | 1966 | |
b404ae82 | 1967 | if (con) |
c030f2e4 | 1968 | return 0; |
1969 | ||
1970 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1971 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1972 | GFP_KERNEL|__GFP_ZERO); | |
1973 | if (!con) | |
1974 | return -ENOMEM; | |
1975 | ||
1976 | con->objs = (struct ras_manager *)(con + 1); | |
1977 | ||
1978 | amdgpu_ras_set_context(adev, con); | |
1979 | ||
5caf466a | 1980 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1981 | &con->supported); | |
fb2a3607 | 1982 | if (!con->hw_supported) { |
5e91160a GC |
1983 | r = 0; |
1984 | goto err_out; | |
fb2a3607 HZ |
1985 | } |
1986 | ||
c030f2e4 | 1987 | con->features = 0; |
1988 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1989 | /* Might need get this flag from vbios. */ |
1990 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1991 | |
4e644fff HZ |
1992 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1993 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1994 | if (r) | |
5e91160a | 1995 | goto err_out; |
4e644fff HZ |
1996 | } |
1997 | ||
1998 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1999 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
2000 | if (r) | |
5e91160a | 2001 | goto err_out; |
4e644fff HZ |
2002 | } |
2003 | ||
5e91160a GC |
2004 | if (amdgpu_ras_fs_init(adev)) { |
2005 | r = -EINVAL; | |
2006 | goto err_out; | |
2007 | } | |
c030f2e4 | 2008 | |
6952e99c | 2009 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 2010 | "hardware ability[%x] ras_mask[%x]\n", |
2011 | con->hw_supported, con->supported); | |
c030f2e4 | 2012 | return 0; |
5e91160a | 2013 | err_out: |
c030f2e4 | 2014 | amdgpu_ras_set_context(adev, NULL); |
2015 | kfree(con); | |
2016 | ||
5e91160a | 2017 | return r; |
c030f2e4 | 2018 | } |
2019 | ||
b293e891 HZ |
2020 | /* helper function to handle common stuff in ip late init phase */ |
2021 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2022 | struct ras_common_if *ras_block, | |
2023 | struct ras_fs_if *fs_info, | |
2024 | struct ras_ih_if *ih_info) | |
2025 | { | |
2026 | int r; | |
2027 | ||
2028 | /* disable RAS feature per IP block if it is not supported */ | |
2029 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2030 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2031 | return 0; | |
2032 | } | |
2033 | ||
2034 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2035 | if (r) { | |
2036 | if (r == -EAGAIN) { | |
2037 | /* request gpu reset. will run again */ | |
2038 | amdgpu_ras_request_reset_on_boot(adev, | |
2039 | ras_block->block); | |
2040 | return 0; | |
df9c8d1a | 2041 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2042 | /* in resume phase, if fail to enable ras, |
2043 | * clean up all ras fs nodes, and disable ras */ | |
2044 | goto cleanup; | |
2045 | } else | |
2046 | return r; | |
2047 | } | |
2048 | ||
2049 | /* in resume phase, no need to create ras fs node */ | |
df9c8d1a | 2050 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2051 | return 0; |
2052 | ||
2053 | if (ih_info->cb) { | |
2054 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2055 | if (r) | |
2056 | goto interrupt; | |
2057 | } | |
2058 | ||
b293e891 HZ |
2059 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2060 | if (r) | |
2061 | goto sysfs; | |
2062 | ||
2063 | return 0; | |
2064 | cleanup: | |
2065 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2066 | sysfs: | |
b293e891 HZ |
2067 | if (ih_info->cb) |
2068 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2069 | interrupt: | |
2070 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2071 | return r; | |
2072 | } | |
2073 | ||
2074 | /* helper function to remove ras fs node and interrupt handler */ | |
2075 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2076 | struct ras_common_if *ras_block, | |
2077 | struct ras_ih_if *ih_info) | |
2078 | { | |
2079 | if (!ras_block || !ih_info) | |
2080 | return; | |
2081 | ||
2082 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 HZ |
2083 | if (ih_info->cb) |
2084 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2085 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2086 | } | |
2087 | ||
a564808e | 2088 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2089 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2090 | */ |
511fdbc3 | 2091 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2092 | { |
2093 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2094 | struct ras_manager *obj, *tmp; | |
2095 | ||
2096 | if (!con) | |
2097 | return; | |
2098 | ||
108c6a63 | 2099 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2100 | /* Set up all other IPs which are not implemented. There is a |
2101 | * tricky thing that IP's actual ras error type should be | |
2102 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2103 | * ERROR_NONE make sense anyway. | |
2104 | */ | |
2105 | amdgpu_ras_enable_all_features(adev, 1); | |
2106 | ||
2107 | /* We enable ras on all hw_supported block, but as boot | |
2108 | * parameter might disable some of them and one or more IP has | |
2109 | * not implemented yet. So we disable them on behalf. | |
2110 | */ | |
108c6a63 | 2111 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2112 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2113 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2114 | /* there should be no any reference. */ | |
2115 | WARN_ON(alive_obj(obj)); | |
2116 | } | |
191051a1 | 2117 | } |
108c6a63 | 2118 | } |
a564808e | 2119 | |
2120 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2121 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2122 | /* setup ras obj state as disabled. | |
2123 | * for init_by_vbios case. | |
2124 | * if we want to enable ras, just enable it in a normal way. | |
2125 | * If we want do disable it, need setup ras obj as enabled, | |
2126 | * then issue another TA disable cmd. | |
2127 | * See feature_enable_on_boot | |
2128 | */ | |
2129 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2130 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2131 | } |
108c6a63 | 2132 | } |
2133 | ||
511fdbc3 | 2134 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2135 | { | |
2136 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2137 | ||
2138 | if (!con) | |
2139 | return; | |
2140 | ||
2141 | amdgpu_ras_disable_all_features(adev, 0); | |
2142 | /* Make sure all ras objects are disabled. */ | |
2143 | if (con->features) | |
2144 | amdgpu_ras_disable_all_features(adev, 1); | |
2145 | } | |
2146 | ||
c030f2e4 | 2147 | /* do some fini work before IP fini as dependence */ |
2148 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2149 | { | |
2150 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2151 | ||
2152 | if (!con) | |
2153 | return 0; | |
2154 | ||
2155 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2156 | amdgpu_ras_disable_all_features(adev, 0); | |
2157 | amdgpu_ras_recovery_fini(adev); | |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2162 | { | |
2163 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2164 | ||
2165 | if (!con) | |
2166 | return 0; | |
2167 | ||
2168 | amdgpu_ras_fs_fini(adev); | |
2169 | amdgpu_ras_interrupt_remove_all(adev); | |
2170 | ||
2171 | WARN(con->features, "Feature mask is not cleared"); | |
2172 | ||
2173 | if (con->features) | |
2174 | amdgpu_ras_disable_all_features(adev, 1); | |
2175 | ||
2176 | amdgpu_ras_set_context(adev, NULL); | |
2177 | kfree(con); | |
2178 | ||
2179 | return 0; | |
2180 | } | |
7c6e68c7 AG |
2181 | |
2182 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2183 | { | |
ed606f8a AG |
2184 | uint32_t hw_supported, supported; |
2185 | ||
2186 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2187 | if (!hw_supported) | |
2188 | return; | |
2189 | ||
7c6e68c7 | 2190 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2191 | dev_info(adev->dev, "uncorrectable hardware error" |
2192 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2193 | |
61934624 | 2194 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2195 | } |
2196 | } | |
bb5c7235 WS |
2197 | |
2198 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2199 | { | |
2200 | if (adev->asic_type == CHIP_VEGA20 && | |
2201 | adev->pm.fw_version <= 0x283400) { | |
2202 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2203 | amdgpu_ras_intr_triggered(); | |
2204 | } | |
2205 | ||
2206 | return false; | |
2207 | } | |
e8fbaf03 GC |
2208 | |
2209 | bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev) | |
2210 | { | |
2211 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2212 | bool exc_err_limit = false; | |
2213 | ||
2214 | if (con && (amdgpu_bad_page_threshold != 0)) | |
2215 | amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control, | |
2216 | &exc_err_limit); | |
2217 | ||
2218 | /* | |
2219 | * We are only interested in variable exc_err_limit, | |
2220 | * as it says if GPU is in bad state or not. | |
2221 | */ | |
2222 | return exc_err_limit; | |
2223 | } |