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drm/buddy: Fix drm buddy info output format
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c
CommitLineData
c030f2e4 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
f867723b 27#include <linux/uaccess.h>
7c6e68c7
AG		 28#include <linux/reboot.h>
29#include <linux/syscalls.h>
05adfd80 30#include <linux/pm_runtime.h>
f867723b 31
c030f2e4 32#include "amdgpu.h"
33#include "amdgpu_ras.h"
b404ae82 34#include "amdgpu_atomfirmware.h"
19744f5f 35#include "amdgpu_xgmi.h"
4e644fff 36#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
9af357bc 37#include "nbio_v4_3.h"
7692e1ee 38#include "nbio_v7_9.h"
f50160cf 39#include "atom.h"
25a2b22e
AG		 40#include "amdgpu_reset.h"
41
12b2cab7
MJ		 42#ifdef CONFIG_X86_MCE_AMD
43#include <asm/mce.h>
c030f2e4 44
12b2cab7
MJ		 45static bool notifier_registered;
46#endif
eb0c3cd4
GC		 47static const char *RAS_FS_NAME = "ras";
48
c030f2e4 49const char *ras_error_string[] = {
50 "none",
51 "parity",
52 "single_correctable",
53 "multi_uncorrectable",
54 "poison",
55};
56
57const char *ras_block_string[] = {
58 "umc",
59 "sdma",
60 "gfx",
61 "mmhub",
62 "athub",
63 "pcie_bif",
64 "hdp",
65 "xgmi_wafl",
66 "df",
67 "smn",
68 "sem",
69 "mp0",
70 "mp1",
71 "fuse",
640ae42e 72 "mca",
a3d63c62
MZZ		 73 "vcn",
74 "jpeg",
c030f2e4 75};
76
640ae42e
JC		 77const char *ras_mca_block_string[] = {
78 "mca_mp0",
79 "mca_mp1",
80 "mca_mpio",
81 "mca_iohc",
82};
83
d5e8ff5f 84struct amdgpu_ras_block_list {
85 /* ras block link */
86 struct list_head node;
87
88 struct amdgpu_ras_block_object *ras_obj;
89};
90
640ae42e
JC		 91const char *get_ras_block_str(struct ras_common_if *ras_block)
92{
93 if (!ras_block)
94 return "NULL";
95
96 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
97 return "OUT OF RANGE";
98
99 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
100 return ras_mca_block_string[ras_block->sub_block_index];
101
102 return ras_block_string[ras_block->block];
103}
104
954ea6aa 105#define ras_block_str(_BLOCK_) \
106 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
8b0fb0e9 107
c030f2e4 108#define ras_err_str(i) (ras_error_string[ffs(i)])
c030f2e4 109
108c6a63 110#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
111
7cdc2ee3
TZ		 112/* inject address is 52 bits */
113#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
114
e4e6a589
LT		 115/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
116#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
c84d4670 117
52dd95f2
GC		 118enum amdgpu_ras_retire_page_reservation {
119 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
120 AMDGPU_RAS_RETIRE_PAGE_PENDING,
121 AMDGPU_RAS_RETIRE_PAGE_FAULT,
122};
7c6e68c7
AG		 123
124atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
125
676deb38
DL		 126static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
127 uint64_t addr);
6e4be987
TZ		 128static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
129 uint64_t addr);
12b2cab7 130#ifdef CONFIG_X86_MCE_AMD
91a1a52d
MJ		 131static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
132struct mce_notifier_adev_list {
133 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
134 int num_gpu;
135};
136static struct mce_notifier_adev_list mce_adev_list;
12b2cab7 137#endif
6e4be987 138
61380faa
JC		 139void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
140{
a9d82d2f 141 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 142 amdgpu_ras_get_context(adev)->error_query_ready = ready;
143}
144
f3167919 145static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
61380faa 146{
a9d82d2f 147 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 148 return amdgpu_ras_get_context(adev)->error_query_ready;
149
150 return false;
151}
152
cbb8f989
JC		 153static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
154{
155 struct ras_err_data err_data = {0, 0, 0, NULL};
156 struct eeprom_table_record err_rec;
157
158 if ((address >= adev->gmc.mc_vram_size) ||
159 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
160 dev_warn(adev->dev,
161 "RAS WARN: input address 0x%llx is invalid.\n",
162 address);
163 return -EINVAL;
164 }
165
166 if (amdgpu_ras_check_bad_page(adev, address)) {
167 dev_warn(adev->dev,
80b0cd0f 168 "RAS WARN: 0x%llx has already been marked as bad page!\n",
cbb8f989
JC		 169 address);
170 return 0;
171 }
172
173 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
cbb8f989 174 err_data.err_addr = &err_rec;
71344a71 175 amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);
cbb8f989
JC		 176
177 if (amdgpu_bad_page_threshold != 0) {
178 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
179 err_data.err_addr_cnt);
4d33e0f1 180 amdgpu_ras_save_bad_pages(adev, NULL);
cbb8f989
JC		 181 }
182
183 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
184 dev_warn(adev->dev, "Clear EEPROM:\n");
185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
186
187 return 0;
188}
189
c030f2e4 190static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
191 size_t size, loff_t *pos)
192{
193 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
194 struct ras_query_if info = {
195 .head = obj->head,
196 };
197 ssize_t s;
198 char val[128];
199
761d86d3 200 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 201 return -EINVAL;
202
2a460963
CL		 203 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
204 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
205 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
206 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
207 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
208 }
209
c030f2e4 210 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
211 "ue", info.ue_count,
212 "ce", info.ce_count);
213 if (*pos >= s)
214 return 0;
215
216 s -= *pos;
217 s = min_t(u64, s, size);
218
219
220 if (copy_to_user(buf, &val[*pos], s))
221 return -EINVAL;
222
223 *pos += s;
224
225 return s;
226}
227
c030f2e4 228static const struct file_operations amdgpu_ras_debugfs_ops = {
229 .owner = THIS_MODULE,
230 .read = amdgpu_ras_debugfs_read,
190211ab 231 .write = NULL,
c030f2e4 232 .llseek = default_llseek
233};
234
96ebb307 235static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
236{
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
240 *block_id = i;
640ae42e 241 if (strcmp(name, ras_block_string[i]) == 0)
96ebb307 242 return 0;
243 }
244 return -EINVAL;
245}
246
247static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
248 const char __user *buf, size_t size,
249 loff_t *pos, struct ras_debug_if *data)
250{
251 ssize_t s = min_t(u64, 64, size);
252 char str[65];
253 char block_name[33];
254 char err[9] = "ue";
255 int op = -1;
256 int block_id;
44494f96 257 uint32_t sub_block;
96ebb307 258 u64 address, value;
2c22ed0b
TZ		 259 /* default value is 0 if the mask is not set by user */
260 u32 instance_mask = 0;
96ebb307 261
262 if (*pos)
263 return -EINVAL;
264 *pos = size;
265
266 memset(str, 0, sizeof(str));
267 memset(data, 0, sizeof(*data));
268
269 if (copy_from_user(str, buf, s))
270 return -EINVAL;
271
272 if (sscanf(str, "disable %32s", block_name) == 1)
273 op = 0;
274 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
275 op = 1;
276 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
277 op = 2;
6df23f4c 278 else if (strstr(str, "retire_page") != NULL)
cbb8f989 279 op = 3;
b076296b 280 else if (str[0] && str[1] && str[2] && str[3])
96ebb307 281 /* ascii string, but commands are not matched. */
282 return -EINVAL;
283
284 if (op != -1) {
cbb8f989 285 if (op == 3) {
546aa546
LT		 286 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
287 sscanf(str, "%*s %llu", &address) != 1)
6cb7a1d4 288 return -EINVAL;
cbb8f989
JC		 289
290 data->op = op;
291 data->inject.address = address;
292
293 return 0;
294 }
295
96ebb307 296 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
297 return -EINVAL;
298
299 data->head.block = block_id;
e1063493
TZ		 300 /* only ue and ce errors are supported */
301 if (!memcmp("ue", err, 2))
302 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
303 else if (!memcmp("ce", err, 2))
304 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
305 else
306 return -EINVAL;
307
96ebb307 308 data->op = op;
309
310 if (op == 2) {
2c22ed0b
TZ		 311 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
312 &sub_block, &address, &value, &instance_mask) != 4 &&
313 sscanf(str, "%*s %*s %*s %u %llu %llu %u",
314 &sub_block, &address, &value, &instance_mask) != 4 &&
315 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
546aa546
LT		 316 &sub_block, &address, &value) != 3 &&
317 sscanf(str, "%*s %*s %*s %u %llu %llu",
6cb7a1d4
LT		 318 &sub_block, &address, &value) != 3)
319 return -EINVAL;
44494f96 320 data->head.sub_block_index = sub_block;
96ebb307 321 data->inject.address = address;
322 data->inject.value = value;
2c22ed0b 323 data->inject.instance_mask = instance_mask;
96ebb307 324 }
325 } else {
73aa8e1a 326 if (size < sizeof(*data))
96ebb307 327 return -EINVAL;
328
329 if (copy_from_user(data, buf, sizeof(*data)))
330 return -EINVAL;
331 }
332
333 return 0;
334}
7c6e68c7 335
f464c5dd
TZ		 336static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
337 struct ras_debug_if *data)
338{
339 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
340 uint32_t mask, inst_mask = data->inject.instance_mask;
341
342 /* no need to set instance mask if there is only one instance */
343 if (num_xcc <= 1 && inst_mask) {
344 data->inject.instance_mask = 0;
345 dev_dbg(adev->dev,
346 "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
347 inst_mask);
348
349 return;
350 }
351
352 switch (data->head.block) {
353 case AMDGPU_RAS_BLOCK__GFX:
354 mask = GENMASK(num_xcc - 1, 0);
355 break;
356 case AMDGPU_RAS_BLOCK__SDMA:
357 mask = GENMASK(adev->sdma.num_instances - 1, 0);
358 break;
e3959cb5
SY		 359 case AMDGPU_RAS_BLOCK__VCN:
360 case AMDGPU_RAS_BLOCK__JPEG:
361 mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0);
362 break;
f464c5dd 363 default:
e3959cb5 364 mask = inst_mask;
f464c5dd
TZ		 365 break;
366 }
367
368 /* remove invalid bits in instance mask */
369 data->inject.instance_mask &= mask;
370 if (inst_mask != data->inject.instance_mask)
371 dev_dbg(adev->dev,
372 "Adjust RAS inject mask 0x%x to 0x%x\n",
373 inst_mask, data->inject.instance_mask);
374}
375
74abc221
TSD		 376/**
377 * DOC: AMDGPU RAS debugfs control interface
36ea1bd2 378 *
737c375b 379 * The control interface accepts struct ras_debug_if which has two members.
36ea1bd2 380 *
381 * First member: ras_debug_if::head or ras_debug_if::inject.
96ebb307 382 *
383 * head is used to indicate which IP block will be under control.
36ea1bd2 384 *
385 * head has four members, they are block, type, sub_block_index, name.
386 * block: which IP will be under control.
387 * type: what kind of error will be enabled/disabled/injected.
388 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
389 * name: the name of IP.
390 *
2c22ed0b 391 * inject has three more members than head, they are address, value and mask.
36ea1bd2 392 * As their names indicate, inject operation will write the
393 * value to the address.
394 *
ef177d11 395 * The second member: struct ras_debug_if::op.
c688a06b 396 * It has three kinds of operations.
879e723d
AZ		 397 *
398 * - 0: disable RAS on the block. Take ::head as its data.
399 * - 1: enable RAS on the block. Take ::head as its data.
400 * - 2: inject errors on the block. Take ::inject as its data.
36ea1bd2 401 *
96ebb307 402 * How to use the interface?
ef177d11 403 *
737c375b 404 * In a program
ef177d11 405 *
737c375b
LT		 406 * Copy the struct ras_debug_if in your code and initialize it.
407 * Write the struct to the control interface.
ef177d11 408 *
737c375b 409 * From shell
96ebb307 410 *
879e723d
AZ		 411 * .. code-block:: bash
412 *
737c375b
LT		 413 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
414 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
2c22ed0b 415 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
879e723d 416 *
737c375b 417 * Where N, is the card which you want to affect.
ef177d11 418 *
737c375b
LT		 419 * "disable" requires only the block.
420 * "enable" requires the block and error type.
421 * "inject" requires the block, error type, address, and value.
c666bbf0 422 *
737c375b 423 * The block is one of: umc, sdma, gfx, etc.
879e723d 424 * see ras_block_string[] for details
c666bbf0 425 *
737c375b
LT		 426 * The error type is one of: ue, ce, where,
427 * ue is multi-uncorrectable
428 * ce is single-correctable
c666bbf0 429 *
737c375b
LT		 430 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
431 * The address and value are hexadecimal numbers, leading 0x is optional.
2c22ed0b 432 * The mask means instance mask, is optional, default value is 0x1.
879e723d 433 *
737c375b 434 * For instance,
879e723d
AZ		 435 *
436 * .. code-block:: bash
96ebb307 437 *
44494f96 438 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
2c22ed0b 439 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
96ebb307 440 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
441 *
737c375b 442 * How to check the result of the operation?
36ea1bd2 443 *
737c375b 444 * To check disable/enable, see "ras" features at,
36ea1bd2 445 * /sys/class/drm/card[0/1/2...]/device/ras/features
446 *
737c375b
LT		 447 * To check inject, see the corresponding error count at,
448 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
36ea1bd2 449 *
879e723d 450 * .. note::
ef177d11 451 * Operations are only allowed on blocks which are supported.
737c375b 452 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
ef177d11
AD		 453 * to see which blocks support RAS on a particular asic.
454 *
36ea1bd2 455 */
cf696091
LT		 456static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
457 const char __user *buf,
458 size_t size, loff_t *pos)
36ea1bd2 459{
460 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
461 struct ras_debug_if data;
462 int ret = 0;
463
61380faa 464 if (!amdgpu_ras_get_error_query_ready(adev)) {
6952e99c
GC		 465 dev_warn(adev->dev, "RAS WARN: error injection "
466 "currently inaccessible\n");
43c4d576
JC		 467 return size;
468 }
469
96ebb307 470 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
471 if (ret)
cf696091 472 return ret;
36ea1bd2 473
80b0cd0f 474 if (data.op == 3) {
cbb8f989 475 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
80b0cd0f 476 if (!ret)
cbb8f989
JC		 477 return size;
478 else
479 return ret;
480 }
481
36ea1bd2 482 if (!amdgpu_ras_is_supported(adev, data.head.block))
483 return -EINVAL;
484
485 switch (data.op) {
486 case 0:
487 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
488 break;
489 case 1:
490 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
491 break;
492 case 2:
43aedbf4
SY		 493 if ((data.inject.address >= adev->gmc.mc_vram_size &&
494 adev->gmc.mc_vram_size) ||
7cdc2ee3 495 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
b0d4783a
GC		 496 dev_warn(adev->dev, "RAS WARN: input address "
497 "0x%llx is invalid.",
498 data.inject.address);
7cdc2ee3
TZ		 499 ret = -EINVAL;
500 break;
501 }
502
6e4be987
TZ		 503 /* umc ce/ue error injection for a bad page is not allowed */
504 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
505 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
c65b0805
LT		 506 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
507 "already been marked as bad!\n",
508 data.inject.address);
6e4be987
TZ		 509 break;
510 }
511
f464c5dd
TZ		 512 amdgpu_ras_instance_mask_check(adev, &data);
513
7cdc2ee3 514 /* data.inject.address is offset instead of absolute gpu address */
36ea1bd2 515 ret = amdgpu_ras_error_inject(adev, &data.inject);
516 break;
96ebb307 517 default:
518 ret = -EINVAL;
519 break;
374bf7bd 520 }
36ea1bd2 521
522 if (ret)
79c04621 523 return ret;
36ea1bd2 524
525 return size;
526}
527
084fe13b
AG		 528/**
529 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
530 *
f77c7109 531 * Some boards contain an EEPROM which is used to persistently store a list of
ef177d11 532 * bad pages which experiences ECC errors in vram. This interface provides
f77c7109
AD		 533 * a way to reset the EEPROM, e.g., after testing error injection.
534 *
535 * Usage:
536 *
537 * .. code-block:: bash
538 *
539 * echo 1 > ../ras/ras_eeprom_reset
540 *
541 * will reset EEPROM table to 0 entries.
542 *
084fe13b 543 */
cf696091
LT		 544static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
545 const char __user *buf,
546 size_t size, loff_t *pos)
084fe13b 547{
bf0b91b7
GC		 548 struct amdgpu_device *adev =
549 (struct amdgpu_device *)file_inode(f)->i_private;
084fe13b
AG		 550 int ret;
551
bf0b91b7 552 ret = amdgpu_ras_eeprom_reset_table(
cf696091 553 &(amdgpu_ras_get_context(adev)->eeprom_control));
084fe13b 554
63d4c081 555 if (!ret) {
cf696091
LT		 556 /* Something was written to EEPROM.
557 */
bf0b91b7
GC		 558 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
559 return size;
560 } else {
cf696091 561 return ret;
bf0b91b7 562 }
084fe13b
AG		 563}
564
36ea1bd2 565static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
566 .owner = THIS_MODULE,
567 .read = NULL,
568 .write = amdgpu_ras_debugfs_ctrl_write,
569 .llseek = default_llseek
570};
571
084fe13b
AG		 572static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
573 .owner = THIS_MODULE,
574 .read = NULL,
575 .write = amdgpu_ras_debugfs_eeprom_write,
576 .llseek = default_llseek
577};
578
f77c7109
AD		 579/**
580 * DOC: AMDGPU RAS sysfs Error Count Interface
581 *
ef177d11 582 * It allows the user to read the error count for each IP block on the gpu through
f77c7109
AD		 583 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
584 *
585 * It outputs the multiple lines which report the uncorrected (ue) and corrected
586 * (ce) error counts.
587 *
588 * The format of one line is below,
589 *
590 * [ce|ue]: count
591 *
592 * Example:
593 *
594 * .. code-block:: bash
595 *
596 * ue: 0
597 * ce: 1
598 *
599 */
c030f2e4 600static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
601 struct device_attribute *attr, char *buf)
602{
603 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
604 struct ras_query_if info = {
605 .head = obj->head,
606 };
607
61380faa 608 if (!amdgpu_ras_get_error_query_ready(obj->adev))
36000c7a 609 return sysfs_emit(buf, "Query currently inaccessible\n");
43c4d576 610
761d86d3 611 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 612 return -EINVAL;
613
2a460963
CL		 614 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
615 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1f0d8e37 616 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
2a460963 617 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
1f0d8e37
MJ		 618 }
619
36000c7a
TT		 620 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
621 "ce", info.ce_count);
c030f2e4 622}
623
624/* obj begin */
625
626#define get_obj(obj) do { (obj)->use++; } while (0)
627#define alive_obj(obj) ((obj)->use)
628
629static inline void put_obj(struct ras_manager *obj)
630{
f0872686 631 if (obj && (--obj->use == 0))
c030f2e4 632 list_del(&obj->node);
f0872686 633 if (obj && (obj->use < 0))
640ae42e 634 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
c030f2e4 635}
636
637/* make one obj and return it. */
638static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
639 struct ras_common_if *head)
640{
641 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
642 struct ras_manager *obj;
643
8ab0d6f0 644 if (!adev->ras_enabled || !con)
c030f2e4 645 return NULL;
646
647 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
648 return NULL;
649
640ae42e
JC		 650 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
651 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
652 return NULL;
653
654 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
655 } else
656 obj = &con->objs[head->block];
657
c030f2e4 658 /* already exist. return obj? */
659 if (alive_obj(obj))
660 return NULL;
661
662 obj->head = *head;
663 obj->adev = adev;
664 list_add(&obj->node, &con->head);
665 get_obj(obj);
666
667 return obj;
668}
669
670/* return an obj equal to head, or the first when head is NULL */
f2a79be1 671struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
c030f2e4 672 struct ras_common_if *head)
673{
674 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
675 struct ras_manager *obj;
676 int i;
677
8ab0d6f0 678 if (!adev->ras_enabled || !con)
c030f2e4 679 return NULL;
680
681 if (head) {
682 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
683 return NULL;
684
640ae42e
JC		 685 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
686 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
687 return NULL;
688
689 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
690 } else
691 obj = &con->objs[head->block];
c030f2e4 692
640ae42e 693 if (alive_obj(obj))
c030f2e4 694 return obj;
c030f2e4 695 } else {
640ae42e 696 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
c030f2e4 697 obj = &con->objs[i];
640ae42e 698 if (alive_obj(obj))
c030f2e4 699 return obj;
c030f2e4 700 }
701 }
702
703 return NULL;
704}
705/* obj end */
706
707/* feature ctl begin */
708static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
e509965e 709 struct ras_common_if *head)
c030f2e4 710{
8ab0d6f0 711 return adev->ras_hw_enabled & BIT(head->block);
c030f2e4 712}
713
714static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
715 struct ras_common_if *head)
716{
717 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
718
719 return con->features & BIT(head->block);
720}
721
722/*
723 * if obj is not created, then create one.
724 * set feature enable flag.
725 */
726static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
727 struct ras_common_if *head, int enable)
728{
729 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
730 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
731
5caf466a 732 /* If hardware does not support ras, then do not create obj.
733 * But if hardware support ras, we can create the obj.
734 * Ras framework checks con->hw_supported to see if it need do
735 * corresponding initialization.
736 * IP checks con->support to see if it need disable ras.
737 */
c030f2e4 738 if (!amdgpu_ras_is_feature_allowed(adev, head))
739 return 0;
c030f2e4 740
741 if (enable) {
742 if (!obj) {
743 obj = amdgpu_ras_create_obj(adev, head);
744 if (!obj)
745 return -EINVAL;
746 } else {
747 /* In case we create obj somewhere else */
748 get_obj(obj);
749 }
750 con->features |= BIT(head->block);
751 } else {
752 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
19d0dfda 753 con->features &= ~BIT(head->block);
c030f2e4 754 put_obj(obj);
755 }
756 }
757
758 return 0;
759}
760
761/* wrapper of psp_ras_enable_features */
762int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
763 struct ras_common_if *head, bool enable)
764{
765 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
7fcffecf 766 union ta_ras_cmd_input *info;
c26cd999 767 int ret = 0;
c030f2e4 768
769 if (!con)
770 return -EINVAL;
771
6fc9d92c
HZ		 772 /* Do not enable ras feature if it is not allowed */
773 if (enable &&
774 head->block != AMDGPU_RAS_BLOCK__GFX &&
775 !amdgpu_ras_is_feature_allowed(adev, head))
776 goto out;
777
778 /* Only enable gfx ras feature from host side */
779 if (head->block == AMDGPU_RAS_BLOCK__GFX &&
780 !amdgpu_sriov_vf(adev) &&
781 !amdgpu_ras_intr_triggered()) {
26093ce1
SY		 782 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
783 if (!info)
784 return -ENOMEM;
785
786 if (!enable) {
787 info->disable_features = (struct ta_ras_disable_features_input) {
788 .block_id = amdgpu_ras_block_to_ta(head->block),
789 .error_type = amdgpu_ras_error_to_ta(head->type),
790 };
791 } else {
792 info->enable_features = (struct ta_ras_enable_features_input) {
793 .block_id = amdgpu_ras_block_to_ta(head->block),
794 .error_type = amdgpu_ras_error_to_ta(head->type),
795 };
796 }
c030f2e4 797
7fcffecf 798 ret = psp_ras_enable_features(&adev->psp, info, enable);
bff77e86 799 if (ret) {
e4348849 800 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
011907fd 801 enable ? "enable":"disable",
640ae42e 802 get_ras_block_str(head),
e4348849 803 amdgpu_ras_is_poison_mode_supported(adev), ret);
7fcffecf 804 goto out;
bff77e86 805 }
c030f2e4 806 }
807
808 /* setup the obj */
809 __amdgpu_ras_feature_enable(adev, head, enable);
7fcffecf 810out:
26093ce1
SY		 811 if (head->block == AMDGPU_RAS_BLOCK__GFX)
812 kfree(info);
7fcffecf 813 return ret;
c030f2e4 814}
815
77de502b 816/* Only used in device probe stage and called only once. */
817int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
818 struct ras_common_if *head, bool enable)
819{
820 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
821 int ret;
822
823 if (!con)
824 return -EINVAL;
825
826 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
7af23ebe 827 if (enable) {
828 /* There is no harm to issue a ras TA cmd regardless of
829 * the currecnt ras state.
830 * If current state == target state, it will do nothing
831 * But sometimes it requests driver to reset and repost
832 * with error code -EAGAIN.
833 */
834 ret = amdgpu_ras_feature_enable(adev, head, 1);
835 /* With old ras TA, we might fail to enable ras.
836 * Log it and just setup the object.
837 * TODO need remove this WA in the future.
838 */
839 if (ret == -EINVAL) {
840 ret = __amdgpu_ras_feature_enable(adev, head, 1);
841 if (!ret)
6952e99c
GC		 842 dev_info(adev->dev,
843 "RAS INFO: %s setup object\n",
640ae42e 844 get_ras_block_str(head));
7af23ebe 845 }
846 } else {
847 /* setup the object then issue a ras TA disable cmd.*/
848 ret = __amdgpu_ras_feature_enable(adev, head, 1);
849 if (ret)
850 return ret;
77de502b 851
970fd197
SY		 852 /* gfx block ras dsiable cmd must send to ras-ta */
853 if (head->block == AMDGPU_RAS_BLOCK__GFX)
854 con->features |= BIT(head->block);
855
77de502b 856 ret = amdgpu_ras_feature_enable(adev, head, 0);
19d0dfda
SY		 857
858 /* clean gfx block ras features flag */
8ab0d6f0 859 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
19d0dfda 860 con->features &= ~BIT(head->block);
7af23ebe 861 }
77de502b 862 } else
863 ret = amdgpu_ras_feature_enable(adev, head, enable);
864
865 return ret;
866}
867
c030f2e4 868static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
869 bool bypass)
870{
871 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
872 struct ras_manager *obj, *tmp;
873
874 list_for_each_entry_safe(obj, tmp, &con->head, node) {
875 /* bypass psp.
876 * aka just release the obj and corresponding flags
877 */
878 if (bypass) {
879 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
880 break;
881 } else {
882 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
883 break;
884 }
289d513b 885 }
c030f2e4 886
887 return con->features;
888}
889
890static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
891 bool bypass)
892{
893 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c030f2e4 894 int i;
640ae42e 895 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
c030f2e4 896
640ae42e 897 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
c030f2e4 898 struct ras_common_if head = {
899 .block = i,
191051a1 900 .type = default_ras_type,
c030f2e4 901 .sub_block_index = 0,
902 };
640ae42e
JC		 903
904 if (i == AMDGPU_RAS_BLOCK__MCA)
905 continue;
906
907 if (bypass) {
908 /*
909 * bypass psp. vbios enable ras for us.
910 * so just create the obj
911 */
912 if (__amdgpu_ras_feature_enable(adev, &head, 1))
913 break;
914 } else {
915 if (amdgpu_ras_feature_enable(adev, &head, 1))
916 break;
917 }
918 }
919
920 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
921 struct ras_common_if head = {
922 .block = AMDGPU_RAS_BLOCK__MCA,
923 .type = default_ras_type,
924 .sub_block_index = i,
925 };
926
c030f2e4 927 if (bypass) {
928 /*
929 * bypass psp. vbios enable ras for us.
930 * so just create the obj
931 */
932 if (__amdgpu_ras_feature_enable(adev, &head, 1))
933 break;
934 } else {
935 if (amdgpu_ras_feature_enable(adev, &head, 1))
936 break;
937 }
289d513b 938 }
c030f2e4 939
940 return con->features;
941}
942/* feature ctl end */
943
e3d833f4 944static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
945 enum amdgpu_ras_block block)
6492e1b0 946{
b6efdb02 947 if (!block_obj)
6492e1b0 948 return -EINVAL;
949
bdb3489c 950 if (block_obj->ras_comm.block == block)
6492e1b0 951 return 0;
640ae42e 952
6492e1b0 953 return -EINVAL;
954}
955
b6efdb02 956static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
6492e1b0 957 enum amdgpu_ras_block block, uint32_t sub_block_index)
640ae42e 958{
d5e8ff5f 959 struct amdgpu_ras_block_list *node, *tmp;
960 struct amdgpu_ras_block_object *obj;
6492e1b0 961
962 if (block >= AMDGPU_RAS_BLOCK__LAST)
963 return NULL;
964
d5e8ff5f 965 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
966 if (!node->ras_obj) {
967 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
968 continue;
969 }
970
971 obj = node->ras_obj;
6492e1b0 972 if (obj->ras_block_match) {
973 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
974 return obj;
975 } else {
976 if (amdgpu_ras_block_match_default(obj, block) == 0)
977 return obj;
978 }
640ae42e 979 }
6492e1b0 980
981 return NULL;
640ae42e
JC		 982}
983
fdcb279d
SY		 984static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
985{
986 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
987 int ret = 0;
988
989 /*
990 * choosing right query method according to
991 * whether smu support query error information
992 */
bc143d8b 993 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
fdcb279d 994 if (ret == -EOPNOTSUPP) {
efe17d5a 995 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
996 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
997 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
fdcb279d
SY		 998
999 /* umc query_ras_error_address is also responsible for clearing
1000 * error status
1001 */
efe17d5a 1002 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1003 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1004 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
fdcb279d 1005 } else if (!ret) {
efe17d5a 1006 if (adev->umc.ras &&
1007 adev->umc.ras->ecc_info_query_ras_error_count)
1008 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
fdcb279d 1009
efe17d5a 1010 if (adev->umc.ras &&
1011 adev->umc.ras->ecc_info_query_ras_error_address)
1012 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
fdcb279d
SY		 1013 }
1014}
1015
c030f2e4 1016/* query/inject/cure begin */
761d86d3 1017int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
4d9f771e 1018 struct ras_query_if *info)
c030f2e4 1019{
b6efdb02 1020 struct amdgpu_ras_block_object *block_obj = NULL;
c030f2e4 1021 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
6f102dba 1022 struct ras_err_data err_data = {0, 0, 0, NULL};
c030f2e4 1023
1024 if (!obj)
1025 return -EINVAL;
c030f2e4 1026
7389a5b8 1027 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
fdcb279d 1028 amdgpu_ras_get_ecc_info(adev, &err_data);
7389a5b8 1029 } else {
1030 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
8b0fb0e9 1031 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1032 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1033 get_ras_block_str(&info->head));
8b0fb0e9 1034 return -EINVAL;
3e81ee9a 1035 }
761d86d3 1036
6c245386 1037 if (block_obj->hw_ops->query_ras_error_count)
1038 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
7389a5b8 1039
1040 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1041 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1042 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1043 if (block_obj->hw_ops->query_ras_error_status)
1044 block_obj->hw_ops->query_ras_error_status(adev);
1045 }
939e2258 1046 }
05a58345
TZ		 1047
1048 obj->err_data.ue_count += err_data.ue_count;
1049 obj->err_data.ce_count += err_data.ce_count;
1050
c030f2e4 1051 info->ue_count = obj->err_data.ue_count;
1052 info->ce_count = obj->err_data.ce_count;
1053
7c6e68c7 1054 if (err_data.ce_count) {
a30f1286
HZ		 1055 if (adev->smuio.funcs &&
1056 adev->smuio.funcs->get_socket_id &&
1057 adev->smuio.funcs->get_die_id) {
1058 dev_info(adev->dev, "socket: %d, die: %d "
1059 "%ld correctable hardware errors "
6952e99c
GC		 1060 "detected in %s block, no user "
1061 "action is needed.\n",
a30f1286
HZ		 1062 adev->smuio.funcs->get_socket_id(adev),
1063 adev->smuio.funcs->get_die_id(adev),
6952e99c 1064 obj->err_data.ce_count,
640ae42e 1065 get_ras_block_str(&info->head));
a30f1286
HZ		 1066 } else {
1067 dev_info(adev->dev, "%ld correctable hardware errors "
6952e99c
GC		 1068 "detected in %s block, no user "
1069 "action is needed.\n",
1070 obj->err_data.ce_count,
640ae42e 1071 get_ras_block_str(&info->head));
a30f1286 1072 }
7c6e68c7
AG		 1073 }
1074 if (err_data.ue_count) {
a30f1286
HZ		 1075 if (adev->smuio.funcs &&
1076 adev->smuio.funcs->get_socket_id &&
1077 adev->smuio.funcs->get_die_id) {
1078 dev_info(adev->dev, "socket: %d, die: %d "
1079 "%ld uncorrectable hardware errors "
6952e99c 1080 "detected in %s block\n",
a30f1286
HZ		 1081 adev->smuio.funcs->get_socket_id(adev),
1082 adev->smuio.funcs->get_die_id(adev),
6952e99c 1083 obj->err_data.ue_count,
640ae42e 1084 get_ras_block_str(&info->head));
a30f1286
HZ		 1085 } else {
1086 dev_info(adev->dev, "%ld uncorrectable hardware errors "
6952e99c
GC		 1087 "detected in %s block\n",
1088 obj->err_data.ue_count,
640ae42e 1089 get_ras_block_str(&info->head));
a30f1286 1090 }
7c6e68c7 1091 }
05a58345 1092
c030f2e4 1093 return 0;
1094}
1095
761d86d3
DL		 1096int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1097 enum amdgpu_ras_block block)
1098{
b6efdb02 1099 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
8b0fb0e9 1100
761d86d3
DL		 1101 if (!amdgpu_ras_is_supported(adev, block))
1102 return -EINVAL;
1103
7389a5b8 1104 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1105 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1106 ras_block_str(block));
7389a5b8 1107 return -EINVAL;
761d86d3
DL		 1108 }
1109
7389a5b8 1110 if (block_obj->hw_ops->reset_ras_error_count)
1111 block_obj->hw_ops->reset_ras_error_count(adev);
5c23e9e0 1112
7389a5b8 1113 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1114 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
8b0fb0e9 1115 if (block_obj->hw_ops->reset_ras_error_status)
1116 block_obj->hw_ops->reset_ras_error_status(adev);
761d86d3 1117 }
5c23e9e0 1118
761d86d3 1119 return 0;
5c23e9e0
JC		 1120}
1121
c030f2e4 1122/* wrapper of psp_ras_trigger_error */
1123int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1124 struct ras_inject_if *info)
1125{
1126 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1127 struct ta_ras_trigger_error_input block_info = {
828cfa29 1128 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1129 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
c030f2e4 1130 .sub_block_index = info->head.sub_block_index,
1131 .address = info->address,
1132 .value = info->value,
1133 };
ab3b9de6
YL		 1134 int ret = -EINVAL;
1135 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1136 info->head.block,
1137 info->head.sub_block_index);
c030f2e4 1138
248c9635
TZ		 1139 /* inject on guest isn't allowed, return success directly */
1140 if (amdgpu_sriov_vf(adev))
1141 return 0;
1142
c030f2e4 1143 if (!obj)
1144 return -EINVAL;
1145
22d4ba53 1146 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1147 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1148 get_ras_block_str(&info->head));
22d4ba53 1149 return -EINVAL;
1150 }
1151
a6c44d25 1152 /* Calculate XGMI relative offset */
a80fe1a6
TZ		 1153 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
1154 info->head.block != AMDGPU_RAS_BLOCK__GFX) {
19744f5f
HZ		 1155 block_info.address =
1156 amdgpu_xgmi_get_relative_phy_addr(adev,
1157 block_info.address);
a6c44d25
JC		 1158 }
1159
27c5f295
TZ		 1160 if (block_obj->hw_ops->ras_error_inject) {
1161 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
2c22ed0b 1162 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
27c5f295 1163 else /* Special ras_error_inject is defined (e.g: xgmi) */
2c22ed0b
TZ		 1164 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1165 info->instance_mask);
27c5f295
TZ		 1166 } else {
1167 /* default path */
1168 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
a5dd40ca
HZ		 1169 }
1170
011907fd
DL		 1171 if (ret)
1172 dev_err(adev->dev, "ras inject %s failed %d\n",
640ae42e 1173 get_ras_block_str(&info->head), ret);
c030f2e4 1174
1175 return ret;
1176}
1177
4d9f771e 1178/**
4a1c9a44
HZ		 1179 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1180 * @adev: pointer to AMD GPU device
1181 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1182 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1183 * @query_info: pointer to ras_query_if
1184 *
1185 * Return 0 for query success or do nothing, otherwise return an error
1186 * on failures
1187 */
1188static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1189 unsigned long *ce_count,
1190 unsigned long *ue_count,
1191 struct ras_query_if *query_info)
1192{
1193 int ret;
1194
1195 if (!query_info)
1196 /* do nothing if query_info is not specified */
1197 return 0;
1198
1199 ret = amdgpu_ras_query_error_status(adev, query_info);
1200 if (ret)
1201 return ret;
1202
1203 *ce_count += query_info->ce_count;
1204 *ue_count += query_info->ue_count;
1205
1206 /* some hardware/IP supports read to clear
1207 * no need to explictly reset the err status after the query call */
1208 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1209 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1210 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1211 dev_warn(adev->dev,
1212 "Failed to reset error counter and error status\n");
1213 }
1214
1215 return 0;
1216}
1217
1218/**
1219 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
bbe04dec
IB		 1220 * @adev: pointer to AMD GPU device
1221 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1222 * @ue_count: pointer to an integer to be set to the count of uncorrectible
4d9f771e 1223 * errors.
4a1c9a44
HZ		 1224 * @query_info: pointer to ras_query_if if the query request is only for
1225 * specific ip block; if info is NULL, then the qurey request is for
1226 * all the ip blocks that support query ras error counters/status
4d9f771e
LT		 1227 *
1228 * If set, @ce_count or @ue_count, count and return the corresponding
1229 * error counts in those integer pointers. Return 0 if the device
1230 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1231 */
1232int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1233 unsigned long *ce_count,
4a1c9a44
HZ		 1234 unsigned long *ue_count,
1235 struct ras_query_if *query_info)
c030f2e4 1236{
1237 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1238 struct ras_manager *obj;
a46751fb 1239 unsigned long ce, ue;
4a1c9a44 1240 int ret;
c030f2e4 1241
8ab0d6f0 1242 if (!adev->ras_enabled || !con)
4d9f771e
LT		 1243 return -EOPNOTSUPP;
1244
1245 /* Don't count since no reporting.
1246 */
1247 if (!ce_count && !ue_count)
1248 return 0;
c030f2e4 1249
a46751fb
LT		 1250 ce = 0;
1251 ue = 0;
4a1c9a44
HZ		 1252 if (!query_info) {
1253 /* query all the ip blocks that support ras query interface */
1254 list_for_each_entry(obj, &con->head, node) {
1255 struct ras_query_if info = {
1256 .head = obj->head,
1257 };
c030f2e4 1258
4a1c9a44 1259 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
2a460963 1260 }
4a1c9a44
HZ		 1261 } else {
1262 /* query specific ip block */
1263 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
c030f2e4 1264 }
1265
4a1c9a44
HZ		 1266 if (ret)
1267 return ret;
1268
a46751fb
LT		 1269 if (ce_count)
1270 *ce_count = ce;
1271
1272 if (ue_count)
1273 *ue_count = ue;
4d9f771e
LT		 1274
1275 return 0;
c030f2e4 1276}
1277/* query/inject/cure end */
1278
1279
1280/* sysfs begin */
1281
466b1793 1282static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1283 struct ras_badpage **bps, unsigned int *count);
1284
1285static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1286{
1287 switch (flags) {
52dd95f2 1288 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
466b1793 1289 return "R";
52dd95f2 1290 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
466b1793 1291 return "P";
52dd95f2 1292 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
466b1793 1293 default:
1294 return "F";
aec576f9 1295 }
466b1793 1296}
1297
f77c7109
AD		 1298/**
1299 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
466b1793 1300 *
1301 * It allows user to read the bad pages of vram on the gpu through
1302 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1303 *
1304 * It outputs multiple lines, and each line stands for one gpu page.
1305 *
1306 * The format of one line is below,
1307 * gpu pfn : gpu page size : flags
1308 *
1309 * gpu pfn and gpu page size are printed in hex format.
1310 * flags can be one of below character,
f77c7109 1311 *
466b1793 1312 * R: reserved, this gpu page is reserved and not able to use.
f77c7109 1313 *
466b1793 1314 * P: pending for reserve, this gpu page is marked as bad, will be reserved
f77c7109
AD		 1315 * in next window of page_reserve.
1316 *
466b1793 1317 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1318 *
f77c7109
AD		 1319 * Examples:
1320 *
1321 * .. code-block:: bash
1322 *
1323 * 0x00000001 : 0x00001000 : R
1324 * 0x00000002 : 0x00001000 : P
1325 *
466b1793 1326 */
1327
1328static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1329 struct kobject *kobj, struct bin_attribute *attr,
1330 char *buf, loff_t ppos, size_t count)
1331{
1332 struct amdgpu_ras *con =
1333 container_of(attr, struct amdgpu_ras, badpages_attr);
1334 struct amdgpu_device *adev = con->adev;
1335 const unsigned int element_size =
1336 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
d6ee400e
SA		 1337 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1338 unsigned int end = div64_ul(ppos + count - 1, element_size);
466b1793 1339 ssize_t s = 0;
1340 struct ras_badpage *bps = NULL;
1341 unsigned int bps_count = 0;
1342
1343 memset(buf, 0, count);
1344
1345 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1346 return 0;
1347
1348 for (; start < end && start < bps_count; start++)
1349 s += scnprintf(&buf[s], element_size + 1,
1350 "0x%08x : 0x%08x : %1s\n",
1351 bps[start].bp,
1352 bps[start].size,
1353 amdgpu_ras_badpage_flags_str(bps[start].flags));
1354
1355 kfree(bps);
1356
1357 return s;
1358}
1359
c030f2e4 1360static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1361 struct device_attribute *attr, char *buf)
1362{
1363 struct amdgpu_ras *con =
1364 container_of(attr, struct amdgpu_ras, features_attr);
c030f2e4 1365
2cffcb66 1366 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
c030f2e4 1367}
1368
f848159b
GC		 1369static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1370{
1371 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1372
1373 sysfs_remove_file_from_group(&adev->dev->kobj,
1374 &con->badpages_attr.attr,
1375 RAS_FS_NAME);
1376}
1377
c030f2e4 1378static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1379{
1380 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1381 struct attribute *attrs[] = {
1382 &con->features_attr.attr,
1383 NULL
1384 };
1385 struct attribute_group group = {
eb0c3cd4 1386 .name = RAS_FS_NAME,
c030f2e4 1387 .attrs = attrs,
1388 };
1389
1390 sysfs_remove_group(&adev->dev->kobj, &group);
1391
1392 return 0;
1393}
1394
1395int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
9252d33d 1396 struct ras_common_if *head)
c030f2e4 1397{
9252d33d 1398 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1399
1400 if (!obj || obj->attr_inuse)
1401 return -EINVAL;
1402
1403 get_obj(obj);
1404
9252d33d 1405 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1406 "%s_err_count", head->name);
c030f2e4 1407
1408 obj->sysfs_attr = (struct device_attribute){
1409 .attr = {
1410 .name = obj->fs_data.sysfs_name,
1411 .mode = S_IRUGO,
1412 },
1413 .show = amdgpu_ras_sysfs_read,
1414 };
163def43 1415 sysfs_attr_init(&obj->sysfs_attr.attr);
c030f2e4 1416
1417 if (sysfs_add_file_to_group(&adev->dev->kobj,
1418 &obj->sysfs_attr.attr,
eb0c3cd4 1419 RAS_FS_NAME)) {
c030f2e4 1420 put_obj(obj);
1421 return -EINVAL;
1422 }
1423
1424 obj->attr_inuse = 1;
1425
1426 return 0;
1427}
1428
1429int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1430 struct ras_common_if *head)
1431{
1432 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1433
1434 if (!obj || !obj->attr_inuse)
1435 return -EINVAL;
1436
1437 sysfs_remove_file_from_group(&adev->dev->kobj,
1438 &obj->sysfs_attr.attr,
eb0c3cd4 1439 RAS_FS_NAME);
c030f2e4 1440 obj->attr_inuse = 0;
1441 put_obj(obj);
1442
1443 return 0;
1444}
1445
1446static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1447{
1448 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1449 struct ras_manager *obj, *tmp;
1450
1451 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1452 amdgpu_ras_sysfs_remove(adev, &obj->head);
1453 }
1454
f848159b
GC		 1455 if (amdgpu_bad_page_threshold != 0)
1456 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1457
c030f2e4 1458 amdgpu_ras_sysfs_remove_feature_node(adev);
1459
1460 return 0;
1461}
1462/* sysfs end */
1463
ef177d11
AD		 1464/**
1465 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1466 *
1467 * Normally when there is an uncorrectable error, the driver will reset
1468 * the GPU to recover. However, in the event of an unrecoverable error,
1469 * the driver provides an interface to reboot the system automatically
1470 * in that event.
1471 *
1472 * The following file in debugfs provides that interface:
1473 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1474 *
1475 * Usage:
1476 *
1477 * .. code-block:: bash
1478 *
1479 * echo true > .../ras/auto_reboot
1480 *
1481 */
c030f2e4 1482/* debugfs begin */
ea1b8c9b 1483static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
36ea1bd2 1484{
1485 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
740f42a2 1486 struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control;
ef0d7d20
LT		 1487 struct drm_minor *minor = adev_to_drm(adev)->primary;
1488 struct dentry *dir;
36ea1bd2 1489
88293c03
ND		 1490 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1491 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1492 &amdgpu_ras_debugfs_ctrl_ops);
1493 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1494 &amdgpu_ras_debugfs_eeprom_ops);
7fb64071
LT		 1495 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1496 &con->bad_page_cnt_threshold);
740f42a2 1497 debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs);
ef0d7d20
LT		 1498 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1499 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
c65b0805
LT		 1500 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1501 &amdgpu_ras_debugfs_eeprom_size_ops);
1502 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1503 S_IRUGO, dir, adev,
1504 &amdgpu_ras_debugfs_eeprom_table_ops);
1505 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
c688a06b
GC		 1506
1507 /*
1508 * After one uncorrectable error happens, usually GPU recovery will
1509 * be scheduled. But due to the known problem in GPU recovery failing
1510 * to bring GPU back, below interface provides one direct way to
1511 * user to reboot system automatically in such case within
1512 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1513 * will never be called.
1514 */
88293c03 1515 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
66459e1d
GC		 1516
1517 /*
1518 * User could set this not to clean up hardware's error count register
1519 * of RAS IPs during ras recovery.
1520 */
88293c03
ND		 1521 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1522 &con->disable_ras_err_cnt_harvest);
1523 return dir;
36ea1bd2 1524}
1525
cedf7884 1526static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
88293c03
ND		 1527 struct ras_fs_if *head,
1528 struct dentry *dir)
c030f2e4 1529{
c030f2e4 1530 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
c030f2e4 1531
88293c03 1532 if (!obj || !dir)
450f30ea 1533 return;
c030f2e4 1534
1535 get_obj(obj);
1536
1537 memcpy(obj->fs_data.debugfs_name,
1538 head->debugfs_name,
1539 sizeof(obj->fs_data.debugfs_name));
1540
88293c03
ND		 1541 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1542 obj, &amdgpu_ras_debugfs_ops);
c030f2e4 1543}
1544
f9317014
TZ		 1545void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1546{
1547 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
88293c03 1548 struct dentry *dir;
c1509f3f 1549 struct ras_manager *obj;
f9317014
TZ		 1550 struct ras_fs_if fs_info;
1551
1552 /*
1553 * it won't be called in resume path, no need to check
1554 * suspend and gpu reset status
1555 */
cedf7884 1556 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
f9317014
TZ		 1557 return;
1558
88293c03 1559 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
f9317014 1560
c1509f3f 1561 list_for_each_entry(obj, &con->head, node) {
f9317014
TZ		 1562 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1563 (obj->attr_inuse == 1)) {
1564 sprintf(fs_info.debugfs_name, "%s_err_inject",
640ae42e 1565 get_ras_block_str(&obj->head));
f9317014 1566 fs_info.head = obj->head;
88293c03 1567 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
f9317014
TZ		 1568 }
1569 }
1570}
1571
c030f2e4 1572/* debugfs end */
1573
1574/* ras fs */
c3d4d45d
GC		 1575static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1576 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1577static DEVICE_ATTR(features, S_IRUGO,
1578 amdgpu_ras_sysfs_features_read, NULL);
c030f2e4 1579static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1580{
c3d4d45d
GC		 1581 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1582 struct attribute_group group = {
1583 .name = RAS_FS_NAME,
1584 };
1585 struct attribute *attrs[] = {
1586 &con->features_attr.attr,
1587 NULL
1588 };
1589 struct bin_attribute *bin_attrs[] = {
1590 NULL,
1591 NULL,
1592 };
a069a9eb 1593 int r;
c030f2e4 1594
c3d4d45d
GC		 1595 /* add features entry */
1596 con->features_attr = dev_attr_features;
1597 group.attrs = attrs;
1598 sysfs_attr_init(attrs[0]);
1599
1600 if (amdgpu_bad_page_threshold != 0) {
1601 /* add bad_page_features entry */
1602 bin_attr_gpu_vram_bad_pages.private = NULL;
1603 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1604 bin_attrs[0] = &con->badpages_attr;
1605 group.bin_attrs = bin_attrs;
1606 sysfs_bin_attr_init(bin_attrs[0]);
1607 }
1608
a069a9eb
AD		 1609 r = sysfs_create_group(&adev->dev->kobj, &group);
1610 if (r)
1611 dev_err(adev->dev, "Failed to create RAS sysfs group!");
f848159b 1612
c030f2e4 1613 return 0;
1614}
1615
1616static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1617{
88293c03
ND		 1618 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1619 struct ras_manager *con_obj, *ip_obj, *tmp;
1620
1621 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1622 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1623 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1624 if (ip_obj)
1625 put_obj(ip_obj);
1626 }
1627 }
1628
c030f2e4 1629 amdgpu_ras_sysfs_remove_all(adev);
1630 return 0;
1631}
1632/* ras fs end */
1633
1634/* ih begin */
b3c76814
TZ		 1635
1636/* For the hardware that cannot enable bif ring for both ras_controller_irq
1637 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1638 * register to check whether the interrupt is triggered or not, and properly
1639 * ack the interrupt if it is there
1640 */
1641void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1642{
950d6425 1643 /* Fatal error events are handled on host side */
8eba7205 1644 if (amdgpu_sriov_vf(adev))
b3c76814
TZ		 1645 return;
1646
1647 if (adev->nbio.ras &&
1648 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1649 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1650
1651 if (adev->nbio.ras &&
1652 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1653 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1654}
1655
66f87949
TZ		 1656static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1657 struct amdgpu_iv_entry *entry)
1658{
b63ac5d3 1659 bool poison_stat = false;
66f87949 1660 struct amdgpu_device *adev = obj->adev;
66f87949
TZ		 1661 struct amdgpu_ras_block_object *block_obj =
1662 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1663
ac7b25d9 1664 if (!block_obj)
b63ac5d3 1665 return;
66f87949 1666
b63ac5d3
TZ		 1667 /* both query_poison_status and handle_poison_consumption are optional,
1668 * but at least one of them should be implemented if we need poison
1669 * consumption handler
1670 */
ac7b25d9 1671 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
b63ac5d3
TZ		 1672 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1673 if (!poison_stat) {
1674 /* Not poison consumption interrupt, no need to handle it */
1675 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1676 block_obj->ras_comm.name);
1677
1678 return;
66f87949
TZ		 1679 }
1680 }
1681
38298ce6 1682 amdgpu_umc_poison_handler(adev, false);
b63ac5d3 1683
ac7b25d9 1684 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
b63ac5d3
TZ		 1685 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1686
1687 /* gpu reset is fallback for failed and default cases */
1688 if (poison_stat) {
1689 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1690 block_obj->ras_comm.name);
66f87949 1691 amdgpu_ras_reset_gpu(adev);
ac7b25d9
YC		 1692 } else {
1693 amdgpu_gfx_poison_consumption_handler(adev, entry);
b63ac5d3 1694 }
66f87949
TZ		 1695}
1696
50a7d025
TZ		 1697static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1698 struct amdgpu_iv_entry *entry)
1699{
1700 dev_info(obj->adev->dev,
1701 "Poison is created, no user action is needed.\n");
1702}
1703
1704static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1705 struct amdgpu_iv_entry *entry)
1706{
1707 struct ras_ih_data *data = &obj->ih_data;
1708 struct ras_err_data err_data = {0, 0, 0, NULL};
1709 int ret;
1710
1711 if (!data->cb)
1712 return;
1713
1714 /* Let IP handle its data, maybe we need get the output
1715 * from the callback to update the error type/count, etc
1716 */
1717 ret = data->cb(obj->adev, &err_data, entry);
1718 /* ue will trigger an interrupt, and in that case
1719 * we need do a reset to recovery the whole system.
1720 * But leave IP do that recovery, here we just dispatch
1721 * the error.
1722 */
1723 if (ret == AMDGPU_RAS_SUCCESS) {
1724 /* these counts could be left as 0 if
1725 * some blocks do not count error number
1726 */
1727 obj->err_data.ue_count += err_data.ue_count;
1728 obj->err_data.ce_count += err_data.ce_count;
1729 }
1730}
1731
c030f2e4 1732static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1733{
1734 struct ras_ih_data *data = &obj->ih_data;
1735 struct amdgpu_iv_entry entry;
c030f2e4 1736
1737 while (data->rptr != data->wptr) {
1738 rmb();
1739 memcpy(&entry, &data->ring[data->rptr],
1740 data->element_size);
1741
1742 wmb();
1743 data->rptr = (data->aligned_element_size +
1744 data->rptr) % data->ring_size;
1745
50a7d025
TZ		 1746 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1747 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1748 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
66f87949
TZ		 1749 else
1750 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
50a7d025
TZ		 1751 } else {
1752 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1753 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1754 else
1755 dev_warn(obj->adev->dev,
1756 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
c030f2e4 1757 }
1758 }
1759}
1760
1761static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1762{
1763 struct ras_ih_data *data =
1764 container_of(work, struct ras_ih_data, ih_work);
1765 struct ras_manager *obj =
1766 container_of(data, struct ras_manager, ih_data);
1767
1768 amdgpu_ras_interrupt_handler(obj);
1769}
1770
1771int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1772 struct ras_dispatch_if *info)
1773{
1774 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1775 struct ras_ih_data *data = &obj->ih_data;
1776
1777 if (!obj)
1778 return -EINVAL;
1779
1780 if (data->inuse == 0)
1781 return 0;
1782
1783 /* Might be overflow... */
1784 memcpy(&data->ring[data->wptr], info->entry,
1785 data->element_size);
1786
1787 wmb();
1788 data->wptr = (data->aligned_element_size +
1789 data->wptr) % data->ring_size;
1790
1791 schedule_work(&data->ih_work);
1792
1793 return 0;
1794}
1795
1796int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
9252d33d 1797 struct ras_common_if *head)
c030f2e4 1798{
9252d33d 1799 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1800 struct ras_ih_data *data;
1801
1802 if (!obj)
1803 return -EINVAL;
1804
1805 data = &obj->ih_data;
1806 if (data->inuse == 0)
1807 return 0;
1808
1809 cancel_work_sync(&data->ih_work);
1810
1811 kfree(data->ring);
1812 memset(data, 0, sizeof(*data));
1813 put_obj(obj);
1814
1815 return 0;
1816}
1817
1818int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
9252d33d 1819 struct ras_common_if *head)
c030f2e4 1820{
9252d33d 1821 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1822 struct ras_ih_data *data;
9252d33d 1823 struct amdgpu_ras_block_object *ras_obj;
c030f2e4 1824
1825 if (!obj) {
1826 /* in case we registe the IH before enable ras feature */
9252d33d 1827 obj = amdgpu_ras_create_obj(adev, head);
c030f2e4 1828 if (!obj)
1829 return -EINVAL;
1830 } else
1831 get_obj(obj);
1832
9252d33d 1833 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1834
c030f2e4 1835 data = &obj->ih_data;
1836 /* add the callback.etc */
1837 *data = (struct ras_ih_data) {
1838 .inuse = 0,
9252d33d 1839 .cb = ras_obj->ras_cb,
c030f2e4 1840 .element_size = sizeof(struct amdgpu_iv_entry),
1841 .rptr = 0,
1842 .wptr = 0,
1843 };
1844
1845 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1846
1847 data->aligned_element_size = ALIGN(data->element_size, 8);
1848 /* the ring can store 64 iv entries. */
1849 data->ring_size = 64 * data->aligned_element_size;
1850 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1851 if (!data->ring) {
1852 put_obj(obj);
1853 return -ENOMEM;
1854 }
1855
1856 /* IH is ready */
1857 data->inuse = 1;
1858
1859 return 0;
1860}
1861
1862static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1863{
1864 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1865 struct ras_manager *obj, *tmp;
1866
1867 list_for_each_entry_safe(obj, tmp, &con->head, node) {
9252d33d 1868 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
c030f2e4 1869 }
1870
1871 return 0;
1872}
1873/* ih end */
1874
313c8fd3
GC		 1875/* traversal all IPs except NBIO to query error counter */
1876static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1877{
1878 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1879 struct ras_manager *obj;
1880
8ab0d6f0 1881 if (!adev->ras_enabled || !con)
313c8fd3
GC		 1882 return;
1883
1884 list_for_each_entry(obj, &con->head, node) {
1885 struct ras_query_if info = {
1886 .head = obj->head,
1887 };
1888
1889 /*
1890 * PCIE_BIF IP has one different isr by ras controller
1891 * interrupt, the specific ras counter query will be
1892 * done in that isr. So skip such block from common
1893 * sync flood interrupt isr calling.
1894 */
1895 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1896 continue;
1897
cf63b702
SY		 1898 /*
1899 * this is a workaround for aldebaran, skip send msg to
1900 * smu to get ecc_info table due to smu handle get ecc
1901 * info table failed temporarily.
1902 * should be removed until smu fix handle ecc_info table.
1903 */
1904 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1905 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1906 continue;
1907
761d86d3 1908 amdgpu_ras_query_error_status(adev, &info);
2a460963
CL		 1909
1910 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
6da15a23
CL		 1911 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1912 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
2a460963
CL		 1913 if (amdgpu_ras_reset_error_status(adev, info.head.block))
1914 dev_warn(adev->dev, "Failed to reset error counter and error status");
1915 }
313c8fd3
GC		 1916 }
1917}
1918
3f975d0f 1919/* Parse RdRspStatus and WrRspStatus */
cd92df93
LJ		 1920static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1921 struct ras_query_if *info)
3f975d0f 1922{
8eb53bb2 1923 struct amdgpu_ras_block_object *block_obj;
3f975d0f
SY		 1924 /*
1925 * Only two block need to query read/write
1926 * RspStatus at current state
1927 */
5e67bba3 1928 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1929 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
b6efdb02 1930 return;
1931
1932 block_obj = amdgpu_ras_get_ras_block(adev,
1933 info->head.block,
1934 info->head.sub_block_index);
5e67bba3 1935
5e67bba3 1936 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1937 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1938 get_ras_block_str(&info->head));
b6efdb02 1939 return;
3f975d0f 1940 }
5e67bba3 1941
1942 if (block_obj->hw_ops->query_ras_error_status)
ab3b9de6 1943 block_obj->hw_ops->query_ras_error_status(adev);
5e67bba3 1944
3f975d0f
SY		 1945}
1946
1947static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1948{
1949 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1950 struct ras_manager *obj;
1951
8ab0d6f0 1952 if (!adev->ras_enabled || !con)
3f975d0f
SY		 1953 return;
1954
1955 list_for_each_entry(obj, &con->head, node) {
1956 struct ras_query_if info = {
1957 .head = obj->head,
1958 };
1959
1960 amdgpu_ras_error_status_query(adev, &info);
1961 }
1962}
1963
c030f2e4 1964/* recovery begin */
466b1793 1965
1966/* return 0 on success.
1967 * caller need free bps.
1968 */
1969static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1970 struct ras_badpage **bps, unsigned int *count)
1971{
1972 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1973 struct ras_err_handler_data *data;
1974 int i = 0;
732f2a30 1975 int ret = 0, status;
466b1793 1976
1977 if (!con || !con->eh_data || !bps || !count)
1978 return -EINVAL;
1979
1980 mutex_lock(&con->recovery_lock);
1981 data = con->eh_data;
1982 if (!data || data->count == 0) {
1983 *bps = NULL;
46cf2fec 1984 ret = -EINVAL;
466b1793 1985 goto out;
1986 }
1987
1988 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1989 if (!*bps) {
1990 ret = -ENOMEM;
1991 goto out;
1992 }
1993
1994 for (; i < data->count; i++) {
1995 (*bps)[i] = (struct ras_badpage){
9dc23a63 1996 .bp = data->bps[i].retired_page,
466b1793 1997 .size = AMDGPU_GPU_PAGE_SIZE,
52dd95f2 1998 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
466b1793 1999 };
ec6aae97 2000 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
676deb38 2001 data->bps[i].retired_page);
732f2a30 2002 if (status == -EBUSY)
52dd95f2 2003 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
732f2a30 2004 else if (status == -ENOENT)
52dd95f2 2005 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
466b1793 2006 }
2007
2008 *count = data->count;
2009out:
2010 mutex_unlock(&con->recovery_lock);
2011 return ret;
2012}
2013
c030f2e4 2014static void amdgpu_ras_do_recovery(struct work_struct *work)
2015{
2016 struct amdgpu_ras *ras =
2017 container_of(work, struct amdgpu_ras, recovery_work);
b3dbd6d3
JC		 2018 struct amdgpu_device *remote_adev = NULL;
2019 struct amdgpu_device *adev = ras->adev;
2020 struct list_head device_list, *device_list_handle = NULL;
b3dbd6d3 2021
f75e94d8 2022 if (!ras->disable_ras_err_cnt_harvest) {
d95e8e97
DL		 2023 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2024
f75e94d8
GC		 2025 /* Build list of devices to query RAS related errors */
2026 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2027 device_list_handle = &hive->device_list;
2028 } else {
2029 INIT_LIST_HEAD(&device_list);
2030 list_add_tail(&adev->gmc.xgmi.head, &device_list);
2031 device_list_handle = &device_list;
2032 }
c030f2e4 2033
f75e94d8 2034 list_for_each_entry(remote_adev,
3f975d0f
SY		 2035 device_list_handle, gmc.xgmi.head) {
2036 amdgpu_ras_query_err_status(remote_adev);
f75e94d8 2037 amdgpu_ras_log_on_err_counter(remote_adev);
3f975d0f 2038 }
d95e8e97
DL		 2039
2040 amdgpu_put_xgmi_hive(hive);
b3dbd6d3 2041 }
313c8fd3 2042
f1549c09
LG		 2043 if (amdgpu_device_should_recover_gpu(ras->adev)) {
2044 struct amdgpu_reset_context reset_context;
2045 memset(&reset_context, 0, sizeof(reset_context));
2046
2047 reset_context.method = AMD_RESET_METHOD_NONE;
2048 reset_context.reset_req_dev = adev;
1a11a65d
YC		 2049
2050 /* Perform full reset in fatal error mode */
2051 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2052 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6c47a79b 2053 else {
1a11a65d 2054 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
f1549c09 2055
6c47a79b
YC		 2056 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2057 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2058 reset_context.method = AMD_RESET_METHOD_MODE2;
2059 }
2c7cd280
YC		 2060
2061 /* Fatal error occurs in poison mode, mode1 reset is used to
2062 * recover gpu.
2063 */
2064 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) {
2065 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET;
2066 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2067 }
6c47a79b
YC		 2068 }
2069
f1549c09
LG		 2070 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2071 }
c030f2e4 2072 atomic_set(&ras->in_recovery, 0);
2073}
2074
c030f2e4 2075/* alloc/realloc bps array */
2076static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2077 struct ras_err_handler_data *data, int pages)
2078{
2079 unsigned int old_space = data->count + data->space_left;
2080 unsigned int new_space = old_space + pages;
9dc23a63
TZ		 2081 unsigned int align_space = ALIGN(new_space, 512);
2082 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
9dc23a63 2083
676deb38 2084 if (!bps) {
c030f2e4 2085 return -ENOMEM;
9dc23a63 2086 }
c030f2e4 2087
2088 if (data->bps) {
9dc23a63 2089 memcpy(bps, data->bps,
c030f2e4 2090 data->count * sizeof(*data->bps));
2091 kfree(data->bps);
2092 }
2093
9dc23a63 2094 data->bps = bps;
c030f2e4 2095 data->space_left += align_space - old_space;
2096 return 0;
2097}
2098
2099/* it deal with vram only. */
2100int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
9dc23a63 2101 struct eeprom_table_record *bps, int pages)
c030f2e4 2102{
2103 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
73aa8e1a 2104 struct ras_err_handler_data *data;
c030f2e4 2105 int ret = 0;
676deb38 2106 uint32_t i;
c030f2e4 2107
73aa8e1a 2108 if (!con || !con->eh_data || !bps || pages <= 0)
c030f2e4 2109 return 0;
2110
2111 mutex_lock(&con->recovery_lock);
73aa8e1a 2112 data = con->eh_data;
c030f2e4 2113 if (!data)
2114 goto out;
2115
676deb38
DL		 2116 for (i = 0; i < pages; i++) {
2117 if (amdgpu_ras_check_bad_page_unlock(con,
2118 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2119 continue;
2120
2121 if (!data->space_left &&
2122 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
c030f2e4 2123 ret = -ENOMEM;
2124 goto out;
2125 }
2126
ec6aae97 2127 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
676deb38
DL		 2128 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2129 AMDGPU_GPU_PAGE_SIZE);
9dc23a63 2130
676deb38
DL		 2131 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2132 data->count++;
2133 data->space_left--;
2134 }
c030f2e4 2135out:
2136 mutex_unlock(&con->recovery_lock);
2137
2138 return ret;
2139}
2140
78ad00c9
TZ		 2141/*
2142 * write error record array to eeprom, the function should be
2143 * protected by recovery_lock
4d33e0f1 2144 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
78ad00c9 2145 */
4d33e0f1
TZ		 2146int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2147 unsigned long *new_cnt)
78ad00c9
TZ		 2148{
2149 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2150 struct ras_err_handler_data *data;
8a3e801f 2151 struct amdgpu_ras_eeprom_control *control;
78ad00c9
TZ		 2152 int save_count;
2153
4d33e0f1
TZ		 2154 if (!con || !con->eh_data) {
2155 if (new_cnt)
2156 *new_cnt = 0;
2157
78ad00c9 2158 return 0;
4d33e0f1 2159 }
78ad00c9 2160
d9a69fe5 2161 mutex_lock(&con->recovery_lock);
8a3e801f 2162 control = &con->eeprom_control;
78ad00c9 2163 data = con->eh_data;
0686627b 2164 save_count = data->count - control->ras_num_recs;
d9a69fe5 2165 mutex_unlock(&con->recovery_lock);
4d33e0f1
TZ		 2166
2167 if (new_cnt)
2168 *new_cnt = save_count / adev->umc.retire_unit;
2169
78ad00c9 2170 /* only new entries are saved */
b1628425 2171 if (save_count > 0) {
63d4c081
LT		 2172 if (amdgpu_ras_eeprom_append(control,
2173 &data->bps[control->ras_num_recs],
2174 save_count)) {
6952e99c 2175 dev_err(adev->dev, "Failed to save EEPROM table data!");
78ad00c9
TZ		 2176 return -EIO;
2177 }
2178
b1628425
GC		 2179 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2180 }
2181
78ad00c9
TZ		 2182 return 0;
2183}
2184
2185/*
2186 * read error record array in eeprom and reserve enough space for
2187 * storing new bad pages
2188 */
2189static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2190{
2191 struct amdgpu_ras_eeprom_control *control =
6457205c 2192 &adev->psp.ras_context.ras->eeprom_control;
e4e6a589
LT		 2193 struct eeprom_table_record *bps;
2194 int ret;
78ad00c9
TZ		 2195
2196 /* no bad page record, skip eeprom access */
0686627b 2197 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
e4e6a589 2198 return 0;
78ad00c9 2199
0686627b 2200 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
78ad00c9
TZ		 2201 if (!bps)
2202 return -ENOMEM;
2203
0686627b 2204 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
e4e6a589 2205 if (ret)
6952e99c 2206 dev_err(adev->dev, "Failed to load EEPROM table records!");
e4e6a589 2207 else
0686627b 2208 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
78ad00c9 2209
78ad00c9
TZ		 2210 kfree(bps);
2211 return ret;
2212}
2213
676deb38
DL		 2214static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2215 uint64_t addr)
2216{
2217 struct ras_err_handler_data *data = con->eh_data;
2218 int i;
2219
2220 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2221 for (i = 0; i < data->count; i++)
2222 if (addr == data->bps[i].retired_page)
2223 return true;
2224
2225 return false;
2226}
2227
6e4be987
TZ		 2228/*
2229 * check if an address belongs to bad page
2230 *
2231 * Note: this check is only for umc block
2232 */
2233static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2234 uint64_t addr)
2235{
2236 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
6e4be987
TZ		 2237 bool ret = false;
2238
2239 if (!con || !con->eh_data)
2240 return ret;
2241
2242 mutex_lock(&con->recovery_lock);
676deb38 2243 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
6e4be987
TZ		 2244 mutex_unlock(&con->recovery_lock);
2245 return ret;
2246}
2247
e5c04edf 2248static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
e4e6a589 2249 uint32_t max_count)
c84d4670 2250{
e5c04edf 2251 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c84d4670
GC		 2252
2253 /*
2254 * Justification of value bad_page_cnt_threshold in ras structure
2255 *
f3cbe70e
TZ		 2256 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2257 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2258 * scenarios accordingly.
c84d4670
GC		 2259 *
2260 * Bad page retirement enablement:
f3cbe70e 2261 * - If amdgpu_bad_page_threshold = -2,
c84d4670
GC		 2262 * bad_page_cnt_threshold = typical value by formula.
2263 *
2264 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2265 * max record length in eeprom, use it directly.
2266 *
2267 * Bad page retirement disablement:
2268 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2269 * functionality is disabled, and bad_page_cnt_threshold will
2270 * take no effect.
2271 */
2272
e4e6a589
LT		 2273 if (amdgpu_bad_page_threshold < 0) {
2274 u64 val = adev->gmc.mc_vram_size;
c84d4670 2275
e4e6a589 2276 do_div(val, RAS_BAD_PAGE_COVER);
e5c04edf 2277 con->bad_page_cnt_threshold = min(lower_32_bits(val),
e4e6a589 2278 max_count);
e5c04edf 2279 } else {
e4e6a589
LT		 2280 con->bad_page_cnt_threshold = min_t(int, max_count,
2281 amdgpu_bad_page_threshold);
c84d4670
GC		 2282 }
2283}
2284
1a6fc071 2285int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
c030f2e4 2286{
2287 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4d1337d2 2288 struct ras_err_handler_data **data;
e4e6a589 2289 u32 max_eeprom_records_count = 0;
b82e65a9 2290 bool exc_err_limit = false;
78ad00c9 2291 int ret;
c030f2e4 2292
e0e146d5 2293 if (!con || amdgpu_sriov_vf(adev))
1d9d2ca8
LT		 2294 return 0;
2295
2296 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2297 * supports RAS and debugfs is enabled, but when
2298 * adev->ras_enabled is unset, i.e. when "ras_enable"
2299 * module parameter is set to 0.
2300 */
2301 con->adev = adev;
2302
2303 if (!adev->ras_enabled)
4d1337d2
AG		 2304 return 0;
2305
1d9d2ca8 2306 data = &con->eh_data;
1a6fc071
TZ		 2307 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2308 if (!*data) {
2309 ret = -ENOMEM;
2310 goto out;
2311 }
c030f2e4 2312
2313 mutex_init(&con->recovery_lock);
2314 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2315 atomic_set(&con->in_recovery, 0);
69691c82 2316 con->eeprom_control.bad_channel_bitmap = 0;
c030f2e4 2317
7f599fed 2318 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control);
e4e6a589 2319 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
c84d4670 2320
e5086659 2321 /* Todo: During test the SMU might fail to read the eeprom through I2C
2322 * when the GPU is pending on XGMI reset during probe time
2323 * (Mostly after second bus reset), skip it now
2324 */
2325 if (adev->gmc.xgmi.pending_reset)
2326 return 0;
b82e65a9
GC		 2327 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2328 /*
2329 * This calling fails when exc_err_limit is true or
2330 * ret != 0.
2331 */
2332 if (exc_err_limit || ret)
1a6fc071 2333 goto free;
78ad00c9 2334
0686627b 2335 if (con->eeprom_control.ras_num_recs) {
78ad00c9
TZ		 2336 ret = amdgpu_ras_load_bad_pages(adev);
2337 if (ret)
1a6fc071 2338 goto free;
513befa6 2339
bc143d8b 2340 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
69691c82
SY		 2341
2342 if (con->update_channel_flag == true) {
2343 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2344 con->update_channel_flag = false;
2345 }
78ad00c9 2346 }
c030f2e4 2347
12b2cab7
MJ		 2348#ifdef CONFIG_X86_MCE_AMD
2349 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2350 (adev->gmc.xgmi.connected_to_cpu))
91a1a52d 2351 amdgpu_register_bad_pages_mca_notifier(adev);
12b2cab7 2352#endif
c030f2e4 2353 return 0;
1a6fc071 2354
1a6fc071 2355free:
1a6fc071 2356 kfree((*data)->bps);
1a6fc071 2357 kfree(*data);
1995b3a3 2358 con->eh_data = NULL;
1a6fc071 2359out:
cf696091 2360 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
1a6fc071 2361
b82e65a9
GC		 2362 /*
2363 * Except error threshold exceeding case, other failure cases in this
2364 * function would not fail amdgpu driver init.
2365 */
2366 if (!exc_err_limit)
2367 ret = 0;
2368 else
2369 ret = -EINVAL;
2370
1a6fc071 2371 return ret;
c030f2e4 2372}
2373
2374static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2375{
2376 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2377 struct ras_err_handler_data *data = con->eh_data;
2378
1a6fc071
TZ		 2379 /* recovery_init failed to init it, fini is useless */
2380 if (!data)
2381 return 0;
2382
c030f2e4 2383 cancel_work_sync(&con->recovery_work);
c030f2e4 2384
2385 mutex_lock(&con->recovery_lock);
2386 con->eh_data = NULL;
2387 kfree(data->bps);
2388 kfree(data);
2389 mutex_unlock(&con->recovery_lock);
2390
2391 return 0;
2392}
2393/* recovery end */
2394
084e2640 2395static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
5436ab94 2396{
82835055
YC		 2397 if (amdgpu_sriov_vf(adev)) {
2398 switch (adev->ip_versions[MP0_HWIP][0]) {
2399 case IP_VERSION(13, 0, 2):
2400 return true;
2401 default:
2402 return false;
2403 }
2404 }
2405
073285ef
YC		 2406 if (adev->asic_type == CHIP_IP_DISCOVERY) {
2407 switch (adev->ip_versions[MP0_HWIP][0]) {
2408 case IP_VERSION(13, 0, 0):
cb906ce3 2409 case IP_VERSION(13, 0, 6):
073285ef
YC		 2410 case IP_VERSION(13, 0, 10):
2411 return true;
2412 default:
2413 return false;
2414 }
2415 }
2416
084e2640
LT		 2417 return adev->asic_type == CHIP_VEGA10 ||
2418 adev->asic_type == CHIP_VEGA20 ||
2419 adev->asic_type == CHIP_ARCTURUS ||
75f06251 2420 adev->asic_type == CHIP_ALDEBARAN ||
084e2640 2421 adev->asic_type == CHIP_SIENNA_CICHLID;
5436ab94
SY		 2422}
2423
f50160cf
SY		 2424/*
2425 * this is workaround for vega20 workstation sku,
2426 * force enable gfx ras, ignore vbios gfx ras flag
2427 * due to GC EDC can not write
2428 */
e509965e 2429static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
f50160cf
SY		 2430{
2431 struct atom_context *ctx = adev->mode_info.atom_context;
2432
2433 if (!ctx)
2434 return;
2435
adf64e21
ML		 2436 if (strnstr(ctx->vbios_pn, "D16406",
2437 sizeof(ctx->vbios_pn)) ||
2438 strnstr(ctx->vbios_pn, "D36002",
2439 sizeof(ctx->vbios_pn)))
8ab0d6f0 2440 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
f50160cf
SY		 2441}
2442
5caf466a 2443/*
2444 * check hardware's ras ability which will be saved in hw_supported.
2445 * if hardware does not support ras, we can skip some ras initializtion and
2446 * forbid some ras operations from IP.
2447 * if software itself, say boot parameter, limit the ras ability. We still
2448 * need allow IP do some limited operations, like disable. In such case,
2449 * we have to initialize ras as normal. but need check if operation is
2450 * allowed or not in each function.
2451 */
e509965e 2452static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
c030f2e4 2453{
8ab0d6f0 2454 adev->ras_hw_enabled = adev->ras_enabled = 0;
c030f2e4 2455
38298ce6 2456 if (!amdgpu_ras_asic_supported(adev))
5caf466a 2457 return;
b404ae82 2458
38298ce6 2459 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
75f06251
HZ		 2460 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2461 dev_info(adev->dev, "MEM ECC is active.\n");
8ab0d6f0 2462 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
e509965e 2463 1 << AMDGPU_RAS_BLOCK__DF);
75f06251
HZ		 2464 } else {
2465 dev_info(adev->dev, "MEM ECC is not presented.\n");
2466 }
88474cca 2467
75f06251
HZ		 2468 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2469 dev_info(adev->dev, "SRAM ECC is active.\n");
3189501e 2470 if (!amdgpu_sriov_vf(adev))
950d6425
SY		 2471 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2472 1 << AMDGPU_RAS_BLOCK__DF);
3189501e 2473 else
950d6425
SY		 2474 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2475 1 << AMDGPU_RAS_BLOCK__SDMA |
2476 1 << AMDGPU_RAS_BLOCK__GFX);
3189501e
TZ		 2477
2478 /* VCN/JPEG RAS can be supported on both bare metal and
2479 * SRIOV environment
2480 */
2481 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2482 adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2483 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2484 1 << AMDGPU_RAS_BLOCK__JPEG);
2485 else
2486 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2487 1 << AMDGPU_RAS_BLOCK__JPEG);
58bc2a9c
SY		 2488
2489 /*
2490 * XGMI RAS is not supported if xgmi num physical nodes
2491 * is zero
2492 */
2493 if (!adev->gmc.xgmi.num_physical_nodes)
2494 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
75f06251
HZ		 2495 } else {
2496 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2497 }
2498 } else {
2499 /* driver only manages a few IP blocks RAS feature
2500 * when GPU is connected cpu through XGMI */
8ab0d6f0 2501 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
e509965e
LT		 2502 1 << AMDGPU_RAS_BLOCK__SDMA |
2503 1 << AMDGPU_RAS_BLOCK__MMHUB);
75f06251 2504 }
88474cca 2505
e509965e 2506 amdgpu_ras_get_quirks(adev);
f50160cf 2507
88474cca 2508 /* hw_supported needs to be aligned with RAS block mask. */
8ab0d6f0 2509 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
b404ae82 2510
276f6e8c
SY		 2511
2512 /*
2513 * Disable ras feature for aqua vanjaram
2514 * by default on apu platform.
2515 */
fcb7a184
SY		 2516 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6) &&
2517 adev->gmc.is_app_apu)
276f6e8c
SY		 2518 adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 :
2519 adev->ras_hw_enabled & amdgpu_ras_mask;
2520 else
2521 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2522 adev->ras_hw_enabled & amdgpu_ras_mask;
c030f2e4 2523}
2524
05adfd80
LT		 2525static void amdgpu_ras_counte_dw(struct work_struct *work)
2526{
2527 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2528 ras_counte_delay_work.work);
2529 struct amdgpu_device *adev = con->adev;
a3fbb0d8 2530 struct drm_device *dev = adev_to_drm(adev);
05adfd80
LT		 2531 unsigned long ce_count, ue_count;
2532 int res;
2533
2534 res = pm_runtime_get_sync(dev->dev);
2535 if (res < 0)
2536 goto Out;
2537
2538 /* Cache new values.
2539 */
4a1c9a44 2540 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
4d9f771e
LT		 2541 atomic_set(&con->ras_ce_count, ce_count);
2542 atomic_set(&con->ras_ue_count, ue_count);
2543 }
05adfd80
LT		 2544
2545 pm_runtime_mark_last_busy(dev->dev);
2546Out:
2547 pm_runtime_put_autosuspend(dev->dev);
2548}
2549
2dd9032b
TZ		 2550static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2551{
2552 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2553 bool df_poison, umc_poison;
2554
2555 /* poison setting is useless on SRIOV guest */
2556 if (amdgpu_sriov_vf(adev) || !con)
2557 return;
2558
2559 /* Init poison supported flag, the default value is false */
2560 if (adev->gmc.xgmi.connected_to_cpu) {
2561 /* enabled by default when GPU is connected to CPU */
2562 con->poison_supported = true;
2563 } else if (adev->df.funcs &&
2564 adev->df.funcs->query_ras_poison_mode &&
2565 adev->umc.ras &&
2566 adev->umc.ras->query_ras_poison_mode) {
2567 df_poison =
2568 adev->df.funcs->query_ras_poison_mode(adev);
2569 umc_poison =
2570 adev->umc.ras->query_ras_poison_mode(adev);
2571
2572 /* Only poison is set in both DF and UMC, we can support it */
2573 if (df_poison && umc_poison)
2574 con->poison_supported = true;
2575 else if (df_poison != umc_poison)
2576 dev_warn(adev->dev,
2577 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2578 df_poison, umc_poison);
2579 }
2580}
2581
c030f2e4 2582int amdgpu_ras_init(struct amdgpu_device *adev)
2583{
2584 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4e644fff 2585 int r;
c030f2e4 2586
b404ae82 2587 if (con)
c030f2e4 2588 return 0;
2589
2590 con = kmalloc(sizeof(struct amdgpu_ras) +
640ae42e
JC		 2591 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2592 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
c030f2e4 2593 GFP_KERNEL|__GFP_ZERO);
2594 if (!con)
2595 return -ENOMEM;
2596
05adfd80
LT		 2597 con->adev = adev;
2598 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2599 atomic_set(&con->ras_ce_count, 0);
2600 atomic_set(&con->ras_ue_count, 0);
2601
c030f2e4 2602 con->objs = (struct ras_manager *)(con + 1);
2603
2604 amdgpu_ras_set_context(adev, con);
2605
e509965e
LT		 2606 amdgpu_ras_check_supported(adev);
2607
7ddd9770 2608 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
970fd197
SY		 2609 /* set gfx block ras context feature for VEGA20 Gaming
2610 * send ras disable cmd to ras ta during ras late init.
2611 */
8ab0d6f0 2612 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
970fd197
SY		 2613 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2614
2615 return 0;
2616 }
2617
5e91160a 2618 r = 0;
5436ab94 2619 goto release_con;
fb2a3607
HZ		 2620 }
2621
69691c82 2622 con->update_channel_flag = false;
c030f2e4 2623 con->features = 0;
2624 INIT_LIST_HEAD(&con->head);
108c6a63 2625 /* Might need get this flag from vbios. */
2626 con->flags = RAS_DEFAULT_FLAGS;
c030f2e4 2627
6e36f231
HZ		 2628 /* initialize nbio ras function ahead of any other
2629 * ras functions so hardware fatal error interrupt
2630 * can be enabled as early as possible */
fdc94d3a
HZ		 2631 switch (adev->ip_versions[NBIO_HWIP][0]) {
2632 case IP_VERSION(7, 4, 0):
2633 case IP_VERSION(7, 4, 1):
2634 case IP_VERSION(7, 4, 4):
2635 if (!adev->gmc.xgmi.connected_to_cpu)
2e54fe5d 2636 adev->nbio.ras = &nbio_v7_4_ras;
6e36f231 2637 break;
9af357bc
HZ		 2638 case IP_VERSION(4, 3, 0):
2639 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2640 /* unlike other generation of nbio ras,
2641 * nbio v4_3 only support fatal error interrupt
2642 * to inform software that DF is freezed due to
2643 * system fatal error event. driver should not
2644 * enable nbio ras in such case. Instead,
2645 * check DF RAS */
2646 adev->nbio.ras = &nbio_v4_3_ras;
2647 break;
7692e1ee
TZ		 2648 case IP_VERSION(7, 9, 0):
2649 if (!adev->gmc.is_app_apu)
2650 adev->nbio.ras = &nbio_v7_9_ras;
2651 break;
6e36f231
HZ		 2652 default:
2653 /* nbio ras is not available */
2654 break;
2655 }
2656
fdc94d3a
HZ		 2657 /* nbio ras block needs to be enabled ahead of other ras blocks
2658 * to handle fatal error */
2659 r = amdgpu_nbio_ras_sw_init(adev);
2660 if (r)
2661 return r;
2662
2e54fe5d 2663 if (adev->nbio.ras &&
2664 adev->nbio.ras->init_ras_controller_interrupt) {
2665 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
4e644fff 2666 if (r)
5436ab94 2667 goto release_con;
4e644fff
HZ		 2668 }
2669
2e54fe5d 2670 if (adev->nbio.ras &&
2671 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2672 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
4e644fff 2673 if (r)
5436ab94 2674 goto release_con;
4e644fff
HZ		 2675 }
2676
2dd9032b 2677 amdgpu_ras_query_poison_mode(adev);
e4348849 2678
5e91160a
GC		 2679 if (amdgpu_ras_fs_init(adev)) {
2680 r = -EINVAL;
5436ab94 2681 goto release_con;
5e91160a 2682 }
c030f2e4 2683
6952e99c 2684 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
e509965e 2685 "hardware ability[%x] ras_mask[%x]\n",
8ab0d6f0 2686 adev->ras_hw_enabled, adev->ras_enabled);
e509965e 2687
c030f2e4 2688 return 0;
5436ab94 2689release_con:
c030f2e4 2690 amdgpu_ras_set_context(adev, NULL);
2691 kfree(con);
2692
5e91160a 2693 return r;
c030f2e4 2694}
2695
8f6368a9 2696int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
134d16d5 2697{
8107e499
HZ		 2698 if (adev->gmc.xgmi.connected_to_cpu ||
2699 adev->gmc.is_app_apu)
134d16d5
JC		 2700 return 1;
2701 return 0;
2702}
2703
2704static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2705 struct ras_common_if *ras_block)
2706{
2707 struct ras_query_if info = {
2708 .head = *ras_block,
2709 };
2710
2711 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2712 return 0;
2713
2714 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2715 DRM_WARN("RAS init harvest failure");
2716
2717 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2718 DRM_WARN("RAS init harvest reset failure");
2719
2720 return 0;
2721}
2722
e4348849
TZ		 2723bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2724{
2725 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2726
2727 if (!con)
2728 return false;
2729
2730 return con->poison_supported;
2731}
2732
b293e891 2733/* helper function to handle common stuff in ip late init phase */
563285c8 2734int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2735 struct ras_common_if *ras_block)
b293e891 2736{
29c9b6cd 2737 struct amdgpu_ras_block_object *ras_obj = NULL;
05adfd80 2738 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4a1c9a44 2739 struct ras_query_if *query_info;
05adfd80 2740 unsigned long ue_count, ce_count;
b293e891
HZ		 2741 int r;
2742
2743 /* disable RAS feature per IP block if it is not supported */
2744 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2745 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2746 return 0;
2747 }
2748
2749 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2750 if (r) {
9080a18f 2751 if (adev->in_suspend || amdgpu_in_reset(adev)) {
b293e891
HZ		 2752 /* in resume phase, if fail to enable ras,
2753 * clean up all ras fs nodes, and disable ras */
2754 goto cleanup;
2755 } else
2756 return r;
2757 }
2758
134d16d5
JC		 2759 /* check for errors on warm reset edc persisant supported ASIC */
2760 amdgpu_persistent_edc_harvesting(adev, ras_block);
2761
b293e891 2762 /* in resume phase, no need to create ras fs node */
53b3f8f4 2763 if (adev->in_suspend || amdgpu_in_reset(adev))
b293e891
HZ		 2764 return 0;
2765
563285c8 2766 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
36780606
TZ		 2767 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2768 (ras_obj->hw_ops->query_poison_status ||
2769 ras_obj->hw_ops->handle_poison_consumption))) {
9252d33d 2770 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
b293e891 2771 if (r)
779596ce 2772 goto cleanup;
b293e891
HZ		 2773 }
2774
f957138c
HZ		 2775 if (ras_obj->hw_ops &&
2776 (ras_obj->hw_ops->query_ras_error_count ||
2777 ras_obj->hw_ops->query_ras_error_status)) {
2778 r = amdgpu_ras_sysfs_create(adev, ras_block);
2779 if (r)
2780 goto interrupt;
b293e891 2781
f957138c
HZ		 2782 /* Those are the cached values at init.
2783 */
2784 query_info = kzalloc(sizeof(*query_info), GFP_KERNEL);
2785 if (!query_info)
2786 return -ENOMEM;
2787 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
4a1c9a44 2788
f957138c
HZ		 2789 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
2790 atomic_set(&con->ras_ce_count, ce_count);
2791 atomic_set(&con->ras_ue_count, ue_count);
2792 }
2793
2794 kfree(query_info);
4d9f771e 2795 }
05adfd80 2796
b293e891 2797 return 0;
779596ce
TR		 2798
2799interrupt:
563285c8 2800 if (ras_obj->ras_cb)
9252d33d 2801 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
779596ce 2802cleanup:
b293e891
HZ		 2803 amdgpu_ras_feature_enable(adev, ras_block, 0);
2804 return r;
2805}
2806
d41ff22a 2807static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
418abce2 2808 struct ras_common_if *ras_block)
2809{
2810 return amdgpu_ras_block_late_init(adev, ras_block);
2811}
2812
b293e891 2813/* helper function to remove ras fs node and interrupt handler */
bdb3489c 2814void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2815 struct ras_common_if *ras_block)
2816{
563285c8 2817 struct amdgpu_ras_block_object *ras_obj;
bdb3489c 2818 if (!ras_block)
2819 return;
2820
563285c8 2821 amdgpu_ras_sysfs_remove(adev, ras_block);
bdb3489c 2822
563285c8 2823 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2824 if (ras_obj->ras_cb)
2825 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
bdb3489c 2826}
2827
80e0c2cb 2828static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2829 struct ras_common_if *ras_block)
2830{
2831 return amdgpu_ras_block_late_fini(adev, ras_block);
2832}
2833
a564808e 2834/* do some init work after IP late init as dependence.
511fdbc3 2835 * and it runs in resume/gpu reset/booting up cases.
a564808e 2836 */
511fdbc3 2837void amdgpu_ras_resume(struct amdgpu_device *adev)
108c6a63 2838{
2839 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2840 struct ras_manager *obj, *tmp;
2841
8ab0d6f0 2842 if (!adev->ras_enabled || !con) {
970fd197
SY		 2843 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2844 amdgpu_release_ras_context(adev);
2845
108c6a63 2846 return;
970fd197 2847 }
108c6a63 2848
108c6a63 2849 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
191051a1 2850 /* Set up all other IPs which are not implemented. There is a
2851 * tricky thing that IP's actual ras error type should be
2852 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2853 * ERROR_NONE make sense anyway.
2854 */
2855 amdgpu_ras_enable_all_features(adev, 1);
2856
2857 /* We enable ras on all hw_supported block, but as boot
2858 * parameter might disable some of them and one or more IP has
2859 * not implemented yet. So we disable them on behalf.
2860 */
108c6a63 2861 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2862 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2863 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2864 /* there should be no any reference. */
2865 WARN_ON(alive_obj(obj));
2866 }
191051a1 2867 }
108c6a63 2868 }
2869}
2870
511fdbc3 2871void amdgpu_ras_suspend(struct amdgpu_device *adev)
2872{
2873 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2874
8ab0d6f0 2875 if (!adev->ras_enabled || !con)
511fdbc3 2876 return;
2877
2878 amdgpu_ras_disable_all_features(adev, 0);
2879 /* Make sure all ras objects are disabled. */
2880 if (con->features)
2881 amdgpu_ras_disable_all_features(adev, 1);
2882}
2883
867e24ca 2884int amdgpu_ras_late_init(struct amdgpu_device *adev)
2885{
2886 struct amdgpu_ras_block_list *node, *tmp;
2887 struct amdgpu_ras_block_object *obj;
2888 int r;
2889
950d6425
SY		 2890 /* Guest side doesn't need init ras feature */
2891 if (amdgpu_sriov_vf(adev))
2892 return 0;
2893
867e24ca 2894 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2895 if (!node->ras_obj) {
2896 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2897 continue;
2898 }
418abce2 2899
867e24ca 2900 obj = node->ras_obj;
2901 if (obj->ras_late_init) {
2902 r = obj->ras_late_init(adev, &obj->ras_comm);
2903 if (r) {
2904 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2905 obj->ras_comm.name, r);
2906 return r;
2907 }
418abce2 2908 } else
2909 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
867e24ca 2910 }
2911
2912 return 0;
2913}
2914
c030f2e4 2915/* do some fini work before IP fini as dependence */
2916int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2917{
2918 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2919
8ab0d6f0 2920 if (!adev->ras_enabled || !con)
c030f2e4 2921 return 0;
2922
72c8c97b 2923
c030f2e4 2924 /* Need disable ras on all IPs here before ip [hw/sw]fini */
642c0401
YC		 2925 if (con->features)
2926 amdgpu_ras_disable_all_features(adev, 0);
c030f2e4 2927 amdgpu_ras_recovery_fini(adev);
2928 return 0;
2929}
2930
2931int amdgpu_ras_fini(struct amdgpu_device *adev)
2932{
d5e8ff5f 2933 struct amdgpu_ras_block_list *ras_node, *tmp;
1f211a82 2934 struct amdgpu_ras_block_object *obj = NULL;
c030f2e4 2935 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2936
8ab0d6f0 2937 if (!adev->ras_enabled || !con)
c030f2e4 2938 return 0;
2939
1f211a82 2940 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2941 if (ras_node->ras_obj) {
2942 obj = ras_node->ras_obj;
2943 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2944 obj->ras_fini)
2945 obj->ras_fini(adev, &obj->ras_comm);
80e0c2cb 2946 else
2947 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
1f211a82 2948 }
2949
2950 /* Clear ras blocks from ras_list and free ras block list node */
2951 list_del(&ras_node->node);
2952 kfree(ras_node);
2953 }
2954
c030f2e4 2955 amdgpu_ras_fs_fini(adev);
2956 amdgpu_ras_interrupt_remove_all(adev);
2957
2958 WARN(con->features, "Feature mask is not cleared");
2959
2960 if (con->features)
2961 amdgpu_ras_disable_all_features(adev, 1);
2962
05adfd80
LT		 2963 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2964
c030f2e4 2965 amdgpu_ras_set_context(adev, NULL);
2966 kfree(con);
2967
2968 return 0;
2969}
7c6e68c7
AG		 2970
2971void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2972{
e509965e 2973 amdgpu_ras_check_supported(adev);
8ab0d6f0 2974 if (!adev->ras_hw_enabled)
ed606f8a
AG		 2975 return;
2976
7c6e68c7 2977 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
2c7cd280
YC		 2978 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2979
6952e99c
GC		 2980 dev_info(adev->dev, "uncorrectable hardware error"
2981 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
d5ea093e 2982
2c7cd280 2983 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET;
61934624 2984 amdgpu_ras_reset_gpu(adev);
7c6e68c7
AG		 2985 }
2986}
bb5c7235
WS		 2987
2988bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2989{
2990 if (adev->asic_type == CHIP_VEGA20 &&
2991 adev->pm.fw_version <= 0x283400) {
2992 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2993 amdgpu_ras_intr_triggered();
2994 }
2995
2996 return false;
2997}
970fd197
SY		 2998
2999void amdgpu_release_ras_context(struct amdgpu_device *adev)
3000{
3001 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
3002
3003 if (!con)
3004 return;
3005
8ab0d6f0 3006 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
970fd197
SY		 3007 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
3008 amdgpu_ras_set_context(adev, NULL);
3009 kfree(con);
3010 }
3011}
12b2cab7
MJ		 3012
3013#ifdef CONFIG_X86_MCE_AMD
3014static struct amdgpu_device *find_adev(uint32_t node_id)
3015{
12b2cab7
MJ		 3016 int i;
3017 struct amdgpu_device *adev = NULL;
3018
91a1a52d
MJ		 3019 for (i = 0; i < mce_adev_list.num_gpu; i++) {
3020 adev = mce_adev_list.devs[i];
12b2cab7 3021
91a1a52d 3022 if (adev && adev->gmc.xgmi.connected_to_cpu &&
12b2cab7
MJ		 3023 adev->gmc.xgmi.physical_node_id == node_id)
3024 break;
3025 adev = NULL;
3026 }
3027
12b2cab7
MJ		 3028 return adev;
3029}
3030
3031#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
3032#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
3033#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3034#define GPU_ID_OFFSET 8
3035
3036static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3037 unsigned long val, void *data)
3038{
3039 struct mce *m = (struct mce *)data;
3040 struct amdgpu_device *adev = NULL;
3041 uint32_t gpu_id = 0;
cd4c99f1 3042 uint32_t umc_inst = 0, ch_inst = 0;
12b2cab7
MJ		 3043
3044 /*
3045 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3046 * and error occurred in DramECC (Extended error code = 0) then only
3047 * process the error, else bail out.
3048 */
91f75eb4 3049 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
12b2cab7
MJ		 3050 (XEC(m->status, 0x3f) == 0x0)))
3051 return NOTIFY_DONE;
3052
3053 /*
3054 * If it is correctable error, return.
3055 */
3056 if (mce_is_correctable(m))
3057 return NOTIFY_OK;
3058
3059 /*
3060 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3061 */
3062 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3063
3064 adev = find_adev(gpu_id);
3065 if (!adev) {
3066 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3067 gpu_id);
3068 return NOTIFY_DONE;
3069 }
3070
3071 /*
3072 * If it is uncorrectable error, then find out UMC instance and
3073 * channel index.
3074 */
3075 umc_inst = GET_UMC_INST(m->ipid);
3076 ch_inst = GET_CHAN_INDEX(m->ipid);
3077
3078 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3079 umc_inst, ch_inst);
3080
24b82292
TZ		 3081 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3082 return NOTIFY_OK;
3083 else
6c0ca748 3084 return NOTIFY_DONE;
12b2cab7
MJ		 3085}
3086
3087static struct notifier_block amdgpu_bad_page_nb = {
3088 .notifier_call = amdgpu_bad_page_notifier,
3089 .priority = MCE_PRIO_UC,
3090};
3091
91a1a52d 3092static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
12b2cab7 3093{
91a1a52d
MJ		 3094 /*
3095 * Add the adev to the mce_adev_list.
3096 * During mode2 reset, amdgpu device is temporarily
3097 * removed from the mgpu_info list which can cause
3098 * page retirement to fail.
3099 * Use this list instead of mgpu_info to find the amdgpu
3100 * device on which the UMC error was reported.
3101 */
3102 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3103
12b2cab7
MJ		 3104 /*
3105 * Register the x86 notifier only once
3106 * with MCE subsystem.
3107 */
3108 if (notifier_registered == false) {
3109 mce_register_decode_chain(&amdgpu_bad_page_nb);
3110 notifier_registered = true;
3111 }
3112}
3113#endif
7cab2124 3114
b6efdb02 3115struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
7cab2124 3116{
3117 if (!adev)
3118 return NULL;
3119
3120 return adev->psp.ras_context.ras;
3121}
3122
b6efdb02 3123int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
7cab2124 3124{
3125 if (!adev)
69f91d32 3126 return -EINVAL;
7cab2124 3127
3128 adev->psp.ras_context.ras = ras_con;
3129 return 0;
3130}
3131
3132/* check if ras is supported on block, say, sdma, gfx */
3133int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3134 unsigned int block)
3135{
8f453c51 3136 int ret = 0;
7cab2124 3137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3138
3139 if (block >= AMDGPU_RAS_BLOCK_COUNT)
3140 return 0;
8f453c51
YC		 3141
3142 ret = ras && (adev->ras_enabled & (1 << block));
3143
3144 /* For the special asic with mem ecc enabled but sram ecc
3145 * not enabled, even if the ras block is not supported on
3146 * .ras_enabled, if the asic supports poison mode and the
3147 * ras block has ras configuration, it can be considered
3148 * that the ras block supports ras function.
3149 */
3150 if (!ret &&
62c4b772 3151 block == AMDGPU_RAS_BLOCK__GFX &&
8f453c51
YC		 3152 amdgpu_ras_is_poison_mode_supported(adev) &&
3153 amdgpu_ras_get_ras_block(adev, block, 0))
3154 ret = 1;
3155
3156 return ret;
7cab2124 3157}
3158
3159int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3160{
3161 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3162
3163 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
25a2b22e 3164 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
7cab2124 3165 return 0;
3166}
3167
3168
6492e1b0 3169/* Register each ip ras block into amdgpu ras */
3170int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
b6efdb02 3171 struct amdgpu_ras_block_object *ras_block_obj)
6492e1b0 3172{
d5e8ff5f 3173 struct amdgpu_ras_block_list *ras_node;
6492e1b0 3174 if (!adev || !ras_block_obj)
3175 return -EINVAL;
3176
d5e8ff5f 3177 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3178 if (!ras_node)
3179 return -ENOMEM;
3180
3181 INIT_LIST_HEAD(&ras_node->node);
3182 ras_node->ras_obj = ras_block_obj;
3183 list_add_tail(&ras_node->node, &adev->ras_list);
6492e1b0 3184
3185 return 0;
3186}
322a7e00
HZ		 3187
3188void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3189{
3190 if (!err_type_name)
3191 return;
3192
3193 switch (err_type) {
3194 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3195 sprintf(err_type_name, "correctable");
3196 break;
3197 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3198 sprintf(err_type_name, "uncorrectable");
3199 break;
3200 default:
3201 sprintf(err_type_name, "unknown");
3202 break;
3203 }
3204}
3205
3206bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3207 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3208 uint32_t instance,
3209 uint32_t *memory_id)
3210{
3211 uint32_t err_status_lo_data, err_status_lo_offset;
3212
3213 if (!reg_entry)
3214 return false;
3215
3216 err_status_lo_offset =
3217 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3218 reg_entry->seg_lo, reg_entry->reg_lo);
3219 err_status_lo_data = RREG32(err_status_lo_offset);
3220
3221 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3222 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3223 return false;
3224
3225 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3226
3227 return true;
3228}
3229
3230bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3231 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3232 uint32_t instance,
3233 unsigned long *err_cnt)
3234{
3235 uint32_t err_status_hi_data, err_status_hi_offset;
3236
3237 if (!reg_entry)
3238 return false;
3239
3240 err_status_hi_offset =
3241 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3242 reg_entry->seg_hi, reg_entry->reg_hi);
3243 err_status_hi_data = RREG32(err_status_hi_offset);
3244
3245 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3246 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
9b337b7d
HZ		 3247 /* keep the check here in case we need to refer to the result later */
3248 dev_dbg(adev->dev, "Invalid err_info field\n");
322a7e00
HZ		 3249
3250 /* read err count */
3251 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3252
3253 return true;
3254}
3255
3256void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3257 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3258 uint32_t reg_list_size,
3259 const struct amdgpu_ras_memory_id_entry *mem_list,
3260 uint32_t mem_list_size,
3261 uint32_t instance,
3262 uint32_t err_type,
3263 unsigned long *err_count)
3264{
3265 uint32_t memory_id;
3266 unsigned long err_cnt;
3267 char err_type_name[16];
3268 uint32_t i, j;
3269
3270 for (i = 0; i < reg_list_size; i++) {
9b337b7d
HZ		 3271 /* query memory_id from err_status_lo */
3272 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3273 instance, &memory_id))
3274 continue;
3275
322a7e00
HZ		 3276 /* query err_cnt from err_status_hi */
3277 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3278 instance, &err_cnt) ||
3279 !err_cnt)
3280 continue;
3281
322a7e00
HZ		 3282 *err_count += err_cnt;
3283
3284 /* log the errors */
3285 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3286 if (!mem_list) {
3287 /* memory_list is not supported */
3288 dev_info(adev->dev,
3289 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3290 err_cnt, err_type_name,
3291 reg_list[i].block_name,
3292 instance, memory_id);
3293 } else {
3294 for (j = 0; j < mem_list_size; j++) {
3295 if (memory_id == mem_list[j].memory_id) {
3296 dev_info(adev->dev,
3297 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3298 err_cnt, err_type_name,
3299 reg_list[i].block_name,
3300 instance, mem_list[j].name);
3301 break;
3302 }
3303 }
3304 }
3305 }
3306}
e53a3250
HZ		 3307
3308void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3309 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3310 uint32_t reg_list_size,
3311 uint32_t instance)
3312{
3313 uint32_t err_status_lo_offset, err_status_hi_offset;
3314 uint32_t i;
3315
3316 for (i = 0; i < reg_list_size; i++) {
3317 err_status_lo_offset =
3318 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3319 reg_list[i].seg_lo, reg_list[i].reg_lo);
3320 err_status_hi_offset =
3321 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3322 reg_list[i].seg_hi, reg_list[i].reg_hi);
3323 WREG32(err_status_lo_offset, 0);
3324 WREG32(err_status_hi_offset, 0);
3325 }
3326}
Linux 6.x block layer and io_uring tree(s)