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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
9af357bc | 37 | #include "nbio_v4_3.h" |
7692e1ee | 38 | #include "nbio_v7_9.h" |
f50160cf | 39 | #include "atom.h" |
25a2b22e AG |
40 | #include "amdgpu_reset.h" |
41 | ||
12b2cab7 MJ |
42 | #ifdef CONFIG_X86_MCE_AMD |
43 | #include <asm/mce.h> | |
c030f2e4 | 44 | |
12b2cab7 MJ |
45 | static bool notifier_registered; |
46 | #endif | |
eb0c3cd4 GC |
47 | static const char *RAS_FS_NAME = "ras"; |
48 | ||
c030f2e4 | 49 | const char *ras_error_string[] = { |
50 | "none", | |
51 | "parity", | |
52 | "single_correctable", | |
53 | "multi_uncorrectable", | |
54 | "poison", | |
55 | }; | |
56 | ||
57 | const char *ras_block_string[] = { | |
58 | "umc", | |
59 | "sdma", | |
60 | "gfx", | |
61 | "mmhub", | |
62 | "athub", | |
63 | "pcie_bif", | |
64 | "hdp", | |
65 | "xgmi_wafl", | |
66 | "df", | |
67 | "smn", | |
68 | "sem", | |
69 | "mp0", | |
70 | "mp1", | |
71 | "fuse", | |
640ae42e | 72 | "mca", |
a3d63c62 MZZ |
73 | "vcn", |
74 | "jpeg", | |
c030f2e4 | 75 | }; |
76 | ||
640ae42e JC |
77 | const char *ras_mca_block_string[] = { |
78 | "mca_mp0", | |
79 | "mca_mp1", | |
80 | "mca_mpio", | |
81 | "mca_iohc", | |
82 | }; | |
83 | ||
d5e8ff5f | 84 | struct amdgpu_ras_block_list { |
85 | /* ras block link */ | |
86 | struct list_head node; | |
87 | ||
88 | struct amdgpu_ras_block_object *ras_obj; | |
89 | }; | |
90 | ||
640ae42e JC |
91 | const char *get_ras_block_str(struct ras_common_if *ras_block) |
92 | { | |
93 | if (!ras_block) | |
94 | return "NULL"; | |
95 | ||
96 | if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) | |
97 | return "OUT OF RANGE"; | |
98 | ||
99 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) | |
100 | return ras_mca_block_string[ras_block->sub_block_index]; | |
101 | ||
102 | return ras_block_string[ras_block->block]; | |
103 | } | |
104 | ||
954ea6aa | 105 | #define ras_block_str(_BLOCK_) \ |
106 | (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") | |
8b0fb0e9 | 107 | |
c030f2e4 | 108 | #define ras_err_str(i) (ras_error_string[ffs(i)]) |
c030f2e4 | 109 | |
108c6a63 | 110 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
111 | ||
7cdc2ee3 TZ |
112 | /* inject address is 52 bits */ |
113 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
114 | ||
e4e6a589 LT |
115 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
116 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) | |
c84d4670 | 117 | |
52dd95f2 GC |
118 | enum amdgpu_ras_retire_page_reservation { |
119 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
120 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
121 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
122 | }; | |
7c6e68c7 AG |
123 | |
124 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
125 | ||
676deb38 DL |
126 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
127 | uint64_t addr); | |
6e4be987 TZ |
128 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
129 | uint64_t addr); | |
12b2cab7 | 130 | #ifdef CONFIG_X86_MCE_AMD |
91a1a52d MJ |
131 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); |
132 | struct mce_notifier_adev_list { | |
133 | struct amdgpu_device *devs[MAX_GPU_INSTANCE]; | |
134 | int num_gpu; | |
135 | }; | |
136 | static struct mce_notifier_adev_list mce_adev_list; | |
12b2cab7 | 137 | #endif |
6e4be987 | 138 | |
61380faa JC |
139 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
140 | { | |
a9d82d2f | 141 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
142 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
143 | } | |
144 | ||
f3167919 | 145 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 146 | { |
a9d82d2f | 147 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
148 | return amdgpu_ras_get_context(adev)->error_query_ready; |
149 | ||
150 | return false; | |
151 | } | |
152 | ||
cbb8f989 JC |
153 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
154 | { | |
5b1270be | 155 | struct ras_err_data err_data; |
cbb8f989 | 156 | struct eeprom_table_record err_rec; |
5b1270be | 157 | int ret; |
cbb8f989 JC |
158 | |
159 | if ((address >= adev->gmc.mc_vram_size) || | |
160 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
161 | dev_warn(adev->dev, | |
162 | "RAS WARN: input address 0x%llx is invalid.\n", | |
163 | address); | |
164 | return -EINVAL; | |
165 | } | |
166 | ||
167 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
168 | dev_warn(adev->dev, | |
80b0cd0f | 169 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
170 | address); |
171 | return 0; | |
172 | } | |
173 | ||
5b1270be YW |
174 | ret = amdgpu_ras_error_data_init(&err_data); |
175 | if (ret) | |
176 | return ret; | |
177 | ||
cbb8f989 | 178 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); |
cbb8f989 | 179 | err_data.err_addr = &err_rec; |
71344a71 | 180 | amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0); |
cbb8f989 JC |
181 | |
182 | if (amdgpu_bad_page_threshold != 0) { | |
183 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
184 | err_data.err_addr_cnt); | |
4d33e0f1 | 185 | amdgpu_ras_save_bad_pages(adev, NULL); |
cbb8f989 JC |
186 | } |
187 | ||
5b1270be YW |
188 | amdgpu_ras_error_data_fini(&err_data); |
189 | ||
cbb8f989 JC |
190 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); |
191 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
192 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
c030f2e4 | 197 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
198 | size_t size, loff_t *pos) | |
199 | { | |
200 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
201 | struct ras_query_if info = { | |
202 | .head = obj->head, | |
203 | }; | |
204 | ssize_t s; | |
205 | char val[128]; | |
206 | ||
761d86d3 | 207 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 208 | return -EINVAL; |
209 | ||
2a460963 | 210 | /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */ |
4e8303cf LL |
211 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
212 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
2a460963 CL |
213 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
214 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); | |
215 | } | |
216 | ||
c030f2e4 | 217 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", |
218 | "ue", info.ue_count, | |
219 | "ce", info.ce_count); | |
220 | if (*pos >= s) | |
221 | return 0; | |
222 | ||
223 | s -= *pos; | |
224 | s = min_t(u64, s, size); | |
225 | ||
226 | ||
227 | if (copy_to_user(buf, &val[*pos], s)) | |
228 | return -EINVAL; | |
229 | ||
230 | *pos += s; | |
231 | ||
232 | return s; | |
233 | } | |
234 | ||
c030f2e4 | 235 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
236 | .owner = THIS_MODULE, | |
237 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 238 | .write = NULL, |
c030f2e4 | 239 | .llseek = default_llseek |
240 | }; | |
241 | ||
96ebb307 | 242 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
243 | { | |
244 | int i; | |
245 | ||
246 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
247 | *block_id = i; | |
640ae42e | 248 | if (strcmp(name, ras_block_string[i]) == 0) |
96ebb307 | 249 | return 0; |
250 | } | |
251 | return -EINVAL; | |
252 | } | |
253 | ||
254 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
255 | const char __user *buf, size_t size, | |
256 | loff_t *pos, struct ras_debug_if *data) | |
257 | { | |
258 | ssize_t s = min_t(u64, 64, size); | |
259 | char str[65]; | |
260 | char block_name[33]; | |
261 | char err[9] = "ue"; | |
262 | int op = -1; | |
263 | int block_id; | |
44494f96 | 264 | uint32_t sub_block; |
96ebb307 | 265 | u64 address, value; |
2c22ed0b TZ |
266 | /* default value is 0 if the mask is not set by user */ |
267 | u32 instance_mask = 0; | |
96ebb307 | 268 | |
269 | if (*pos) | |
270 | return -EINVAL; | |
271 | *pos = size; | |
272 | ||
273 | memset(str, 0, sizeof(str)); | |
274 | memset(data, 0, sizeof(*data)); | |
275 | ||
276 | if (copy_from_user(str, buf, s)) | |
277 | return -EINVAL; | |
278 | ||
279 | if (sscanf(str, "disable %32s", block_name) == 1) | |
280 | op = 0; | |
281 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
282 | op = 1; | |
283 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
284 | op = 2; | |
6df23f4c | 285 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 286 | op = 3; |
b076296b | 287 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 288 | /* ascii string, but commands are not matched. */ |
289 | return -EINVAL; | |
290 | ||
291 | if (op != -1) { | |
cbb8f989 | 292 | if (op == 3) { |
546aa546 LT |
293 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
294 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 295 | return -EINVAL; |
cbb8f989 JC |
296 | |
297 | data->op = op; | |
298 | data->inject.address = address; | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
96ebb307 | 303 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
304 | return -EINVAL; | |
305 | ||
306 | data->head.block = block_id; | |
e1063493 TZ |
307 | /* only ue and ce errors are supported */ |
308 | if (!memcmp("ue", err, 2)) | |
309 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
310 | else if (!memcmp("ce", err, 2)) | |
311 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
312 | else | |
313 | return -EINVAL; | |
314 | ||
96ebb307 | 315 | data->op = op; |
316 | ||
317 | if (op == 2) { | |
2c22ed0b TZ |
318 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x", |
319 | &sub_block, &address, &value, &instance_mask) != 4 && | |
320 | sscanf(str, "%*s %*s %*s %u %llu %llu %u", | |
321 | &sub_block, &address, &value, &instance_mask) != 4 && | |
322 | sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
546aa546 LT |
323 | &sub_block, &address, &value) != 3 && |
324 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
325 | &sub_block, &address, &value) != 3) |
326 | return -EINVAL; | |
44494f96 | 327 | data->head.sub_block_index = sub_block; |
96ebb307 | 328 | data->inject.address = address; |
329 | data->inject.value = value; | |
2c22ed0b | 330 | data->inject.instance_mask = instance_mask; |
96ebb307 | 331 | } |
332 | } else { | |
73aa8e1a | 333 | if (size < sizeof(*data)) |
96ebb307 | 334 | return -EINVAL; |
335 | ||
336 | if (copy_from_user(data, buf, sizeof(*data))) | |
337 | return -EINVAL; | |
338 | } | |
339 | ||
340 | return 0; | |
341 | } | |
7c6e68c7 | 342 | |
f464c5dd TZ |
343 | static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev, |
344 | struct ras_debug_if *data) | |
345 | { | |
346 | int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; | |
347 | uint32_t mask, inst_mask = data->inject.instance_mask; | |
348 | ||
349 | /* no need to set instance mask if there is only one instance */ | |
350 | if (num_xcc <= 1 && inst_mask) { | |
351 | data->inject.instance_mask = 0; | |
352 | dev_dbg(adev->dev, | |
353 | "RAS inject mask(0x%x) isn't supported and force it to 0.\n", | |
354 | inst_mask); | |
355 | ||
356 | return; | |
357 | } | |
358 | ||
359 | switch (data->head.block) { | |
360 | case AMDGPU_RAS_BLOCK__GFX: | |
361 | mask = GENMASK(num_xcc - 1, 0); | |
362 | break; | |
363 | case AMDGPU_RAS_BLOCK__SDMA: | |
364 | mask = GENMASK(adev->sdma.num_instances - 1, 0); | |
365 | break; | |
e3959cb5 SY |
366 | case AMDGPU_RAS_BLOCK__VCN: |
367 | case AMDGPU_RAS_BLOCK__JPEG: | |
368 | mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); | |
369 | break; | |
f464c5dd | 370 | default: |
e3959cb5 | 371 | mask = inst_mask; |
f464c5dd TZ |
372 | break; |
373 | } | |
374 | ||
375 | /* remove invalid bits in instance mask */ | |
376 | data->inject.instance_mask &= mask; | |
377 | if (inst_mask != data->inject.instance_mask) | |
378 | dev_dbg(adev->dev, | |
379 | "Adjust RAS inject mask 0x%x to 0x%x\n", | |
380 | inst_mask, data->inject.instance_mask); | |
381 | } | |
382 | ||
74abc221 TSD |
383 | /** |
384 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 385 | * |
737c375b | 386 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 387 | * |
388 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 389 | * |
390 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 391 | * |
392 | * head has four members, they are block, type, sub_block_index, name. | |
393 | * block: which IP will be under control. | |
394 | * type: what kind of error will be enabled/disabled/injected. | |
395 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
396 | * name: the name of IP. | |
397 | * | |
2c22ed0b | 398 | * inject has three more members than head, they are address, value and mask. |
36ea1bd2 | 399 | * As their names indicate, inject operation will write the |
400 | * value to the address. | |
401 | * | |
ef177d11 | 402 | * The second member: struct ras_debug_if::op. |
c688a06b | 403 | * It has three kinds of operations. |
879e723d AZ |
404 | * |
405 | * - 0: disable RAS on the block. Take ::head as its data. | |
406 | * - 1: enable RAS on the block. Take ::head as its data. | |
407 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 408 | * |
96ebb307 | 409 | * How to use the interface? |
ef177d11 | 410 | * |
737c375b | 411 | * In a program |
ef177d11 | 412 | * |
737c375b LT |
413 | * Copy the struct ras_debug_if in your code and initialize it. |
414 | * Write the struct to the control interface. | |
ef177d11 | 415 | * |
737c375b | 416 | * From shell |
96ebb307 | 417 | * |
879e723d AZ |
418 | * .. code-block:: bash |
419 | * | |
737c375b LT |
420 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
421 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
2c22ed0b | 422 | * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
879e723d | 423 | * |
737c375b | 424 | * Where N, is the card which you want to affect. |
ef177d11 | 425 | * |
737c375b LT |
426 | * "disable" requires only the block. |
427 | * "enable" requires the block and error type. | |
428 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 429 | * |
737c375b | 430 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 431 | * see ras_block_string[] for details |
c666bbf0 | 432 | * |
737c375b LT |
433 | * The error type is one of: ue, ce, where, |
434 | * ue is multi-uncorrectable | |
435 | * ce is single-correctable | |
c666bbf0 | 436 | * |
737c375b LT |
437 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
438 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
2c22ed0b | 439 | * The mask means instance mask, is optional, default value is 0x1. |
879e723d | 440 | * |
737c375b | 441 | * For instance, |
879e723d AZ |
442 | * |
443 | * .. code-block:: bash | |
96ebb307 | 444 | * |
44494f96 | 445 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
2c22ed0b | 446 | * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
96ebb307 | 447 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
448 | * | |
737c375b | 449 | * How to check the result of the operation? |
36ea1bd2 | 450 | * |
737c375b | 451 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 452 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
453 | * | |
737c375b LT |
454 | * To check inject, see the corresponding error count at, |
455 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 456 | * |
879e723d | 457 | * .. note:: |
ef177d11 | 458 | * Operations are only allowed on blocks which are supported. |
737c375b | 459 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
460 | * to see which blocks support RAS on a particular asic. |
461 | * | |
36ea1bd2 | 462 | */ |
cf696091 LT |
463 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
464 | const char __user *buf, | |
465 | size_t size, loff_t *pos) | |
36ea1bd2 | 466 | { |
467 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
468 | struct ras_debug_if data; | |
469 | int ret = 0; | |
470 | ||
61380faa | 471 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
472 | dev_warn(adev->dev, "RAS WARN: error injection " |
473 | "currently inaccessible\n"); | |
43c4d576 JC |
474 | return size; |
475 | } | |
476 | ||
96ebb307 | 477 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
478 | if (ret) | |
cf696091 | 479 | return ret; |
36ea1bd2 | 480 | |
80b0cd0f | 481 | if (data.op == 3) { |
cbb8f989 | 482 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 483 | if (!ret) |
cbb8f989 JC |
484 | return size; |
485 | else | |
486 | return ret; | |
487 | } | |
488 | ||
36ea1bd2 | 489 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
490 | return -EINVAL; | |
491 | ||
492 | switch (data.op) { | |
493 | case 0: | |
494 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
495 | break; | |
496 | case 1: | |
497 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
498 | break; | |
499 | case 2: | |
43aedbf4 SY |
500 | if ((data.inject.address >= adev->gmc.mc_vram_size && |
501 | adev->gmc.mc_vram_size) || | |
7cdc2ee3 | 502 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { |
b0d4783a GC |
503 | dev_warn(adev->dev, "RAS WARN: input address " |
504 | "0x%llx is invalid.", | |
505 | data.inject.address); | |
7cdc2ee3 TZ |
506 | ret = -EINVAL; |
507 | break; | |
508 | } | |
509 | ||
6e4be987 TZ |
510 | /* umc ce/ue error injection for a bad page is not allowed */ |
511 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
512 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
c65b0805 LT |
513 | dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " |
514 | "already been marked as bad!\n", | |
515 | data.inject.address); | |
6e4be987 TZ |
516 | break; |
517 | } | |
518 | ||
f464c5dd TZ |
519 | amdgpu_ras_instance_mask_check(adev, &data); |
520 | ||
7cdc2ee3 | 521 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 522 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
523 | break; | |
96ebb307 | 524 | default: |
525 | ret = -EINVAL; | |
526 | break; | |
374bf7bd | 527 | } |
36ea1bd2 | 528 | |
529 | if (ret) | |
79c04621 | 530 | return ret; |
36ea1bd2 | 531 | |
532 | return size; | |
533 | } | |
534 | ||
084fe13b AG |
535 | /** |
536 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
537 | * | |
f77c7109 | 538 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 539 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
540 | * a way to reset the EEPROM, e.g., after testing error injection. |
541 | * | |
542 | * Usage: | |
543 | * | |
544 | * .. code-block:: bash | |
545 | * | |
546 | * echo 1 > ../ras/ras_eeprom_reset | |
547 | * | |
548 | * will reset EEPROM table to 0 entries. | |
549 | * | |
084fe13b | 550 | */ |
cf696091 LT |
551 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
552 | const char __user *buf, | |
553 | size_t size, loff_t *pos) | |
084fe13b | 554 | { |
bf0b91b7 GC |
555 | struct amdgpu_device *adev = |
556 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
557 | int ret; |
558 | ||
bf0b91b7 | 559 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 560 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 561 | |
63d4c081 | 562 | if (!ret) { |
cf696091 LT |
563 | /* Something was written to EEPROM. |
564 | */ | |
bf0b91b7 GC |
565 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
566 | return size; | |
567 | } else { | |
cf696091 | 568 | return ret; |
bf0b91b7 | 569 | } |
084fe13b AG |
570 | } |
571 | ||
36ea1bd2 | 572 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
573 | .owner = THIS_MODULE, | |
574 | .read = NULL, | |
575 | .write = amdgpu_ras_debugfs_ctrl_write, | |
576 | .llseek = default_llseek | |
577 | }; | |
578 | ||
084fe13b AG |
579 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
580 | .owner = THIS_MODULE, | |
581 | .read = NULL, | |
582 | .write = amdgpu_ras_debugfs_eeprom_write, | |
583 | .llseek = default_llseek | |
584 | }; | |
585 | ||
f77c7109 AD |
586 | /** |
587 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
588 | * | |
ef177d11 | 589 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
590 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
591 | * | |
592 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
593 | * (ce) error counts. | |
594 | * | |
595 | * The format of one line is below, | |
596 | * | |
597 | * [ce|ue]: count | |
598 | * | |
599 | * Example: | |
600 | * | |
601 | * .. code-block:: bash | |
602 | * | |
603 | * ue: 0 | |
604 | * ce: 1 | |
605 | * | |
606 | */ | |
c030f2e4 | 607 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
608 | struct device_attribute *attr, char *buf) | |
609 | { | |
610 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
611 | struct ras_query_if info = { | |
612 | .head = obj->head, | |
613 | }; | |
614 | ||
61380faa | 615 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 616 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 617 | |
761d86d3 | 618 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 619 | return -EINVAL; |
620 | ||
4e8303cf LL |
621 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
622 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
1f0d8e37 | 623 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
2a460963 | 624 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); |
1f0d8e37 MJ |
625 | } |
626 | ||
36000c7a TT |
627 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
628 | "ce", info.ce_count); | |
c030f2e4 | 629 | } |
630 | ||
631 | /* obj begin */ | |
632 | ||
633 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
634 | #define alive_obj(obj) ((obj)->use) | |
635 | ||
636 | static inline void put_obj(struct ras_manager *obj) | |
637 | { | |
f0872686 | 638 | if (obj && (--obj->use == 0)) |
c030f2e4 | 639 | list_del(&obj->node); |
f0872686 | 640 | if (obj && (obj->use < 0)) |
640ae42e | 641 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); |
c030f2e4 | 642 | } |
643 | ||
644 | /* make one obj and return it. */ | |
645 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
646 | struct ras_common_if *head) | |
647 | { | |
648 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
649 | struct ras_manager *obj; | |
650 | ||
8ab0d6f0 | 651 | if (!adev->ras_enabled || !con) |
c030f2e4 | 652 | return NULL; |
653 | ||
654 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
655 | return NULL; | |
656 | ||
640ae42e JC |
657 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
658 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
659 | return NULL; | |
660 | ||
661 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
662 | } else | |
663 | obj = &con->objs[head->block]; | |
664 | ||
c030f2e4 | 665 | /* already exist. return obj? */ |
666 | if (alive_obj(obj)) | |
667 | return NULL; | |
668 | ||
669 | obj->head = *head; | |
670 | obj->adev = adev; | |
671 | list_add(&obj->node, &con->head); | |
672 | get_obj(obj); | |
673 | ||
674 | return obj; | |
675 | } | |
676 | ||
677 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 678 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 679 | struct ras_common_if *head) |
680 | { | |
681 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
682 | struct ras_manager *obj; | |
683 | int i; | |
684 | ||
8ab0d6f0 | 685 | if (!adev->ras_enabled || !con) |
c030f2e4 | 686 | return NULL; |
687 | ||
688 | if (head) { | |
689 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
690 | return NULL; | |
691 | ||
640ae42e JC |
692 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
693 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
694 | return NULL; | |
695 | ||
696 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
697 | } else | |
698 | obj = &con->objs[head->block]; | |
c030f2e4 | 699 | |
640ae42e | 700 | if (alive_obj(obj)) |
c030f2e4 | 701 | return obj; |
c030f2e4 | 702 | } else { |
640ae42e | 703 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { |
c030f2e4 | 704 | obj = &con->objs[i]; |
640ae42e | 705 | if (alive_obj(obj)) |
c030f2e4 | 706 | return obj; |
c030f2e4 | 707 | } |
708 | } | |
709 | ||
710 | return NULL; | |
711 | } | |
712 | /* obj end */ | |
713 | ||
714 | /* feature ctl begin */ | |
715 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 716 | struct ras_common_if *head) |
c030f2e4 | 717 | { |
8ab0d6f0 | 718 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 719 | } |
720 | ||
721 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
722 | struct ras_common_if *head) | |
723 | { | |
724 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
725 | ||
726 | return con->features & BIT(head->block); | |
727 | } | |
728 | ||
729 | /* | |
730 | * if obj is not created, then create one. | |
731 | * set feature enable flag. | |
732 | */ | |
733 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
734 | struct ras_common_if *head, int enable) | |
735 | { | |
736 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
737 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
738 | ||
5caf466a | 739 | /* If hardware does not support ras, then do not create obj. |
740 | * But if hardware support ras, we can create the obj. | |
741 | * Ras framework checks con->hw_supported to see if it need do | |
742 | * corresponding initialization. | |
743 | * IP checks con->support to see if it need disable ras. | |
744 | */ | |
c030f2e4 | 745 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
746 | return 0; | |
c030f2e4 | 747 | |
748 | if (enable) { | |
749 | if (!obj) { | |
750 | obj = amdgpu_ras_create_obj(adev, head); | |
751 | if (!obj) | |
752 | return -EINVAL; | |
753 | } else { | |
754 | /* In case we create obj somewhere else */ | |
755 | get_obj(obj); | |
756 | } | |
757 | con->features |= BIT(head->block); | |
758 | } else { | |
759 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 760 | con->features &= ~BIT(head->block); |
c030f2e4 | 761 | put_obj(obj); |
762 | } | |
763 | } | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | /* wrapper of psp_ras_enable_features */ | |
769 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
770 | struct ras_common_if *head, bool enable) | |
771 | { | |
772 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 773 | union ta_ras_cmd_input *info; |
bf7aa8be | 774 | int ret; |
c030f2e4 | 775 | |
776 | if (!con) | |
777 | return -EINVAL; | |
778 | ||
ec70578c HZ |
779 | /* For non-gfx ip, do not enable ras feature if it is not allowed */ |
780 | /* For gfx ip, regardless of feature support status, */ | |
781 | /* Force issue enable or disable ras feature commands */ | |
782 | if (head->block != AMDGPU_RAS_BLOCK__GFX && | |
6fc9d92c | 783 | !amdgpu_ras_is_feature_allowed(adev, head)) |
bf7aa8be | 784 | return 0; |
6fc9d92c HZ |
785 | |
786 | /* Only enable gfx ras feature from host side */ | |
787 | if (head->block == AMDGPU_RAS_BLOCK__GFX && | |
788 | !amdgpu_sriov_vf(adev) && | |
789 | !amdgpu_ras_intr_triggered()) { | |
26093ce1 SY |
790 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
791 | if (!info) | |
792 | return -ENOMEM; | |
793 | ||
794 | if (!enable) { | |
795 | info->disable_features = (struct ta_ras_disable_features_input) { | |
796 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
797 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
798 | }; | |
799 | } else { | |
800 | info->enable_features = (struct ta_ras_enable_features_input) { | |
801 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
802 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
803 | }; | |
804 | } | |
c030f2e4 | 805 | |
7fcffecf | 806 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 807 | if (ret) { |
e4348849 | 808 | dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", |
011907fd | 809 | enable ? "enable":"disable", |
640ae42e | 810 | get_ras_block_str(head), |
e4348849 | 811 | amdgpu_ras_is_poison_mode_supported(adev), ret); |
5838f74c | 812 | kfree(info); |
bf7aa8be | 813 | return ret; |
bff77e86 | 814 | } |
bf7aa8be HZ |
815 | |
816 | kfree(info); | |
c030f2e4 | 817 | } |
818 | ||
819 | /* setup the obj */ | |
820 | __amdgpu_ras_feature_enable(adev, head, enable); | |
bf7aa8be HZ |
821 | |
822 | return 0; | |
c030f2e4 | 823 | } |
824 | ||
77de502b | 825 | /* Only used in device probe stage and called only once. */ |
826 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
827 | struct ras_common_if *head, bool enable) | |
828 | { | |
829 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
830 | int ret; | |
831 | ||
832 | if (!con) | |
833 | return -EINVAL; | |
834 | ||
835 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 836 | if (enable) { |
837 | /* There is no harm to issue a ras TA cmd regardless of | |
838 | * the currecnt ras state. | |
839 | * If current state == target state, it will do nothing | |
840 | * But sometimes it requests driver to reset and repost | |
841 | * with error code -EAGAIN. | |
842 | */ | |
843 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
844 | /* With old ras TA, we might fail to enable ras. | |
845 | * Log it and just setup the object. | |
846 | * TODO need remove this WA in the future. | |
847 | */ | |
848 | if (ret == -EINVAL) { | |
849 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
850 | if (!ret) | |
6952e99c GC |
851 | dev_info(adev->dev, |
852 | "RAS INFO: %s setup object\n", | |
640ae42e | 853 | get_ras_block_str(head)); |
7af23ebe | 854 | } |
855 | } else { | |
856 | /* setup the object then issue a ras TA disable cmd.*/ | |
857 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
858 | if (ret) | |
859 | return ret; | |
77de502b | 860 | |
970fd197 SY |
861 | /* gfx block ras dsiable cmd must send to ras-ta */ |
862 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
863 | con->features |= BIT(head->block); | |
864 | ||
77de502b | 865 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
866 | |
867 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 868 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 869 | con->features &= ~BIT(head->block); |
7af23ebe | 870 | } |
77de502b | 871 | } else |
872 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
873 | ||
874 | return ret; | |
875 | } | |
876 | ||
c030f2e4 | 877 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
878 | bool bypass) | |
879 | { | |
880 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
881 | struct ras_manager *obj, *tmp; | |
882 | ||
883 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
884 | /* bypass psp. | |
885 | * aka just release the obj and corresponding flags | |
886 | */ | |
887 | if (bypass) { | |
888 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
889 | break; | |
890 | } else { | |
891 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
892 | break; | |
893 | } | |
289d513b | 894 | } |
c030f2e4 | 895 | |
896 | return con->features; | |
897 | } | |
898 | ||
899 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
900 | bool bypass) | |
901 | { | |
902 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 903 | int i; |
640ae42e | 904 | const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; |
c030f2e4 | 905 | |
640ae42e | 906 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { |
c030f2e4 | 907 | struct ras_common_if head = { |
908 | .block = i, | |
191051a1 | 909 | .type = default_ras_type, |
c030f2e4 | 910 | .sub_block_index = 0, |
911 | }; | |
640ae42e JC |
912 | |
913 | if (i == AMDGPU_RAS_BLOCK__MCA) | |
914 | continue; | |
915 | ||
916 | if (bypass) { | |
917 | /* | |
918 | * bypass psp. vbios enable ras for us. | |
919 | * so just create the obj | |
920 | */ | |
921 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
922 | break; | |
923 | } else { | |
924 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
925 | break; | |
926 | } | |
927 | } | |
928 | ||
929 | for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { | |
930 | struct ras_common_if head = { | |
931 | .block = AMDGPU_RAS_BLOCK__MCA, | |
932 | .type = default_ras_type, | |
933 | .sub_block_index = i, | |
934 | }; | |
935 | ||
c030f2e4 | 936 | if (bypass) { |
937 | /* | |
938 | * bypass psp. vbios enable ras for us. | |
939 | * so just create the obj | |
940 | */ | |
941 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
942 | break; | |
943 | } else { | |
944 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
945 | break; | |
946 | } | |
289d513b | 947 | } |
c030f2e4 | 948 | |
949 | return con->features; | |
950 | } | |
951 | /* feature ctl end */ | |
952 | ||
e3d833f4 | 953 | static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, |
954 | enum amdgpu_ras_block block) | |
6492e1b0 | 955 | { |
b6efdb02 | 956 | if (!block_obj) |
6492e1b0 | 957 | return -EINVAL; |
958 | ||
bdb3489c | 959 | if (block_obj->ras_comm.block == block) |
6492e1b0 | 960 | return 0; |
640ae42e | 961 | |
6492e1b0 | 962 | return -EINVAL; |
963 | } | |
964 | ||
b6efdb02 | 965 | static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, |
6492e1b0 | 966 | enum amdgpu_ras_block block, uint32_t sub_block_index) |
640ae42e | 967 | { |
d5e8ff5f | 968 | struct amdgpu_ras_block_list *node, *tmp; |
969 | struct amdgpu_ras_block_object *obj; | |
6492e1b0 | 970 | |
971 | if (block >= AMDGPU_RAS_BLOCK__LAST) | |
972 | return NULL; | |
973 | ||
d5e8ff5f | 974 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
975 | if (!node->ras_obj) { | |
976 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
977 | continue; | |
978 | } | |
979 | ||
980 | obj = node->ras_obj; | |
6492e1b0 | 981 | if (obj->ras_block_match) { |
982 | if (obj->ras_block_match(obj, block, sub_block_index) == 0) | |
983 | return obj; | |
984 | } else { | |
985 | if (amdgpu_ras_block_match_default(obj, block) == 0) | |
986 | return obj; | |
987 | } | |
640ae42e | 988 | } |
6492e1b0 | 989 | |
990 | return NULL; | |
640ae42e JC |
991 | } |
992 | ||
fdcb279d SY |
993 | static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) |
994 | { | |
995 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
996 | int ret = 0; | |
997 | ||
998 | /* | |
999 | * choosing right query method according to | |
1000 | * whether smu support query error information | |
1001 | */ | |
bc143d8b | 1002 | ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); |
fdcb279d | 1003 | if (ret == -EOPNOTSUPP) { |
efe17d5a | 1004 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
1005 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count) | |
1006 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); | |
fdcb279d SY |
1007 | |
1008 | /* umc query_ras_error_address is also responsible for clearing | |
1009 | * error status | |
1010 | */ | |
efe17d5a | 1011 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
1012 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address) | |
1013 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); | |
fdcb279d | 1014 | } else if (!ret) { |
efe17d5a | 1015 | if (adev->umc.ras && |
1016 | adev->umc.ras->ecc_info_query_ras_error_count) | |
1017 | adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); | |
fdcb279d | 1018 | |
efe17d5a | 1019 | if (adev->umc.ras && |
1020 | adev->umc.ras->ecc_info_query_ras_error_address) | |
1021 | adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); | |
fdcb279d SY |
1022 | } |
1023 | } | |
1024 | ||
5b1270be YW |
1025 | static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev, |
1026 | struct ras_query_if *query_if, | |
1027 | struct ras_err_data *err_data, | |
1028 | bool is_ue) | |
1029 | { | |
1030 | struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head); | |
1031 | const char *blk_name = get_ras_block_str(&query_if->head); | |
1032 | struct amdgpu_smuio_mcm_config_info *mcm_info; | |
1033 | struct ras_err_node *err_node; | |
1034 | struct ras_err_info *err_info; | |
1035 | ||
1036 | if (is_ue) | |
1037 | dev_info(adev->dev, "%ld uncorrectable hardware errors detected in %s block\n", | |
1038 | ras_mgr->err_data.ue_count, blk_name); | |
1039 | else | |
1040 | dev_info(adev->dev, "%ld correctable hardware errors detected in %s block\n", | |
49c260be | 1041 | ras_mgr->err_data.ce_count, blk_name); |
5b1270be YW |
1042 | |
1043 | for_each_ras_error(err_node, err_data) { | |
1044 | err_info = &err_node->err_info; | |
1045 | mcm_info = &err_info->mcm_info; | |
1046 | if (is_ue && err_info->ue_count) { | |
1047 | dev_info(adev->dev, "socket: %d, die: %d " | |
1048 | "%lld uncorrectable hardware errors detected in %s block\n", | |
1049 | mcm_info->socket_id, | |
1050 | mcm_info->die_id, | |
1051 | err_info->ue_count, | |
1052 | blk_name); | |
1053 | } else if (!is_ue && err_info->ce_count) { | |
1054 | dev_info(adev->dev, "socket: %d, die: %d " | |
1055 | "%lld correctable hardware errors detected in %s block\n", | |
1056 | mcm_info->socket_id, | |
1057 | mcm_info->die_id, | |
49c260be | 1058 | err_info->ce_count, |
5b1270be YW |
1059 | blk_name); |
1060 | } | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, | |
1065 | struct ras_query_if *query_if, | |
1066 | struct ras_err_data *err_data) | |
1067 | { | |
1068 | struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head); | |
1069 | const char *blk_name = get_ras_block_str(&query_if->head); | |
1070 | ||
1071 | if (err_data->ce_count) { | |
1072 | if (!list_empty(&err_data->err_node_list)) { | |
1073 | amdgpu_ras_error_print_error_data(adev, query_if, | |
1074 | err_data, false); | |
1075 | } else if (!adev->aid_mask && | |
1076 | adev->smuio.funcs && | |
1077 | adev->smuio.funcs->get_socket_id && | |
1078 | adev->smuio.funcs->get_die_id) { | |
1079 | dev_info(adev->dev, "socket: %d, die: %d " | |
1080 | "%ld correctable hardware errors " | |
1081 | "detected in %s block, no user " | |
1082 | "action is needed.\n", | |
1083 | adev->smuio.funcs->get_socket_id(adev), | |
1084 | adev->smuio.funcs->get_die_id(adev), | |
1085 | ras_mgr->err_data.ce_count, | |
1086 | blk_name); | |
1087 | } else { | |
1088 | dev_info(adev->dev, "%ld correctable hardware errors " | |
1089 | "detected in %s block, no user " | |
1090 | "action is needed.\n", | |
1091 | ras_mgr->err_data.ce_count, | |
1092 | blk_name); | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | if (err_data->ue_count) { | |
1097 | if (!list_empty(&err_data->err_node_list)) { | |
1098 | amdgpu_ras_error_print_error_data(adev, query_if, | |
1099 | err_data, true); | |
1100 | } else if (!adev->aid_mask && | |
1101 | adev->smuio.funcs && | |
1102 | adev->smuio.funcs->get_socket_id && | |
1103 | adev->smuio.funcs->get_die_id) { | |
1104 | dev_info(adev->dev, "socket: %d, die: %d " | |
1105 | "%ld uncorrectable hardware errors " | |
1106 | "detected in %s block\n", | |
1107 | adev->smuio.funcs->get_socket_id(adev), | |
1108 | adev->smuio.funcs->get_die_id(adev), | |
1109 | ras_mgr->err_data.ue_count, | |
1110 | blk_name); | |
1111 | } else { | |
1112 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
1113 | "detected in %s block\n", | |
1114 | ras_mgr->err_data.ue_count, | |
1115 | blk_name); | |
1116 | } | |
1117 | } | |
1118 | ||
1119 | } | |
1120 | ||
c030f2e4 | 1121 | /* query/inject/cure begin */ |
761d86d3 | 1122 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
4d9f771e | 1123 | struct ras_query_if *info) |
c030f2e4 | 1124 | { |
b6efdb02 | 1125 | struct amdgpu_ras_block_object *block_obj = NULL; |
c030f2e4 | 1126 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); |
5b1270be YW |
1127 | struct ras_err_data err_data; |
1128 | int ret; | |
c030f2e4 | 1129 | |
1130 | if (!obj) | |
1131 | return -EINVAL; | |
c030f2e4 | 1132 | |
5b1270be YW |
1133 | ret = amdgpu_ras_error_data_init(&err_data); |
1134 | if (ret) | |
1135 | return ret; | |
1136 | ||
7389a5b8 | 1137 | if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { |
fdcb279d | 1138 | amdgpu_ras_get_ecc_info(adev, &err_data); |
7389a5b8 | 1139 | } else { |
1140 | block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); | |
8b0fb0e9 | 1141 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1142 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1143 | get_ras_block_str(&info->head)); | |
5b1270be YW |
1144 | ret = -EINVAL; |
1145 | goto out_fini_err_data; | |
3e81ee9a | 1146 | } |
761d86d3 | 1147 | |
6c245386 | 1148 | if (block_obj->hw_ops->query_ras_error_count) |
1149 | block_obj->hw_ops->query_ras_error_count(adev, &err_data); | |
7389a5b8 | 1150 | |
1151 | if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || | |
1152 | (info->head.block == AMDGPU_RAS_BLOCK__GFX) || | |
1153 | (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
1154 | if (block_obj->hw_ops->query_ras_error_status) | |
1155 | block_obj->hw_ops->query_ras_error_status(adev); | |
1156 | } | |
939e2258 | 1157 | } |
05a58345 TZ |
1158 | |
1159 | obj->err_data.ue_count += err_data.ue_count; | |
1160 | obj->err_data.ce_count += err_data.ce_count; | |
1161 | ||
c030f2e4 | 1162 | info->ue_count = obj->err_data.ue_count; |
1163 | info->ce_count = obj->err_data.ce_count; | |
1164 | ||
5b1270be | 1165 | amdgpu_ras_error_generate_report(adev, info, &err_data); |
05a58345 | 1166 | |
5b1270be YW |
1167 | out_fini_err_data: |
1168 | amdgpu_ras_error_data_fini(&err_data); | |
1169 | ||
1170 | return ret; | |
c030f2e4 | 1171 | } |
1172 | ||
472c5fb2 | 1173 | int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, |
761d86d3 DL |
1174 | enum amdgpu_ras_block block) |
1175 | { | |
b6efdb02 | 1176 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); |
8b0fb0e9 | 1177 | |
a83f2bf1 | 1178 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 | 1179 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
472c5fb2 TZ |
1180 | ras_block_str(block)); |
1181 | return -EOPNOTSUPP; | |
761d86d3 DL |
1182 | } |
1183 | ||
a83f2bf1 | 1184 | if (!amdgpu_ras_is_supported(adev, block)) |
472c5fb2 | 1185 | return -EOPNOTSUPP; |
a83f2bf1 | 1186 | |
7389a5b8 | 1187 | if (block_obj->hw_ops->reset_ras_error_count) |
1188 | block_obj->hw_ops->reset_ras_error_count(adev); | |
5c23e9e0 | 1189 | |
472c5fb2 TZ |
1190 | return 0; |
1191 | } | |
1192 | ||
1193 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, | |
1194 | enum amdgpu_ras_block block) | |
1195 | { | |
1196 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); | |
1197 | ||
1198 | if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP) | |
1199 | return 0; | |
1200 | ||
7389a5b8 | 1201 | if ((block == AMDGPU_RAS_BLOCK__GFX) || |
1202 | (block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
8b0fb0e9 | 1203 | if (block_obj->hw_ops->reset_ras_error_status) |
1204 | block_obj->hw_ops->reset_ras_error_status(adev); | |
761d86d3 | 1205 | } |
5c23e9e0 | 1206 | |
761d86d3 | 1207 | return 0; |
5c23e9e0 JC |
1208 | } |
1209 | ||
c030f2e4 | 1210 | /* wrapper of psp_ras_trigger_error */ |
1211 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
1212 | struct ras_inject_if *info) | |
1213 | { | |
1214 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1215 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1216 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1217 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1218 | .sub_block_index = info->head.sub_block_index, |
1219 | .address = info->address, | |
1220 | .value = info->value, | |
1221 | }; | |
ab3b9de6 YL |
1222 | int ret = -EINVAL; |
1223 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, | |
1224 | info->head.block, | |
1225 | info->head.sub_block_index); | |
c030f2e4 | 1226 | |
248c9635 TZ |
1227 | /* inject on guest isn't allowed, return success directly */ |
1228 | if (amdgpu_sriov_vf(adev)) | |
1229 | return 0; | |
1230 | ||
c030f2e4 | 1231 | if (!obj) |
1232 | return -EINVAL; | |
1233 | ||
22d4ba53 | 1234 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1235 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1236 | get_ras_block_str(&info->head)); | |
22d4ba53 | 1237 | return -EINVAL; |
1238 | } | |
1239 | ||
a6c44d25 | 1240 | /* Calculate XGMI relative offset */ |
a80fe1a6 TZ |
1241 | if (adev->gmc.xgmi.num_physical_nodes > 1 && |
1242 | info->head.block != AMDGPU_RAS_BLOCK__GFX) { | |
19744f5f HZ |
1243 | block_info.address = |
1244 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1245 | block_info.address); | |
a6c44d25 JC |
1246 | } |
1247 | ||
27c5f295 TZ |
1248 | if (block_obj->hw_ops->ras_error_inject) { |
1249 | if (info->head.block == AMDGPU_RAS_BLOCK__GFX) | |
2c22ed0b | 1250 | ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask); |
27c5f295 | 1251 | else /* Special ras_error_inject is defined (e.g: xgmi) */ |
2c22ed0b TZ |
1252 | ret = block_obj->hw_ops->ras_error_inject(adev, &block_info, |
1253 | info->instance_mask); | |
27c5f295 TZ |
1254 | } else { |
1255 | /* default path */ | |
1256 | ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask); | |
a5dd40ca HZ |
1257 | } |
1258 | ||
011907fd DL |
1259 | if (ret) |
1260 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
640ae42e | 1261 | get_ras_block_str(&info->head), ret); |
c030f2e4 | 1262 | |
1263 | return ret; | |
1264 | } | |
1265 | ||
4d9f771e | 1266 | /** |
4a1c9a44 HZ |
1267 | * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP |
1268 | * @adev: pointer to AMD GPU device | |
1269 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1270 | * @ue_count: pointer to an integer to be set to the count of uncorrectible errors. | |
1271 | * @query_info: pointer to ras_query_if | |
1272 | * | |
1273 | * Return 0 for query success or do nothing, otherwise return an error | |
1274 | * on failures | |
1275 | */ | |
1276 | static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev, | |
1277 | unsigned long *ce_count, | |
1278 | unsigned long *ue_count, | |
1279 | struct ras_query_if *query_info) | |
1280 | { | |
1281 | int ret; | |
1282 | ||
1283 | if (!query_info) | |
1284 | /* do nothing if query_info is not specified */ | |
1285 | return 0; | |
1286 | ||
1287 | ret = amdgpu_ras_query_error_status(adev, query_info); | |
1288 | if (ret) | |
1289 | return ret; | |
1290 | ||
1291 | *ce_count += query_info->ce_count; | |
1292 | *ue_count += query_info->ue_count; | |
1293 | ||
1294 | /* some hardware/IP supports read to clear | |
1295 | * no need to explictly reset the err status after the query call */ | |
4e8303cf LL |
1296 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
1297 | amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
4a1c9a44 HZ |
1298 | if (amdgpu_ras_reset_error_status(adev, query_info->head.block)) |
1299 | dev_warn(adev->dev, | |
1300 | "Failed to reset error counter and error status\n"); | |
1301 | } | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
1306 | /** | |
1307 | * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP | |
bbe04dec IB |
1308 | * @adev: pointer to AMD GPU device |
1309 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1310 | * @ue_count: pointer to an integer to be set to the count of uncorrectible | |
4d9f771e | 1311 | * errors. |
4a1c9a44 HZ |
1312 | * @query_info: pointer to ras_query_if if the query request is only for |
1313 | * specific ip block; if info is NULL, then the qurey request is for | |
1314 | * all the ip blocks that support query ras error counters/status | |
4d9f771e LT |
1315 | * |
1316 | * If set, @ce_count or @ue_count, count and return the corresponding | |
1317 | * error counts in those integer pointers. Return 0 if the device | |
1318 | * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
1319 | */ | |
1320 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
1321 | unsigned long *ce_count, | |
4a1c9a44 HZ |
1322 | unsigned long *ue_count, |
1323 | struct ras_query_if *query_info) | |
c030f2e4 | 1324 | { |
1325 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1326 | struct ras_manager *obj; | |
a46751fb | 1327 | unsigned long ce, ue; |
4a1c9a44 | 1328 | int ret; |
c030f2e4 | 1329 | |
8ab0d6f0 | 1330 | if (!adev->ras_enabled || !con) |
4d9f771e LT |
1331 | return -EOPNOTSUPP; |
1332 | ||
1333 | /* Don't count since no reporting. | |
1334 | */ | |
1335 | if (!ce_count && !ue_count) | |
1336 | return 0; | |
c030f2e4 | 1337 | |
a46751fb LT |
1338 | ce = 0; |
1339 | ue = 0; | |
4a1c9a44 HZ |
1340 | if (!query_info) { |
1341 | /* query all the ip blocks that support ras query interface */ | |
1342 | list_for_each_entry(obj, &con->head, node) { | |
1343 | struct ras_query_if info = { | |
1344 | .head = obj->head, | |
1345 | }; | |
c030f2e4 | 1346 | |
4a1c9a44 | 1347 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info); |
2a460963 | 1348 | } |
4a1c9a44 HZ |
1349 | } else { |
1350 | /* query specific ip block */ | |
1351 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info); | |
c030f2e4 | 1352 | } |
1353 | ||
4a1c9a44 HZ |
1354 | if (ret) |
1355 | return ret; | |
1356 | ||
a46751fb LT |
1357 | if (ce_count) |
1358 | *ce_count = ce; | |
1359 | ||
1360 | if (ue_count) | |
1361 | *ue_count = ue; | |
4d9f771e LT |
1362 | |
1363 | return 0; | |
c030f2e4 | 1364 | } |
1365 | /* query/inject/cure end */ | |
1366 | ||
1367 | ||
1368 | /* sysfs begin */ | |
1369 | ||
466b1793 | 1370 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1371 | struct ras_badpage **bps, unsigned int *count); | |
1372 | ||
1373 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1374 | { | |
1375 | switch (flags) { | |
52dd95f2 | 1376 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1377 | return "R"; |
52dd95f2 | 1378 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1379 | return "P"; |
52dd95f2 | 1380 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1381 | default: |
1382 | return "F"; | |
aec576f9 | 1383 | } |
466b1793 | 1384 | } |
1385 | ||
f77c7109 AD |
1386 | /** |
1387 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1388 | * |
1389 | * It allows user to read the bad pages of vram on the gpu through | |
1390 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1391 | * | |
1392 | * It outputs multiple lines, and each line stands for one gpu page. | |
1393 | * | |
1394 | * The format of one line is below, | |
1395 | * gpu pfn : gpu page size : flags | |
1396 | * | |
1397 | * gpu pfn and gpu page size are printed in hex format. | |
1398 | * flags can be one of below character, | |
f77c7109 | 1399 | * |
466b1793 | 1400 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1401 | * |
466b1793 | 1402 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1403 | * in next window of page_reserve. |
1404 | * | |
466b1793 | 1405 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1406 | * | |
f77c7109 AD |
1407 | * Examples: |
1408 | * | |
1409 | * .. code-block:: bash | |
1410 | * | |
1411 | * 0x00000001 : 0x00001000 : R | |
1412 | * 0x00000002 : 0x00001000 : P | |
1413 | * | |
466b1793 | 1414 | */ |
1415 | ||
1416 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1417 | struct kobject *kobj, struct bin_attribute *attr, | |
1418 | char *buf, loff_t ppos, size_t count) | |
1419 | { | |
1420 | struct amdgpu_ras *con = | |
1421 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1422 | struct amdgpu_device *adev = con->adev; | |
1423 | const unsigned int element_size = | |
1424 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1425 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1426 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1427 | ssize_t s = 0; |
1428 | struct ras_badpage *bps = NULL; | |
1429 | unsigned int bps_count = 0; | |
1430 | ||
1431 | memset(buf, 0, count); | |
1432 | ||
1433 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1434 | return 0; | |
1435 | ||
1436 | for (; start < end && start < bps_count; start++) | |
1437 | s += scnprintf(&buf[s], element_size + 1, | |
1438 | "0x%08x : 0x%08x : %1s\n", | |
1439 | bps[start].bp, | |
1440 | bps[start].size, | |
1441 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1442 | ||
1443 | kfree(bps); | |
1444 | ||
1445 | return s; | |
1446 | } | |
1447 | ||
c030f2e4 | 1448 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1449 | struct device_attribute *attr, char *buf) | |
1450 | { | |
1451 | struct amdgpu_ras *con = | |
1452 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1453 | |
2cffcb66 | 1454 | return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1455 | } |
1456 | ||
625e5f38 AK |
1457 | static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev, |
1458 | struct device_attribute *attr, char *buf) | |
1459 | { | |
1460 | struct amdgpu_ras *con = | |
1461 | container_of(attr, struct amdgpu_ras, version_attr); | |
1462 | return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version); | |
1463 | } | |
1464 | ||
1465 | static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev, | |
1466 | struct device_attribute *attr, char *buf) | |
1467 | { | |
1468 | struct amdgpu_ras *con = | |
1469 | container_of(attr, struct amdgpu_ras, schema_attr); | |
1470 | return sysfs_emit(buf, "schema: 0x%x\n", con->schema); | |
1471 | } | |
1472 | ||
f848159b GC |
1473 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1474 | { | |
1475 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1476 | ||
1477 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1478 | &con->badpages_attr.attr, | |
1479 | RAS_FS_NAME); | |
1480 | } | |
1481 | ||
625e5f38 | 1482 | static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev) |
c030f2e4 | 1483 | { |
1484 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1485 | struct attribute *attrs[] = { | |
1486 | &con->features_attr.attr, | |
625e5f38 AK |
1487 | &con->version_attr.attr, |
1488 | &con->schema_attr.attr, | |
c030f2e4 | 1489 | NULL |
1490 | }; | |
1491 | struct attribute_group group = { | |
eb0c3cd4 | 1492 | .name = RAS_FS_NAME, |
c030f2e4 | 1493 | .attrs = attrs, |
1494 | }; | |
1495 | ||
1496 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
9252d33d | 1502 | struct ras_common_if *head) |
c030f2e4 | 1503 | { |
9252d33d | 1504 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1505 | |
1506 | if (!obj || obj->attr_inuse) | |
1507 | return -EINVAL; | |
1508 | ||
1509 | get_obj(obj); | |
1510 | ||
9252d33d | 1511 | snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), |
1512 | "%s_err_count", head->name); | |
c030f2e4 | 1513 | |
1514 | obj->sysfs_attr = (struct device_attribute){ | |
1515 | .attr = { | |
1516 | .name = obj->fs_data.sysfs_name, | |
1517 | .mode = S_IRUGO, | |
1518 | }, | |
1519 | .show = amdgpu_ras_sysfs_read, | |
1520 | }; | |
163def43 | 1521 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1522 | |
1523 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1524 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1525 | RAS_FS_NAME)) { |
c030f2e4 | 1526 | put_obj(obj); |
1527 | return -EINVAL; | |
1528 | } | |
1529 | ||
1530 | obj->attr_inuse = 1; | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1536 | struct ras_common_if *head) | |
1537 | { | |
1538 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1539 | ||
1540 | if (!obj || !obj->attr_inuse) | |
1541 | return -EINVAL; | |
1542 | ||
1543 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1544 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1545 | RAS_FS_NAME); |
c030f2e4 | 1546 | obj->attr_inuse = 0; |
1547 | put_obj(obj); | |
1548 | ||
1549 | return 0; | |
1550 | } | |
1551 | ||
1552 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1553 | { | |
1554 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1555 | struct ras_manager *obj, *tmp; | |
1556 | ||
1557 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1558 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1559 | } | |
1560 | ||
f848159b GC |
1561 | if (amdgpu_bad_page_threshold != 0) |
1562 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1563 | ||
625e5f38 | 1564 | amdgpu_ras_sysfs_remove_dev_attr_node(adev); |
c030f2e4 | 1565 | |
1566 | return 0; | |
1567 | } | |
1568 | /* sysfs end */ | |
1569 | ||
ef177d11 AD |
1570 | /** |
1571 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1572 | * | |
1573 | * Normally when there is an uncorrectable error, the driver will reset | |
1574 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1575 | * the driver provides an interface to reboot the system automatically | |
1576 | * in that event. | |
1577 | * | |
1578 | * The following file in debugfs provides that interface: | |
1579 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1580 | * | |
1581 | * Usage: | |
1582 | * | |
1583 | * .. code-block:: bash | |
1584 | * | |
1585 | * echo true > .../ras/auto_reboot | |
1586 | * | |
1587 | */ | |
c030f2e4 | 1588 | /* debugfs begin */ |
ea1b8c9b | 1589 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1590 | { |
1591 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
740f42a2 | 1592 | struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control; |
ef0d7d20 LT |
1593 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1594 | struct dentry *dir; | |
36ea1bd2 | 1595 | |
88293c03 ND |
1596 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1597 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1598 | &amdgpu_ras_debugfs_ctrl_ops); | |
1599 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1600 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1601 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1602 | &con->bad_page_cnt_threshold); | |
740f42a2 | 1603 | debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs); |
ef0d7d20 LT |
1604 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1605 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c65b0805 LT |
1606 | debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, |
1607 | &amdgpu_ras_debugfs_eeprom_size_ops); | |
1608 | con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", | |
1609 | S_IRUGO, dir, adev, | |
1610 | &amdgpu_ras_debugfs_eeprom_table_ops); | |
1611 | amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); | |
c688a06b GC |
1612 | |
1613 | /* | |
1614 | * After one uncorrectable error happens, usually GPU recovery will | |
1615 | * be scheduled. But due to the known problem in GPU recovery failing | |
1616 | * to bring GPU back, below interface provides one direct way to | |
1617 | * user to reboot system automatically in such case within | |
1618 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1619 | * will never be called. | |
1620 | */ | |
88293c03 | 1621 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1622 | |
1623 | /* | |
1624 | * User could set this not to clean up hardware's error count register | |
1625 | * of RAS IPs during ras recovery. | |
1626 | */ | |
88293c03 ND |
1627 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1628 | &con->disable_ras_err_cnt_harvest); | |
1629 | return dir; | |
36ea1bd2 | 1630 | } |
1631 | ||
cedf7884 | 1632 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1633 | struct ras_fs_if *head, |
1634 | struct dentry *dir) | |
c030f2e4 | 1635 | { |
c030f2e4 | 1636 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1637 | |
88293c03 | 1638 | if (!obj || !dir) |
450f30ea | 1639 | return; |
c030f2e4 | 1640 | |
1641 | get_obj(obj); | |
1642 | ||
1643 | memcpy(obj->fs_data.debugfs_name, | |
1644 | head->debugfs_name, | |
1645 | sizeof(obj->fs_data.debugfs_name)); | |
1646 | ||
88293c03 ND |
1647 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1648 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1649 | } |
1650 | ||
f9317014 TZ |
1651 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1652 | { | |
1653 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1654 | struct dentry *dir; |
c1509f3f | 1655 | struct ras_manager *obj; |
f9317014 TZ |
1656 | struct ras_fs_if fs_info; |
1657 | ||
1658 | /* | |
1659 | * it won't be called in resume path, no need to check | |
1660 | * suspend and gpu reset status | |
1661 | */ | |
cedf7884 | 1662 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1663 | return; |
1664 | ||
88293c03 | 1665 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1666 | |
c1509f3f | 1667 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1668 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1669 | (obj->attr_inuse == 1)) { | |
1670 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
640ae42e | 1671 | get_ras_block_str(&obj->head)); |
f9317014 | 1672 | fs_info.head = obj->head; |
88293c03 | 1673 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1674 | } |
1675 | } | |
4051844c YW |
1676 | |
1677 | amdgpu_mca_smu_debugfs_init(adev, dir); | |
f9317014 TZ |
1678 | } |
1679 | ||
c030f2e4 | 1680 | /* debugfs end */ |
1681 | ||
1682 | /* ras fs */ | |
c3d4d45d GC |
1683 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1684 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1685 | static DEVICE_ATTR(features, S_IRUGO, | |
1686 | amdgpu_ras_sysfs_features_read, NULL); | |
625e5f38 AK |
1687 | static DEVICE_ATTR(version, 0444, |
1688 | amdgpu_ras_sysfs_version_show, NULL); | |
1689 | static DEVICE_ATTR(schema, 0444, | |
1690 | amdgpu_ras_sysfs_schema_show, NULL); | |
c030f2e4 | 1691 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1692 | { | |
c3d4d45d GC |
1693 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1694 | struct attribute_group group = { | |
1695 | .name = RAS_FS_NAME, | |
1696 | }; | |
1697 | struct attribute *attrs[] = { | |
1698 | &con->features_attr.attr, | |
625e5f38 AK |
1699 | &con->version_attr.attr, |
1700 | &con->schema_attr.attr, | |
c3d4d45d GC |
1701 | NULL |
1702 | }; | |
1703 | struct bin_attribute *bin_attrs[] = { | |
1704 | NULL, | |
1705 | NULL, | |
1706 | }; | |
a069a9eb | 1707 | int r; |
c030f2e4 | 1708 | |
625e5f38 AK |
1709 | group.attrs = attrs; |
1710 | ||
c3d4d45d GC |
1711 | /* add features entry */ |
1712 | con->features_attr = dev_attr_features; | |
c3d4d45d GC |
1713 | sysfs_attr_init(attrs[0]); |
1714 | ||
625e5f38 AK |
1715 | /* add version entry */ |
1716 | con->version_attr = dev_attr_version; | |
1717 | sysfs_attr_init(attrs[1]); | |
1718 | ||
1719 | /* add schema entry */ | |
1720 | con->schema_attr = dev_attr_schema; | |
1721 | sysfs_attr_init(attrs[2]); | |
1722 | ||
c3d4d45d GC |
1723 | if (amdgpu_bad_page_threshold != 0) { |
1724 | /* add bad_page_features entry */ | |
1725 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1726 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1727 | bin_attrs[0] = &con->badpages_attr; | |
1728 | group.bin_attrs = bin_attrs; | |
1729 | sysfs_bin_attr_init(bin_attrs[0]); | |
1730 | } | |
1731 | ||
a069a9eb AD |
1732 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1733 | if (r) | |
1734 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1735 | |
c030f2e4 | 1736 | return 0; |
1737 | } | |
1738 | ||
1739 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1740 | { | |
88293c03 ND |
1741 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1742 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1743 | ||
1744 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1745 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1746 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1747 | if (ip_obj) | |
1748 | put_obj(ip_obj); | |
1749 | } | |
1750 | } | |
1751 | ||
c030f2e4 | 1752 | amdgpu_ras_sysfs_remove_all(adev); |
1753 | return 0; | |
1754 | } | |
1755 | /* ras fs end */ | |
1756 | ||
1757 | /* ih begin */ | |
b3c76814 TZ |
1758 | |
1759 | /* For the hardware that cannot enable bif ring for both ras_controller_irq | |
1760 | * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status | |
1761 | * register to check whether the interrupt is triggered or not, and properly | |
1762 | * ack the interrupt if it is there | |
1763 | */ | |
1764 | void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) | |
1765 | { | |
950d6425 | 1766 | /* Fatal error events are handled on host side */ |
8eba7205 | 1767 | if (amdgpu_sriov_vf(adev)) |
b3c76814 TZ |
1768 | return; |
1769 | ||
1770 | if (adev->nbio.ras && | |
1771 | adev->nbio.ras->handle_ras_controller_intr_no_bifring) | |
1772 | adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); | |
1773 | ||
1774 | if (adev->nbio.ras && | |
1775 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) | |
1776 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); | |
1777 | } | |
1778 | ||
66f87949 TZ |
1779 | static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj, |
1780 | struct amdgpu_iv_entry *entry) | |
1781 | { | |
b63ac5d3 | 1782 | bool poison_stat = false; |
66f87949 | 1783 | struct amdgpu_device *adev = obj->adev; |
66f87949 TZ |
1784 | struct amdgpu_ras_block_object *block_obj = |
1785 | amdgpu_ras_get_ras_block(adev, obj->head.block, 0); | |
1786 | ||
ac7b25d9 | 1787 | if (!block_obj) |
b63ac5d3 | 1788 | return; |
66f87949 | 1789 | |
b63ac5d3 TZ |
1790 | /* both query_poison_status and handle_poison_consumption are optional, |
1791 | * but at least one of them should be implemented if we need poison | |
1792 | * consumption handler | |
1793 | */ | |
ac7b25d9 | 1794 | if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { |
b63ac5d3 TZ |
1795 | poison_stat = block_obj->hw_ops->query_poison_status(adev); |
1796 | if (!poison_stat) { | |
1797 | /* Not poison consumption interrupt, no need to handle it */ | |
1798 | dev_info(adev->dev, "No RAS poison status in %s poison IH.\n", | |
1799 | block_obj->ras_comm.name); | |
1800 | ||
1801 | return; | |
66f87949 TZ |
1802 | } |
1803 | } | |
1804 | ||
38298ce6 | 1805 | amdgpu_umc_poison_handler(adev, false); |
b63ac5d3 | 1806 | |
ac7b25d9 | 1807 | if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) |
b63ac5d3 TZ |
1808 | poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); |
1809 | ||
1810 | /* gpu reset is fallback for failed and default cases */ | |
1811 | if (poison_stat) { | |
1812 | dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n", | |
1813 | block_obj->ras_comm.name); | |
66f87949 | 1814 | amdgpu_ras_reset_gpu(adev); |
ac7b25d9 YC |
1815 | } else { |
1816 | amdgpu_gfx_poison_consumption_handler(adev, entry); | |
b63ac5d3 | 1817 | } |
66f87949 TZ |
1818 | } |
1819 | ||
50a7d025 TZ |
1820 | static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj, |
1821 | struct amdgpu_iv_entry *entry) | |
1822 | { | |
1823 | dev_info(obj->adev->dev, | |
1824 | "Poison is created, no user action is needed.\n"); | |
1825 | } | |
1826 | ||
1827 | static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, | |
1828 | struct amdgpu_iv_entry *entry) | |
1829 | { | |
1830 | struct ras_ih_data *data = &obj->ih_data; | |
5b1270be | 1831 | struct ras_err_data err_data; |
50a7d025 TZ |
1832 | int ret; |
1833 | ||
1834 | if (!data->cb) | |
1835 | return; | |
1836 | ||
5b1270be YW |
1837 | ret = amdgpu_ras_error_data_init(&err_data); |
1838 | if (ret) | |
1839 | return; | |
1840 | ||
50a7d025 TZ |
1841 | /* Let IP handle its data, maybe we need get the output |
1842 | * from the callback to update the error type/count, etc | |
1843 | */ | |
1844 | ret = data->cb(obj->adev, &err_data, entry); | |
1845 | /* ue will trigger an interrupt, and in that case | |
1846 | * we need do a reset to recovery the whole system. | |
1847 | * But leave IP do that recovery, here we just dispatch | |
1848 | * the error. | |
1849 | */ | |
1850 | if (ret == AMDGPU_RAS_SUCCESS) { | |
1851 | /* these counts could be left as 0 if | |
1852 | * some blocks do not count error number | |
1853 | */ | |
1854 | obj->err_data.ue_count += err_data.ue_count; | |
1855 | obj->err_data.ce_count += err_data.ce_count; | |
1856 | } | |
5b1270be YW |
1857 | |
1858 | amdgpu_ras_error_data_fini(&err_data); | |
50a7d025 TZ |
1859 | } |
1860 | ||
c030f2e4 | 1861 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) |
1862 | { | |
1863 | struct ras_ih_data *data = &obj->ih_data; | |
1864 | struct amdgpu_iv_entry entry; | |
c030f2e4 | 1865 | |
1866 | while (data->rptr != data->wptr) { | |
1867 | rmb(); | |
1868 | memcpy(&entry, &data->ring[data->rptr], | |
1869 | data->element_size); | |
1870 | ||
1871 | wmb(); | |
1872 | data->rptr = (data->aligned_element_size + | |
1873 | data->rptr) % data->ring_size; | |
1874 | ||
50a7d025 TZ |
1875 | if (amdgpu_ras_is_poison_mode_supported(obj->adev)) { |
1876 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
1877 | amdgpu_ras_interrupt_poison_creation_handler(obj, &entry); | |
66f87949 TZ |
1878 | else |
1879 | amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry); | |
50a7d025 TZ |
1880 | } else { |
1881 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
1882 | amdgpu_ras_interrupt_umc_handler(obj, &entry); | |
1883 | else | |
1884 | dev_warn(obj->adev->dev, | |
1885 | "No RAS interrupt handler for non-UMC block with poison disabled.\n"); | |
c030f2e4 | 1886 | } |
1887 | } | |
1888 | } | |
1889 | ||
1890 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1891 | { | |
1892 | struct ras_ih_data *data = | |
1893 | container_of(work, struct ras_ih_data, ih_work); | |
1894 | struct ras_manager *obj = | |
1895 | container_of(data, struct ras_manager, ih_data); | |
1896 | ||
1897 | amdgpu_ras_interrupt_handler(obj); | |
1898 | } | |
1899 | ||
1900 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1901 | struct ras_dispatch_if *info) | |
1902 | { | |
1903 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1904 | struct ras_ih_data *data = &obj->ih_data; | |
1905 | ||
1906 | if (!obj) | |
1907 | return -EINVAL; | |
1908 | ||
1909 | if (data->inuse == 0) | |
1910 | return 0; | |
1911 | ||
1912 | /* Might be overflow... */ | |
1913 | memcpy(&data->ring[data->wptr], info->entry, | |
1914 | data->element_size); | |
1915 | ||
1916 | wmb(); | |
1917 | data->wptr = (data->aligned_element_size + | |
1918 | data->wptr) % data->ring_size; | |
1919 | ||
1920 | schedule_work(&data->ih_work); | |
1921 | ||
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
9252d33d | 1926 | struct ras_common_if *head) |
c030f2e4 | 1927 | { |
9252d33d | 1928 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1929 | struct ras_ih_data *data; |
1930 | ||
1931 | if (!obj) | |
1932 | return -EINVAL; | |
1933 | ||
1934 | data = &obj->ih_data; | |
1935 | if (data->inuse == 0) | |
1936 | return 0; | |
1937 | ||
1938 | cancel_work_sync(&data->ih_work); | |
1939 | ||
1940 | kfree(data->ring); | |
1941 | memset(data, 0, sizeof(*data)); | |
1942 | put_obj(obj); | |
1943 | ||
1944 | return 0; | |
1945 | } | |
1946 | ||
1947 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
9252d33d | 1948 | struct ras_common_if *head) |
c030f2e4 | 1949 | { |
9252d33d | 1950 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1951 | struct ras_ih_data *data; |
9252d33d | 1952 | struct amdgpu_ras_block_object *ras_obj; |
c030f2e4 | 1953 | |
1954 | if (!obj) { | |
1955 | /* in case we registe the IH before enable ras feature */ | |
9252d33d | 1956 | obj = amdgpu_ras_create_obj(adev, head); |
c030f2e4 | 1957 | if (!obj) |
1958 | return -EINVAL; | |
1959 | } else | |
1960 | get_obj(obj); | |
1961 | ||
9252d33d | 1962 | ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); |
1963 | ||
c030f2e4 | 1964 | data = &obj->ih_data; |
1965 | /* add the callback.etc */ | |
1966 | *data = (struct ras_ih_data) { | |
1967 | .inuse = 0, | |
9252d33d | 1968 | .cb = ras_obj->ras_cb, |
c030f2e4 | 1969 | .element_size = sizeof(struct amdgpu_iv_entry), |
1970 | .rptr = 0, | |
1971 | .wptr = 0, | |
1972 | }; | |
1973 | ||
1974 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1975 | ||
1976 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1977 | /* the ring can store 64 iv entries. */ | |
1978 | data->ring_size = 64 * data->aligned_element_size; | |
1979 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1980 | if (!data->ring) { | |
1981 | put_obj(obj); | |
1982 | return -ENOMEM; | |
1983 | } | |
1984 | ||
1985 | /* IH is ready */ | |
1986 | data->inuse = 1; | |
1987 | ||
1988 | return 0; | |
1989 | } | |
1990 | ||
1991 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1992 | { | |
1993 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1994 | struct ras_manager *obj, *tmp; | |
1995 | ||
1996 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
9252d33d | 1997 | amdgpu_ras_interrupt_remove_handler(adev, &obj->head); |
c030f2e4 | 1998 | } |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | /* ih end */ | |
2003 | ||
313c8fd3 GC |
2004 | /* traversal all IPs except NBIO to query error counter */ |
2005 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
2006 | { | |
2007 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2008 | struct ras_manager *obj; | |
2009 | ||
8ab0d6f0 | 2010 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
2011 | return; |
2012 | ||
2013 | list_for_each_entry(obj, &con->head, node) { | |
2014 | struct ras_query_if info = { | |
2015 | .head = obj->head, | |
2016 | }; | |
2017 | ||
2018 | /* | |
2019 | * PCIE_BIF IP has one different isr by ras controller | |
2020 | * interrupt, the specific ras counter query will be | |
2021 | * done in that isr. So skip such block from common | |
2022 | * sync flood interrupt isr calling. | |
2023 | */ | |
2024 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
2025 | continue; | |
2026 | ||
cf63b702 SY |
2027 | /* |
2028 | * this is a workaround for aldebaran, skip send msg to | |
2029 | * smu to get ecc_info table due to smu handle get ecc | |
2030 | * info table failed temporarily. | |
2031 | * should be removed until smu fix handle ecc_info table. | |
2032 | */ | |
2033 | if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
4e8303cf LL |
2034 | (amdgpu_ip_version(adev, MP1_HWIP, 0) == |
2035 | IP_VERSION(13, 0, 2))) | |
cf63b702 SY |
2036 | continue; |
2037 | ||
761d86d3 | 2038 | amdgpu_ras_query_error_status(adev, &info); |
2a460963 | 2039 | |
4e8303cf LL |
2040 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != |
2041 | IP_VERSION(11, 0, 2) && | |
2042 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
2043 | IP_VERSION(11, 0, 4) && | |
2044 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
2045 | IP_VERSION(13, 0, 0)) { | |
2a460963 CL |
2046 | if (amdgpu_ras_reset_error_status(adev, info.head.block)) |
2047 | dev_warn(adev->dev, "Failed to reset error counter and error status"); | |
2048 | } | |
313c8fd3 GC |
2049 | } |
2050 | } | |
2051 | ||
3f975d0f | 2052 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
2053 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
2054 | struct ras_query_if *info) | |
3f975d0f | 2055 | { |
8eb53bb2 | 2056 | struct amdgpu_ras_block_object *block_obj; |
3f975d0f SY |
2057 | /* |
2058 | * Only two block need to query read/write | |
2059 | * RspStatus at current state | |
2060 | */ | |
5e67bba3 | 2061 | if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && |
2062 | (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) | |
b6efdb02 | 2063 | return; |
2064 | ||
2065 | block_obj = amdgpu_ras_get_ras_block(adev, | |
2066 | info->head.block, | |
2067 | info->head.sub_block_index); | |
5e67bba3 | 2068 | |
5e67bba3 | 2069 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
2070 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
2071 | get_ras_block_str(&info->head)); | |
b6efdb02 | 2072 | return; |
3f975d0f | 2073 | } |
5e67bba3 | 2074 | |
2075 | if (block_obj->hw_ops->query_ras_error_status) | |
ab3b9de6 | 2076 | block_obj->hw_ops->query_ras_error_status(adev); |
5e67bba3 | 2077 | |
3f975d0f SY |
2078 | } |
2079 | ||
2080 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
2081 | { | |
2082 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2083 | struct ras_manager *obj; | |
2084 | ||
8ab0d6f0 | 2085 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
2086 | return; |
2087 | ||
2088 | list_for_each_entry(obj, &con->head, node) { | |
2089 | struct ras_query_if info = { | |
2090 | .head = obj->head, | |
2091 | }; | |
2092 | ||
2093 | amdgpu_ras_error_status_query(adev, &info); | |
2094 | } | |
2095 | } | |
2096 | ||
c030f2e4 | 2097 | /* recovery begin */ |
466b1793 | 2098 | |
2099 | /* return 0 on success. | |
2100 | * caller need free bps. | |
2101 | */ | |
2102 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
2103 | struct ras_badpage **bps, unsigned int *count) | |
2104 | { | |
2105 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2106 | struct ras_err_handler_data *data; | |
2107 | int i = 0; | |
732f2a30 | 2108 | int ret = 0, status; |
466b1793 | 2109 | |
2110 | if (!con || !con->eh_data || !bps || !count) | |
2111 | return -EINVAL; | |
2112 | ||
2113 | mutex_lock(&con->recovery_lock); | |
2114 | data = con->eh_data; | |
2115 | if (!data || data->count == 0) { | |
2116 | *bps = NULL; | |
46cf2fec | 2117 | ret = -EINVAL; |
466b1793 | 2118 | goto out; |
2119 | } | |
2120 | ||
2121 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
2122 | if (!*bps) { | |
2123 | ret = -ENOMEM; | |
2124 | goto out; | |
2125 | } | |
2126 | ||
2127 | for (; i < data->count; i++) { | |
2128 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 2129 | .bp = data->bps[i].retired_page, |
466b1793 | 2130 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 2131 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 2132 | }; |
ec6aae97 | 2133 | status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, |
676deb38 | 2134 | data->bps[i].retired_page); |
732f2a30 | 2135 | if (status == -EBUSY) |
52dd95f2 | 2136 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 2137 | else if (status == -ENOENT) |
52dd95f2 | 2138 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 2139 | } |
2140 | ||
2141 | *count = data->count; | |
2142 | out: | |
2143 | mutex_unlock(&con->recovery_lock); | |
2144 | return ret; | |
2145 | } | |
2146 | ||
c030f2e4 | 2147 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
2148 | { | |
2149 | struct amdgpu_ras *ras = | |
2150 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
2151 | struct amdgpu_device *remote_adev = NULL; |
2152 | struct amdgpu_device *adev = ras->adev; | |
2153 | struct list_head device_list, *device_list_handle = NULL; | |
53dd920c | 2154 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
b3dbd6d3 | 2155 | |
53dd920c AK |
2156 | if (hive) |
2157 | atomic_set(&hive->ras_recovery, 1); | |
f75e94d8 | 2158 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 | 2159 | |
f75e94d8 GC |
2160 | /* Build list of devices to query RAS related errors */ |
2161 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
2162 | device_list_handle = &hive->device_list; | |
2163 | } else { | |
2164 | INIT_LIST_HEAD(&device_list); | |
2165 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
2166 | device_list_handle = &device_list; | |
2167 | } | |
c030f2e4 | 2168 | |
f75e94d8 | 2169 | list_for_each_entry(remote_adev, |
3f975d0f SY |
2170 | device_list_handle, gmc.xgmi.head) { |
2171 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 2172 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 2173 | } |
d95e8e97 | 2174 | |
b3dbd6d3 | 2175 | } |
313c8fd3 | 2176 | |
f1549c09 LG |
2177 | if (amdgpu_device_should_recover_gpu(ras->adev)) { |
2178 | struct amdgpu_reset_context reset_context; | |
2179 | memset(&reset_context, 0, sizeof(reset_context)); | |
2180 | ||
2181 | reset_context.method = AMD_RESET_METHOD_NONE; | |
2182 | reset_context.reset_req_dev = adev; | |
1a11a65d YC |
2183 | |
2184 | /* Perform full reset in fatal error mode */ | |
2185 | if (!amdgpu_ras_is_poison_mode_supported(ras->adev)) | |
2186 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
6c47a79b | 2187 | else { |
1a11a65d | 2188 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
f1549c09 | 2189 | |
6c47a79b YC |
2190 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) { |
2191 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
2192 | reset_context.method = AMD_RESET_METHOD_MODE2; | |
2193 | } | |
2c7cd280 YC |
2194 | |
2195 | /* Fatal error occurs in poison mode, mode1 reset is used to | |
2196 | * recover gpu. | |
2197 | */ | |
2198 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) { | |
2199 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET; | |
2200 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
1b98a5f8 YC |
2201 | |
2202 | psp_fatal_error_recovery_quirk(&adev->psp); | |
2c7cd280 | 2203 | } |
6c47a79b YC |
2204 | } |
2205 | ||
f1549c09 LG |
2206 | amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); |
2207 | } | |
c030f2e4 | 2208 | atomic_set(&ras->in_recovery, 0); |
53dd920c AK |
2209 | if (hive) { |
2210 | atomic_set(&hive->ras_recovery, 0); | |
2211 | amdgpu_put_xgmi_hive(hive); | |
2212 | } | |
c030f2e4 | 2213 | } |
2214 | ||
c030f2e4 | 2215 | /* alloc/realloc bps array */ |
2216 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
2217 | struct ras_err_handler_data *data, int pages) | |
2218 | { | |
2219 | unsigned int old_space = data->count + data->space_left; | |
2220 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
2221 | unsigned int align_space = ALIGN(new_space, 512); |
2222 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 2223 | |
676deb38 | 2224 | if (!bps) { |
c030f2e4 | 2225 | return -ENOMEM; |
9dc23a63 | 2226 | } |
c030f2e4 | 2227 | |
2228 | if (data->bps) { | |
9dc23a63 | 2229 | memcpy(bps, data->bps, |
c030f2e4 | 2230 | data->count * sizeof(*data->bps)); |
2231 | kfree(data->bps); | |
2232 | } | |
2233 | ||
9dc23a63 | 2234 | data->bps = bps; |
c030f2e4 | 2235 | data->space_left += align_space - old_space; |
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | /* it deal with vram only. */ | |
2240 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 2241 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 2242 | { |
2243 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 2244 | struct ras_err_handler_data *data; |
c030f2e4 | 2245 | int ret = 0; |
676deb38 | 2246 | uint32_t i; |
c030f2e4 | 2247 | |
73aa8e1a | 2248 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 2249 | return 0; |
2250 | ||
2251 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 2252 | data = con->eh_data; |
c030f2e4 | 2253 | if (!data) |
2254 | goto out; | |
2255 | ||
676deb38 DL |
2256 | for (i = 0; i < pages; i++) { |
2257 | if (amdgpu_ras_check_bad_page_unlock(con, | |
2258 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
2259 | continue; | |
2260 | ||
2261 | if (!data->space_left && | |
2262 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 2263 | ret = -ENOMEM; |
2264 | goto out; | |
2265 | } | |
2266 | ||
ec6aae97 | 2267 | amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, |
676deb38 DL |
2268 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, |
2269 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 2270 | |
676deb38 DL |
2271 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
2272 | data->count++; | |
2273 | data->space_left--; | |
2274 | } | |
c030f2e4 | 2275 | out: |
2276 | mutex_unlock(&con->recovery_lock); | |
2277 | ||
2278 | return ret; | |
2279 | } | |
2280 | ||
78ad00c9 TZ |
2281 | /* |
2282 | * write error record array to eeprom, the function should be | |
2283 | * protected by recovery_lock | |
4d33e0f1 | 2284 | * new_cnt: new added UE count, excluding reserved bad pages, can be NULL |
78ad00c9 | 2285 | */ |
4d33e0f1 TZ |
2286 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, |
2287 | unsigned long *new_cnt) | |
78ad00c9 TZ |
2288 | { |
2289 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2290 | struct ras_err_handler_data *data; | |
8a3e801f | 2291 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
2292 | int save_count; |
2293 | ||
4d33e0f1 TZ |
2294 | if (!con || !con->eh_data) { |
2295 | if (new_cnt) | |
2296 | *new_cnt = 0; | |
2297 | ||
78ad00c9 | 2298 | return 0; |
4d33e0f1 | 2299 | } |
78ad00c9 | 2300 | |
d9a69fe5 | 2301 | mutex_lock(&con->recovery_lock); |
8a3e801f | 2302 | control = &con->eeprom_control; |
78ad00c9 | 2303 | data = con->eh_data; |
0686627b | 2304 | save_count = data->count - control->ras_num_recs; |
d9a69fe5 | 2305 | mutex_unlock(&con->recovery_lock); |
4d33e0f1 TZ |
2306 | |
2307 | if (new_cnt) | |
2308 | *new_cnt = save_count / adev->umc.retire_unit; | |
2309 | ||
78ad00c9 | 2310 | /* only new entries are saved */ |
b1628425 | 2311 | if (save_count > 0) { |
63d4c081 LT |
2312 | if (amdgpu_ras_eeprom_append(control, |
2313 | &data->bps[control->ras_num_recs], | |
2314 | save_count)) { | |
6952e99c | 2315 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
2316 | return -EIO; |
2317 | } | |
2318 | ||
b1628425 GC |
2319 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
2320 | } | |
2321 | ||
78ad00c9 TZ |
2322 | return 0; |
2323 | } | |
2324 | ||
2325 | /* | |
2326 | * read error record array in eeprom and reserve enough space for | |
2327 | * storing new bad pages | |
2328 | */ | |
2329 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
2330 | { | |
2331 | struct amdgpu_ras_eeprom_control *control = | |
6457205c | 2332 | &adev->psp.ras_context.ras->eeprom_control; |
e4e6a589 LT |
2333 | struct eeprom_table_record *bps; |
2334 | int ret; | |
78ad00c9 TZ |
2335 | |
2336 | /* no bad page record, skip eeprom access */ | |
0686627b | 2337 | if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) |
e4e6a589 | 2338 | return 0; |
78ad00c9 | 2339 | |
0686627b | 2340 | bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); |
78ad00c9 TZ |
2341 | if (!bps) |
2342 | return -ENOMEM; | |
2343 | ||
0686627b | 2344 | ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); |
e4e6a589 | 2345 | if (ret) |
6952e99c | 2346 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
e4e6a589 | 2347 | else |
0686627b | 2348 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); |
78ad00c9 | 2349 | |
78ad00c9 TZ |
2350 | kfree(bps); |
2351 | return ret; | |
2352 | } | |
2353 | ||
676deb38 DL |
2354 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
2355 | uint64_t addr) | |
2356 | { | |
2357 | struct ras_err_handler_data *data = con->eh_data; | |
2358 | int i; | |
2359 | ||
2360 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
2361 | for (i = 0; i < data->count; i++) | |
2362 | if (addr == data->bps[i].retired_page) | |
2363 | return true; | |
2364 | ||
2365 | return false; | |
2366 | } | |
2367 | ||
6e4be987 TZ |
2368 | /* |
2369 | * check if an address belongs to bad page | |
2370 | * | |
2371 | * Note: this check is only for umc block | |
2372 | */ | |
2373 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
2374 | uint64_t addr) | |
2375 | { | |
2376 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
2377 | bool ret = false; |
2378 | ||
2379 | if (!con || !con->eh_data) | |
2380 | return ret; | |
2381 | ||
2382 | mutex_lock(&con->recovery_lock); | |
676deb38 | 2383 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
2384 | mutex_unlock(&con->recovery_lock); |
2385 | return ret; | |
2386 | } | |
2387 | ||
e5c04edf | 2388 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
e4e6a589 | 2389 | uint32_t max_count) |
c84d4670 | 2390 | { |
e5c04edf | 2391 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
2392 | |
2393 | /* | |
2394 | * Justification of value bad_page_cnt_threshold in ras structure | |
2395 | * | |
f3cbe70e TZ |
2396 | * Generally, 0 <= amdgpu_bad_page_threshold <= max record length |
2397 | * in eeprom or amdgpu_bad_page_threshold == -2, introduce two | |
2398 | * scenarios accordingly. | |
c84d4670 GC |
2399 | * |
2400 | * Bad page retirement enablement: | |
f3cbe70e | 2401 | * - If amdgpu_bad_page_threshold = -2, |
c84d4670 GC |
2402 | * bad_page_cnt_threshold = typical value by formula. |
2403 | * | |
2404 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
2405 | * max record length in eeprom, use it directly. | |
2406 | * | |
2407 | * Bad page retirement disablement: | |
2408 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
2409 | * functionality is disabled, and bad_page_cnt_threshold will | |
2410 | * take no effect. | |
2411 | */ | |
2412 | ||
e4e6a589 LT |
2413 | if (amdgpu_bad_page_threshold < 0) { |
2414 | u64 val = adev->gmc.mc_vram_size; | |
c84d4670 | 2415 | |
e4e6a589 | 2416 | do_div(val, RAS_BAD_PAGE_COVER); |
e5c04edf | 2417 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
e4e6a589 | 2418 | max_count); |
e5c04edf | 2419 | } else { |
e4e6a589 LT |
2420 | con->bad_page_cnt_threshold = min_t(int, max_count, |
2421 | amdgpu_bad_page_threshold); | |
c84d4670 GC |
2422 | } |
2423 | } | |
2424 | ||
1a6fc071 | 2425 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 2426 | { |
2427 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 2428 | struct ras_err_handler_data **data; |
e4e6a589 | 2429 | u32 max_eeprom_records_count = 0; |
b82e65a9 | 2430 | bool exc_err_limit = false; |
78ad00c9 | 2431 | int ret; |
c030f2e4 | 2432 | |
e0e146d5 | 2433 | if (!con || amdgpu_sriov_vf(adev)) |
1d9d2ca8 LT |
2434 | return 0; |
2435 | ||
2436 | /* Allow access to RAS EEPROM via debugfs, when the ASIC | |
2437 | * supports RAS and debugfs is enabled, but when | |
2438 | * adev->ras_enabled is unset, i.e. when "ras_enable" | |
2439 | * module parameter is set to 0. | |
2440 | */ | |
2441 | con->adev = adev; | |
2442 | ||
2443 | if (!adev->ras_enabled) | |
4d1337d2 AG |
2444 | return 0; |
2445 | ||
1d9d2ca8 | 2446 | data = &con->eh_data; |
1a6fc071 TZ |
2447 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
2448 | if (!*data) { | |
2449 | ret = -ENOMEM; | |
2450 | goto out; | |
2451 | } | |
c030f2e4 | 2452 | |
2453 | mutex_init(&con->recovery_lock); | |
2454 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
2455 | atomic_set(&con->in_recovery, 0); | |
69691c82 | 2456 | con->eeprom_control.bad_channel_bitmap = 0; |
c030f2e4 | 2457 | |
7f599fed | 2458 | max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); |
e4e6a589 | 2459 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); |
c84d4670 | 2460 | |
e5086659 | 2461 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
2462 | * when the GPU is pending on XGMI reset during probe time | |
2463 | * (Mostly after second bus reset), skip it now | |
2464 | */ | |
2465 | if (adev->gmc.xgmi.pending_reset) | |
2466 | return 0; | |
b82e65a9 GC |
2467 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
2468 | /* | |
2469 | * This calling fails when exc_err_limit is true or | |
2470 | * ret != 0. | |
2471 | */ | |
2472 | if (exc_err_limit || ret) | |
1a6fc071 | 2473 | goto free; |
78ad00c9 | 2474 | |
0686627b | 2475 | if (con->eeprom_control.ras_num_recs) { |
78ad00c9 TZ |
2476 | ret = amdgpu_ras_load_bad_pages(adev); |
2477 | if (ret) | |
1a6fc071 | 2478 | goto free; |
513befa6 | 2479 | |
bc143d8b | 2480 | amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); |
69691c82 SY |
2481 | |
2482 | if (con->update_channel_flag == true) { | |
2483 | amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); | |
2484 | con->update_channel_flag = false; | |
2485 | } | |
78ad00c9 | 2486 | } |
c030f2e4 | 2487 | |
12b2cab7 MJ |
2488 | #ifdef CONFIG_X86_MCE_AMD |
2489 | if ((adev->asic_type == CHIP_ALDEBARAN) && | |
2490 | (adev->gmc.xgmi.connected_to_cpu)) | |
91a1a52d | 2491 | amdgpu_register_bad_pages_mca_notifier(adev); |
12b2cab7 | 2492 | #endif |
c030f2e4 | 2493 | return 0; |
1a6fc071 | 2494 | |
1a6fc071 | 2495 | free: |
1a6fc071 | 2496 | kfree((*data)->bps); |
1a6fc071 | 2497 | kfree(*data); |
1995b3a3 | 2498 | con->eh_data = NULL; |
1a6fc071 | 2499 | out: |
cf696091 | 2500 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2501 | |
b82e65a9 GC |
2502 | /* |
2503 | * Except error threshold exceeding case, other failure cases in this | |
2504 | * function would not fail amdgpu driver init. | |
2505 | */ | |
2506 | if (!exc_err_limit) | |
2507 | ret = 0; | |
2508 | else | |
2509 | ret = -EINVAL; | |
2510 | ||
1a6fc071 | 2511 | return ret; |
c030f2e4 | 2512 | } |
2513 | ||
2514 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2515 | { | |
2516 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2517 | struct ras_err_handler_data *data = con->eh_data; | |
2518 | ||
1a6fc071 TZ |
2519 | /* recovery_init failed to init it, fini is useless */ |
2520 | if (!data) | |
2521 | return 0; | |
2522 | ||
c030f2e4 | 2523 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2524 | |
2525 | mutex_lock(&con->recovery_lock); | |
2526 | con->eh_data = NULL; | |
2527 | kfree(data->bps); | |
2528 | kfree(data); | |
2529 | mutex_unlock(&con->recovery_lock); | |
2530 | ||
2531 | return 0; | |
2532 | } | |
2533 | /* recovery end */ | |
2534 | ||
084e2640 | 2535 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2536 | { |
82835055 | 2537 | if (amdgpu_sriov_vf(adev)) { |
4e8303cf | 2538 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
82835055 | 2539 | case IP_VERSION(13, 0, 2): |
80578f16 | 2540 | case IP_VERSION(13, 0, 6): |
82835055 YC |
2541 | return true; |
2542 | default: | |
2543 | return false; | |
2544 | } | |
2545 | } | |
2546 | ||
073285ef | 2547 | if (adev->asic_type == CHIP_IP_DISCOVERY) { |
4e8303cf | 2548 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
073285ef | 2549 | case IP_VERSION(13, 0, 0): |
cb906ce3 | 2550 | case IP_VERSION(13, 0, 6): |
073285ef YC |
2551 | case IP_VERSION(13, 0, 10): |
2552 | return true; | |
2553 | default: | |
2554 | return false; | |
2555 | } | |
2556 | } | |
2557 | ||
084e2640 LT |
2558 | return adev->asic_type == CHIP_VEGA10 || |
2559 | adev->asic_type == CHIP_VEGA20 || | |
2560 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2561 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2562 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2563 | } |
2564 | ||
f50160cf SY |
2565 | /* |
2566 | * this is workaround for vega20 workstation sku, | |
2567 | * force enable gfx ras, ignore vbios gfx ras flag | |
2568 | * due to GC EDC can not write | |
2569 | */ | |
e509965e | 2570 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2571 | { |
2572 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2573 | ||
2574 | if (!ctx) | |
2575 | return; | |
2576 | ||
adf64e21 ML |
2577 | if (strnstr(ctx->vbios_pn, "D16406", |
2578 | sizeof(ctx->vbios_pn)) || | |
2579 | strnstr(ctx->vbios_pn, "D36002", | |
2580 | sizeof(ctx->vbios_pn))) | |
8ab0d6f0 | 2581 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2582 | } |
2583 | ||
5caf466a | 2584 | /* |
2585 | * check hardware's ras ability which will be saved in hw_supported. | |
2586 | * if hardware does not support ras, we can skip some ras initializtion and | |
2587 | * forbid some ras operations from IP. | |
2588 | * if software itself, say boot parameter, limit the ras ability. We still | |
2589 | * need allow IP do some limited operations, like disable. In such case, | |
2590 | * we have to initialize ras as normal. but need check if operation is | |
2591 | * allowed or not in each function. | |
2592 | */ | |
e509965e | 2593 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2594 | { |
8ab0d6f0 | 2595 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2596 | |
38298ce6 | 2597 | if (!amdgpu_ras_asic_supported(adev)) |
5caf466a | 2598 | return; |
b404ae82 | 2599 | |
38298ce6 | 2600 | if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { |
75f06251 HZ |
2601 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
2602 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2603 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2604 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2605 | } else { |
2606 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2607 | } | |
88474cca | 2608 | |
75f06251 HZ |
2609 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2610 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
3189501e | 2611 | if (!amdgpu_sriov_vf(adev)) |
950d6425 SY |
2612 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
2613 | 1 << AMDGPU_RAS_BLOCK__DF); | |
3189501e | 2614 | else |
950d6425 SY |
2615 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | |
2616 | 1 << AMDGPU_RAS_BLOCK__SDMA | | |
2617 | 1 << AMDGPU_RAS_BLOCK__GFX); | |
3189501e TZ |
2618 | |
2619 | /* VCN/JPEG RAS can be supported on both bare metal and | |
2620 | * SRIOV environment | |
2621 | */ | |
4e8303cf LL |
2622 | if (amdgpu_ip_version(adev, VCN_HWIP, 0) == |
2623 | IP_VERSION(2, 6, 0) || | |
2624 | amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
9248462d HZ |
2625 | IP_VERSION(4, 0, 0) || |
2626 | amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
2627 | IP_VERSION(4, 0, 3)) | |
3189501e TZ |
2628 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | |
2629 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
2630 | else | |
2631 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | | |
2632 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
58bc2a9c SY |
2633 | |
2634 | /* | |
2635 | * XGMI RAS is not supported if xgmi num physical nodes | |
2636 | * is zero | |
2637 | */ | |
2638 | if (!adev->gmc.xgmi.num_physical_nodes) | |
2639 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); | |
75f06251 HZ |
2640 | } else { |
2641 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2642 | } | |
2643 | } else { | |
2644 | /* driver only manages a few IP blocks RAS feature | |
2645 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2646 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2647 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2648 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2649 | } |
88474cca | 2650 | |
e509965e | 2651 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2652 | |
88474cca | 2653 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2654 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2655 | |
66d64e4e SY |
2656 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2657 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2658 | } |
2659 | ||
05adfd80 LT |
2660 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2661 | { | |
2662 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2663 | ras_counte_delay_work.work); | |
2664 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2665 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2666 | unsigned long ce_count, ue_count; |
2667 | int res; | |
2668 | ||
2669 | res = pm_runtime_get_sync(dev->dev); | |
2670 | if (res < 0) | |
2671 | goto Out; | |
2672 | ||
2673 | /* Cache new values. | |
2674 | */ | |
4a1c9a44 | 2675 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) { |
4d9f771e LT |
2676 | atomic_set(&con->ras_ce_count, ce_count); |
2677 | atomic_set(&con->ras_ue_count, ue_count); | |
2678 | } | |
05adfd80 LT |
2679 | |
2680 | pm_runtime_mark_last_busy(dev->dev); | |
2681 | Out: | |
2682 | pm_runtime_put_autosuspend(dev->dev); | |
2683 | } | |
2684 | ||
2dd9032b TZ |
2685 | static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) |
2686 | { | |
2687 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2688 | bool df_poison, umc_poison; | |
2689 | ||
2690 | /* poison setting is useless on SRIOV guest */ | |
2691 | if (amdgpu_sriov_vf(adev) || !con) | |
2692 | return; | |
2693 | ||
2694 | /* Init poison supported flag, the default value is false */ | |
2695 | if (adev->gmc.xgmi.connected_to_cpu) { | |
2696 | /* enabled by default when GPU is connected to CPU */ | |
2697 | con->poison_supported = true; | |
2698 | } else if (adev->df.funcs && | |
2699 | adev->df.funcs->query_ras_poison_mode && | |
2700 | adev->umc.ras && | |
2701 | adev->umc.ras->query_ras_poison_mode) { | |
2702 | df_poison = | |
2703 | adev->df.funcs->query_ras_poison_mode(adev); | |
2704 | umc_poison = | |
2705 | adev->umc.ras->query_ras_poison_mode(adev); | |
2706 | ||
2707 | /* Only poison is set in both DF and UMC, we can support it */ | |
2708 | if (df_poison && umc_poison) | |
2709 | con->poison_supported = true; | |
2710 | else if (df_poison != umc_poison) | |
2711 | dev_warn(adev->dev, | |
2712 | "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
2713 | df_poison, umc_poison); | |
2714 | } | |
2715 | } | |
2716 | ||
625e5f38 AK |
2717 | static int amdgpu_get_ras_schema(struct amdgpu_device *adev) |
2718 | { | |
2719 | return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 | | |
2720 | AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE | | |
2721 | AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE | | |
2722 | AMDGPU_RAS_ERROR__PARITY; | |
2723 | } | |
2724 | ||
c030f2e4 | 2725 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2726 | { | |
2727 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2728 | int r; |
c030f2e4 | 2729 | |
b404ae82 | 2730 | if (con) |
c030f2e4 | 2731 | return 0; |
2732 | ||
2733 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
640ae42e JC |
2734 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + |
2735 | sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, | |
c030f2e4 | 2736 | GFP_KERNEL|__GFP_ZERO); |
2737 | if (!con) | |
2738 | return -ENOMEM; | |
2739 | ||
05adfd80 LT |
2740 | con->adev = adev; |
2741 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2742 | atomic_set(&con->ras_ce_count, 0); | |
2743 | atomic_set(&con->ras_ue_count, 0); | |
2744 | ||
c030f2e4 | 2745 | con->objs = (struct ras_manager *)(con + 1); |
2746 | ||
2747 | amdgpu_ras_set_context(adev, con); | |
2748 | ||
e509965e LT |
2749 | amdgpu_ras_check_supported(adev); |
2750 | ||
7ddd9770 | 2751 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2752 | /* set gfx block ras context feature for VEGA20 Gaming |
2753 | * send ras disable cmd to ras ta during ras late init. | |
2754 | */ | |
8ab0d6f0 | 2755 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2756 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2757 | ||
2758 | return 0; | |
2759 | } | |
2760 | ||
5e91160a | 2761 | r = 0; |
5436ab94 | 2762 | goto release_con; |
fb2a3607 HZ |
2763 | } |
2764 | ||
69691c82 | 2765 | con->update_channel_flag = false; |
c030f2e4 | 2766 | con->features = 0; |
625e5f38 | 2767 | con->schema = 0; |
c030f2e4 | 2768 | INIT_LIST_HEAD(&con->head); |
108c6a63 | 2769 | /* Might need get this flag from vbios. */ |
2770 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2771 | |
6e36f231 HZ |
2772 | /* initialize nbio ras function ahead of any other |
2773 | * ras functions so hardware fatal error interrupt | |
2774 | * can be enabled as early as possible */ | |
4e8303cf | 2775 | switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { |
fdc94d3a HZ |
2776 | case IP_VERSION(7, 4, 0): |
2777 | case IP_VERSION(7, 4, 1): | |
2778 | case IP_VERSION(7, 4, 4): | |
2779 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2e54fe5d | 2780 | adev->nbio.ras = &nbio_v7_4_ras; |
6e36f231 | 2781 | break; |
9af357bc HZ |
2782 | case IP_VERSION(4, 3, 0): |
2783 | if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) | |
2784 | /* unlike other generation of nbio ras, | |
2785 | * nbio v4_3 only support fatal error interrupt | |
2786 | * to inform software that DF is freezed due to | |
2787 | * system fatal error event. driver should not | |
2788 | * enable nbio ras in such case. Instead, | |
2789 | * check DF RAS */ | |
2790 | adev->nbio.ras = &nbio_v4_3_ras; | |
2791 | break; | |
7692e1ee TZ |
2792 | case IP_VERSION(7, 9, 0): |
2793 | if (!adev->gmc.is_app_apu) | |
2794 | adev->nbio.ras = &nbio_v7_9_ras; | |
2795 | break; | |
6e36f231 HZ |
2796 | default: |
2797 | /* nbio ras is not available */ | |
2798 | break; | |
2799 | } | |
2800 | ||
fdc94d3a HZ |
2801 | /* nbio ras block needs to be enabled ahead of other ras blocks |
2802 | * to handle fatal error */ | |
2803 | r = amdgpu_nbio_ras_sw_init(adev); | |
2804 | if (r) | |
2805 | return r; | |
2806 | ||
2e54fe5d | 2807 | if (adev->nbio.ras && |
2808 | adev->nbio.ras->init_ras_controller_interrupt) { | |
2809 | r = adev->nbio.ras->init_ras_controller_interrupt(adev); | |
4e644fff | 2810 | if (r) |
5436ab94 | 2811 | goto release_con; |
4e644fff HZ |
2812 | } |
2813 | ||
2e54fe5d | 2814 | if (adev->nbio.ras && |
2815 | adev->nbio.ras->init_ras_err_event_athub_interrupt) { | |
2816 | r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2817 | if (r) |
5436ab94 | 2818 | goto release_con; |
4e644fff HZ |
2819 | } |
2820 | ||
2dd9032b | 2821 | amdgpu_ras_query_poison_mode(adev); |
e4348849 | 2822 | |
625e5f38 AK |
2823 | /* Get RAS schema for particular SOC */ |
2824 | con->schema = amdgpu_get_ras_schema(adev); | |
2825 | ||
5e91160a GC |
2826 | if (amdgpu_ras_fs_init(adev)) { |
2827 | r = -EINVAL; | |
5436ab94 | 2828 | goto release_con; |
5e91160a | 2829 | } |
c030f2e4 | 2830 | |
6952e99c | 2831 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2832 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2833 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2834 | |
c030f2e4 | 2835 | return 0; |
5436ab94 | 2836 | release_con: |
c030f2e4 | 2837 | amdgpu_ras_set_context(adev, NULL); |
2838 | kfree(con); | |
2839 | ||
5e91160a | 2840 | return r; |
c030f2e4 | 2841 | } |
2842 | ||
8f6368a9 | 2843 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 | 2844 | { |
8107e499 HZ |
2845 | if (adev->gmc.xgmi.connected_to_cpu || |
2846 | adev->gmc.is_app_apu) | |
134d16d5 JC |
2847 | return 1; |
2848 | return 0; | |
2849 | } | |
2850 | ||
2851 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2852 | struct ras_common_if *ras_block) | |
2853 | { | |
2854 | struct ras_query_if info = { | |
2855 | .head = *ras_block, | |
2856 | }; | |
2857 | ||
2858 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2859 | return 0; | |
2860 | ||
2861 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2862 | DRM_WARN("RAS init harvest failure"); | |
2863 | ||
2864 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2865 | DRM_WARN("RAS init harvest reset failure"); | |
2866 | ||
2867 | return 0; | |
2868 | } | |
2869 | ||
e4348849 TZ |
2870 | bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) |
2871 | { | |
2872 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2873 | ||
2874 | if (!con) | |
2875 | return false; | |
2876 | ||
2877 | return con->poison_supported; | |
2878 | } | |
2879 | ||
b293e891 | 2880 | /* helper function to handle common stuff in ip late init phase */ |
563285c8 | 2881 | int amdgpu_ras_block_late_init(struct amdgpu_device *adev, |
2882 | struct ras_common_if *ras_block) | |
b293e891 | 2883 | { |
29c9b6cd | 2884 | struct amdgpu_ras_block_object *ras_obj = NULL; |
05adfd80 | 2885 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
4a1c9a44 | 2886 | struct ras_query_if *query_info; |
05adfd80 | 2887 | unsigned long ue_count, ce_count; |
b293e891 HZ |
2888 | int r; |
2889 | ||
2890 | /* disable RAS feature per IP block if it is not supported */ | |
2891 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2892 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2893 | return 0; | |
2894 | } | |
2895 | ||
2896 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2897 | if (r) { | |
9080a18f | 2898 | if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2899 | /* in resume phase, if fail to enable ras, |
2900 | * clean up all ras fs nodes, and disable ras */ | |
2901 | goto cleanup; | |
2902 | } else | |
2903 | return r; | |
2904 | } | |
2905 | ||
134d16d5 JC |
2906 | /* check for errors on warm reset edc persisant supported ASIC */ |
2907 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2908 | ||
b293e891 | 2909 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2910 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2911 | return 0; |
2912 | ||
563285c8 | 2913 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
36780606 TZ |
2914 | if (ras_obj->ras_cb || (ras_obj->hw_ops && |
2915 | (ras_obj->hw_ops->query_poison_status || | |
2916 | ras_obj->hw_ops->handle_poison_consumption))) { | |
9252d33d | 2917 | r = amdgpu_ras_interrupt_add_handler(adev, ras_block); |
b293e891 | 2918 | if (r) |
779596ce | 2919 | goto cleanup; |
b293e891 HZ |
2920 | } |
2921 | ||
f957138c HZ |
2922 | if (ras_obj->hw_ops && |
2923 | (ras_obj->hw_ops->query_ras_error_count || | |
2924 | ras_obj->hw_ops->query_ras_error_status)) { | |
2925 | r = amdgpu_ras_sysfs_create(adev, ras_block); | |
2926 | if (r) | |
2927 | goto interrupt; | |
b293e891 | 2928 | |
f957138c HZ |
2929 | /* Those are the cached values at init. |
2930 | */ | |
2931 | query_info = kzalloc(sizeof(*query_info), GFP_KERNEL); | |
2932 | if (!query_info) | |
2933 | return -ENOMEM; | |
2934 | memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if)); | |
4a1c9a44 | 2935 | |
f957138c HZ |
2936 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) { |
2937 | atomic_set(&con->ras_ce_count, ce_count); | |
2938 | atomic_set(&con->ras_ue_count, ue_count); | |
2939 | } | |
2940 | ||
2941 | kfree(query_info); | |
4d9f771e | 2942 | } |
05adfd80 | 2943 | |
b293e891 | 2944 | return 0; |
779596ce TR |
2945 | |
2946 | interrupt: | |
563285c8 | 2947 | if (ras_obj->ras_cb) |
9252d33d | 2948 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); |
779596ce | 2949 | cleanup: |
b293e891 HZ |
2950 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2951 | return r; | |
2952 | } | |
2953 | ||
d41ff22a | 2954 | static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev, |
418abce2 | 2955 | struct ras_common_if *ras_block) |
2956 | { | |
2957 | return amdgpu_ras_block_late_init(adev, ras_block); | |
2958 | } | |
2959 | ||
b293e891 | 2960 | /* helper function to remove ras fs node and interrupt handler */ |
bdb3489c | 2961 | void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, |
2962 | struct ras_common_if *ras_block) | |
2963 | { | |
563285c8 | 2964 | struct amdgpu_ras_block_object *ras_obj; |
bdb3489c | 2965 | if (!ras_block) |
2966 | return; | |
2967 | ||
563285c8 | 2968 | amdgpu_ras_sysfs_remove(adev, ras_block); |
bdb3489c | 2969 | |
563285c8 | 2970 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
2971 | if (ras_obj->ras_cb) | |
2972 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); | |
bdb3489c | 2973 | } |
2974 | ||
80e0c2cb | 2975 | static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev, |
2976 | struct ras_common_if *ras_block) | |
2977 | { | |
2978 | return amdgpu_ras_block_late_fini(adev, ras_block); | |
2979 | } | |
2980 | ||
a564808e | 2981 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2982 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2983 | */ |
511fdbc3 | 2984 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2985 | { |
2986 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2987 | struct ras_manager *obj, *tmp; | |
2988 | ||
8ab0d6f0 | 2989 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2990 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2991 | amdgpu_release_ras_context(adev); | |
2992 | ||
108c6a63 | 2993 | return; |
970fd197 | 2994 | } |
108c6a63 | 2995 | |
108c6a63 | 2996 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2997 | /* Set up all other IPs which are not implemented. There is a |
2998 | * tricky thing that IP's actual ras error type should be | |
2999 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
3000 | * ERROR_NONE make sense anyway. | |
3001 | */ | |
3002 | amdgpu_ras_enable_all_features(adev, 1); | |
3003 | ||
3004 | /* We enable ras on all hw_supported block, but as boot | |
3005 | * parameter might disable some of them and one or more IP has | |
3006 | * not implemented yet. So we disable them on behalf. | |
3007 | */ | |
108c6a63 | 3008 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
3009 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
3010 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
3011 | /* there should be no any reference. */ | |
3012 | WARN_ON(alive_obj(obj)); | |
3013 | } | |
191051a1 | 3014 | } |
108c6a63 | 3015 | } |
3016 | } | |
3017 | ||
511fdbc3 | 3018 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
3019 | { | |
3020 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3021 | ||
8ab0d6f0 | 3022 | if (!adev->ras_enabled || !con) |
511fdbc3 | 3023 | return; |
3024 | ||
3025 | amdgpu_ras_disable_all_features(adev, 0); | |
3026 | /* Make sure all ras objects are disabled. */ | |
3027 | if (con->features) | |
3028 | amdgpu_ras_disable_all_features(adev, 1); | |
3029 | } | |
3030 | ||
867e24ca | 3031 | int amdgpu_ras_late_init(struct amdgpu_device *adev) |
3032 | { | |
3033 | struct amdgpu_ras_block_list *node, *tmp; | |
3034 | struct amdgpu_ras_block_object *obj; | |
3035 | int r; | |
3036 | ||
950d6425 SY |
3037 | /* Guest side doesn't need init ras feature */ |
3038 | if (amdgpu_sriov_vf(adev)) | |
3039 | return 0; | |
3040 | ||
867e24ca | 3041 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
3042 | if (!node->ras_obj) { | |
3043 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
3044 | continue; | |
3045 | } | |
418abce2 | 3046 | |
867e24ca | 3047 | obj = node->ras_obj; |
3048 | if (obj->ras_late_init) { | |
3049 | r = obj->ras_late_init(adev, &obj->ras_comm); | |
3050 | if (r) { | |
3051 | dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n", | |
3052 | obj->ras_comm.name, r); | |
3053 | return r; | |
3054 | } | |
418abce2 | 3055 | } else |
3056 | amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); | |
867e24ca | 3057 | } |
3058 | ||
3059 | return 0; | |
3060 | } | |
3061 | ||
c030f2e4 | 3062 | /* do some fini work before IP fini as dependence */ |
3063 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
3064 | { | |
3065 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3066 | ||
8ab0d6f0 | 3067 | if (!adev->ras_enabled || !con) |
c030f2e4 | 3068 | return 0; |
3069 | ||
72c8c97b | 3070 | |
c030f2e4 | 3071 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
642c0401 YC |
3072 | if (con->features) |
3073 | amdgpu_ras_disable_all_features(adev, 0); | |
c030f2e4 | 3074 | amdgpu_ras_recovery_fini(adev); |
3075 | return 0; | |
3076 | } | |
3077 | ||
3078 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
3079 | { | |
d5e8ff5f | 3080 | struct amdgpu_ras_block_list *ras_node, *tmp; |
1f211a82 | 3081 | struct amdgpu_ras_block_object *obj = NULL; |
c030f2e4 | 3082 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
3083 | ||
8ab0d6f0 | 3084 | if (!adev->ras_enabled || !con) |
c030f2e4 | 3085 | return 0; |
3086 | ||
1f211a82 | 3087 | list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { |
3088 | if (ras_node->ras_obj) { | |
3089 | obj = ras_node->ras_obj; | |
3090 | if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) && | |
3091 | obj->ras_fini) | |
3092 | obj->ras_fini(adev, &obj->ras_comm); | |
80e0c2cb | 3093 | else |
3094 | amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm); | |
1f211a82 | 3095 | } |
3096 | ||
3097 | /* Clear ras blocks from ras_list and free ras block list node */ | |
3098 | list_del(&ras_node->node); | |
3099 | kfree(ras_node); | |
3100 | } | |
3101 | ||
c030f2e4 | 3102 | amdgpu_ras_fs_fini(adev); |
3103 | amdgpu_ras_interrupt_remove_all(adev); | |
3104 | ||
3105 | WARN(con->features, "Feature mask is not cleared"); | |
3106 | ||
3107 | if (con->features) | |
3108 | amdgpu_ras_disable_all_features(adev, 1); | |
3109 | ||
05adfd80 LT |
3110 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
3111 | ||
c030f2e4 | 3112 | amdgpu_ras_set_context(adev, NULL); |
3113 | kfree(con); | |
3114 | ||
3115 | return 0; | |
3116 | } | |
7c6e68c7 AG |
3117 | |
3118 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
3119 | { | |
3120 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { | |
2c7cd280 YC |
3121 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
3122 | ||
6952e99c GC |
3123 | dev_info(adev->dev, "uncorrectable hardware error" |
3124 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 3125 | |
2c7cd280 | 3126 | ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; |
61934624 | 3127 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
3128 | } |
3129 | } | |
bb5c7235 WS |
3130 | |
3131 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
3132 | { | |
3133 | if (adev->asic_type == CHIP_VEGA20 && | |
3134 | adev->pm.fw_version <= 0x283400) { | |
3135 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
3136 | amdgpu_ras_intr_triggered(); | |
3137 | } | |
3138 | ||
3139 | return false; | |
3140 | } | |
970fd197 SY |
3141 | |
3142 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
3143 | { | |
3144 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3145 | ||
3146 | if (!con) | |
3147 | return; | |
3148 | ||
8ab0d6f0 | 3149 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
3150 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
3151 | amdgpu_ras_set_context(adev, NULL); | |
3152 | kfree(con); | |
3153 | } | |
3154 | } | |
12b2cab7 MJ |
3155 | |
3156 | #ifdef CONFIG_X86_MCE_AMD | |
3157 | static struct amdgpu_device *find_adev(uint32_t node_id) | |
3158 | { | |
12b2cab7 MJ |
3159 | int i; |
3160 | struct amdgpu_device *adev = NULL; | |
3161 | ||
91a1a52d MJ |
3162 | for (i = 0; i < mce_adev_list.num_gpu; i++) { |
3163 | adev = mce_adev_list.devs[i]; | |
12b2cab7 | 3164 | |
91a1a52d | 3165 | if (adev && adev->gmc.xgmi.connected_to_cpu && |
12b2cab7 MJ |
3166 | adev->gmc.xgmi.physical_node_id == node_id) |
3167 | break; | |
3168 | adev = NULL; | |
3169 | } | |
3170 | ||
12b2cab7 MJ |
3171 | return adev; |
3172 | } | |
3173 | ||
3174 | #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) | |
3175 | #define GET_UMC_INST(m) (((m) >> 21) & 0x7) | |
3176 | #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) | |
3177 | #define GPU_ID_OFFSET 8 | |
3178 | ||
3179 | static int amdgpu_bad_page_notifier(struct notifier_block *nb, | |
3180 | unsigned long val, void *data) | |
3181 | { | |
3182 | struct mce *m = (struct mce *)data; | |
3183 | struct amdgpu_device *adev = NULL; | |
3184 | uint32_t gpu_id = 0; | |
cd4c99f1 | 3185 | uint32_t umc_inst = 0, ch_inst = 0; |
12b2cab7 MJ |
3186 | |
3187 | /* | |
3188 | * If the error was generated in UMC_V2, which belongs to GPU UMCs, | |
3189 | * and error occurred in DramECC (Extended error code = 0) then only | |
3190 | * process the error, else bail out. | |
3191 | */ | |
91f75eb4 | 3192 | if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && |
12b2cab7 MJ |
3193 | (XEC(m->status, 0x3f) == 0x0))) |
3194 | return NOTIFY_DONE; | |
3195 | ||
3196 | /* | |
3197 | * If it is correctable error, return. | |
3198 | */ | |
3199 | if (mce_is_correctable(m)) | |
3200 | return NOTIFY_OK; | |
3201 | ||
3202 | /* | |
3203 | * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. | |
3204 | */ | |
3205 | gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; | |
3206 | ||
3207 | adev = find_adev(gpu_id); | |
3208 | if (!adev) { | |
3209 | DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, | |
3210 | gpu_id); | |
3211 | return NOTIFY_DONE; | |
3212 | } | |
3213 | ||
3214 | /* | |
3215 | * If it is uncorrectable error, then find out UMC instance and | |
3216 | * channel index. | |
3217 | */ | |
3218 | umc_inst = GET_UMC_INST(m->ipid); | |
3219 | ch_inst = GET_CHAN_INDEX(m->ipid); | |
3220 | ||
3221 | dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", | |
3222 | umc_inst, ch_inst); | |
3223 | ||
24b82292 TZ |
3224 | if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) |
3225 | return NOTIFY_OK; | |
3226 | else | |
6c0ca748 | 3227 | return NOTIFY_DONE; |
12b2cab7 MJ |
3228 | } |
3229 | ||
3230 | static struct notifier_block amdgpu_bad_page_nb = { | |
3231 | .notifier_call = amdgpu_bad_page_notifier, | |
3232 | .priority = MCE_PRIO_UC, | |
3233 | }; | |
3234 | ||
91a1a52d | 3235 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) |
12b2cab7 | 3236 | { |
91a1a52d MJ |
3237 | /* |
3238 | * Add the adev to the mce_adev_list. | |
3239 | * During mode2 reset, amdgpu device is temporarily | |
3240 | * removed from the mgpu_info list which can cause | |
3241 | * page retirement to fail. | |
3242 | * Use this list instead of mgpu_info to find the amdgpu | |
3243 | * device on which the UMC error was reported. | |
3244 | */ | |
3245 | mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; | |
3246 | ||
12b2cab7 MJ |
3247 | /* |
3248 | * Register the x86 notifier only once | |
3249 | * with MCE subsystem. | |
3250 | */ | |
3251 | if (notifier_registered == false) { | |
3252 | mce_register_decode_chain(&amdgpu_bad_page_nb); | |
3253 | notifier_registered = true; | |
3254 | } | |
3255 | } | |
3256 | #endif | |
7cab2124 | 3257 | |
b6efdb02 | 3258 | struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) |
7cab2124 | 3259 | { |
3260 | if (!adev) | |
3261 | return NULL; | |
3262 | ||
3263 | return adev->psp.ras_context.ras; | |
3264 | } | |
3265 | ||
b6efdb02 | 3266 | int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) |
7cab2124 | 3267 | { |
3268 | if (!adev) | |
69f91d32 | 3269 | return -EINVAL; |
7cab2124 | 3270 | |
3271 | adev->psp.ras_context.ras = ras_con; | |
3272 | return 0; | |
3273 | } | |
3274 | ||
3275 | /* check if ras is supported on block, say, sdma, gfx */ | |
3276 | int amdgpu_ras_is_supported(struct amdgpu_device *adev, | |
3277 | unsigned int block) | |
3278 | { | |
8f453c51 | 3279 | int ret = 0; |
7cab2124 | 3280 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
3281 | ||
3282 | if (block >= AMDGPU_RAS_BLOCK_COUNT) | |
3283 | return 0; | |
8f453c51 YC |
3284 | |
3285 | ret = ras && (adev->ras_enabled & (1 << block)); | |
3286 | ||
3287 | /* For the special asic with mem ecc enabled but sram ecc | |
3288 | * not enabled, even if the ras block is not supported on | |
3289 | * .ras_enabled, if the asic supports poison mode and the | |
3290 | * ras block has ras configuration, it can be considered | |
3291 | * that the ras block supports ras function. | |
3292 | */ | |
3293 | if (!ret && | |
bc0f8080 CL |
3294 | (block == AMDGPU_RAS_BLOCK__GFX || |
3295 | block == AMDGPU_RAS_BLOCK__SDMA || | |
3296 | block == AMDGPU_RAS_BLOCK__VCN || | |
3297 | block == AMDGPU_RAS_BLOCK__JPEG) && | |
8f453c51 YC |
3298 | amdgpu_ras_is_poison_mode_supported(adev) && |
3299 | amdgpu_ras_get_ras_block(adev, block, 0)) | |
3300 | ret = 1; | |
3301 | ||
3302 | return ret; | |
7cab2124 | 3303 | } |
3304 | ||
3305 | int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) | |
3306 | { | |
3307 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
3308 | ||
3309 | if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) | |
25a2b22e | 3310 | amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); |
7cab2124 | 3311 | return 0; |
3312 | } | |
3313 | ||
8096df76 TZ |
3314 | void amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable) |
3315 | { | |
3316 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3317 | ||
3318 | if (con) | |
3319 | con->is_mca_debug_mode = enable; | |
3320 | } | |
3321 | ||
3322 | bool amdgpu_ras_get_mca_debug_mode(struct amdgpu_device *adev) | |
3323 | { | |
3324 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3325 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; | |
3326 | ||
3327 | if (!con) | |
3328 | return false; | |
3329 | ||
3330 | if (mca_funcs && mca_funcs->mca_set_debug_mode) | |
3331 | return con->is_mca_debug_mode; | |
3332 | else | |
3333 | return true; | |
3334 | } | |
7cab2124 | 3335 | |
6492e1b0 | 3336 | /* Register each ip ras block into amdgpu ras */ |
3337 | int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, | |
b6efdb02 | 3338 | struct amdgpu_ras_block_object *ras_block_obj) |
6492e1b0 | 3339 | { |
d5e8ff5f | 3340 | struct amdgpu_ras_block_list *ras_node; |
6492e1b0 | 3341 | if (!adev || !ras_block_obj) |
3342 | return -EINVAL; | |
3343 | ||
d5e8ff5f | 3344 | ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); |
3345 | if (!ras_node) | |
3346 | return -ENOMEM; | |
3347 | ||
3348 | INIT_LIST_HEAD(&ras_node->node); | |
3349 | ras_node->ras_obj = ras_block_obj; | |
3350 | list_add_tail(&ras_node->node, &adev->ras_list); | |
6492e1b0 | 3351 | |
3352 | return 0; | |
3353 | } | |
322a7e00 HZ |
3354 | |
3355 | void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name) | |
3356 | { | |
3357 | if (!err_type_name) | |
3358 | return; | |
3359 | ||
3360 | switch (err_type) { | |
3361 | case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: | |
3362 | sprintf(err_type_name, "correctable"); | |
3363 | break; | |
3364 | case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: | |
3365 | sprintf(err_type_name, "uncorrectable"); | |
3366 | break; | |
3367 | default: | |
3368 | sprintf(err_type_name, "unknown"); | |
3369 | break; | |
3370 | } | |
3371 | } | |
3372 | ||
3373 | bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, | |
3374 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3375 | uint32_t instance, | |
3376 | uint32_t *memory_id) | |
3377 | { | |
3378 | uint32_t err_status_lo_data, err_status_lo_offset; | |
3379 | ||
3380 | if (!reg_entry) | |
3381 | return false; | |
3382 | ||
3383 | err_status_lo_offset = | |
3384 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3385 | reg_entry->seg_lo, reg_entry->reg_lo); | |
3386 | err_status_lo_data = RREG32(err_status_lo_offset); | |
3387 | ||
3388 | if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && | |
3389 | !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG)) | |
3390 | return false; | |
3391 | ||
3392 | *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID); | |
3393 | ||
3394 | return true; | |
3395 | } | |
3396 | ||
3397 | bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, | |
3398 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3399 | uint32_t instance, | |
3400 | unsigned long *err_cnt) | |
3401 | { | |
3402 | uint32_t err_status_hi_data, err_status_hi_offset; | |
3403 | ||
3404 | if (!reg_entry) | |
3405 | return false; | |
3406 | ||
3407 | err_status_hi_offset = | |
3408 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3409 | reg_entry->seg_hi, reg_entry->reg_hi); | |
3410 | err_status_hi_data = RREG32(err_status_hi_offset); | |
3411 | ||
3412 | if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && | |
3413 | !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG)) | |
9b337b7d HZ |
3414 | /* keep the check here in case we need to refer to the result later */ |
3415 | dev_dbg(adev->dev, "Invalid err_info field\n"); | |
322a7e00 HZ |
3416 | |
3417 | /* read err count */ | |
3418 | *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT); | |
3419 | ||
3420 | return true; | |
3421 | } | |
3422 | ||
3423 | void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, | |
3424 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3425 | uint32_t reg_list_size, | |
3426 | const struct amdgpu_ras_memory_id_entry *mem_list, | |
3427 | uint32_t mem_list_size, | |
3428 | uint32_t instance, | |
3429 | uint32_t err_type, | |
3430 | unsigned long *err_count) | |
3431 | { | |
3432 | uint32_t memory_id; | |
3433 | unsigned long err_cnt; | |
3434 | char err_type_name[16]; | |
3435 | uint32_t i, j; | |
3436 | ||
3437 | for (i = 0; i < reg_list_size; i++) { | |
9b337b7d HZ |
3438 | /* query memory_id from err_status_lo */ |
3439 | if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i], | |
3440 | instance, &memory_id)) | |
3441 | continue; | |
3442 | ||
322a7e00 HZ |
3443 | /* query err_cnt from err_status_hi */ |
3444 | if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i], | |
3445 | instance, &err_cnt) || | |
3446 | !err_cnt) | |
3447 | continue; | |
3448 | ||
322a7e00 HZ |
3449 | *err_count += err_cnt; |
3450 | ||
3451 | /* log the errors */ | |
3452 | amdgpu_ras_get_error_type_name(err_type, err_type_name); | |
3453 | if (!mem_list) { | |
3454 | /* memory_list is not supported */ | |
3455 | dev_info(adev->dev, | |
3456 | "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n", | |
3457 | err_cnt, err_type_name, | |
3458 | reg_list[i].block_name, | |
3459 | instance, memory_id); | |
3460 | } else { | |
3461 | for (j = 0; j < mem_list_size; j++) { | |
3462 | if (memory_id == mem_list[j].memory_id) { | |
3463 | dev_info(adev->dev, | |
3464 | "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n", | |
3465 | err_cnt, err_type_name, | |
3466 | reg_list[i].block_name, | |
3467 | instance, mem_list[j].name); | |
3468 | break; | |
3469 | } | |
3470 | } | |
3471 | } | |
3472 | } | |
3473 | } | |
e53a3250 HZ |
3474 | |
3475 | void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, | |
3476 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3477 | uint32_t reg_list_size, | |
3478 | uint32_t instance) | |
3479 | { | |
3480 | uint32_t err_status_lo_offset, err_status_hi_offset; | |
3481 | uint32_t i; | |
3482 | ||
3483 | for (i = 0; i < reg_list_size; i++) { | |
3484 | err_status_lo_offset = | |
3485 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3486 | reg_list[i].seg_lo, reg_list[i].reg_lo); | |
3487 | err_status_hi_offset = | |
3488 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3489 | reg_list[i].seg_hi, reg_list[i].reg_hi); | |
3490 | WREG32(err_status_lo_offset, 0); | |
3491 | WREG32(err_status_hi_offset, 0); | |
3492 | } | |
3493 | } | |
5b1270be YW |
3494 | |
3495 | int amdgpu_ras_error_data_init(struct ras_err_data *err_data) | |
3496 | { | |
3497 | memset(err_data, 0, sizeof(*err_data)); | |
3498 | ||
3499 | INIT_LIST_HEAD(&err_data->err_node_list); | |
3500 | ||
3501 | return 0; | |
3502 | } | |
3503 | ||
3504 | static void amdgpu_ras_error_node_release(struct ras_err_node *err_node) | |
3505 | { | |
3506 | if (!err_node) | |
3507 | return; | |
3508 | ||
3509 | list_del(&err_node->node); | |
3510 | kvfree(err_node); | |
3511 | } | |
3512 | ||
3513 | void amdgpu_ras_error_data_fini(struct ras_err_data *err_data) | |
3514 | { | |
3515 | struct ras_err_node *err_node, *tmp; | |
3516 | ||
8a656611 | 3517 | list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node) |
5b1270be | 3518 | amdgpu_ras_error_node_release(err_node); |
5b1270be YW |
3519 | } |
3520 | ||
3521 | static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data, | |
3522 | struct amdgpu_smuio_mcm_config_info *mcm_info) | |
3523 | { | |
3524 | struct ras_err_node *err_node; | |
3525 | struct amdgpu_smuio_mcm_config_info *ref_id; | |
3526 | ||
3527 | if (!err_data || !mcm_info) | |
3528 | return NULL; | |
3529 | ||
3530 | for_each_ras_error(err_node, err_data) { | |
3531 | ref_id = &err_node->err_info.mcm_info; | |
3532 | if ((mcm_info->socket_id >= 0 && mcm_info->socket_id != ref_id->socket_id) || | |
3533 | (mcm_info->die_id >= 0 && mcm_info->die_id != ref_id->die_id)) | |
3534 | continue; | |
3535 | ||
3536 | return err_node; | |
3537 | } | |
3538 | ||
3539 | return NULL; | |
3540 | } | |
3541 | ||
3542 | static struct ras_err_node *amdgpu_ras_error_node_new(void) | |
3543 | { | |
3544 | struct ras_err_node *err_node; | |
3545 | ||
3546 | err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL); | |
3547 | if (!err_node) | |
3548 | return NULL; | |
3549 | ||
3550 | INIT_LIST_HEAD(&err_node->node); | |
3551 | ||
3552 | return err_node; | |
3553 | } | |
3554 | ||
3555 | static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data, | |
3556 | struct amdgpu_smuio_mcm_config_info *mcm_info) | |
3557 | { | |
3558 | struct ras_err_node *err_node; | |
3559 | ||
3560 | err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info); | |
3561 | if (err_node) | |
3562 | return &err_node->err_info; | |
3563 | ||
3564 | err_node = amdgpu_ras_error_node_new(); | |
3565 | if (!err_node) | |
3566 | return NULL; | |
3567 | ||
3568 | memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info)); | |
3569 | ||
3570 | err_data->err_list_count++; | |
3571 | list_add_tail(&err_node->node, &err_data->err_node_list); | |
3572 | ||
3573 | return &err_node->err_info; | |
3574 | } | |
3575 | ||
3576 | int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, | |
3577 | struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count) | |
3578 | { | |
3579 | struct ras_err_info *err_info; | |
3580 | ||
3581 | if (!err_data || !mcm_info) | |
3582 | return -EINVAL; | |
3583 | ||
3584 | if (!count) | |
3585 | return 0; | |
3586 | ||
3587 | err_info = amdgpu_ras_error_get_info(err_data, mcm_info); | |
3588 | if (!err_info) | |
3589 | return -EINVAL; | |
3590 | ||
3591 | err_info->ue_count += count; | |
3592 | err_data->ue_count += count; | |
3593 | ||
3594 | return 0; | |
3595 | } | |
3596 | ||
3597 | int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, | |
3598 | struct amdgpu_smuio_mcm_config_info *mcm_info, u64 count) | |
3599 | { | |
3600 | struct ras_err_info *err_info; | |
3601 | ||
3602 | if (!err_data || !mcm_info) | |
3603 | return -EINVAL; | |
3604 | ||
3605 | if (!count) | |
3606 | return 0; | |
3607 | ||
3608 | err_info = amdgpu_ras_error_get_info(err_data, mcm_info); | |
3609 | if (!err_info) | |
3610 | return -EINVAL; | |
3611 | ||
3612 | err_info->ce_count += count; | |
3613 | err_data->ce_count += count; | |
3614 | ||
3615 | return 0; | |
3616 | } |