Commit | Line | Data |
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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
f50160cf | 37 | #include "atom.h" |
12b2cab7 MJ |
38 | #ifdef CONFIG_X86_MCE_AMD |
39 | #include <asm/mce.h> | |
c030f2e4 | 40 | |
12b2cab7 MJ |
41 | static bool notifier_registered; |
42 | #endif | |
eb0c3cd4 GC |
43 | static const char *RAS_FS_NAME = "ras"; |
44 | ||
c030f2e4 | 45 | const char *ras_error_string[] = { |
46 | "none", | |
47 | "parity", | |
48 | "single_correctable", | |
49 | "multi_uncorrectable", | |
50 | "poison", | |
51 | }; | |
52 | ||
53 | const char *ras_block_string[] = { | |
54 | "umc", | |
55 | "sdma", | |
56 | "gfx", | |
57 | "mmhub", | |
58 | "athub", | |
59 | "pcie_bif", | |
60 | "hdp", | |
61 | "xgmi_wafl", | |
62 | "df", | |
63 | "smn", | |
64 | "sem", | |
65 | "mp0", | |
66 | "mp1", | |
67 | "fuse", | |
640ae42e | 68 | "mca", |
c030f2e4 | 69 | }; |
70 | ||
640ae42e JC |
71 | const char *ras_mca_block_string[] = { |
72 | "mca_mp0", | |
73 | "mca_mp1", | |
74 | "mca_mpio", | |
75 | "mca_iohc", | |
76 | }; | |
77 | ||
d5e8ff5f | 78 | struct amdgpu_ras_block_list { |
79 | /* ras block link */ | |
80 | struct list_head node; | |
81 | ||
82 | struct amdgpu_ras_block_object *ras_obj; | |
83 | }; | |
84 | ||
640ae42e JC |
85 | const char *get_ras_block_str(struct ras_common_if *ras_block) |
86 | { | |
87 | if (!ras_block) | |
88 | return "NULL"; | |
89 | ||
90 | if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) | |
91 | return "OUT OF RANGE"; | |
92 | ||
93 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) | |
94 | return ras_mca_block_string[ras_block->sub_block_index]; | |
95 | ||
96 | return ras_block_string[ras_block->block]; | |
97 | } | |
98 | ||
954ea6aa | 99 | #define ras_block_str(_BLOCK_) \ |
100 | (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") | |
8b0fb0e9 | 101 | |
c030f2e4 | 102 | #define ras_err_str(i) (ras_error_string[ffs(i)]) |
c030f2e4 | 103 | |
108c6a63 | 104 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
105 | ||
7cdc2ee3 TZ |
106 | /* inject address is 52 bits */ |
107 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
108 | ||
e4e6a589 LT |
109 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
110 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) | |
c84d4670 | 111 | |
52dd95f2 GC |
112 | enum amdgpu_ras_retire_page_reservation { |
113 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
114 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
115 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
116 | }; | |
7c6e68c7 AG |
117 | |
118 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
119 | ||
676deb38 DL |
120 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
121 | uint64_t addr); | |
6e4be987 TZ |
122 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
123 | uint64_t addr); | |
12b2cab7 | 124 | #ifdef CONFIG_X86_MCE_AMD |
91a1a52d MJ |
125 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); |
126 | struct mce_notifier_adev_list { | |
127 | struct amdgpu_device *devs[MAX_GPU_INSTANCE]; | |
128 | int num_gpu; | |
129 | }; | |
130 | static struct mce_notifier_adev_list mce_adev_list; | |
12b2cab7 | 131 | #endif |
6e4be987 | 132 | |
61380faa JC |
133 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
134 | { | |
a9d82d2f | 135 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
136 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
137 | } | |
138 | ||
f3167919 | 139 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 140 | { |
a9d82d2f | 141 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
142 | return amdgpu_ras_get_context(adev)->error_query_ready; |
143 | ||
144 | return false; | |
145 | } | |
146 | ||
cbb8f989 JC |
147 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
148 | { | |
149 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
150 | struct eeprom_table_record err_rec; | |
151 | ||
152 | if ((address >= adev->gmc.mc_vram_size) || | |
153 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
154 | dev_warn(adev->dev, | |
155 | "RAS WARN: input address 0x%llx is invalid.\n", | |
156 | address); | |
157 | return -EINVAL; | |
158 | } | |
159 | ||
160 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
161 | dev_warn(adev->dev, | |
80b0cd0f | 162 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
163 | address); |
164 | return 0; | |
165 | } | |
166 | ||
167 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
cbb8f989 | 168 | err_data.err_addr = &err_rec; |
400013b2 TZ |
169 | amdgpu_umc_fill_error_record(&err_data, address, |
170 | (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0); | |
cbb8f989 JC |
171 | |
172 | if (amdgpu_bad_page_threshold != 0) { | |
173 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
174 | err_data.err_addr_cnt); | |
175 | amdgpu_ras_save_bad_pages(adev); | |
176 | } | |
177 | ||
178 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
179 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
180 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
c030f2e4 | 185 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
186 | size_t size, loff_t *pos) | |
187 | { | |
188 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
189 | struct ras_query_if info = { | |
190 | .head = obj->head, | |
191 | }; | |
192 | ssize_t s; | |
193 | char val[128]; | |
194 | ||
761d86d3 | 195 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 196 | return -EINVAL; |
197 | ||
198 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
199 | "ue", info.ue_count, | |
200 | "ce", info.ce_count); | |
201 | if (*pos >= s) | |
202 | return 0; | |
203 | ||
204 | s -= *pos; | |
205 | s = min_t(u64, s, size); | |
206 | ||
207 | ||
208 | if (copy_to_user(buf, &val[*pos], s)) | |
209 | return -EINVAL; | |
210 | ||
211 | *pos += s; | |
212 | ||
213 | return s; | |
214 | } | |
215 | ||
c030f2e4 | 216 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
217 | .owner = THIS_MODULE, | |
218 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 219 | .write = NULL, |
c030f2e4 | 220 | .llseek = default_llseek |
221 | }; | |
222 | ||
96ebb307 | 223 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
224 | { | |
225 | int i; | |
226 | ||
227 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
228 | *block_id = i; | |
640ae42e | 229 | if (strcmp(name, ras_block_string[i]) == 0) |
96ebb307 | 230 | return 0; |
231 | } | |
232 | return -EINVAL; | |
233 | } | |
234 | ||
235 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
236 | const char __user *buf, size_t size, | |
237 | loff_t *pos, struct ras_debug_if *data) | |
238 | { | |
239 | ssize_t s = min_t(u64, 64, size); | |
240 | char str[65]; | |
241 | char block_name[33]; | |
242 | char err[9] = "ue"; | |
243 | int op = -1; | |
244 | int block_id; | |
44494f96 | 245 | uint32_t sub_block; |
96ebb307 | 246 | u64 address, value; |
247 | ||
248 | if (*pos) | |
249 | return -EINVAL; | |
250 | *pos = size; | |
251 | ||
252 | memset(str, 0, sizeof(str)); | |
253 | memset(data, 0, sizeof(*data)); | |
254 | ||
255 | if (copy_from_user(str, buf, s)) | |
256 | return -EINVAL; | |
257 | ||
258 | if (sscanf(str, "disable %32s", block_name) == 1) | |
259 | op = 0; | |
260 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
261 | op = 1; | |
262 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
263 | op = 2; | |
6df23f4c | 264 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 265 | op = 3; |
b076296b | 266 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 267 | /* ascii string, but commands are not matched. */ |
268 | return -EINVAL; | |
269 | ||
270 | if (op != -1) { | |
cbb8f989 | 271 | if (op == 3) { |
546aa546 LT |
272 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
273 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 274 | return -EINVAL; |
cbb8f989 JC |
275 | |
276 | data->op = op; | |
277 | data->inject.address = address; | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
96ebb307 | 282 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
283 | return -EINVAL; | |
284 | ||
285 | data->head.block = block_id; | |
e1063493 TZ |
286 | /* only ue and ce errors are supported */ |
287 | if (!memcmp("ue", err, 2)) | |
288 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
289 | else if (!memcmp("ce", err, 2)) | |
290 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
291 | else | |
292 | return -EINVAL; | |
293 | ||
96ebb307 | 294 | data->op = op; |
295 | ||
296 | if (op == 2) { | |
546aa546 LT |
297 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", |
298 | &sub_block, &address, &value) != 3 && | |
299 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
300 | &sub_block, &address, &value) != 3) |
301 | return -EINVAL; | |
44494f96 | 302 | data->head.sub_block_index = sub_block; |
96ebb307 | 303 | data->inject.address = address; |
304 | data->inject.value = value; | |
305 | } | |
306 | } else { | |
73aa8e1a | 307 | if (size < sizeof(*data)) |
96ebb307 | 308 | return -EINVAL; |
309 | ||
310 | if (copy_from_user(data, buf, sizeof(*data))) | |
311 | return -EINVAL; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
7c6e68c7 | 316 | |
74abc221 TSD |
317 | /** |
318 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 319 | * |
737c375b | 320 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 321 | * |
322 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 323 | * |
324 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 325 | * |
326 | * head has four members, they are block, type, sub_block_index, name. | |
327 | * block: which IP will be under control. | |
328 | * type: what kind of error will be enabled/disabled/injected. | |
329 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
330 | * name: the name of IP. | |
331 | * | |
332 | * inject has two more members than head, they are address, value. | |
333 | * As their names indicate, inject operation will write the | |
334 | * value to the address. | |
335 | * | |
ef177d11 | 336 | * The second member: struct ras_debug_if::op. |
c688a06b | 337 | * It has three kinds of operations. |
879e723d AZ |
338 | * |
339 | * - 0: disable RAS on the block. Take ::head as its data. | |
340 | * - 1: enable RAS on the block. Take ::head as its data. | |
341 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 342 | * |
96ebb307 | 343 | * How to use the interface? |
ef177d11 | 344 | * |
737c375b | 345 | * In a program |
ef177d11 | 346 | * |
737c375b LT |
347 | * Copy the struct ras_debug_if in your code and initialize it. |
348 | * Write the struct to the control interface. | |
ef177d11 | 349 | * |
737c375b | 350 | * From shell |
96ebb307 | 351 | * |
879e723d AZ |
352 | * .. code-block:: bash |
353 | * | |
737c375b LT |
354 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
355 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
356 | * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
879e723d | 357 | * |
737c375b | 358 | * Where N, is the card which you want to affect. |
ef177d11 | 359 | * |
737c375b LT |
360 | * "disable" requires only the block. |
361 | * "enable" requires the block and error type. | |
362 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 363 | * |
737c375b | 364 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 365 | * see ras_block_string[] for details |
c666bbf0 | 366 | * |
737c375b LT |
367 | * The error type is one of: ue, ce, where, |
368 | * ue is multi-uncorrectable | |
369 | * ce is single-correctable | |
c666bbf0 | 370 | * |
737c375b LT |
371 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
372 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
879e723d | 373 | * |
737c375b | 374 | * For instance, |
879e723d AZ |
375 | * |
376 | * .. code-block:: bash | |
96ebb307 | 377 | * |
44494f96 TZ |
378 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
379 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 380 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
381 | * | |
737c375b | 382 | * How to check the result of the operation? |
36ea1bd2 | 383 | * |
737c375b | 384 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 385 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
386 | * | |
737c375b LT |
387 | * To check inject, see the corresponding error count at, |
388 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 389 | * |
879e723d | 390 | * .. note:: |
ef177d11 | 391 | * Operations are only allowed on blocks which are supported. |
737c375b | 392 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
393 | * to see which blocks support RAS on a particular asic. |
394 | * | |
36ea1bd2 | 395 | */ |
cf696091 LT |
396 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
397 | const char __user *buf, | |
398 | size_t size, loff_t *pos) | |
36ea1bd2 | 399 | { |
400 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
401 | struct ras_debug_if data; | |
402 | int ret = 0; | |
403 | ||
61380faa | 404 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
405 | dev_warn(adev->dev, "RAS WARN: error injection " |
406 | "currently inaccessible\n"); | |
43c4d576 JC |
407 | return size; |
408 | } | |
409 | ||
96ebb307 | 410 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
411 | if (ret) | |
cf696091 | 412 | return ret; |
36ea1bd2 | 413 | |
80b0cd0f | 414 | if (data.op == 3) { |
cbb8f989 | 415 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 416 | if (!ret) |
cbb8f989 JC |
417 | return size; |
418 | else | |
419 | return ret; | |
420 | } | |
421 | ||
36ea1bd2 | 422 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
423 | return -EINVAL; | |
424 | ||
425 | switch (data.op) { | |
426 | case 0: | |
427 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
428 | break; | |
429 | case 1: | |
430 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
431 | break; | |
432 | case 2: | |
7cdc2ee3 TZ |
433 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
434 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
435 | dev_warn(adev->dev, "RAS WARN: input address " |
436 | "0x%llx is invalid.", | |
437 | data.inject.address); | |
7cdc2ee3 TZ |
438 | ret = -EINVAL; |
439 | break; | |
440 | } | |
441 | ||
6e4be987 TZ |
442 | /* umc ce/ue error injection for a bad page is not allowed */ |
443 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
444 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
c65b0805 LT |
445 | dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " |
446 | "already been marked as bad!\n", | |
447 | data.inject.address); | |
6e4be987 TZ |
448 | break; |
449 | } | |
450 | ||
7cdc2ee3 | 451 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 452 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
453 | break; | |
96ebb307 | 454 | default: |
455 | ret = -EINVAL; | |
456 | break; | |
374bf7bd | 457 | } |
36ea1bd2 | 458 | |
459 | if (ret) | |
79c04621 | 460 | return ret; |
36ea1bd2 | 461 | |
462 | return size; | |
463 | } | |
464 | ||
084fe13b AG |
465 | /** |
466 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
467 | * | |
f77c7109 | 468 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 469 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
470 | * a way to reset the EEPROM, e.g., after testing error injection. |
471 | * | |
472 | * Usage: | |
473 | * | |
474 | * .. code-block:: bash | |
475 | * | |
476 | * echo 1 > ../ras/ras_eeprom_reset | |
477 | * | |
478 | * will reset EEPROM table to 0 entries. | |
479 | * | |
084fe13b | 480 | */ |
cf696091 LT |
481 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
482 | const char __user *buf, | |
483 | size_t size, loff_t *pos) | |
084fe13b | 484 | { |
bf0b91b7 GC |
485 | struct amdgpu_device *adev = |
486 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
487 | int ret; |
488 | ||
bf0b91b7 | 489 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 490 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 491 | |
63d4c081 | 492 | if (!ret) { |
cf696091 LT |
493 | /* Something was written to EEPROM. |
494 | */ | |
bf0b91b7 GC |
495 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
496 | return size; | |
497 | } else { | |
cf696091 | 498 | return ret; |
bf0b91b7 | 499 | } |
084fe13b AG |
500 | } |
501 | ||
36ea1bd2 | 502 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
503 | .owner = THIS_MODULE, | |
504 | .read = NULL, | |
505 | .write = amdgpu_ras_debugfs_ctrl_write, | |
506 | .llseek = default_llseek | |
507 | }; | |
508 | ||
084fe13b AG |
509 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
510 | .owner = THIS_MODULE, | |
511 | .read = NULL, | |
512 | .write = amdgpu_ras_debugfs_eeprom_write, | |
513 | .llseek = default_llseek | |
514 | }; | |
515 | ||
f77c7109 AD |
516 | /** |
517 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
518 | * | |
ef177d11 | 519 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
520 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
521 | * | |
522 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
523 | * (ce) error counts. | |
524 | * | |
525 | * The format of one line is below, | |
526 | * | |
527 | * [ce|ue]: count | |
528 | * | |
529 | * Example: | |
530 | * | |
531 | * .. code-block:: bash | |
532 | * | |
533 | * ue: 0 | |
534 | * ce: 1 | |
535 | * | |
536 | */ | |
c030f2e4 | 537 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
538 | struct device_attribute *attr, char *buf) | |
539 | { | |
540 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
541 | struct ras_query_if info = { | |
542 | .head = obj->head, | |
543 | }; | |
544 | ||
61380faa | 545 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 546 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 547 | |
761d86d3 | 548 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 549 | return -EINVAL; |
550 | ||
1f0d8e37 MJ |
551 | if (obj->adev->asic_type == CHIP_ALDEBARAN) { |
552 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) | |
553 | DRM_WARN("Failed to reset error counter and error status"); | |
554 | } | |
555 | ||
36000c7a TT |
556 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
557 | "ce", info.ce_count); | |
c030f2e4 | 558 | } |
559 | ||
560 | /* obj begin */ | |
561 | ||
562 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
563 | #define alive_obj(obj) ((obj)->use) | |
564 | ||
565 | static inline void put_obj(struct ras_manager *obj) | |
566 | { | |
f0872686 | 567 | if (obj && (--obj->use == 0)) |
c030f2e4 | 568 | list_del(&obj->node); |
f0872686 | 569 | if (obj && (obj->use < 0)) |
640ae42e | 570 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); |
c030f2e4 | 571 | } |
572 | ||
573 | /* make one obj and return it. */ | |
574 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
575 | struct ras_common_if *head) | |
576 | { | |
577 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
578 | struct ras_manager *obj; | |
579 | ||
8ab0d6f0 | 580 | if (!adev->ras_enabled || !con) |
c030f2e4 | 581 | return NULL; |
582 | ||
583 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
584 | return NULL; | |
585 | ||
640ae42e JC |
586 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
587 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
588 | return NULL; | |
589 | ||
590 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
591 | } else | |
592 | obj = &con->objs[head->block]; | |
593 | ||
c030f2e4 | 594 | /* already exist. return obj? */ |
595 | if (alive_obj(obj)) | |
596 | return NULL; | |
597 | ||
598 | obj->head = *head; | |
599 | obj->adev = adev; | |
600 | list_add(&obj->node, &con->head); | |
601 | get_obj(obj); | |
602 | ||
603 | return obj; | |
604 | } | |
605 | ||
606 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 607 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 608 | struct ras_common_if *head) |
609 | { | |
610 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
611 | struct ras_manager *obj; | |
612 | int i; | |
613 | ||
8ab0d6f0 | 614 | if (!adev->ras_enabled || !con) |
c030f2e4 | 615 | return NULL; |
616 | ||
617 | if (head) { | |
618 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
619 | return NULL; | |
620 | ||
640ae42e JC |
621 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
622 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
623 | return NULL; | |
624 | ||
625 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
626 | } else | |
627 | obj = &con->objs[head->block]; | |
c030f2e4 | 628 | |
640ae42e | 629 | if (alive_obj(obj)) |
c030f2e4 | 630 | return obj; |
c030f2e4 | 631 | } else { |
640ae42e | 632 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { |
c030f2e4 | 633 | obj = &con->objs[i]; |
640ae42e | 634 | if (alive_obj(obj)) |
c030f2e4 | 635 | return obj; |
c030f2e4 | 636 | } |
637 | } | |
638 | ||
639 | return NULL; | |
640 | } | |
641 | /* obj end */ | |
642 | ||
643 | /* feature ctl begin */ | |
644 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 645 | struct ras_common_if *head) |
c030f2e4 | 646 | { |
8ab0d6f0 | 647 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 648 | } |
649 | ||
650 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
651 | struct ras_common_if *head) | |
652 | { | |
653 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
654 | ||
655 | return con->features & BIT(head->block); | |
656 | } | |
657 | ||
658 | /* | |
659 | * if obj is not created, then create one. | |
660 | * set feature enable flag. | |
661 | */ | |
662 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
663 | struct ras_common_if *head, int enable) | |
664 | { | |
665 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
666 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
667 | ||
5caf466a | 668 | /* If hardware does not support ras, then do not create obj. |
669 | * But if hardware support ras, we can create the obj. | |
670 | * Ras framework checks con->hw_supported to see if it need do | |
671 | * corresponding initialization. | |
672 | * IP checks con->support to see if it need disable ras. | |
673 | */ | |
c030f2e4 | 674 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
675 | return 0; | |
c030f2e4 | 676 | |
677 | if (enable) { | |
678 | if (!obj) { | |
679 | obj = amdgpu_ras_create_obj(adev, head); | |
680 | if (!obj) | |
681 | return -EINVAL; | |
682 | } else { | |
683 | /* In case we create obj somewhere else */ | |
684 | get_obj(obj); | |
685 | } | |
686 | con->features |= BIT(head->block); | |
687 | } else { | |
688 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 689 | con->features &= ~BIT(head->block); |
c030f2e4 | 690 | put_obj(obj); |
691 | } | |
692 | } | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | /* wrapper of psp_ras_enable_features */ | |
698 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
699 | struct ras_common_if *head, bool enable) | |
700 | { | |
701 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 702 | union ta_ras_cmd_input *info; |
c030f2e4 | 703 | int ret; |
704 | ||
705 | if (!con) | |
706 | return -EINVAL; | |
707 | ||
f3729f7b | 708 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
709 | if (!info) |
710 | return -ENOMEM; | |
711 | ||
c030f2e4 | 712 | if (!enable) { |
7fcffecf | 713 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 714 | .block_id = amdgpu_ras_block_to_ta(head->block), |
715 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 716 | }; |
717 | } else { | |
7fcffecf | 718 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 719 | .block_id = amdgpu_ras_block_to_ta(head->block), |
720 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 721 | }; |
722 | } | |
723 | ||
724 | /* Do not enable if it is not allowed. */ | |
725 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
c030f2e4 | 726 | |
bff77e86 | 727 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 728 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 729 | if (ret) { |
e4348849 | 730 | dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", |
011907fd | 731 | enable ? "enable":"disable", |
640ae42e | 732 | get_ras_block_str(head), |
e4348849 | 733 | amdgpu_ras_is_poison_mode_supported(adev), ret); |
7fcffecf | 734 | goto out; |
bff77e86 | 735 | } |
c030f2e4 | 736 | } |
737 | ||
738 | /* setup the obj */ | |
739 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
740 | ret = 0; |
741 | out: | |
742 | kfree(info); | |
743 | return ret; | |
c030f2e4 | 744 | } |
745 | ||
77de502b | 746 | /* Only used in device probe stage and called only once. */ |
747 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
748 | struct ras_common_if *head, bool enable) | |
749 | { | |
750 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
751 | int ret; | |
752 | ||
753 | if (!con) | |
754 | return -EINVAL; | |
755 | ||
756 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 757 | if (enable) { |
758 | /* There is no harm to issue a ras TA cmd regardless of | |
759 | * the currecnt ras state. | |
760 | * If current state == target state, it will do nothing | |
761 | * But sometimes it requests driver to reset and repost | |
762 | * with error code -EAGAIN. | |
763 | */ | |
764 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
765 | /* With old ras TA, we might fail to enable ras. | |
766 | * Log it and just setup the object. | |
767 | * TODO need remove this WA in the future. | |
768 | */ | |
769 | if (ret == -EINVAL) { | |
770 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
771 | if (!ret) | |
6952e99c GC |
772 | dev_info(adev->dev, |
773 | "RAS INFO: %s setup object\n", | |
640ae42e | 774 | get_ras_block_str(head)); |
7af23ebe | 775 | } |
776 | } else { | |
777 | /* setup the object then issue a ras TA disable cmd.*/ | |
778 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
779 | if (ret) | |
780 | return ret; | |
77de502b | 781 | |
970fd197 SY |
782 | /* gfx block ras dsiable cmd must send to ras-ta */ |
783 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
784 | con->features |= BIT(head->block); | |
785 | ||
77de502b | 786 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
787 | |
788 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 789 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 790 | con->features &= ~BIT(head->block); |
7af23ebe | 791 | } |
77de502b | 792 | } else |
793 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
794 | ||
795 | return ret; | |
796 | } | |
797 | ||
c030f2e4 | 798 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
799 | bool bypass) | |
800 | { | |
801 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
802 | struct ras_manager *obj, *tmp; | |
803 | ||
804 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
805 | /* bypass psp. | |
806 | * aka just release the obj and corresponding flags | |
807 | */ | |
808 | if (bypass) { | |
809 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
810 | break; | |
811 | } else { | |
812 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
813 | break; | |
814 | } | |
289d513b | 815 | } |
c030f2e4 | 816 | |
817 | return con->features; | |
818 | } | |
819 | ||
820 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
821 | bool bypass) | |
822 | { | |
823 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 824 | int i; |
640ae42e | 825 | const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; |
c030f2e4 | 826 | |
640ae42e | 827 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { |
c030f2e4 | 828 | struct ras_common_if head = { |
829 | .block = i, | |
191051a1 | 830 | .type = default_ras_type, |
c030f2e4 | 831 | .sub_block_index = 0, |
832 | }; | |
640ae42e JC |
833 | |
834 | if (i == AMDGPU_RAS_BLOCK__MCA) | |
835 | continue; | |
836 | ||
837 | if (bypass) { | |
838 | /* | |
839 | * bypass psp. vbios enable ras for us. | |
840 | * so just create the obj | |
841 | */ | |
842 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
843 | break; | |
844 | } else { | |
845 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
846 | break; | |
847 | } | |
848 | } | |
849 | ||
850 | for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { | |
851 | struct ras_common_if head = { | |
852 | .block = AMDGPU_RAS_BLOCK__MCA, | |
853 | .type = default_ras_type, | |
854 | .sub_block_index = i, | |
855 | }; | |
856 | ||
c030f2e4 | 857 | if (bypass) { |
858 | /* | |
859 | * bypass psp. vbios enable ras for us. | |
860 | * so just create the obj | |
861 | */ | |
862 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
863 | break; | |
864 | } else { | |
865 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
866 | break; | |
867 | } | |
289d513b | 868 | } |
c030f2e4 | 869 | |
870 | return con->features; | |
871 | } | |
872 | /* feature ctl end */ | |
873 | ||
e3d833f4 | 874 | static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, |
875 | enum amdgpu_ras_block block) | |
6492e1b0 | 876 | { |
b6efdb02 | 877 | if (!block_obj) |
6492e1b0 | 878 | return -EINVAL; |
879 | ||
bdb3489c | 880 | if (block_obj->ras_comm.block == block) |
6492e1b0 | 881 | return 0; |
640ae42e | 882 | |
6492e1b0 | 883 | return -EINVAL; |
884 | } | |
885 | ||
b6efdb02 | 886 | static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, |
6492e1b0 | 887 | enum amdgpu_ras_block block, uint32_t sub_block_index) |
640ae42e | 888 | { |
d5e8ff5f | 889 | struct amdgpu_ras_block_list *node, *tmp; |
890 | struct amdgpu_ras_block_object *obj; | |
6492e1b0 | 891 | |
892 | if (block >= AMDGPU_RAS_BLOCK__LAST) | |
893 | return NULL; | |
894 | ||
895 | if (!amdgpu_ras_is_supported(adev, block)) | |
896 | return NULL; | |
897 | ||
d5e8ff5f | 898 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
899 | if (!node->ras_obj) { | |
900 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
901 | continue; | |
902 | } | |
903 | ||
904 | obj = node->ras_obj; | |
6492e1b0 | 905 | if (obj->ras_block_match) { |
906 | if (obj->ras_block_match(obj, block, sub_block_index) == 0) | |
907 | return obj; | |
908 | } else { | |
909 | if (amdgpu_ras_block_match_default(obj, block) == 0) | |
910 | return obj; | |
911 | } | |
640ae42e | 912 | } |
6492e1b0 | 913 | |
914 | return NULL; | |
640ae42e JC |
915 | } |
916 | ||
fdcb279d SY |
917 | static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) |
918 | { | |
919 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
920 | int ret = 0; | |
921 | ||
922 | /* | |
923 | * choosing right query method according to | |
924 | * whether smu support query error information | |
925 | */ | |
bc143d8b | 926 | ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); |
fdcb279d | 927 | if (ret == -EOPNOTSUPP) { |
efe17d5a | 928 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
929 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count) | |
930 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); | |
fdcb279d SY |
931 | |
932 | /* umc query_ras_error_address is also responsible for clearing | |
933 | * error status | |
934 | */ | |
efe17d5a | 935 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
936 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address) | |
937 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); | |
fdcb279d | 938 | } else if (!ret) { |
efe17d5a | 939 | if (adev->umc.ras && |
940 | adev->umc.ras->ecc_info_query_ras_error_count) | |
941 | adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); | |
fdcb279d | 942 | |
efe17d5a | 943 | if (adev->umc.ras && |
944 | adev->umc.ras->ecc_info_query_ras_error_address) | |
945 | adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); | |
fdcb279d SY |
946 | } |
947 | } | |
948 | ||
c030f2e4 | 949 | /* query/inject/cure begin */ |
761d86d3 | 950 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
4d9f771e | 951 | struct ras_query_if *info) |
c030f2e4 | 952 | { |
b6efdb02 | 953 | struct amdgpu_ras_block_object *block_obj = NULL; |
c030f2e4 | 954 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); |
6f102dba | 955 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 956 | |
957 | if (!obj) | |
958 | return -EINVAL; | |
c030f2e4 | 959 | |
7389a5b8 | 960 | if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { |
fdcb279d | 961 | amdgpu_ras_get_ecc_info(adev, &err_data); |
7389a5b8 | 962 | } else { |
963 | block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); | |
8b0fb0e9 | 964 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
965 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
966 | get_ras_block_str(&info->head)); | |
8b0fb0e9 | 967 | return -EINVAL; |
3e81ee9a | 968 | } |
761d86d3 | 969 | |
6c245386 | 970 | if (block_obj->hw_ops->query_ras_error_count) |
971 | block_obj->hw_ops->query_ras_error_count(adev, &err_data); | |
7389a5b8 | 972 | |
973 | if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || | |
974 | (info->head.block == AMDGPU_RAS_BLOCK__GFX) || | |
975 | (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
976 | if (block_obj->hw_ops->query_ras_error_status) | |
977 | block_obj->hw_ops->query_ras_error_status(adev); | |
978 | } | |
939e2258 | 979 | } |
05a58345 TZ |
980 | |
981 | obj->err_data.ue_count += err_data.ue_count; | |
982 | obj->err_data.ce_count += err_data.ce_count; | |
983 | ||
c030f2e4 | 984 | info->ue_count = obj->err_data.ue_count; |
985 | info->ce_count = obj->err_data.ce_count; | |
986 | ||
7c6e68c7 | 987 | if (err_data.ce_count) { |
a30f1286 HZ |
988 | if (adev->smuio.funcs && |
989 | adev->smuio.funcs->get_socket_id && | |
990 | adev->smuio.funcs->get_die_id) { | |
991 | dev_info(adev->dev, "socket: %d, die: %d " | |
992 | "%ld correctable hardware errors " | |
6952e99c GC |
993 | "detected in %s block, no user " |
994 | "action is needed.\n", | |
a30f1286 HZ |
995 | adev->smuio.funcs->get_socket_id(adev), |
996 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 997 | obj->err_data.ce_count, |
640ae42e | 998 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
999 | } else { |
1000 | dev_info(adev->dev, "%ld correctable hardware errors " | |
6952e99c GC |
1001 | "detected in %s block, no user " |
1002 | "action is needed.\n", | |
1003 | obj->err_data.ce_count, | |
640ae42e | 1004 | get_ras_block_str(&info->head)); |
a30f1286 | 1005 | } |
7c6e68c7 AG |
1006 | } |
1007 | if (err_data.ue_count) { | |
a30f1286 HZ |
1008 | if (adev->smuio.funcs && |
1009 | adev->smuio.funcs->get_socket_id && | |
1010 | adev->smuio.funcs->get_die_id) { | |
1011 | dev_info(adev->dev, "socket: %d, die: %d " | |
1012 | "%ld uncorrectable hardware errors " | |
6952e99c | 1013 | "detected in %s block\n", |
a30f1286 HZ |
1014 | adev->smuio.funcs->get_socket_id(adev), |
1015 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 1016 | obj->err_data.ue_count, |
640ae42e | 1017 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
1018 | } else { |
1019 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
6952e99c GC |
1020 | "detected in %s block\n", |
1021 | obj->err_data.ue_count, | |
640ae42e | 1022 | get_ras_block_str(&info->head)); |
a30f1286 | 1023 | } |
7c6e68c7 | 1024 | } |
05a58345 | 1025 | |
eb601e61 JC |
1026 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) |
1027 | amdgpu_ras_reset_error_status(adev, info->head.block); | |
1028 | ||
c030f2e4 | 1029 | return 0; |
1030 | } | |
1031 | ||
761d86d3 DL |
1032 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
1033 | enum amdgpu_ras_block block) | |
1034 | { | |
b6efdb02 | 1035 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); |
8b0fb0e9 | 1036 | |
761d86d3 DL |
1037 | if (!amdgpu_ras_is_supported(adev, block)) |
1038 | return -EINVAL; | |
1039 | ||
7389a5b8 | 1040 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1041 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1042 | ras_block_str(block)); | |
7389a5b8 | 1043 | return -EINVAL; |
761d86d3 DL |
1044 | } |
1045 | ||
7389a5b8 | 1046 | if (block_obj->hw_ops->reset_ras_error_count) |
1047 | block_obj->hw_ops->reset_ras_error_count(adev); | |
5c23e9e0 | 1048 | |
7389a5b8 | 1049 | if ((block == AMDGPU_RAS_BLOCK__GFX) || |
1050 | (block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
8b0fb0e9 | 1051 | if (block_obj->hw_ops->reset_ras_error_status) |
1052 | block_obj->hw_ops->reset_ras_error_status(adev); | |
761d86d3 | 1053 | } |
5c23e9e0 | 1054 | |
761d86d3 | 1055 | return 0; |
5c23e9e0 JC |
1056 | } |
1057 | ||
c030f2e4 | 1058 | /* wrapper of psp_ras_trigger_error */ |
1059 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
1060 | struct ras_inject_if *info) | |
1061 | { | |
1062 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1063 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1064 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1065 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1066 | .sub_block_index = info->head.sub_block_index, |
1067 | .address = info->address, | |
1068 | .value = info->value, | |
1069 | }; | |
ab3b9de6 YL |
1070 | int ret = -EINVAL; |
1071 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, | |
1072 | info->head.block, | |
1073 | info->head.sub_block_index); | |
c030f2e4 | 1074 | |
1075 | if (!obj) | |
1076 | return -EINVAL; | |
1077 | ||
22d4ba53 | 1078 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1079 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1080 | get_ras_block_str(&info->head)); | |
22d4ba53 | 1081 | return -EINVAL; |
1082 | } | |
1083 | ||
a6c44d25 JC |
1084 | /* Calculate XGMI relative offset */ |
1085 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
1086 | block_info.address = |
1087 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1088 | block_info.address); | |
a6c44d25 JC |
1089 | } |
1090 | ||
22d4ba53 | 1091 | if (info->head.block == AMDGPU_RAS_BLOCK__GFX) { |
8b0fb0e9 | 1092 | if (block_obj->hw_ops->ras_error_inject) |
1093 | ret = block_obj->hw_ops->ras_error_inject(adev, info); | |
22d4ba53 | 1094 | } else { |
1095 | /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */ | |
1096 | if (block_obj->hw_ops->ras_error_inject) | |
1097 | ret = block_obj->hw_ops->ras_error_inject(adev, &block_info); | |
1098 | else /*If not defined .ras_error_inject, use default ras_error_inject*/ | |
1099 | ret = psp_ras_trigger_error(&adev->psp, &block_info); | |
a5dd40ca HZ |
1100 | } |
1101 | ||
011907fd DL |
1102 | if (ret) |
1103 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
640ae42e | 1104 | get_ras_block_str(&info->head), ret); |
c030f2e4 | 1105 | |
1106 | return ret; | |
1107 | } | |
1108 | ||
4d9f771e LT |
1109 | /** |
1110 | * amdgpu_ras_query_error_count -- Get error counts of all IPs | |
bbe04dec IB |
1111 | * @adev: pointer to AMD GPU device |
1112 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1113 | * @ue_count: pointer to an integer to be set to the count of uncorrectible | |
4d9f771e LT |
1114 | * errors. |
1115 | * | |
1116 | * If set, @ce_count or @ue_count, count and return the corresponding | |
1117 | * error counts in those integer pointers. Return 0 if the device | |
1118 | * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
1119 | */ | |
1120 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
1121 | unsigned long *ce_count, | |
1122 | unsigned long *ue_count) | |
c030f2e4 | 1123 | { |
1124 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1125 | struct ras_manager *obj; | |
a46751fb | 1126 | unsigned long ce, ue; |
c030f2e4 | 1127 | |
8ab0d6f0 | 1128 | if (!adev->ras_enabled || !con) |
4d9f771e LT |
1129 | return -EOPNOTSUPP; |
1130 | ||
1131 | /* Don't count since no reporting. | |
1132 | */ | |
1133 | if (!ce_count && !ue_count) | |
1134 | return 0; | |
c030f2e4 | 1135 | |
a46751fb LT |
1136 | ce = 0; |
1137 | ue = 0; | |
c030f2e4 | 1138 | list_for_each_entry(obj, &con->head, node) { |
1139 | struct ras_query_if info = { | |
1140 | .head = obj->head, | |
1141 | }; | |
4d9f771e | 1142 | int res; |
c030f2e4 | 1143 | |
4d9f771e LT |
1144 | res = amdgpu_ras_query_error_status(adev, &info); |
1145 | if (res) | |
1146 | return res; | |
c030f2e4 | 1147 | |
a46751fb LT |
1148 | ce += info.ce_count; |
1149 | ue += info.ue_count; | |
c030f2e4 | 1150 | } |
1151 | ||
a46751fb LT |
1152 | if (ce_count) |
1153 | *ce_count = ce; | |
1154 | ||
1155 | if (ue_count) | |
1156 | *ue_count = ue; | |
4d9f771e LT |
1157 | |
1158 | return 0; | |
c030f2e4 | 1159 | } |
1160 | /* query/inject/cure end */ | |
1161 | ||
1162 | ||
1163 | /* sysfs begin */ | |
1164 | ||
466b1793 | 1165 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1166 | struct ras_badpage **bps, unsigned int *count); | |
1167 | ||
1168 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1169 | { | |
1170 | switch (flags) { | |
52dd95f2 | 1171 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1172 | return "R"; |
52dd95f2 | 1173 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1174 | return "P"; |
52dd95f2 | 1175 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1176 | default: |
1177 | return "F"; | |
aec576f9 | 1178 | } |
466b1793 | 1179 | } |
1180 | ||
f77c7109 AD |
1181 | /** |
1182 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1183 | * |
1184 | * It allows user to read the bad pages of vram on the gpu through | |
1185 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1186 | * | |
1187 | * It outputs multiple lines, and each line stands for one gpu page. | |
1188 | * | |
1189 | * The format of one line is below, | |
1190 | * gpu pfn : gpu page size : flags | |
1191 | * | |
1192 | * gpu pfn and gpu page size are printed in hex format. | |
1193 | * flags can be one of below character, | |
f77c7109 | 1194 | * |
466b1793 | 1195 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1196 | * |
466b1793 | 1197 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1198 | * in next window of page_reserve. |
1199 | * | |
466b1793 | 1200 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1201 | * | |
f77c7109 AD |
1202 | * Examples: |
1203 | * | |
1204 | * .. code-block:: bash | |
1205 | * | |
1206 | * 0x00000001 : 0x00001000 : R | |
1207 | * 0x00000002 : 0x00001000 : P | |
1208 | * | |
466b1793 | 1209 | */ |
1210 | ||
1211 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1212 | struct kobject *kobj, struct bin_attribute *attr, | |
1213 | char *buf, loff_t ppos, size_t count) | |
1214 | { | |
1215 | struct amdgpu_ras *con = | |
1216 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1217 | struct amdgpu_device *adev = con->adev; | |
1218 | const unsigned int element_size = | |
1219 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1220 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1221 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1222 | ssize_t s = 0; |
1223 | struct ras_badpage *bps = NULL; | |
1224 | unsigned int bps_count = 0; | |
1225 | ||
1226 | memset(buf, 0, count); | |
1227 | ||
1228 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1229 | return 0; | |
1230 | ||
1231 | for (; start < end && start < bps_count; start++) | |
1232 | s += scnprintf(&buf[s], element_size + 1, | |
1233 | "0x%08x : 0x%08x : %1s\n", | |
1234 | bps[start].bp, | |
1235 | bps[start].size, | |
1236 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1237 | ||
1238 | kfree(bps); | |
1239 | ||
1240 | return s; | |
1241 | } | |
1242 | ||
c030f2e4 | 1243 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1244 | struct device_attribute *attr, char *buf) | |
1245 | { | |
1246 | struct amdgpu_ras *con = | |
1247 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1248 | |
5212a3bd | 1249 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1250 | } |
1251 | ||
f848159b GC |
1252 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1253 | { | |
1254 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1255 | ||
1256 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1257 | &con->badpages_attr.attr, | |
1258 | RAS_FS_NAME); | |
1259 | } | |
1260 | ||
c030f2e4 | 1261 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1262 | { | |
1263 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1264 | struct attribute *attrs[] = { | |
1265 | &con->features_attr.attr, | |
1266 | NULL | |
1267 | }; | |
1268 | struct attribute_group group = { | |
eb0c3cd4 | 1269 | .name = RAS_FS_NAME, |
c030f2e4 | 1270 | .attrs = attrs, |
1271 | }; | |
1272 | ||
1273 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1278 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
9252d33d | 1279 | struct ras_common_if *head) |
c030f2e4 | 1280 | { |
9252d33d | 1281 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1282 | |
1283 | if (!obj || obj->attr_inuse) | |
1284 | return -EINVAL; | |
1285 | ||
1286 | get_obj(obj); | |
1287 | ||
9252d33d | 1288 | snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), |
1289 | "%s_err_count", head->name); | |
c030f2e4 | 1290 | |
1291 | obj->sysfs_attr = (struct device_attribute){ | |
1292 | .attr = { | |
1293 | .name = obj->fs_data.sysfs_name, | |
1294 | .mode = S_IRUGO, | |
1295 | }, | |
1296 | .show = amdgpu_ras_sysfs_read, | |
1297 | }; | |
163def43 | 1298 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1299 | |
1300 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1301 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1302 | RAS_FS_NAME)) { |
c030f2e4 | 1303 | put_obj(obj); |
1304 | return -EINVAL; | |
1305 | } | |
1306 | ||
1307 | obj->attr_inuse = 1; | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1313 | struct ras_common_if *head) | |
1314 | { | |
1315 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1316 | ||
1317 | if (!obj || !obj->attr_inuse) | |
1318 | return -EINVAL; | |
1319 | ||
1320 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1321 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1322 | RAS_FS_NAME); |
c030f2e4 | 1323 | obj->attr_inuse = 0; |
1324 | put_obj(obj); | |
1325 | ||
1326 | return 0; | |
1327 | } | |
1328 | ||
1329 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1330 | { | |
1331 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1332 | struct ras_manager *obj, *tmp; | |
1333 | ||
1334 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1335 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1336 | } | |
1337 | ||
f848159b GC |
1338 | if (amdgpu_bad_page_threshold != 0) |
1339 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1340 | ||
c030f2e4 | 1341 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | /* sysfs end */ | |
1346 | ||
ef177d11 AD |
1347 | /** |
1348 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1349 | * | |
1350 | * Normally when there is an uncorrectable error, the driver will reset | |
1351 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1352 | * the driver provides an interface to reboot the system automatically | |
1353 | * in that event. | |
1354 | * | |
1355 | * The following file in debugfs provides that interface: | |
1356 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1357 | * | |
1358 | * Usage: | |
1359 | * | |
1360 | * .. code-block:: bash | |
1361 | * | |
1362 | * echo true > .../ras/auto_reboot | |
1363 | * | |
1364 | */ | |
c030f2e4 | 1365 | /* debugfs begin */ |
ea1b8c9b | 1366 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1367 | { |
1368 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
ef0d7d20 LT |
1369 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1370 | struct dentry *dir; | |
36ea1bd2 | 1371 | |
88293c03 ND |
1372 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1373 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1374 | &amdgpu_ras_debugfs_ctrl_ops); | |
1375 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1376 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1377 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1378 | &con->bad_page_cnt_threshold); | |
ef0d7d20 LT |
1379 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1380 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c65b0805 LT |
1381 | debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, |
1382 | &amdgpu_ras_debugfs_eeprom_size_ops); | |
1383 | con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", | |
1384 | S_IRUGO, dir, adev, | |
1385 | &amdgpu_ras_debugfs_eeprom_table_ops); | |
1386 | amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); | |
c688a06b GC |
1387 | |
1388 | /* | |
1389 | * After one uncorrectable error happens, usually GPU recovery will | |
1390 | * be scheduled. But due to the known problem in GPU recovery failing | |
1391 | * to bring GPU back, below interface provides one direct way to | |
1392 | * user to reboot system automatically in such case within | |
1393 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1394 | * will never be called. | |
1395 | */ | |
88293c03 | 1396 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1397 | |
1398 | /* | |
1399 | * User could set this not to clean up hardware's error count register | |
1400 | * of RAS IPs during ras recovery. | |
1401 | */ | |
88293c03 ND |
1402 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1403 | &con->disable_ras_err_cnt_harvest); | |
1404 | return dir; | |
36ea1bd2 | 1405 | } |
1406 | ||
cedf7884 | 1407 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1408 | struct ras_fs_if *head, |
1409 | struct dentry *dir) | |
c030f2e4 | 1410 | { |
c030f2e4 | 1411 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1412 | |
88293c03 | 1413 | if (!obj || !dir) |
450f30ea | 1414 | return; |
c030f2e4 | 1415 | |
1416 | get_obj(obj); | |
1417 | ||
1418 | memcpy(obj->fs_data.debugfs_name, | |
1419 | head->debugfs_name, | |
1420 | sizeof(obj->fs_data.debugfs_name)); | |
1421 | ||
88293c03 ND |
1422 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1423 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1424 | } |
1425 | ||
f9317014 TZ |
1426 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1427 | { | |
1428 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1429 | struct dentry *dir; |
c1509f3f | 1430 | struct ras_manager *obj; |
f9317014 TZ |
1431 | struct ras_fs_if fs_info; |
1432 | ||
1433 | /* | |
1434 | * it won't be called in resume path, no need to check | |
1435 | * suspend and gpu reset status | |
1436 | */ | |
cedf7884 | 1437 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1438 | return; |
1439 | ||
88293c03 | 1440 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1441 | |
c1509f3f | 1442 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1443 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1444 | (obj->attr_inuse == 1)) { | |
1445 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
640ae42e | 1446 | get_ras_block_str(&obj->head)); |
f9317014 | 1447 | fs_info.head = obj->head; |
88293c03 | 1448 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1449 | } |
1450 | } | |
1451 | } | |
1452 | ||
c030f2e4 | 1453 | /* debugfs end */ |
1454 | ||
1455 | /* ras fs */ | |
c3d4d45d GC |
1456 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1457 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1458 | static DEVICE_ATTR(features, S_IRUGO, | |
1459 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1460 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1461 | { | |
c3d4d45d GC |
1462 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1463 | struct attribute_group group = { | |
1464 | .name = RAS_FS_NAME, | |
1465 | }; | |
1466 | struct attribute *attrs[] = { | |
1467 | &con->features_attr.attr, | |
1468 | NULL | |
1469 | }; | |
1470 | struct bin_attribute *bin_attrs[] = { | |
1471 | NULL, | |
1472 | NULL, | |
1473 | }; | |
a069a9eb | 1474 | int r; |
c030f2e4 | 1475 | |
c3d4d45d GC |
1476 | /* add features entry */ |
1477 | con->features_attr = dev_attr_features; | |
1478 | group.attrs = attrs; | |
1479 | sysfs_attr_init(attrs[0]); | |
1480 | ||
1481 | if (amdgpu_bad_page_threshold != 0) { | |
1482 | /* add bad_page_features entry */ | |
1483 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1484 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1485 | bin_attrs[0] = &con->badpages_attr; | |
1486 | group.bin_attrs = bin_attrs; | |
1487 | sysfs_bin_attr_init(bin_attrs[0]); | |
1488 | } | |
1489 | ||
a069a9eb AD |
1490 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1491 | if (r) | |
1492 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1493 | |
c030f2e4 | 1494 | return 0; |
1495 | } | |
1496 | ||
1497 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1498 | { | |
88293c03 ND |
1499 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1500 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1501 | ||
1502 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1503 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1504 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1505 | if (ip_obj) | |
1506 | put_obj(ip_obj); | |
1507 | } | |
1508 | } | |
1509 | ||
c030f2e4 | 1510 | amdgpu_ras_sysfs_remove_all(adev); |
1511 | return 0; | |
1512 | } | |
1513 | /* ras fs end */ | |
1514 | ||
1515 | /* ih begin */ | |
1516 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1517 | { | |
1518 | struct ras_ih_data *data = &obj->ih_data; | |
1519 | struct amdgpu_iv_entry entry; | |
1520 | int ret; | |
cf04dfd0 | 1521 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1522 | |
1523 | while (data->rptr != data->wptr) { | |
1524 | rmb(); | |
1525 | memcpy(&entry, &data->ring[data->rptr], | |
1526 | data->element_size); | |
1527 | ||
1528 | wmb(); | |
1529 | data->rptr = (data->aligned_element_size + | |
1530 | data->rptr) % data->ring_size; | |
1531 | ||
c030f2e4 | 1532 | if (data->cb) { |
f524dd54 TZ |
1533 | if (amdgpu_ras_is_poison_mode_supported(obj->adev) && |
1534 | obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
1535 | dev_info(obj->adev->dev, | |
1536 | "Poison is created, no user action is needed.\n"); | |
1537 | else { | |
1538 | /* Let IP handle its data, maybe we need get the output | |
1539 | * from the callback to udpate the error type/count, etc | |
1540 | */ | |
b54ce6c9 | 1541 | memset(&err_data, 0, sizeof(err_data)); |
f524dd54 TZ |
1542 | ret = data->cb(obj->adev, &err_data, &entry); |
1543 | /* ue will trigger an interrupt, and in that case | |
1544 | * we need do a reset to recovery the whole system. | |
1545 | * But leave IP do that recovery, here we just dispatch | |
1546 | * the error. | |
51437623 | 1547 | */ |
f524dd54 TZ |
1548 | if (ret == AMDGPU_RAS_SUCCESS) { |
1549 | /* these counts could be left as 0 if | |
1550 | * some blocks do not count error number | |
1551 | */ | |
1552 | obj->err_data.ue_count += err_data.ue_count; | |
1553 | obj->err_data.ce_count += err_data.ce_count; | |
1554 | } | |
c030f2e4 | 1555 | } |
c030f2e4 | 1556 | } |
1557 | } | |
1558 | } | |
1559 | ||
1560 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1561 | { | |
1562 | struct ras_ih_data *data = | |
1563 | container_of(work, struct ras_ih_data, ih_work); | |
1564 | struct ras_manager *obj = | |
1565 | container_of(data, struct ras_manager, ih_data); | |
1566 | ||
1567 | amdgpu_ras_interrupt_handler(obj); | |
1568 | } | |
1569 | ||
1570 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1571 | struct ras_dispatch_if *info) | |
1572 | { | |
1573 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1574 | struct ras_ih_data *data = &obj->ih_data; | |
1575 | ||
1576 | if (!obj) | |
1577 | return -EINVAL; | |
1578 | ||
1579 | if (data->inuse == 0) | |
1580 | return 0; | |
1581 | ||
1582 | /* Might be overflow... */ | |
1583 | memcpy(&data->ring[data->wptr], info->entry, | |
1584 | data->element_size); | |
1585 | ||
1586 | wmb(); | |
1587 | data->wptr = (data->aligned_element_size + | |
1588 | data->wptr) % data->ring_size; | |
1589 | ||
1590 | schedule_work(&data->ih_work); | |
1591 | ||
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
9252d33d | 1596 | struct ras_common_if *head) |
c030f2e4 | 1597 | { |
9252d33d | 1598 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1599 | struct ras_ih_data *data; |
1600 | ||
1601 | if (!obj) | |
1602 | return -EINVAL; | |
1603 | ||
1604 | data = &obj->ih_data; | |
1605 | if (data->inuse == 0) | |
1606 | return 0; | |
1607 | ||
1608 | cancel_work_sync(&data->ih_work); | |
1609 | ||
1610 | kfree(data->ring); | |
1611 | memset(data, 0, sizeof(*data)); | |
1612 | put_obj(obj); | |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
9252d33d | 1618 | struct ras_common_if *head) |
c030f2e4 | 1619 | { |
9252d33d | 1620 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1621 | struct ras_ih_data *data; |
9252d33d | 1622 | struct amdgpu_ras_block_object *ras_obj; |
c030f2e4 | 1623 | |
1624 | if (!obj) { | |
1625 | /* in case we registe the IH before enable ras feature */ | |
9252d33d | 1626 | obj = amdgpu_ras_create_obj(adev, head); |
c030f2e4 | 1627 | if (!obj) |
1628 | return -EINVAL; | |
1629 | } else | |
1630 | get_obj(obj); | |
1631 | ||
9252d33d | 1632 | ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); |
1633 | ||
c030f2e4 | 1634 | data = &obj->ih_data; |
1635 | /* add the callback.etc */ | |
1636 | *data = (struct ras_ih_data) { | |
1637 | .inuse = 0, | |
9252d33d | 1638 | .cb = ras_obj->ras_cb, |
c030f2e4 | 1639 | .element_size = sizeof(struct amdgpu_iv_entry), |
1640 | .rptr = 0, | |
1641 | .wptr = 0, | |
1642 | }; | |
1643 | ||
1644 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1645 | ||
1646 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1647 | /* the ring can store 64 iv entries. */ | |
1648 | data->ring_size = 64 * data->aligned_element_size; | |
1649 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1650 | if (!data->ring) { | |
1651 | put_obj(obj); | |
1652 | return -ENOMEM; | |
1653 | } | |
1654 | ||
1655 | /* IH is ready */ | |
1656 | data->inuse = 1; | |
1657 | ||
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1662 | { | |
1663 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1664 | struct ras_manager *obj, *tmp; | |
1665 | ||
1666 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
9252d33d | 1667 | amdgpu_ras_interrupt_remove_handler(adev, &obj->head); |
c030f2e4 | 1668 | } |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | /* ih end */ | |
1673 | ||
313c8fd3 GC |
1674 | /* traversal all IPs except NBIO to query error counter */ |
1675 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1676 | { | |
1677 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1678 | struct ras_manager *obj; | |
1679 | ||
8ab0d6f0 | 1680 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
1681 | return; |
1682 | ||
1683 | list_for_each_entry(obj, &con->head, node) { | |
1684 | struct ras_query_if info = { | |
1685 | .head = obj->head, | |
1686 | }; | |
1687 | ||
1688 | /* | |
1689 | * PCIE_BIF IP has one different isr by ras controller | |
1690 | * interrupt, the specific ras counter query will be | |
1691 | * done in that isr. So skip such block from common | |
1692 | * sync flood interrupt isr calling. | |
1693 | */ | |
1694 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1695 | continue; | |
1696 | ||
cf63b702 SY |
1697 | /* |
1698 | * this is a workaround for aldebaran, skip send msg to | |
1699 | * smu to get ecc_info table due to smu handle get ecc | |
1700 | * info table failed temporarily. | |
1701 | * should be removed until smu fix handle ecc_info table. | |
1702 | */ | |
1703 | if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
1704 | (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2))) | |
1705 | continue; | |
1706 | ||
761d86d3 | 1707 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1708 | } |
1709 | } | |
1710 | ||
3f975d0f | 1711 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1712 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1713 | struct ras_query_if *info) | |
3f975d0f | 1714 | { |
8eb53bb2 | 1715 | struct amdgpu_ras_block_object *block_obj; |
3f975d0f SY |
1716 | /* |
1717 | * Only two block need to query read/write | |
1718 | * RspStatus at current state | |
1719 | */ | |
5e67bba3 | 1720 | if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && |
1721 | (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) | |
b6efdb02 | 1722 | return; |
1723 | ||
1724 | block_obj = amdgpu_ras_get_ras_block(adev, | |
1725 | info->head.block, | |
1726 | info->head.sub_block_index); | |
5e67bba3 | 1727 | |
5e67bba3 | 1728 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1729 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1730 | get_ras_block_str(&info->head)); | |
b6efdb02 | 1731 | return; |
3f975d0f | 1732 | } |
5e67bba3 | 1733 | |
1734 | if (block_obj->hw_ops->query_ras_error_status) | |
ab3b9de6 | 1735 | block_obj->hw_ops->query_ras_error_status(adev); |
5e67bba3 | 1736 | |
3f975d0f SY |
1737 | } |
1738 | ||
1739 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1740 | { | |
1741 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1742 | struct ras_manager *obj; | |
1743 | ||
8ab0d6f0 | 1744 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
1745 | return; |
1746 | ||
1747 | list_for_each_entry(obj, &con->head, node) { | |
1748 | struct ras_query_if info = { | |
1749 | .head = obj->head, | |
1750 | }; | |
1751 | ||
1752 | amdgpu_ras_error_status_query(adev, &info); | |
1753 | } | |
1754 | } | |
1755 | ||
c030f2e4 | 1756 | /* recovery begin */ |
466b1793 | 1757 | |
1758 | /* return 0 on success. | |
1759 | * caller need free bps. | |
1760 | */ | |
1761 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1762 | struct ras_badpage **bps, unsigned int *count) | |
1763 | { | |
1764 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1765 | struct ras_err_handler_data *data; | |
1766 | int i = 0; | |
732f2a30 | 1767 | int ret = 0, status; |
466b1793 | 1768 | |
1769 | if (!con || !con->eh_data || !bps || !count) | |
1770 | return -EINVAL; | |
1771 | ||
1772 | mutex_lock(&con->recovery_lock); | |
1773 | data = con->eh_data; | |
1774 | if (!data || data->count == 0) { | |
1775 | *bps = NULL; | |
46cf2fec | 1776 | ret = -EINVAL; |
466b1793 | 1777 | goto out; |
1778 | } | |
1779 | ||
1780 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1781 | if (!*bps) { | |
1782 | ret = -ENOMEM; | |
1783 | goto out; | |
1784 | } | |
1785 | ||
1786 | for (; i < data->count; i++) { | |
1787 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1788 | .bp = data->bps[i].retired_page, |
466b1793 | 1789 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1790 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1791 | }; |
ec6aae97 | 1792 | status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, |
676deb38 | 1793 | data->bps[i].retired_page); |
732f2a30 | 1794 | if (status == -EBUSY) |
52dd95f2 | 1795 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1796 | else if (status == -ENOENT) |
52dd95f2 | 1797 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1798 | } |
1799 | ||
1800 | *count = data->count; | |
1801 | out: | |
1802 | mutex_unlock(&con->recovery_lock); | |
1803 | return ret; | |
1804 | } | |
1805 | ||
c030f2e4 | 1806 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1807 | { | |
1808 | struct amdgpu_ras *ras = | |
1809 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1810 | struct amdgpu_device *remote_adev = NULL; |
1811 | struct amdgpu_device *adev = ras->adev; | |
1812 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1813 | |
f75e94d8 | 1814 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1815 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1816 | ||
f75e94d8 GC |
1817 | /* Build list of devices to query RAS related errors */ |
1818 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1819 | device_list_handle = &hive->device_list; | |
1820 | } else { | |
1821 | INIT_LIST_HEAD(&device_list); | |
1822 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1823 | device_list_handle = &device_list; | |
1824 | } | |
c030f2e4 | 1825 | |
f75e94d8 | 1826 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1827 | device_list_handle, gmc.xgmi.head) { |
1828 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1829 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1830 | } |
d95e8e97 DL |
1831 | |
1832 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1833 | } |
313c8fd3 | 1834 | |
93af20f7 | 1835 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1836 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1837 | atomic_set(&ras->in_recovery, 0); |
1838 | } | |
1839 | ||
c030f2e4 | 1840 | /* alloc/realloc bps array */ |
1841 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1842 | struct ras_err_handler_data *data, int pages) | |
1843 | { | |
1844 | unsigned int old_space = data->count + data->space_left; | |
1845 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1846 | unsigned int align_space = ALIGN(new_space, 512); |
1847 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1848 | |
676deb38 | 1849 | if (!bps) { |
9dc23a63 | 1850 | kfree(bps); |
c030f2e4 | 1851 | return -ENOMEM; |
9dc23a63 | 1852 | } |
c030f2e4 | 1853 | |
1854 | if (data->bps) { | |
9dc23a63 | 1855 | memcpy(bps, data->bps, |
c030f2e4 | 1856 | data->count * sizeof(*data->bps)); |
1857 | kfree(data->bps); | |
1858 | } | |
1859 | ||
9dc23a63 | 1860 | data->bps = bps; |
c030f2e4 | 1861 | data->space_left += align_space - old_space; |
1862 | return 0; | |
1863 | } | |
1864 | ||
1865 | /* it deal with vram only. */ | |
1866 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1867 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1868 | { |
1869 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1870 | struct ras_err_handler_data *data; |
c030f2e4 | 1871 | int ret = 0; |
676deb38 | 1872 | uint32_t i; |
c030f2e4 | 1873 | |
73aa8e1a | 1874 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1875 | return 0; |
1876 | ||
1877 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1878 | data = con->eh_data; |
c030f2e4 | 1879 | if (!data) |
1880 | goto out; | |
1881 | ||
676deb38 DL |
1882 | for (i = 0; i < pages; i++) { |
1883 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1884 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1885 | continue; | |
1886 | ||
1887 | if (!data->space_left && | |
1888 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1889 | ret = -ENOMEM; |
1890 | goto out; | |
1891 | } | |
1892 | ||
ec6aae97 | 1893 | amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, |
676deb38 DL |
1894 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, |
1895 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1896 | |
676deb38 DL |
1897 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1898 | data->count++; | |
1899 | data->space_left--; | |
1900 | } | |
c030f2e4 | 1901 | out: |
1902 | mutex_unlock(&con->recovery_lock); | |
1903 | ||
1904 | return ret; | |
1905 | } | |
1906 | ||
78ad00c9 TZ |
1907 | /* |
1908 | * write error record array to eeprom, the function should be | |
1909 | * protected by recovery_lock | |
1910 | */ | |
22503d80 | 1911 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1912 | { |
1913 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1914 | struct ras_err_handler_data *data; | |
8a3e801f | 1915 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1916 | int save_count; |
1917 | ||
1918 | if (!con || !con->eh_data) | |
1919 | return 0; | |
1920 | ||
d9a69fe5 | 1921 | mutex_lock(&con->recovery_lock); |
8a3e801f | 1922 | control = &con->eeprom_control; |
78ad00c9 | 1923 | data = con->eh_data; |
0686627b | 1924 | save_count = data->count - control->ras_num_recs; |
d9a69fe5 | 1925 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1926 | /* only new entries are saved */ |
b1628425 | 1927 | if (save_count > 0) { |
63d4c081 LT |
1928 | if (amdgpu_ras_eeprom_append(control, |
1929 | &data->bps[control->ras_num_recs], | |
1930 | save_count)) { | |
6952e99c | 1931 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1932 | return -EIO; |
1933 | } | |
1934 | ||
b1628425 GC |
1935 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1936 | } | |
1937 | ||
78ad00c9 TZ |
1938 | return 0; |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * read error record array in eeprom and reserve enough space for | |
1943 | * storing new bad pages | |
1944 | */ | |
1945 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1946 | { | |
1947 | struct amdgpu_ras_eeprom_control *control = | |
6457205c | 1948 | &adev->psp.ras_context.ras->eeprom_control; |
e4e6a589 LT |
1949 | struct eeprom_table_record *bps; |
1950 | int ret; | |
78ad00c9 TZ |
1951 | |
1952 | /* no bad page record, skip eeprom access */ | |
0686627b | 1953 | if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) |
e4e6a589 | 1954 | return 0; |
78ad00c9 | 1955 | |
0686627b | 1956 | bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); |
78ad00c9 TZ |
1957 | if (!bps) |
1958 | return -ENOMEM; | |
1959 | ||
0686627b | 1960 | ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); |
e4e6a589 | 1961 | if (ret) |
6952e99c | 1962 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
e4e6a589 | 1963 | else |
0686627b | 1964 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); |
78ad00c9 | 1965 | |
78ad00c9 TZ |
1966 | kfree(bps); |
1967 | return ret; | |
1968 | } | |
1969 | ||
676deb38 DL |
1970 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1971 | uint64_t addr) | |
1972 | { | |
1973 | struct ras_err_handler_data *data = con->eh_data; | |
1974 | int i; | |
1975 | ||
1976 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1977 | for (i = 0; i < data->count; i++) | |
1978 | if (addr == data->bps[i].retired_page) | |
1979 | return true; | |
1980 | ||
1981 | return false; | |
1982 | } | |
1983 | ||
6e4be987 TZ |
1984 | /* |
1985 | * check if an address belongs to bad page | |
1986 | * | |
1987 | * Note: this check is only for umc block | |
1988 | */ | |
1989 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1990 | uint64_t addr) | |
1991 | { | |
1992 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1993 | bool ret = false; |
1994 | ||
1995 | if (!con || !con->eh_data) | |
1996 | return ret; | |
1997 | ||
1998 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1999 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
2000 | mutex_unlock(&con->recovery_lock); |
2001 | return ret; | |
2002 | } | |
2003 | ||
e5c04edf | 2004 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
e4e6a589 | 2005 | uint32_t max_count) |
c84d4670 | 2006 | { |
e5c04edf | 2007 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
2008 | |
2009 | /* | |
2010 | * Justification of value bad_page_cnt_threshold in ras structure | |
2011 | * | |
2012 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
2013 | * in eeprom, and introduce two scenarios accordingly. | |
2014 | * | |
2015 | * Bad page retirement enablement: | |
2016 | * - If amdgpu_bad_page_threshold = -1, | |
2017 | * bad_page_cnt_threshold = typical value by formula. | |
2018 | * | |
2019 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
2020 | * max record length in eeprom, use it directly. | |
2021 | * | |
2022 | * Bad page retirement disablement: | |
2023 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
2024 | * functionality is disabled, and bad_page_cnt_threshold will | |
2025 | * take no effect. | |
2026 | */ | |
2027 | ||
e4e6a589 LT |
2028 | if (amdgpu_bad_page_threshold < 0) { |
2029 | u64 val = adev->gmc.mc_vram_size; | |
c84d4670 | 2030 | |
e4e6a589 | 2031 | do_div(val, RAS_BAD_PAGE_COVER); |
e5c04edf | 2032 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
e4e6a589 | 2033 | max_count); |
e5c04edf | 2034 | } else { |
e4e6a589 LT |
2035 | con->bad_page_cnt_threshold = min_t(int, max_count, |
2036 | amdgpu_bad_page_threshold); | |
c84d4670 GC |
2037 | } |
2038 | } | |
2039 | ||
1a6fc071 | 2040 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 2041 | { |
2042 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 2043 | struct ras_err_handler_data **data; |
e4e6a589 | 2044 | u32 max_eeprom_records_count = 0; |
b82e65a9 | 2045 | bool exc_err_limit = false; |
78ad00c9 | 2046 | int ret; |
c030f2e4 | 2047 | |
1d9d2ca8 LT |
2048 | if (!con) |
2049 | return 0; | |
2050 | ||
2051 | /* Allow access to RAS EEPROM via debugfs, when the ASIC | |
2052 | * supports RAS and debugfs is enabled, but when | |
2053 | * adev->ras_enabled is unset, i.e. when "ras_enable" | |
2054 | * module parameter is set to 0. | |
2055 | */ | |
2056 | con->adev = adev; | |
2057 | ||
2058 | if (!adev->ras_enabled) | |
4d1337d2 AG |
2059 | return 0; |
2060 | ||
1d9d2ca8 | 2061 | data = &con->eh_data; |
1a6fc071 TZ |
2062 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
2063 | if (!*data) { | |
2064 | ret = -ENOMEM; | |
2065 | goto out; | |
2066 | } | |
c030f2e4 | 2067 | |
2068 | mutex_init(&con->recovery_lock); | |
2069 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
2070 | atomic_set(&con->in_recovery, 0); | |
c030f2e4 | 2071 | |
e4e6a589 LT |
2072 | max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(); |
2073 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); | |
c84d4670 | 2074 | |
e5086659 | 2075 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
2076 | * when the GPU is pending on XGMI reset during probe time | |
2077 | * (Mostly after second bus reset), skip it now | |
2078 | */ | |
2079 | if (adev->gmc.xgmi.pending_reset) | |
2080 | return 0; | |
b82e65a9 GC |
2081 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
2082 | /* | |
2083 | * This calling fails when exc_err_limit is true or | |
2084 | * ret != 0. | |
2085 | */ | |
2086 | if (exc_err_limit || ret) | |
1a6fc071 | 2087 | goto free; |
78ad00c9 | 2088 | |
0686627b | 2089 | if (con->eeprom_control.ras_num_recs) { |
78ad00c9 TZ |
2090 | ret = amdgpu_ras_load_bad_pages(adev); |
2091 | if (ret) | |
1a6fc071 | 2092 | goto free; |
513befa6 | 2093 | |
bc143d8b | 2094 | amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); |
78ad00c9 | 2095 | } |
c030f2e4 | 2096 | |
12b2cab7 MJ |
2097 | #ifdef CONFIG_X86_MCE_AMD |
2098 | if ((adev->asic_type == CHIP_ALDEBARAN) && | |
2099 | (adev->gmc.xgmi.connected_to_cpu)) | |
91a1a52d | 2100 | amdgpu_register_bad_pages_mca_notifier(adev); |
12b2cab7 | 2101 | #endif |
c030f2e4 | 2102 | return 0; |
1a6fc071 | 2103 | |
1a6fc071 | 2104 | free: |
1a6fc071 | 2105 | kfree((*data)->bps); |
1a6fc071 | 2106 | kfree(*data); |
1995b3a3 | 2107 | con->eh_data = NULL; |
1a6fc071 | 2108 | out: |
cf696091 | 2109 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2110 | |
b82e65a9 GC |
2111 | /* |
2112 | * Except error threshold exceeding case, other failure cases in this | |
2113 | * function would not fail amdgpu driver init. | |
2114 | */ | |
2115 | if (!exc_err_limit) | |
2116 | ret = 0; | |
2117 | else | |
2118 | ret = -EINVAL; | |
2119 | ||
1a6fc071 | 2120 | return ret; |
c030f2e4 | 2121 | } |
2122 | ||
2123 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2124 | { | |
2125 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2126 | struct ras_err_handler_data *data = con->eh_data; | |
2127 | ||
1a6fc071 TZ |
2128 | /* recovery_init failed to init it, fini is useless */ |
2129 | if (!data) | |
2130 | return 0; | |
2131 | ||
c030f2e4 | 2132 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2133 | |
2134 | mutex_lock(&con->recovery_lock); | |
2135 | con->eh_data = NULL; | |
2136 | kfree(data->bps); | |
2137 | kfree(data); | |
2138 | mutex_unlock(&con->recovery_lock); | |
2139 | ||
2140 | return 0; | |
2141 | } | |
2142 | /* recovery end */ | |
2143 | ||
084e2640 | 2144 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2145 | { |
084e2640 LT |
2146 | return adev->asic_type == CHIP_VEGA10 || |
2147 | adev->asic_type == CHIP_VEGA20 || | |
2148 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2149 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2150 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2151 | } |
2152 | ||
f50160cf SY |
2153 | /* |
2154 | * this is workaround for vega20 workstation sku, | |
2155 | * force enable gfx ras, ignore vbios gfx ras flag | |
2156 | * due to GC EDC can not write | |
2157 | */ | |
e509965e | 2158 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2159 | { |
2160 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2161 | ||
2162 | if (!ctx) | |
2163 | return; | |
2164 | ||
2165 | if (strnstr(ctx->vbios_version, "D16406", | |
e11d5e0d SY |
2166 | sizeof(ctx->vbios_version)) || |
2167 | strnstr(ctx->vbios_version, "D36002", | |
2168 | sizeof(ctx->vbios_version))) | |
8ab0d6f0 | 2169 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2170 | } |
2171 | ||
5caf466a | 2172 | /* |
2173 | * check hardware's ras ability which will be saved in hw_supported. | |
2174 | * if hardware does not support ras, we can skip some ras initializtion and | |
2175 | * forbid some ras operations from IP. | |
2176 | * if software itself, say boot parameter, limit the ras ability. We still | |
2177 | * need allow IP do some limited operations, like disable. In such case, | |
2178 | * we have to initialize ras as normal. but need check if operation is | |
2179 | * allowed or not in each function. | |
2180 | */ | |
e509965e | 2181 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2182 | { |
8ab0d6f0 | 2183 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2184 | |
88474cca | 2185 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 2186 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 2187 | return; |
b404ae82 | 2188 | |
75f06251 HZ |
2189 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2190 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2191 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2192 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2193 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2194 | } else { |
2195 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2196 | } | |
88474cca | 2197 | |
75f06251 HZ |
2198 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2199 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
8ab0d6f0 | 2200 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2201 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2202 | } else { |
2203 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2204 | } | |
2205 | } else { | |
2206 | /* driver only manages a few IP blocks RAS feature | |
2207 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2208 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2209 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2210 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2211 | } |
88474cca | 2212 | |
e509965e | 2213 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2214 | |
88474cca | 2215 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2216 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2217 | |
8ab0d6f0 LT |
2218 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2219 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2220 | } |
2221 | ||
05adfd80 LT |
2222 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2223 | { | |
2224 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2225 | ras_counte_delay_work.work); | |
2226 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2227 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2228 | unsigned long ce_count, ue_count; |
2229 | int res; | |
2230 | ||
2231 | res = pm_runtime_get_sync(dev->dev); | |
2232 | if (res < 0) | |
2233 | goto Out; | |
2234 | ||
2235 | /* Cache new values. | |
2236 | */ | |
4d9f771e LT |
2237 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { |
2238 | atomic_set(&con->ras_ce_count, ce_count); | |
2239 | atomic_set(&con->ras_ue_count, ue_count); | |
2240 | } | |
05adfd80 LT |
2241 | |
2242 | pm_runtime_mark_last_busy(dev->dev); | |
2243 | Out: | |
2244 | pm_runtime_put_autosuspend(dev->dev); | |
2245 | } | |
2246 | ||
c030f2e4 | 2247 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2248 | { | |
2249 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2250 | int r; |
e4348849 | 2251 | bool df_poison, umc_poison; |
c030f2e4 | 2252 | |
b404ae82 | 2253 | if (con) |
c030f2e4 | 2254 | return 0; |
2255 | ||
2256 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
640ae42e JC |
2257 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + |
2258 | sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, | |
c030f2e4 | 2259 | GFP_KERNEL|__GFP_ZERO); |
2260 | if (!con) | |
2261 | return -ENOMEM; | |
2262 | ||
05adfd80 LT |
2263 | con->adev = adev; |
2264 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2265 | atomic_set(&con->ras_ce_count, 0); | |
2266 | atomic_set(&con->ras_ue_count, 0); | |
2267 | ||
c030f2e4 | 2268 | con->objs = (struct ras_manager *)(con + 1); |
2269 | ||
2270 | amdgpu_ras_set_context(adev, con); | |
2271 | ||
e509965e LT |
2272 | amdgpu_ras_check_supported(adev); |
2273 | ||
7ddd9770 | 2274 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2275 | /* set gfx block ras context feature for VEGA20 Gaming |
2276 | * send ras disable cmd to ras ta during ras late init. | |
2277 | */ | |
8ab0d6f0 | 2278 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2279 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2280 | ||
2281 | return 0; | |
2282 | } | |
2283 | ||
5e91160a | 2284 | r = 0; |
5436ab94 | 2285 | goto release_con; |
fb2a3607 HZ |
2286 | } |
2287 | ||
c030f2e4 | 2288 | con->features = 0; |
2289 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2290 | /* Might need get this flag from vbios. */ |
2291 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2292 | |
6e36f231 HZ |
2293 | /* initialize nbio ras function ahead of any other |
2294 | * ras functions so hardware fatal error interrupt | |
2295 | * can be enabled as early as possible */ | |
2296 | switch (adev->asic_type) { | |
2297 | case CHIP_VEGA20: | |
2298 | case CHIP_ARCTURUS: | |
2299 | case CHIP_ALDEBARAN: | |
2e54fe5d | 2300 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2301 | adev->nbio.ras = &nbio_v7_4_ras; | |
2302 | amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block); | |
80ed77f9 | 2303 | adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm; |
2e54fe5d | 2304 | } |
6e36f231 HZ |
2305 | break; |
2306 | default: | |
2307 | /* nbio ras is not available */ | |
2308 | break; | |
2309 | } | |
2310 | ||
2e54fe5d | 2311 | if (adev->nbio.ras && |
2312 | adev->nbio.ras->init_ras_controller_interrupt) { | |
2313 | r = adev->nbio.ras->init_ras_controller_interrupt(adev); | |
4e644fff | 2314 | if (r) |
5436ab94 | 2315 | goto release_con; |
4e644fff HZ |
2316 | } |
2317 | ||
2e54fe5d | 2318 | if (adev->nbio.ras && |
2319 | adev->nbio.ras->init_ras_err_event_athub_interrupt) { | |
2320 | r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2321 | if (r) |
5436ab94 | 2322 | goto release_con; |
4e644fff HZ |
2323 | } |
2324 | ||
e4348849 | 2325 | /* Init poison supported flag, the default value is false */ |
655ff353 TZ |
2326 | if (adev->gmc.xgmi.connected_to_cpu) { |
2327 | /* enabled by default when GPU is connected to CPU */ | |
2328 | con->poison_supported = true; | |
2329 | } | |
2330 | else if (adev->df.funcs && | |
e4348849 | 2331 | adev->df.funcs->query_ras_poison_mode && |
efe17d5a | 2332 | adev->umc.ras && |
2333 | adev->umc.ras->query_ras_poison_mode) { | |
e4348849 TZ |
2334 | df_poison = |
2335 | adev->df.funcs->query_ras_poison_mode(adev); | |
2336 | umc_poison = | |
efe17d5a | 2337 | adev->umc.ras->query_ras_poison_mode(adev); |
e4348849 TZ |
2338 | /* Only poison is set in both DF and UMC, we can support it */ |
2339 | if (df_poison && umc_poison) | |
2340 | con->poison_supported = true; | |
2341 | else if (df_poison != umc_poison) | |
2342 | dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
2343 | df_poison, umc_poison); | |
2344 | } | |
2345 | ||
5e91160a GC |
2346 | if (amdgpu_ras_fs_init(adev)) { |
2347 | r = -EINVAL; | |
5436ab94 | 2348 | goto release_con; |
5e91160a | 2349 | } |
c030f2e4 | 2350 | |
6952e99c | 2351 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2352 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2353 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2354 | |
c030f2e4 | 2355 | return 0; |
5436ab94 | 2356 | release_con: |
c030f2e4 | 2357 | amdgpu_ras_set_context(adev, NULL); |
2358 | kfree(con); | |
2359 | ||
5e91160a | 2360 | return r; |
c030f2e4 | 2361 | } |
2362 | ||
8f6368a9 | 2363 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 JC |
2364 | { |
2365 | if (adev->gmc.xgmi.connected_to_cpu) | |
2366 | return 1; | |
2367 | return 0; | |
2368 | } | |
2369 | ||
2370 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2371 | struct ras_common_if *ras_block) | |
2372 | { | |
2373 | struct ras_query_if info = { | |
2374 | .head = *ras_block, | |
2375 | }; | |
2376 | ||
2377 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2378 | return 0; | |
2379 | ||
2380 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2381 | DRM_WARN("RAS init harvest failure"); | |
2382 | ||
2383 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2384 | DRM_WARN("RAS init harvest reset failure"); | |
2385 | ||
2386 | return 0; | |
2387 | } | |
2388 | ||
e4348849 TZ |
2389 | bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) |
2390 | { | |
2391 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2392 | ||
2393 | if (!con) | |
2394 | return false; | |
2395 | ||
2396 | return con->poison_supported; | |
2397 | } | |
2398 | ||
b293e891 HZ |
2399 | /* helper function to handle common stuff in ip late init phase */ |
2400 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2401 | struct ras_common_if *ras_block, | |
2402 | struct ras_fs_if *fs_info, | |
2403 | struct ras_ih_if *ih_info) | |
2404 | { | |
05adfd80 LT |
2405 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2406 | unsigned long ue_count, ce_count; | |
b293e891 HZ |
2407 | int r; |
2408 | ||
2409 | /* disable RAS feature per IP block if it is not supported */ | |
2410 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2411 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2412 | return 0; | |
2413 | } | |
2414 | ||
2415 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2416 | if (r) { | |
9080a18f | 2417 | if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2418 | /* in resume phase, if fail to enable ras, |
2419 | * clean up all ras fs nodes, and disable ras */ | |
2420 | goto cleanup; | |
2421 | } else | |
2422 | return r; | |
2423 | } | |
2424 | ||
134d16d5 JC |
2425 | /* check for errors on warm reset edc persisant supported ASIC */ |
2426 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2427 | ||
b293e891 | 2428 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2429 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2430 | return 0; |
2431 | ||
2432 | if (ih_info->cb) { | |
9252d33d | 2433 | r = amdgpu_ras_interrupt_add_handler(adev, ras_block); |
b293e891 HZ |
2434 | if (r) |
2435 | goto interrupt; | |
2436 | } | |
2437 | ||
9252d33d | 2438 | r = amdgpu_ras_sysfs_create(adev, ras_block); |
b293e891 HZ |
2439 | if (r) |
2440 | goto sysfs; | |
2441 | ||
05adfd80 LT |
2442 | /* Those are the cached values at init. |
2443 | */ | |
4d9f771e LT |
2444 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { |
2445 | atomic_set(&con->ras_ce_count, ce_count); | |
2446 | atomic_set(&con->ras_ue_count, ue_count); | |
2447 | } | |
05adfd80 | 2448 | |
b293e891 HZ |
2449 | return 0; |
2450 | cleanup: | |
2451 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2452 | sysfs: | |
b293e891 | 2453 | if (ih_info->cb) |
9252d33d | 2454 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); |
b293e891 HZ |
2455 | interrupt: |
2456 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2457 | return r; | |
2458 | } | |
2459 | ||
bdb3489c | 2460 | int amdgpu_ras_block_late_init(struct amdgpu_device *adev, |
2461 | struct ras_common_if *ras_block) | |
2462 | { | |
2463 | char sysfs_name[32]; | |
2464 | struct ras_ih_if ih_info; | |
2465 | struct ras_fs_if fs_info; | |
2466 | struct amdgpu_ras_block_object *obj; | |
2467 | ||
2468 | obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); | |
2469 | ih_info.cb = obj->ras_cb; | |
2470 | ih_info.head = *ras_block; | |
2471 | snprintf(sysfs_name, sizeof(sysfs_name), "%s_err_count", ras_block->name); | |
2472 | fs_info.sysfs_name = (const char *)sysfs_name; | |
2473 | fs_info.head = *ras_block; | |
2474 | return amdgpu_ras_late_init(adev, ras_block, &fs_info, &ih_info); | |
2475 | } | |
2476 | ||
b293e891 HZ |
2477 | /* helper function to remove ras fs node and interrupt handler */ |
2478 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2479 | struct ras_common_if *ras_block, | |
2480 | struct ras_ih_if *ih_info) | |
2481 | { | |
2482 | if (!ras_block || !ih_info) | |
2483 | return; | |
2484 | ||
2485 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2486 | if (ih_info->cb) |
9252d33d | 2487 | amdgpu_ras_interrupt_remove_handler(adev, &ih_info->head); |
b293e891 HZ |
2488 | } |
2489 | ||
bdb3489c | 2490 | void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, |
2491 | struct ras_common_if *ras_block) | |
2492 | { | |
2493 | struct ras_ih_if ih_info; | |
2494 | struct amdgpu_ras_block_object *obj; | |
2495 | ||
2496 | if (!ras_block) | |
2497 | return; | |
2498 | ||
2499 | obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); | |
2500 | ih_info.head = *ras_block; | |
2501 | ih_info.cb = obj->ras_cb; | |
2502 | ||
2503 | amdgpu_ras_late_fini(adev, ras_block, &ih_info); | |
2504 | } | |
2505 | ||
a564808e | 2506 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2507 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2508 | */ |
511fdbc3 | 2509 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2510 | { |
2511 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2512 | struct ras_manager *obj, *tmp; | |
2513 | ||
8ab0d6f0 | 2514 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2515 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2516 | amdgpu_release_ras_context(adev); | |
2517 | ||
108c6a63 | 2518 | return; |
970fd197 | 2519 | } |
108c6a63 | 2520 | |
108c6a63 | 2521 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2522 | /* Set up all other IPs which are not implemented. There is a |
2523 | * tricky thing that IP's actual ras error type should be | |
2524 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2525 | * ERROR_NONE make sense anyway. | |
2526 | */ | |
2527 | amdgpu_ras_enable_all_features(adev, 1); | |
2528 | ||
2529 | /* We enable ras on all hw_supported block, but as boot | |
2530 | * parameter might disable some of them and one or more IP has | |
2531 | * not implemented yet. So we disable them on behalf. | |
2532 | */ | |
108c6a63 | 2533 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2534 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2535 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2536 | /* there should be no any reference. */ | |
2537 | WARN_ON(alive_obj(obj)); | |
2538 | } | |
191051a1 | 2539 | } |
108c6a63 | 2540 | } |
2541 | } | |
2542 | ||
511fdbc3 | 2543 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2544 | { | |
2545 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2546 | ||
8ab0d6f0 | 2547 | if (!adev->ras_enabled || !con) |
511fdbc3 | 2548 | return; |
2549 | ||
2550 | amdgpu_ras_disable_all_features(adev, 0); | |
2551 | /* Make sure all ras objects are disabled. */ | |
2552 | if (con->features) | |
2553 | amdgpu_ras_disable_all_features(adev, 1); | |
2554 | } | |
2555 | ||
c030f2e4 | 2556 | /* do some fini work before IP fini as dependence */ |
2557 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2558 | { | |
2559 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2560 | ||
8ab0d6f0 | 2561 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2562 | return 0; |
2563 | ||
72c8c97b | 2564 | |
c030f2e4 | 2565 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
2566 | amdgpu_ras_disable_all_features(adev, 0); | |
2567 | amdgpu_ras_recovery_fini(adev); | |
2568 | return 0; | |
2569 | } | |
2570 | ||
2571 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2572 | { | |
d5e8ff5f | 2573 | struct amdgpu_ras_block_list *ras_node, *tmp; |
c030f2e4 | 2574 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2575 | ||
8ab0d6f0 | 2576 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2577 | return 0; |
2578 | ||
2579 | amdgpu_ras_fs_fini(adev); | |
2580 | amdgpu_ras_interrupt_remove_all(adev); | |
2581 | ||
2582 | WARN(con->features, "Feature mask is not cleared"); | |
2583 | ||
2584 | if (con->features) | |
2585 | amdgpu_ras_disable_all_features(adev, 1); | |
2586 | ||
05adfd80 LT |
2587 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
2588 | ||
c030f2e4 | 2589 | amdgpu_ras_set_context(adev, NULL); |
2590 | kfree(con); | |
2591 | ||
d5e8ff5f | 2592 | /* Clear ras blocks from ras_list and free ras block list node */ |
2593 | list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { | |
2594 | list_del(&ras_node->node); | |
2595 | kfree(ras_node); | |
2596 | } | |
2597 | ||
c030f2e4 | 2598 | return 0; |
2599 | } | |
7c6e68c7 AG |
2600 | |
2601 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2602 | { | |
e509965e | 2603 | amdgpu_ras_check_supported(adev); |
8ab0d6f0 | 2604 | if (!adev->ras_hw_enabled) |
ed606f8a AG |
2605 | return; |
2606 | ||
7c6e68c7 | 2607 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2608 | dev_info(adev->dev, "uncorrectable hardware error" |
2609 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2610 | |
61934624 | 2611 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2612 | } |
2613 | } | |
bb5c7235 WS |
2614 | |
2615 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2616 | { | |
2617 | if (adev->asic_type == CHIP_VEGA20 && | |
2618 | adev->pm.fw_version <= 0x283400) { | |
2619 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2620 | amdgpu_ras_intr_triggered(); | |
2621 | } | |
2622 | ||
2623 | return false; | |
2624 | } | |
970fd197 SY |
2625 | |
2626 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2627 | { | |
2628 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2629 | ||
2630 | if (!con) | |
2631 | return; | |
2632 | ||
8ab0d6f0 | 2633 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
2634 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
2635 | amdgpu_ras_set_context(adev, NULL); | |
2636 | kfree(con); | |
2637 | } | |
2638 | } | |
12b2cab7 MJ |
2639 | |
2640 | #ifdef CONFIG_X86_MCE_AMD | |
2641 | static struct amdgpu_device *find_adev(uint32_t node_id) | |
2642 | { | |
12b2cab7 MJ |
2643 | int i; |
2644 | struct amdgpu_device *adev = NULL; | |
2645 | ||
91a1a52d MJ |
2646 | for (i = 0; i < mce_adev_list.num_gpu; i++) { |
2647 | adev = mce_adev_list.devs[i]; | |
12b2cab7 | 2648 | |
91a1a52d | 2649 | if (adev && adev->gmc.xgmi.connected_to_cpu && |
12b2cab7 MJ |
2650 | adev->gmc.xgmi.physical_node_id == node_id) |
2651 | break; | |
2652 | adev = NULL; | |
2653 | } | |
2654 | ||
12b2cab7 MJ |
2655 | return adev; |
2656 | } | |
2657 | ||
2658 | #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) | |
2659 | #define GET_UMC_INST(m) (((m) >> 21) & 0x7) | |
2660 | #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) | |
2661 | #define GPU_ID_OFFSET 8 | |
2662 | ||
2663 | static int amdgpu_bad_page_notifier(struct notifier_block *nb, | |
2664 | unsigned long val, void *data) | |
2665 | { | |
2666 | struct mce *m = (struct mce *)data; | |
2667 | struct amdgpu_device *adev = NULL; | |
2668 | uint32_t gpu_id = 0; | |
2669 | uint32_t umc_inst = 0; | |
2670 | uint32_t ch_inst, channel_index = 0; | |
2671 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
2672 | struct eeprom_table_record err_rec; | |
2673 | uint64_t retired_page; | |
2674 | ||
2675 | /* | |
2676 | * If the error was generated in UMC_V2, which belongs to GPU UMCs, | |
2677 | * and error occurred in DramECC (Extended error code = 0) then only | |
2678 | * process the error, else bail out. | |
2679 | */ | |
91f75eb4 | 2680 | if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && |
12b2cab7 MJ |
2681 | (XEC(m->status, 0x3f) == 0x0))) |
2682 | return NOTIFY_DONE; | |
2683 | ||
2684 | /* | |
2685 | * If it is correctable error, return. | |
2686 | */ | |
2687 | if (mce_is_correctable(m)) | |
2688 | return NOTIFY_OK; | |
2689 | ||
2690 | /* | |
2691 | * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. | |
2692 | */ | |
2693 | gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; | |
2694 | ||
2695 | adev = find_adev(gpu_id); | |
2696 | if (!adev) { | |
2697 | DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, | |
2698 | gpu_id); | |
2699 | return NOTIFY_DONE; | |
2700 | } | |
2701 | ||
2702 | /* | |
2703 | * If it is uncorrectable error, then find out UMC instance and | |
2704 | * channel index. | |
2705 | */ | |
2706 | umc_inst = GET_UMC_INST(m->ipid); | |
2707 | ch_inst = GET_CHAN_INDEX(m->ipid); | |
2708 | ||
2709 | dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", | |
2710 | umc_inst, ch_inst); | |
2711 | ||
12b2cab7 MJ |
2712 | /* |
2713 | * Translate UMC channel address to Physical address | |
2714 | */ | |
2715 | channel_index = | |
2716 | adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num | |
2717 | + ch_inst]; | |
2718 | ||
2719 | retired_page = ADDR_OF_8KB_BLOCK(m->addr) | | |
2720 | ADDR_OF_256B_BLOCK(channel_index) | | |
2721 | OFFSET_IN_256B_BLOCK(m->addr); | |
2722 | ||
400013b2 | 2723 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); |
12b2cab7 | 2724 | err_data.err_addr = &err_rec; |
400013b2 TZ |
2725 | amdgpu_umc_fill_error_record(&err_data, m->addr, |
2726 | retired_page, channel_index, umc_inst); | |
12b2cab7 MJ |
2727 | |
2728 | if (amdgpu_bad_page_threshold != 0) { | |
2729 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
2730 | err_data.err_addr_cnt); | |
2731 | amdgpu_ras_save_bad_pages(adev); | |
2732 | } | |
2733 | ||
2734 | return NOTIFY_OK; | |
2735 | } | |
2736 | ||
2737 | static struct notifier_block amdgpu_bad_page_nb = { | |
2738 | .notifier_call = amdgpu_bad_page_notifier, | |
2739 | .priority = MCE_PRIO_UC, | |
2740 | }; | |
2741 | ||
91a1a52d | 2742 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) |
12b2cab7 | 2743 | { |
91a1a52d MJ |
2744 | /* |
2745 | * Add the adev to the mce_adev_list. | |
2746 | * During mode2 reset, amdgpu device is temporarily | |
2747 | * removed from the mgpu_info list which can cause | |
2748 | * page retirement to fail. | |
2749 | * Use this list instead of mgpu_info to find the amdgpu | |
2750 | * device on which the UMC error was reported. | |
2751 | */ | |
2752 | mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; | |
2753 | ||
12b2cab7 MJ |
2754 | /* |
2755 | * Register the x86 notifier only once | |
2756 | * with MCE subsystem. | |
2757 | */ | |
2758 | if (notifier_registered == false) { | |
2759 | mce_register_decode_chain(&amdgpu_bad_page_nb); | |
2760 | notifier_registered = true; | |
2761 | } | |
2762 | } | |
2763 | #endif | |
7cab2124 | 2764 | |
b6efdb02 | 2765 | struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) |
7cab2124 | 2766 | { |
2767 | if (!adev) | |
2768 | return NULL; | |
2769 | ||
2770 | return adev->psp.ras_context.ras; | |
2771 | } | |
2772 | ||
b6efdb02 | 2773 | int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) |
7cab2124 | 2774 | { |
2775 | if (!adev) | |
69f91d32 | 2776 | return -EINVAL; |
7cab2124 | 2777 | |
2778 | adev->psp.ras_context.ras = ras_con; | |
2779 | return 0; | |
2780 | } | |
2781 | ||
2782 | /* check if ras is supported on block, say, sdma, gfx */ | |
2783 | int amdgpu_ras_is_supported(struct amdgpu_device *adev, | |
2784 | unsigned int block) | |
2785 | { | |
2786 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2787 | ||
2788 | if (block >= AMDGPU_RAS_BLOCK_COUNT) | |
2789 | return 0; | |
2790 | return ras && (adev->ras_enabled & (1 << block)); | |
2791 | } | |
2792 | ||
2793 | int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) | |
2794 | { | |
2795 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2796 | ||
2797 | if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) | |
2798 | schedule_work(&ras->recovery_work); | |
2799 | return 0; | |
2800 | } | |
2801 | ||
2802 | ||
6492e1b0 | 2803 | /* Register each ip ras block into amdgpu ras */ |
2804 | int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, | |
b6efdb02 | 2805 | struct amdgpu_ras_block_object *ras_block_obj) |
6492e1b0 | 2806 | { |
d5e8ff5f | 2807 | struct amdgpu_ras_block_list *ras_node; |
6492e1b0 | 2808 | if (!adev || !ras_block_obj) |
2809 | return -EINVAL; | |
2810 | ||
df01fe73 | 2811 | if (!amdgpu_ras_asic_supported(adev)) |
2812 | return 0; | |
2813 | ||
d5e8ff5f | 2814 | ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); |
2815 | if (!ras_node) | |
2816 | return -ENOMEM; | |
2817 | ||
2818 | INIT_LIST_HEAD(&ras_node->node); | |
2819 | ras_node->ras_obj = ras_block_obj; | |
2820 | list_add_tail(&ras_node->node, &adev->ras_list); | |
6492e1b0 | 2821 | |
2822 | return 0; | |
2823 | } |