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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
eb0c3cd4 GC |
37 | static const char *RAS_FS_NAME = "ras"; |
38 | ||
c030f2e4 | 39 | const char *ras_error_string[] = { |
40 | "none", | |
41 | "parity", | |
42 | "single_correctable", | |
43 | "multi_uncorrectable", | |
44 | "poison", | |
45 | }; | |
46 | ||
47 | const char *ras_block_string[] = { | |
48 | "umc", | |
49 | "sdma", | |
50 | "gfx", | |
51 | "mmhub", | |
52 | "athub", | |
53 | "pcie_bif", | |
54 | "hdp", | |
55 | "xgmi_wafl", | |
56 | "df", | |
57 | "smn", | |
58 | "sem", | |
59 | "mp0", | |
60 | "mp1", | |
61 | "fuse", | |
62 | }; | |
63 | ||
64 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
65 | #define ras_block_str(i) (ras_block_string[i]) | |
66 | ||
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
c84d4670 GC |
72 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
73 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
74 | ||
52dd95f2 GC |
75 | enum amdgpu_ras_retire_page_reservation { |
76 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
77 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
78 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
79 | }; | |
7c6e68c7 AG |
80 | |
81 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
82 | ||
676deb38 DL |
83 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
84 | uint64_t addr); | |
6e4be987 TZ |
85 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
86 | uint64_t addr); | |
87 | ||
61380faa JC |
88 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
89 | { | |
a9d82d2f | 90 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
91 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
92 | } | |
93 | ||
f3167919 | 94 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 95 | { |
a9d82d2f | 96 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
97 | return amdgpu_ras_get_context(adev)->error_query_ready; |
98 | ||
99 | return false; | |
100 | } | |
101 | ||
c030f2e4 | 102 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
103 | size_t size, loff_t *pos) | |
104 | { | |
105 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
106 | struct ras_query_if info = { | |
107 | .head = obj->head, | |
108 | }; | |
109 | ssize_t s; | |
110 | char val[128]; | |
111 | ||
761d86d3 | 112 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 113 | return -EINVAL; |
114 | ||
115 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
116 | "ue", info.ue_count, | |
117 | "ce", info.ce_count); | |
118 | if (*pos >= s) | |
119 | return 0; | |
120 | ||
121 | s -= *pos; | |
122 | s = min_t(u64, s, size); | |
123 | ||
124 | ||
125 | if (copy_to_user(buf, &val[*pos], s)) | |
126 | return -EINVAL; | |
127 | ||
128 | *pos += s; | |
129 | ||
130 | return s; | |
131 | } | |
132 | ||
c030f2e4 | 133 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
134 | .owner = THIS_MODULE, | |
135 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 136 | .write = NULL, |
c030f2e4 | 137 | .llseek = default_llseek |
138 | }; | |
139 | ||
96ebb307 | 140 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
141 | { | |
142 | int i; | |
143 | ||
144 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
145 | *block_id = i; | |
146 | if (strcmp(name, ras_block_str(i)) == 0) | |
147 | return 0; | |
148 | } | |
149 | return -EINVAL; | |
150 | } | |
151 | ||
152 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
153 | const char __user *buf, size_t size, | |
154 | loff_t *pos, struct ras_debug_if *data) | |
155 | { | |
156 | ssize_t s = min_t(u64, 64, size); | |
157 | char str[65]; | |
158 | char block_name[33]; | |
159 | char err[9] = "ue"; | |
160 | int op = -1; | |
161 | int block_id; | |
44494f96 | 162 | uint32_t sub_block; |
96ebb307 | 163 | u64 address, value; |
164 | ||
165 | if (*pos) | |
166 | return -EINVAL; | |
167 | *pos = size; | |
168 | ||
169 | memset(str, 0, sizeof(str)); | |
170 | memset(data, 0, sizeof(*data)); | |
171 | ||
172 | if (copy_from_user(str, buf, s)) | |
173 | return -EINVAL; | |
174 | ||
175 | if (sscanf(str, "disable %32s", block_name) == 1) | |
176 | op = 0; | |
177 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
178 | op = 1; | |
179 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
180 | op = 2; | |
b076296b | 181 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 182 | /* ascii string, but commands are not matched. */ |
183 | return -EINVAL; | |
184 | ||
185 | if (op != -1) { | |
186 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
187 | return -EINVAL; | |
188 | ||
189 | data->head.block = block_id; | |
e1063493 TZ |
190 | /* only ue and ce errors are supported */ |
191 | if (!memcmp("ue", err, 2)) | |
192 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
193 | else if (!memcmp("ce", err, 2)) | |
194 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
195 | else | |
196 | return -EINVAL; | |
197 | ||
96ebb307 | 198 | data->op = op; |
199 | ||
200 | if (op == 2) { | |
44494f96 TZ |
201 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
202 | &sub_block, &address, &value) != 3) | |
203 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
204 | &sub_block, &address, &value) != 3) | |
96ebb307 | 205 | return -EINVAL; |
44494f96 | 206 | data->head.sub_block_index = sub_block; |
96ebb307 | 207 | data->inject.address = address; |
208 | data->inject.value = value; | |
209 | } | |
210 | } else { | |
73aa8e1a | 211 | if (size < sizeof(*data)) |
96ebb307 | 212 | return -EINVAL; |
213 | ||
214 | if (copy_from_user(data, buf, sizeof(*data))) | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } | |
7c6e68c7 | 220 | |
74abc221 TSD |
221 | /** |
222 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 223 | * |
224 | * It accepts struct ras_debug_if who has two members. | |
225 | * | |
226 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 227 | * |
228 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 229 | * |
230 | * head has four members, they are block, type, sub_block_index, name. | |
231 | * block: which IP will be under control. | |
232 | * type: what kind of error will be enabled/disabled/injected. | |
233 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
234 | * name: the name of IP. | |
235 | * | |
236 | * inject has two more members than head, they are address, value. | |
237 | * As their names indicate, inject operation will write the | |
238 | * value to the address. | |
239 | * | |
ef177d11 | 240 | * The second member: struct ras_debug_if::op. |
c688a06b | 241 | * It has three kinds of operations. |
879e723d AZ |
242 | * |
243 | * - 0: disable RAS on the block. Take ::head as its data. | |
244 | * - 1: enable RAS on the block. Take ::head as its data. | |
245 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 246 | * |
96ebb307 | 247 | * How to use the interface? |
ef177d11 AD |
248 | * |
249 | * Programs | |
250 | * | |
251 | * Copy the struct ras_debug_if in your codes and initialize it. | |
252 | * Write the struct to the control node. | |
253 | * | |
254 | * Shells | |
96ebb307 | 255 | * |
879e723d AZ |
256 | * .. code-block:: bash |
257 | * | |
a20bfd0f | 258 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 259 | * |
ef177d11 AD |
260 | * Parameters: |
261 | * | |
879e723d AZ |
262 | * op: disable, enable, inject |
263 | * disable: only block is needed | |
264 | * enable: block and error are needed | |
265 | * inject: error, address, value are needed | |
a20bfd0f | 266 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
267 | * see ras_block_string[] for details |
268 | * error: ue, ce | |
269 | * ue: multi_uncorrectable | |
270 | * ce: single_correctable | |
271 | * sub_block: | |
272 | * sub block index, pass 0 if there is no sub block | |
273 | * | |
274 | * here are some examples for bash commands: | |
275 | * | |
276 | * .. code-block:: bash | |
96ebb307 | 277 | * |
44494f96 TZ |
278 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
279 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 280 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
281 | * | |
36ea1bd2 | 282 | * How to check the result? |
283 | * | |
284 | * For disable/enable, please check ras features at | |
285 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
286 | * | |
287 | * For inject, please check corresponding err count at | |
288 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
289 | * | |
879e723d | 290 | * .. note:: |
ef177d11 | 291 | * Operations are only allowed on blocks which are supported. |
879e723d | 292 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
293 | * to see which blocks support RAS on a particular asic. |
294 | * | |
36ea1bd2 | 295 | */ |
296 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
297 | size_t size, loff_t *pos) | |
298 | { | |
299 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
300 | struct ras_debug_if data; | |
301 | int ret = 0; | |
302 | ||
61380faa | 303 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
304 | dev_warn(adev->dev, "RAS WARN: error injection " |
305 | "currently inaccessible\n"); | |
43c4d576 JC |
306 | return size; |
307 | } | |
308 | ||
96ebb307 | 309 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
310 | if (ret) | |
36ea1bd2 | 311 | return -EINVAL; |
312 | ||
36ea1bd2 | 313 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
314 | return -EINVAL; | |
315 | ||
316 | switch (data.op) { | |
317 | case 0: | |
318 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
319 | break; | |
320 | case 1: | |
321 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
322 | break; | |
323 | case 2: | |
7cdc2ee3 TZ |
324 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
325 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
326 | dev_warn(adev->dev, "RAS WARN: input address " |
327 | "0x%llx is invalid.", | |
328 | data.inject.address); | |
7cdc2ee3 TZ |
329 | ret = -EINVAL; |
330 | break; | |
331 | } | |
332 | ||
6e4be987 TZ |
333 | /* umc ce/ue error injection for a bad page is not allowed */ |
334 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
335 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
336 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
337 | "as bad before error injection!\n", | |
6e4be987 TZ |
338 | data.inject.address); |
339 | break; | |
340 | } | |
341 | ||
7cdc2ee3 | 342 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 343 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
344 | break; | |
96ebb307 | 345 | default: |
346 | ret = -EINVAL; | |
347 | break; | |
374bf7bd | 348 | } |
36ea1bd2 | 349 | |
350 | if (ret) | |
351 | return -EINVAL; | |
352 | ||
353 | return size; | |
354 | } | |
355 | ||
084fe13b AG |
356 | /** |
357 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
358 | * | |
f77c7109 | 359 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 360 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
361 | * a way to reset the EEPROM, e.g., after testing error injection. |
362 | * | |
363 | * Usage: | |
364 | * | |
365 | * .. code-block:: bash | |
366 | * | |
367 | * echo 1 > ../ras/ras_eeprom_reset | |
368 | * | |
369 | * will reset EEPROM table to 0 entries. | |
370 | * | |
084fe13b AG |
371 | */ |
372 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
373 | size_t size, loff_t *pos) | |
374 | { | |
bf0b91b7 GC |
375 | struct amdgpu_device *adev = |
376 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
377 | int ret; |
378 | ||
bf0b91b7 GC |
379 | ret = amdgpu_ras_eeprom_reset_table( |
380 | &(amdgpu_ras_get_context(adev)->eeprom_control)); | |
084fe13b | 381 | |
bf0b91b7 GC |
382 | if (ret == 1) { |
383 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; | |
384 | return size; | |
385 | } else { | |
386 | return -EIO; | |
387 | } | |
084fe13b AG |
388 | } |
389 | ||
36ea1bd2 | 390 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
391 | .owner = THIS_MODULE, | |
392 | .read = NULL, | |
393 | .write = amdgpu_ras_debugfs_ctrl_write, | |
394 | .llseek = default_llseek | |
395 | }; | |
396 | ||
084fe13b AG |
397 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
398 | .owner = THIS_MODULE, | |
399 | .read = NULL, | |
400 | .write = amdgpu_ras_debugfs_eeprom_write, | |
401 | .llseek = default_llseek | |
402 | }; | |
403 | ||
f77c7109 AD |
404 | /** |
405 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
406 | * | |
ef177d11 | 407 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
408 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
409 | * | |
410 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
411 | * (ce) error counts. | |
412 | * | |
413 | * The format of one line is below, | |
414 | * | |
415 | * [ce|ue]: count | |
416 | * | |
417 | * Example: | |
418 | * | |
419 | * .. code-block:: bash | |
420 | * | |
421 | * ue: 0 | |
422 | * ce: 1 | |
423 | * | |
424 | */ | |
c030f2e4 | 425 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
426 | struct device_attribute *attr, char *buf) | |
427 | { | |
428 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
429 | struct ras_query_if info = { | |
430 | .head = obj->head, | |
431 | }; | |
432 | ||
61380faa | 433 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 434 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 435 | |
761d86d3 | 436 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 437 | return -EINVAL; |
438 | ||
36000c7a TT |
439 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
440 | "ce", info.ce_count); | |
c030f2e4 | 441 | } |
442 | ||
443 | /* obj begin */ | |
444 | ||
445 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
446 | #define alive_obj(obj) ((obj)->use) | |
447 | ||
448 | static inline void put_obj(struct ras_manager *obj) | |
449 | { | |
f0872686 | 450 | if (obj && (--obj->use == 0)) |
c030f2e4 | 451 | list_del(&obj->node); |
f0872686 BZ |
452 | if (obj && (obj->use < 0)) |
453 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
c030f2e4 | 454 | } |
455 | ||
456 | /* make one obj and return it. */ | |
457 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
458 | struct ras_common_if *head) | |
459 | { | |
460 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
461 | struct ras_manager *obj; | |
462 | ||
970fd197 | 463 | if (!adev->ras_features || !con) |
c030f2e4 | 464 | return NULL; |
465 | ||
466 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
467 | return NULL; | |
468 | ||
469 | obj = &con->objs[head->block]; | |
470 | /* already exist. return obj? */ | |
471 | if (alive_obj(obj)) | |
472 | return NULL; | |
473 | ||
474 | obj->head = *head; | |
475 | obj->adev = adev; | |
476 | list_add(&obj->node, &con->head); | |
477 | get_obj(obj); | |
478 | ||
479 | return obj; | |
480 | } | |
481 | ||
482 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 483 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 484 | struct ras_common_if *head) |
485 | { | |
486 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
487 | struct ras_manager *obj; | |
488 | int i; | |
489 | ||
970fd197 | 490 | if (!adev->ras_features || !con) |
c030f2e4 | 491 | return NULL; |
492 | ||
493 | if (head) { | |
494 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
495 | return NULL; | |
496 | ||
497 | obj = &con->objs[head->block]; | |
498 | ||
499 | if (alive_obj(obj)) { | |
500 | WARN_ON(head->block != obj->head.block); | |
501 | return obj; | |
502 | } | |
503 | } else { | |
504 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
505 | obj = &con->objs[i]; | |
506 | if (alive_obj(obj)) { | |
507 | WARN_ON(i != obj->head.block); | |
508 | return obj; | |
509 | } | |
510 | } | |
511 | } | |
512 | ||
513 | return NULL; | |
514 | } | |
515 | /* obj end */ | |
516 | ||
f3167919 | 517 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
f3729f7b DV |
518 | const char* invoke_type, |
519 | const char* block_name, | |
520 | enum ta_ras_status ret) | |
a200034b JC |
521 | { |
522 | switch (ret) { | |
523 | case TA_RAS_STATUS__SUCCESS: | |
524 | return; | |
525 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
526 | dev_warn(adev->dev, | |
527 | "RAS WARN: %s %s currently unavailable\n", | |
528 | invoke_type, | |
529 | block_name); | |
530 | break; | |
531 | default: | |
532 | dev_err(adev->dev, | |
533 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
534 | invoke_type, | |
535 | block_name, | |
536 | ret); | |
537 | } | |
538 | } | |
539 | ||
c030f2e4 | 540 | /* feature ctl begin */ |
541 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
542 | struct ras_common_if *head) | |
543 | { | |
5caf466a | 544 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
545 | ||
546 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 547 | } |
548 | ||
549 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
550 | struct ras_common_if *head) | |
551 | { | |
552 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
553 | ||
554 | return con->features & BIT(head->block); | |
555 | } | |
556 | ||
557 | /* | |
558 | * if obj is not created, then create one. | |
559 | * set feature enable flag. | |
560 | */ | |
561 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
562 | struct ras_common_if *head, int enable) | |
563 | { | |
564 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
565 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
566 | ||
5caf466a | 567 | /* If hardware does not support ras, then do not create obj. |
568 | * But if hardware support ras, we can create the obj. | |
569 | * Ras framework checks con->hw_supported to see if it need do | |
570 | * corresponding initialization. | |
571 | * IP checks con->support to see if it need disable ras. | |
572 | */ | |
c030f2e4 | 573 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
574 | return 0; | |
575 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
576 | return 0; | |
577 | ||
578 | if (enable) { | |
579 | if (!obj) { | |
580 | obj = amdgpu_ras_create_obj(adev, head); | |
581 | if (!obj) | |
582 | return -EINVAL; | |
583 | } else { | |
584 | /* In case we create obj somewhere else */ | |
585 | get_obj(obj); | |
586 | } | |
587 | con->features |= BIT(head->block); | |
588 | } else { | |
589 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
970fd197 SY |
590 | /* skip clean gfx ras context feature for VEGA20 Gaming. |
591 | * will clean later | |
592 | */ | |
593 | if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX))) | |
594 | con->features &= ~BIT(head->block); | |
c030f2e4 | 595 | put_obj(obj); |
596 | } | |
597 | } | |
598 | ||
599 | return 0; | |
600 | } | |
601 | ||
602 | /* wrapper of psp_ras_enable_features */ | |
603 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
604 | struct ras_common_if *head, bool enable) | |
605 | { | |
606 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 607 | union ta_ras_cmd_input *info; |
c030f2e4 | 608 | int ret; |
609 | ||
610 | if (!con) | |
611 | return -EINVAL; | |
612 | ||
f3729f7b | 613 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
614 | if (!info) |
615 | return -ENOMEM; | |
616 | ||
c030f2e4 | 617 | if (!enable) { |
7fcffecf | 618 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 619 | .block_id = amdgpu_ras_block_to_ta(head->block), |
620 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 621 | }; |
622 | } else { | |
7fcffecf | 623 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 624 | .block_id = amdgpu_ras_block_to_ta(head->block), |
625 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 626 | }; |
627 | } | |
628 | ||
629 | /* Do not enable if it is not allowed. */ | |
630 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
631 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
632 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
633 | ret = 0; | |
634 | goto out; | |
635 | } | |
c030f2e4 | 636 | |
bff77e86 | 637 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 638 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 639 | if (ret) { |
a200034b JC |
640 | amdgpu_ras_parse_status_code(adev, |
641 | enable ? "enable":"disable", | |
642 | ras_block_str(head->block), | |
643 | (enum ta_ras_status)ret); | |
bff77e86 | 644 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
645 | ret = -EAGAIN; |
646 | else | |
647 | ret = -EINVAL; | |
648 | ||
649 | goto out; | |
bff77e86 | 650 | } |
c030f2e4 | 651 | } |
652 | ||
653 | /* setup the obj */ | |
654 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
655 | ret = 0; |
656 | out: | |
657 | kfree(info); | |
658 | return ret; | |
c030f2e4 | 659 | } |
660 | ||
77de502b | 661 | /* Only used in device probe stage and called only once. */ |
662 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
663 | struct ras_common_if *head, bool enable) | |
664 | { | |
665 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
666 | int ret; | |
667 | ||
668 | if (!con) | |
669 | return -EINVAL; | |
670 | ||
671 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 672 | if (enable) { |
673 | /* There is no harm to issue a ras TA cmd regardless of | |
674 | * the currecnt ras state. | |
675 | * If current state == target state, it will do nothing | |
676 | * But sometimes it requests driver to reset and repost | |
677 | * with error code -EAGAIN. | |
678 | */ | |
679 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
680 | /* With old ras TA, we might fail to enable ras. | |
681 | * Log it and just setup the object. | |
682 | * TODO need remove this WA in the future. | |
683 | */ | |
684 | if (ret == -EINVAL) { | |
685 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
686 | if (!ret) | |
6952e99c GC |
687 | dev_info(adev->dev, |
688 | "RAS INFO: %s setup object\n", | |
7af23ebe | 689 | ras_block_str(head->block)); |
690 | } | |
691 | } else { | |
692 | /* setup the object then issue a ras TA disable cmd.*/ | |
693 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
694 | if (ret) | |
695 | return ret; | |
77de502b | 696 | |
970fd197 SY |
697 | /* gfx block ras dsiable cmd must send to ras-ta */ |
698 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
699 | con->features |= BIT(head->block); | |
700 | ||
77de502b | 701 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 702 | } |
77de502b | 703 | } else |
704 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
705 | ||
706 | return ret; | |
707 | } | |
708 | ||
c030f2e4 | 709 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
710 | bool bypass) | |
711 | { | |
712 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
713 | struct ras_manager *obj, *tmp; | |
714 | ||
715 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
716 | /* bypass psp. | |
717 | * aka just release the obj and corresponding flags | |
718 | */ | |
719 | if (bypass) { | |
720 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
721 | break; | |
722 | } else { | |
723 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
724 | break; | |
725 | } | |
289d513b | 726 | } |
c030f2e4 | 727 | |
728 | return con->features; | |
729 | } | |
730 | ||
731 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
732 | bool bypass) | |
733 | { | |
734 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
735 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
736 | int i; | |
191051a1 | 737 | const enum amdgpu_ras_error_type default_ras_type = |
738 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 739 | |
740 | for (i = 0; i < ras_block_count; i++) { | |
741 | struct ras_common_if head = { | |
742 | .block = i, | |
191051a1 | 743 | .type = default_ras_type, |
c030f2e4 | 744 | .sub_block_index = 0, |
745 | }; | |
746 | strcpy(head.name, ras_block_str(i)); | |
747 | if (bypass) { | |
748 | /* | |
749 | * bypass psp. vbios enable ras for us. | |
750 | * so just create the obj | |
751 | */ | |
752 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
753 | break; | |
754 | } else { | |
755 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
756 | break; | |
757 | } | |
289d513b | 758 | } |
c030f2e4 | 759 | |
760 | return con->features; | |
761 | } | |
762 | /* feature ctl end */ | |
763 | ||
764 | /* query/inject/cure begin */ | |
761d86d3 DL |
765 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
766 | struct ras_query_if *info) | |
c030f2e4 | 767 | { |
768 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 769 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 770 | int i; |
c030f2e4 | 771 | |
772 | if (!obj) | |
773 | return -EINVAL; | |
c030f2e4 | 774 | |
939e2258 HZ |
775 | switch (info->head.block) { |
776 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
777 | if (adev->umc.funcs->query_ras_error_count) |
778 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
779 | /* umc query_ras_error_address is also responsible for clearing |
780 | * error status | |
781 | */ | |
782 | if (adev->umc.funcs->query_ras_error_address) | |
783 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 784 | break; |
3e81ee9a HZ |
785 | case AMDGPU_RAS_BLOCK__SDMA: |
786 | if (adev->sdma.funcs->query_ras_error_count) { | |
787 | for (i = 0; i < adev->sdma.num_instances; i++) | |
788 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
789 | &err_data); | |
790 | } | |
791 | break; | |
83b0582c DL |
792 | case AMDGPU_RAS_BLOCK__GFX: |
793 | if (adev->gfx.funcs->query_ras_error_count) | |
794 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 DL |
795 | |
796 | if (adev->gfx.funcs->query_ras_error_status) | |
797 | adev->gfx.funcs->query_ras_error_status(adev); | |
83b0582c | 798 | break; |
9fb2d8de | 799 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
800 | if (adev->mmhub.funcs->query_ras_error_count) |
801 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 DL |
802 | |
803 | if (adev->mmhub.funcs->query_ras_error_status) | |
804 | adev->mmhub.funcs->query_ras_error_status(adev); | |
9fb2d8de | 805 | break; |
d7bd680d GC |
806 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
807 | if (adev->nbio.funcs->query_ras_error_count) | |
808 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
809 | break; | |
ec01fe2d HZ |
810 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
811 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
812 | break; | |
939e2258 HZ |
813 | default: |
814 | break; | |
815 | } | |
05a58345 TZ |
816 | |
817 | obj->err_data.ue_count += err_data.ue_count; | |
818 | obj->err_data.ce_count += err_data.ce_count; | |
819 | ||
c030f2e4 | 820 | info->ue_count = obj->err_data.ue_count; |
821 | info->ce_count = obj->err_data.ce_count; | |
822 | ||
7c6e68c7 | 823 | if (err_data.ce_count) { |
6952e99c GC |
824 | dev_info(adev->dev, "%ld correctable hardware errors " |
825 | "detected in %s block, no user " | |
826 | "action is needed.\n", | |
827 | obj->err_data.ce_count, | |
828 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
829 | } |
830 | if (err_data.ue_count) { | |
6952e99c GC |
831 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
832 | "detected in %s block\n", | |
833 | obj->err_data.ue_count, | |
834 | ras_block_str(info->head.block)); | |
7c6e68c7 | 835 | } |
05a58345 | 836 | |
c030f2e4 | 837 | return 0; |
838 | } | |
839 | ||
761d86d3 DL |
840 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
841 | enum amdgpu_ras_block block) | |
842 | { | |
843 | if (!amdgpu_ras_is_supported(adev, block)) | |
844 | return -EINVAL; | |
845 | ||
846 | switch (block) { | |
847 | case AMDGPU_RAS_BLOCK__GFX: | |
848 | if (adev->gfx.funcs->reset_ras_error_count) | |
849 | adev->gfx.funcs->reset_ras_error_count(adev); | |
850 | ||
851 | if (adev->gfx.funcs->reset_ras_error_status) | |
852 | adev->gfx.funcs->reset_ras_error_status(adev); | |
853 | break; | |
854 | case AMDGPU_RAS_BLOCK__MMHUB: | |
855 | if (adev->mmhub.funcs->reset_ras_error_count) | |
856 | adev->mmhub.funcs->reset_ras_error_count(adev); | |
857 | break; | |
858 | case AMDGPU_RAS_BLOCK__SDMA: | |
859 | if (adev->sdma.funcs->reset_ras_error_count) | |
860 | adev->sdma.funcs->reset_ras_error_count(adev); | |
861 | break; | |
862 | default: | |
863 | break; | |
864 | } | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
5c23e9e0 | 869 | /* Trigger XGMI/WAFL error */ |
f3167919 | 870 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
871 | struct ta_ras_trigger_error_input *block_info) |
872 | { | |
873 | int ret; | |
874 | ||
875 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
876 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
877 | ||
878 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
879 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
880 | ||
881 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
882 | ||
883 | if (amdgpu_ras_intr_triggered()) | |
884 | return ret; | |
885 | ||
886 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
887 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
888 | ||
fe2d9f5a | 889 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) |
5c23e9e0 JC |
890 | dev_warn(adev->dev, "Failed to allow df cstate"); |
891 | ||
892 | return ret; | |
893 | } | |
894 | ||
c030f2e4 | 895 | /* wrapper of psp_ras_trigger_error */ |
896 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
897 | struct ras_inject_if *info) | |
898 | { | |
899 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
900 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 901 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
902 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 903 | .sub_block_index = info->head.sub_block_index, |
904 | .address = info->address, | |
905 | .value = info->value, | |
906 | }; | |
907 | int ret = 0; | |
908 | ||
909 | if (!obj) | |
910 | return -EINVAL; | |
911 | ||
a6c44d25 JC |
912 | /* Calculate XGMI relative offset */ |
913 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
914 | block_info.address = |
915 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
916 | block_info.address); | |
a6c44d25 JC |
917 | } |
918 | ||
83b0582c DL |
919 | switch (info->head.block) { |
920 | case AMDGPU_RAS_BLOCK__GFX: | |
921 | if (adev->gfx.funcs->ras_error_inject) | |
922 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
923 | else | |
924 | ret = -EINVAL; | |
925 | break; | |
926 | case AMDGPU_RAS_BLOCK__UMC: | |
5a434527 | 927 | case AMDGPU_RAS_BLOCK__SDMA: |
9fb2d8de | 928 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 929 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
930 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
931 | break; | |
5c23e9e0 JC |
932 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
933 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
934 | break; | |
83b0582c | 935 | default: |
6952e99c | 936 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 937 | ras_block_str(info->head.block)); |
83b0582c | 938 | ret = -EINVAL; |
a5dd40ca HZ |
939 | } |
940 | ||
a200034b JC |
941 | amdgpu_ras_parse_status_code(adev, |
942 | "inject", | |
943 | ras_block_str(info->head.block), | |
944 | (enum ta_ras_status)ret); | |
c030f2e4 | 945 | |
946 | return ret; | |
947 | } | |
948 | ||
c030f2e4 | 949 | /* get the total error counts on all IPs */ |
64cc5414 | 950 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 951 | bool is_ce) |
952 | { | |
953 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
954 | struct ras_manager *obj; | |
955 | struct ras_err_data data = {0, 0}; | |
956 | ||
970fd197 | 957 | if (!adev->ras_features || !con) |
64cc5414 | 958 | return 0; |
c030f2e4 | 959 | |
960 | list_for_each_entry(obj, &con->head, node) { | |
961 | struct ras_query_if info = { | |
962 | .head = obj->head, | |
963 | }; | |
964 | ||
761d86d3 | 965 | if (amdgpu_ras_query_error_status(adev, &info)) |
64cc5414 | 966 | return 0; |
c030f2e4 | 967 | |
968 | data.ce_count += info.ce_count; | |
969 | data.ue_count += info.ue_count; | |
970 | } | |
971 | ||
972 | return is_ce ? data.ce_count : data.ue_count; | |
973 | } | |
974 | /* query/inject/cure end */ | |
975 | ||
976 | ||
977 | /* sysfs begin */ | |
978 | ||
466b1793 | 979 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
980 | struct ras_badpage **bps, unsigned int *count); | |
981 | ||
982 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
983 | { | |
984 | switch (flags) { | |
52dd95f2 | 985 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 986 | return "R"; |
52dd95f2 | 987 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 988 | return "P"; |
52dd95f2 | 989 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 990 | default: |
991 | return "F"; | |
aec576f9 | 992 | } |
466b1793 | 993 | } |
994 | ||
f77c7109 AD |
995 | /** |
996 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 997 | * |
998 | * It allows user to read the bad pages of vram on the gpu through | |
999 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1000 | * | |
1001 | * It outputs multiple lines, and each line stands for one gpu page. | |
1002 | * | |
1003 | * The format of one line is below, | |
1004 | * gpu pfn : gpu page size : flags | |
1005 | * | |
1006 | * gpu pfn and gpu page size are printed in hex format. | |
1007 | * flags can be one of below character, | |
f77c7109 | 1008 | * |
466b1793 | 1009 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1010 | * |
466b1793 | 1011 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1012 | * in next window of page_reserve. |
1013 | * | |
466b1793 | 1014 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1015 | * | |
f77c7109 AD |
1016 | * Examples: |
1017 | * | |
1018 | * .. code-block:: bash | |
1019 | * | |
1020 | * 0x00000001 : 0x00001000 : R | |
1021 | * 0x00000002 : 0x00001000 : P | |
1022 | * | |
466b1793 | 1023 | */ |
1024 | ||
1025 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1026 | struct kobject *kobj, struct bin_attribute *attr, | |
1027 | char *buf, loff_t ppos, size_t count) | |
1028 | { | |
1029 | struct amdgpu_ras *con = | |
1030 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1031 | struct amdgpu_device *adev = con->adev; | |
1032 | const unsigned int element_size = | |
1033 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1034 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1035 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1036 | ssize_t s = 0; |
1037 | struct ras_badpage *bps = NULL; | |
1038 | unsigned int bps_count = 0; | |
1039 | ||
1040 | memset(buf, 0, count); | |
1041 | ||
1042 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1043 | return 0; | |
1044 | ||
1045 | for (; start < end && start < bps_count; start++) | |
1046 | s += scnprintf(&buf[s], element_size + 1, | |
1047 | "0x%08x : 0x%08x : %1s\n", | |
1048 | bps[start].bp, | |
1049 | bps[start].size, | |
1050 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1051 | ||
1052 | kfree(bps); | |
1053 | ||
1054 | return s; | |
1055 | } | |
1056 | ||
c030f2e4 | 1057 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1058 | struct device_attribute *attr, char *buf) | |
1059 | { | |
1060 | struct amdgpu_ras *con = | |
1061 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1062 | |
5212a3bd | 1063 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1064 | } |
1065 | ||
f848159b GC |
1066 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1067 | { | |
1068 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1069 | ||
1070 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1071 | &con->badpages_attr.attr, | |
1072 | RAS_FS_NAME); | |
1073 | } | |
1074 | ||
c030f2e4 | 1075 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1076 | { | |
1077 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1078 | struct attribute *attrs[] = { | |
1079 | &con->features_attr.attr, | |
1080 | NULL | |
1081 | }; | |
1082 | struct attribute_group group = { | |
eb0c3cd4 | 1083 | .name = RAS_FS_NAME, |
c030f2e4 | 1084 | .attrs = attrs, |
1085 | }; | |
1086 | ||
1087 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1093 | struct ras_fs_if *head) | |
1094 | { | |
1095 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1096 | ||
1097 | if (!obj || obj->attr_inuse) | |
1098 | return -EINVAL; | |
1099 | ||
1100 | get_obj(obj); | |
1101 | ||
1102 | memcpy(obj->fs_data.sysfs_name, | |
1103 | head->sysfs_name, | |
1104 | sizeof(obj->fs_data.sysfs_name)); | |
1105 | ||
1106 | obj->sysfs_attr = (struct device_attribute){ | |
1107 | .attr = { | |
1108 | .name = obj->fs_data.sysfs_name, | |
1109 | .mode = S_IRUGO, | |
1110 | }, | |
1111 | .show = amdgpu_ras_sysfs_read, | |
1112 | }; | |
163def43 | 1113 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1114 | |
1115 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1116 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1117 | RAS_FS_NAME)) { |
c030f2e4 | 1118 | put_obj(obj); |
1119 | return -EINVAL; | |
1120 | } | |
1121 | ||
1122 | obj->attr_inuse = 1; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1128 | struct ras_common_if *head) | |
1129 | { | |
1130 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1131 | ||
1132 | if (!obj || !obj->attr_inuse) | |
1133 | return -EINVAL; | |
1134 | ||
1135 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1136 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1137 | RAS_FS_NAME); |
c030f2e4 | 1138 | obj->attr_inuse = 0; |
1139 | put_obj(obj); | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1145 | { | |
1146 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1147 | struct ras_manager *obj, *tmp; | |
1148 | ||
1149 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1150 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1151 | } | |
1152 | ||
f848159b GC |
1153 | if (amdgpu_bad_page_threshold != 0) |
1154 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1155 | ||
c030f2e4 | 1156 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | /* sysfs end */ | |
1161 | ||
ef177d11 AD |
1162 | /** |
1163 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1164 | * | |
1165 | * Normally when there is an uncorrectable error, the driver will reset | |
1166 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1167 | * the driver provides an interface to reboot the system automatically | |
1168 | * in that event. | |
1169 | * | |
1170 | * The following file in debugfs provides that interface: | |
1171 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1172 | * | |
1173 | * Usage: | |
1174 | * | |
1175 | * .. code-block:: bash | |
1176 | * | |
1177 | * echo true > .../ras/auto_reboot | |
1178 | * | |
1179 | */ | |
c030f2e4 | 1180 | /* debugfs begin */ |
ea1b8c9b | 1181 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1182 | { |
1183 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1184 | struct dentry *dir; |
4a580877 | 1185 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
36ea1bd2 | 1186 | |
88293c03 ND |
1187 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1188 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1189 | &amdgpu_ras_debugfs_ctrl_ops); | |
1190 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1191 | &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1192 | |
1193 | /* | |
1194 | * After one uncorrectable error happens, usually GPU recovery will | |
1195 | * be scheduled. But due to the known problem in GPU recovery failing | |
1196 | * to bring GPU back, below interface provides one direct way to | |
1197 | * user to reboot system automatically in such case within | |
1198 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1199 | * will never be called. | |
1200 | */ | |
88293c03 | 1201 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1202 | |
1203 | /* | |
1204 | * User could set this not to clean up hardware's error count register | |
1205 | * of RAS IPs during ras recovery. | |
1206 | */ | |
88293c03 ND |
1207 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1208 | &con->disable_ras_err_cnt_harvest); | |
1209 | return dir; | |
36ea1bd2 | 1210 | } |
1211 | ||
cedf7884 | 1212 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1213 | struct ras_fs_if *head, |
1214 | struct dentry *dir) | |
c030f2e4 | 1215 | { |
c030f2e4 | 1216 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1217 | |
88293c03 | 1218 | if (!obj || !dir) |
450f30ea | 1219 | return; |
c030f2e4 | 1220 | |
1221 | get_obj(obj); | |
1222 | ||
1223 | memcpy(obj->fs_data.debugfs_name, | |
1224 | head->debugfs_name, | |
1225 | sizeof(obj->fs_data.debugfs_name)); | |
1226 | ||
88293c03 ND |
1227 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1228 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1229 | } |
1230 | ||
f9317014 TZ |
1231 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1232 | { | |
1233 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1234 | struct dentry *dir; |
c1509f3f | 1235 | struct ras_manager *obj; |
f9317014 TZ |
1236 | struct ras_fs_if fs_info; |
1237 | ||
1238 | /* | |
1239 | * it won't be called in resume path, no need to check | |
1240 | * suspend and gpu reset status | |
1241 | */ | |
cedf7884 | 1242 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1243 | return; |
1244 | ||
88293c03 | 1245 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1246 | |
c1509f3f | 1247 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1248 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1249 | (obj->attr_inuse == 1)) { | |
1250 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1251 | ras_block_str(obj->head.block)); | |
1252 | fs_info.head = obj->head; | |
88293c03 | 1253 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1254 | } |
1255 | } | |
1256 | } | |
1257 | ||
c030f2e4 | 1258 | /* debugfs end */ |
1259 | ||
1260 | /* ras fs */ | |
c3d4d45d GC |
1261 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1262 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1263 | static DEVICE_ATTR(features, S_IRUGO, | |
1264 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1265 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1266 | { | |
c3d4d45d GC |
1267 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1268 | struct attribute_group group = { | |
1269 | .name = RAS_FS_NAME, | |
1270 | }; | |
1271 | struct attribute *attrs[] = { | |
1272 | &con->features_attr.attr, | |
1273 | NULL | |
1274 | }; | |
1275 | struct bin_attribute *bin_attrs[] = { | |
1276 | NULL, | |
1277 | NULL, | |
1278 | }; | |
a069a9eb | 1279 | int r; |
c030f2e4 | 1280 | |
c3d4d45d GC |
1281 | /* add features entry */ |
1282 | con->features_attr = dev_attr_features; | |
1283 | group.attrs = attrs; | |
1284 | sysfs_attr_init(attrs[0]); | |
1285 | ||
1286 | if (amdgpu_bad_page_threshold != 0) { | |
1287 | /* add bad_page_features entry */ | |
1288 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1289 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1290 | bin_attrs[0] = &con->badpages_attr; | |
1291 | group.bin_attrs = bin_attrs; | |
1292 | sysfs_bin_attr_init(bin_attrs[0]); | |
1293 | } | |
1294 | ||
a069a9eb AD |
1295 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1296 | if (r) | |
1297 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1298 | |
c030f2e4 | 1299 | return 0; |
1300 | } | |
1301 | ||
1302 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1303 | { | |
88293c03 ND |
1304 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1305 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1306 | ||
1307 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1308 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1309 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1310 | if (ip_obj) | |
1311 | put_obj(ip_obj); | |
1312 | } | |
1313 | } | |
1314 | ||
c030f2e4 | 1315 | amdgpu_ras_sysfs_remove_all(adev); |
1316 | return 0; | |
1317 | } | |
1318 | /* ras fs end */ | |
1319 | ||
1320 | /* ih begin */ | |
1321 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1322 | { | |
1323 | struct ras_ih_data *data = &obj->ih_data; | |
1324 | struct amdgpu_iv_entry entry; | |
1325 | int ret; | |
cf04dfd0 | 1326 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1327 | |
1328 | while (data->rptr != data->wptr) { | |
1329 | rmb(); | |
1330 | memcpy(&entry, &data->ring[data->rptr], | |
1331 | data->element_size); | |
1332 | ||
1333 | wmb(); | |
1334 | data->rptr = (data->aligned_element_size + | |
1335 | data->rptr) % data->ring_size; | |
1336 | ||
1337 | /* Let IP handle its data, maybe we need get the output | |
1338 | * from the callback to udpate the error type/count, etc | |
1339 | */ | |
1340 | if (data->cb) { | |
cf04dfd0 | 1341 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1342 | /* ue will trigger an interrupt, and in that case |
1343 | * we need do a reset to recovery the whole system. | |
1344 | * But leave IP do that recovery, here we just dispatch | |
1345 | * the error. | |
1346 | */ | |
bd2280da | 1347 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1348 | /* these counts could be left as 0 if |
1349 | * some blocks do not count error number | |
1350 | */ | |
cf04dfd0 | 1351 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1352 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1353 | } |
c030f2e4 | 1354 | } |
1355 | } | |
1356 | } | |
1357 | ||
1358 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1359 | { | |
1360 | struct ras_ih_data *data = | |
1361 | container_of(work, struct ras_ih_data, ih_work); | |
1362 | struct ras_manager *obj = | |
1363 | container_of(data, struct ras_manager, ih_data); | |
1364 | ||
1365 | amdgpu_ras_interrupt_handler(obj); | |
1366 | } | |
1367 | ||
1368 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1369 | struct ras_dispatch_if *info) | |
1370 | { | |
1371 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1372 | struct ras_ih_data *data = &obj->ih_data; | |
1373 | ||
1374 | if (!obj) | |
1375 | return -EINVAL; | |
1376 | ||
1377 | if (data->inuse == 0) | |
1378 | return 0; | |
1379 | ||
1380 | /* Might be overflow... */ | |
1381 | memcpy(&data->ring[data->wptr], info->entry, | |
1382 | data->element_size); | |
1383 | ||
1384 | wmb(); | |
1385 | data->wptr = (data->aligned_element_size + | |
1386 | data->wptr) % data->ring_size; | |
1387 | ||
1388 | schedule_work(&data->ih_work); | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
1393 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1394 | struct ras_ih_if *info) | |
1395 | { | |
1396 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1397 | struct ras_ih_data *data; | |
1398 | ||
1399 | if (!obj) | |
1400 | return -EINVAL; | |
1401 | ||
1402 | data = &obj->ih_data; | |
1403 | if (data->inuse == 0) | |
1404 | return 0; | |
1405 | ||
1406 | cancel_work_sync(&data->ih_work); | |
1407 | ||
1408 | kfree(data->ring); | |
1409 | memset(data, 0, sizeof(*data)); | |
1410 | put_obj(obj); | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | ||
1415 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1416 | struct ras_ih_if *info) | |
1417 | { | |
1418 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1419 | struct ras_ih_data *data; | |
1420 | ||
1421 | if (!obj) { | |
1422 | /* in case we registe the IH before enable ras feature */ | |
1423 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1424 | if (!obj) | |
1425 | return -EINVAL; | |
1426 | } else | |
1427 | get_obj(obj); | |
1428 | ||
1429 | data = &obj->ih_data; | |
1430 | /* add the callback.etc */ | |
1431 | *data = (struct ras_ih_data) { | |
1432 | .inuse = 0, | |
1433 | .cb = info->cb, | |
1434 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1435 | .rptr = 0, | |
1436 | .wptr = 0, | |
1437 | }; | |
1438 | ||
1439 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1440 | ||
1441 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1442 | /* the ring can store 64 iv entries. */ | |
1443 | data->ring_size = 64 * data->aligned_element_size; | |
1444 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1445 | if (!data->ring) { | |
1446 | put_obj(obj); | |
1447 | return -ENOMEM; | |
1448 | } | |
1449 | ||
1450 | /* IH is ready */ | |
1451 | data->inuse = 1; | |
1452 | ||
1453 | return 0; | |
1454 | } | |
1455 | ||
1456 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1457 | { | |
1458 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1459 | struct ras_manager *obj, *tmp; | |
1460 | ||
1461 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1462 | struct ras_ih_if info = { | |
1463 | .head = obj->head, | |
1464 | }; | |
1465 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1466 | } | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | /* ih end */ | |
1471 | ||
313c8fd3 GC |
1472 | /* traversal all IPs except NBIO to query error counter */ |
1473 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1474 | { | |
1475 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1476 | struct ras_manager *obj; | |
1477 | ||
970fd197 | 1478 | if (!adev->ras_features || !con) |
313c8fd3 GC |
1479 | return; |
1480 | ||
1481 | list_for_each_entry(obj, &con->head, node) { | |
1482 | struct ras_query_if info = { | |
1483 | .head = obj->head, | |
1484 | }; | |
1485 | ||
1486 | /* | |
1487 | * PCIE_BIF IP has one different isr by ras controller | |
1488 | * interrupt, the specific ras counter query will be | |
1489 | * done in that isr. So skip such block from common | |
1490 | * sync flood interrupt isr calling. | |
1491 | */ | |
1492 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1493 | continue; | |
1494 | ||
761d86d3 | 1495 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1496 | } |
1497 | } | |
1498 | ||
3f975d0f | 1499 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1500 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1501 | struct ras_query_if *info) | |
3f975d0f SY |
1502 | { |
1503 | /* | |
1504 | * Only two block need to query read/write | |
1505 | * RspStatus at current state | |
1506 | */ | |
1507 | switch (info->head.block) { | |
1508 | case AMDGPU_RAS_BLOCK__GFX: | |
1509 | if (adev->gfx.funcs->query_ras_error_status) | |
1510 | adev->gfx.funcs->query_ras_error_status(adev); | |
1511 | break; | |
1512 | case AMDGPU_RAS_BLOCK__MMHUB: | |
1513 | if (adev->mmhub.funcs->query_ras_error_status) | |
1514 | adev->mmhub.funcs->query_ras_error_status(adev); | |
1515 | break; | |
1516 | default: | |
1517 | break; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1522 | { | |
1523 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1524 | struct ras_manager *obj; | |
1525 | ||
970fd197 | 1526 | if (!adev->ras_features || !con) |
3f975d0f SY |
1527 | return; |
1528 | ||
1529 | list_for_each_entry(obj, &con->head, node) { | |
1530 | struct ras_query_if info = { | |
1531 | .head = obj->head, | |
1532 | }; | |
1533 | ||
1534 | amdgpu_ras_error_status_query(adev, &info); | |
1535 | } | |
1536 | } | |
1537 | ||
c030f2e4 | 1538 | /* recovery begin */ |
466b1793 | 1539 | |
1540 | /* return 0 on success. | |
1541 | * caller need free bps. | |
1542 | */ | |
1543 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1544 | struct ras_badpage **bps, unsigned int *count) | |
1545 | { | |
1546 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1547 | struct ras_err_handler_data *data; | |
1548 | int i = 0; | |
732f2a30 | 1549 | int ret = 0, status; |
466b1793 | 1550 | |
1551 | if (!con || !con->eh_data || !bps || !count) | |
1552 | return -EINVAL; | |
1553 | ||
1554 | mutex_lock(&con->recovery_lock); | |
1555 | data = con->eh_data; | |
1556 | if (!data || data->count == 0) { | |
1557 | *bps = NULL; | |
46cf2fec | 1558 | ret = -EINVAL; |
466b1793 | 1559 | goto out; |
1560 | } | |
1561 | ||
1562 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1563 | if (!*bps) { | |
1564 | ret = -ENOMEM; | |
1565 | goto out; | |
1566 | } | |
1567 | ||
1568 | for (; i < data->count; i++) { | |
1569 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1570 | .bp = data->bps[i].retired_page, |
466b1793 | 1571 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1572 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1573 | }; |
732f2a30 | 1574 | status = amdgpu_vram_mgr_query_page_status( |
676deb38 DL |
1575 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), |
1576 | data->bps[i].retired_page); | |
732f2a30 | 1577 | if (status == -EBUSY) |
52dd95f2 | 1578 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1579 | else if (status == -ENOENT) |
52dd95f2 | 1580 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1581 | } |
1582 | ||
1583 | *count = data->count; | |
1584 | out: | |
1585 | mutex_unlock(&con->recovery_lock); | |
1586 | return ret; | |
1587 | } | |
1588 | ||
c030f2e4 | 1589 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1590 | { | |
1591 | struct amdgpu_ras *ras = | |
1592 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1593 | struct amdgpu_device *remote_adev = NULL; |
1594 | struct amdgpu_device *adev = ras->adev; | |
1595 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1596 | |
f75e94d8 | 1597 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1598 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1599 | ||
f75e94d8 GC |
1600 | /* Build list of devices to query RAS related errors */ |
1601 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1602 | device_list_handle = &hive->device_list; | |
1603 | } else { | |
1604 | INIT_LIST_HEAD(&device_list); | |
1605 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1606 | device_list_handle = &device_list; | |
1607 | } | |
c030f2e4 | 1608 | |
f75e94d8 | 1609 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1610 | device_list_handle, gmc.xgmi.head) { |
1611 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1612 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1613 | } |
d95e8e97 DL |
1614 | |
1615 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1616 | } |
313c8fd3 | 1617 | |
93af20f7 | 1618 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1619 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1620 | atomic_set(&ras->in_recovery, 0); |
1621 | } | |
1622 | ||
c030f2e4 | 1623 | /* alloc/realloc bps array */ |
1624 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1625 | struct ras_err_handler_data *data, int pages) | |
1626 | { | |
1627 | unsigned int old_space = data->count + data->space_left; | |
1628 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1629 | unsigned int align_space = ALIGN(new_space, 512); |
1630 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1631 | |
676deb38 | 1632 | if (!bps) { |
9dc23a63 | 1633 | kfree(bps); |
c030f2e4 | 1634 | return -ENOMEM; |
9dc23a63 | 1635 | } |
c030f2e4 | 1636 | |
1637 | if (data->bps) { | |
9dc23a63 | 1638 | memcpy(bps, data->bps, |
c030f2e4 | 1639 | data->count * sizeof(*data->bps)); |
1640 | kfree(data->bps); | |
1641 | } | |
1642 | ||
9dc23a63 | 1643 | data->bps = bps; |
c030f2e4 | 1644 | data->space_left += align_space - old_space; |
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | /* it deal with vram only. */ | |
1649 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1650 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1651 | { |
1652 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1653 | struct ras_err_handler_data *data; |
c030f2e4 | 1654 | int ret = 0; |
676deb38 | 1655 | uint32_t i; |
c030f2e4 | 1656 | |
73aa8e1a | 1657 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1658 | return 0; |
1659 | ||
1660 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1661 | data = con->eh_data; |
c030f2e4 | 1662 | if (!data) |
1663 | goto out; | |
1664 | ||
676deb38 DL |
1665 | for (i = 0; i < pages; i++) { |
1666 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1667 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1668 | continue; | |
1669 | ||
1670 | if (!data->space_left && | |
1671 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1672 | ret = -ENOMEM; |
1673 | goto out; | |
1674 | } | |
1675 | ||
676deb38 DL |
1676 | amdgpu_vram_mgr_reserve_range( |
1677 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1678 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1679 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1680 | |
676deb38 DL |
1681 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1682 | data->count++; | |
1683 | data->space_left--; | |
1684 | } | |
c030f2e4 | 1685 | out: |
1686 | mutex_unlock(&con->recovery_lock); | |
1687 | ||
1688 | return ret; | |
1689 | } | |
1690 | ||
78ad00c9 TZ |
1691 | /* |
1692 | * write error record array to eeprom, the function should be | |
1693 | * protected by recovery_lock | |
1694 | */ | |
22503d80 | 1695 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1696 | { |
1697 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1698 | struct ras_err_handler_data *data; | |
8a3e801f | 1699 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1700 | int save_count; |
1701 | ||
1702 | if (!con || !con->eh_data) | |
1703 | return 0; | |
1704 | ||
8a3e801f | 1705 | control = &con->eeprom_control; |
78ad00c9 TZ |
1706 | data = con->eh_data; |
1707 | save_count = data->count - control->num_recs; | |
1708 | /* only new entries are saved */ | |
b1628425 | 1709 | if (save_count > 0) { |
0771b0bf | 1710 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1711 | &data->bps[control->num_recs], |
1712 | true, | |
1713 | save_count)) { | |
6952e99c | 1714 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1715 | return -EIO; |
1716 | } | |
1717 | ||
b1628425 GC |
1718 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1719 | } | |
1720 | ||
78ad00c9 TZ |
1721 | return 0; |
1722 | } | |
1723 | ||
1724 | /* | |
1725 | * read error record array in eeprom and reserve enough space for | |
1726 | * storing new bad pages | |
1727 | */ | |
1728 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1729 | { | |
1730 | struct amdgpu_ras_eeprom_control *control = | |
1731 | &adev->psp.ras.ras->eeprom_control; | |
1732 | struct eeprom_table_record *bps = NULL; | |
1733 | int ret = 0; | |
1734 | ||
1735 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1736 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1737 | return ret; |
1738 | ||
1739 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1740 | if (!bps) | |
1741 | return -ENOMEM; | |
1742 | ||
1743 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1744 | control->num_recs)) { | |
6952e99c | 1745 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1746 | ret = -EIO; |
1747 | goto out; | |
1748 | } | |
1749 | ||
1750 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1751 | ||
1752 | out: | |
1753 | kfree(bps); | |
1754 | return ret; | |
1755 | } | |
1756 | ||
676deb38 DL |
1757 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1758 | uint64_t addr) | |
1759 | { | |
1760 | struct ras_err_handler_data *data = con->eh_data; | |
1761 | int i; | |
1762 | ||
1763 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1764 | for (i = 0; i < data->count; i++) | |
1765 | if (addr == data->bps[i].retired_page) | |
1766 | return true; | |
1767 | ||
1768 | return false; | |
1769 | } | |
1770 | ||
6e4be987 TZ |
1771 | /* |
1772 | * check if an address belongs to bad page | |
1773 | * | |
1774 | * Note: this check is only for umc block | |
1775 | */ | |
1776 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1777 | uint64_t addr) | |
1778 | { | |
1779 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1780 | bool ret = false; |
1781 | ||
1782 | if (!con || !con->eh_data) | |
1783 | return ret; | |
1784 | ||
1785 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1786 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1787 | mutex_unlock(&con->recovery_lock); |
1788 | return ret; | |
1789 | } | |
1790 | ||
e5c04edf CK |
1791 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1792 | uint32_t max_length) | |
c84d4670 | 1793 | { |
e5c04edf | 1794 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
1795 | int tmp_threshold = amdgpu_bad_page_threshold; |
1796 | u64 val; | |
1797 | ||
1798 | /* | |
1799 | * Justification of value bad_page_cnt_threshold in ras structure | |
1800 | * | |
1801 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1802 | * in eeprom, and introduce two scenarios accordingly. | |
1803 | * | |
1804 | * Bad page retirement enablement: | |
1805 | * - If amdgpu_bad_page_threshold = -1, | |
1806 | * bad_page_cnt_threshold = typical value by formula. | |
1807 | * | |
1808 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1809 | * max record length in eeprom, use it directly. | |
1810 | * | |
1811 | * Bad page retirement disablement: | |
1812 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1813 | * functionality is disabled, and bad_page_cnt_threshold will | |
1814 | * take no effect. | |
1815 | */ | |
1816 | ||
1817 | if (tmp_threshold < -1) | |
1818 | tmp_threshold = -1; | |
1819 | else if (tmp_threshold > max_length) | |
1820 | tmp_threshold = max_length; | |
1821 | ||
1822 | if (tmp_threshold == -1) { | |
e5c04edf | 1823 | val = adev->gmc.mc_vram_size; |
c84d4670 | 1824 | do_div(val, RAS_BAD_PAGE_RATE); |
e5c04edf CK |
1825 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
1826 | max_length); | |
1827 | } else { | |
1828 | con->bad_page_cnt_threshold = tmp_threshold; | |
c84d4670 GC |
1829 | } |
1830 | } | |
1831 | ||
1a6fc071 | 1832 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1833 | { |
1834 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1835 | struct ras_err_handler_data **data; |
e5c04edf | 1836 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1837 | bool exc_err_limit = false; |
78ad00c9 | 1838 | int ret; |
c030f2e4 | 1839 | |
970fd197 | 1840 | if (adev->ras_features && con) |
4d1337d2 AG |
1841 | data = &con->eh_data; |
1842 | else | |
1843 | return 0; | |
1844 | ||
1a6fc071 TZ |
1845 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1846 | if (!*data) { | |
1847 | ret = -ENOMEM; | |
1848 | goto out; | |
1849 | } | |
c030f2e4 | 1850 | |
1851 | mutex_init(&con->recovery_lock); | |
1852 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1853 | atomic_set(&con->in_recovery, 0); | |
1854 | con->adev = adev; | |
1855 | ||
e5c04edf CK |
1856 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1857 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
c84d4670 | 1858 | |
e5086659 | 1859 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
1860 | * when the GPU is pending on XGMI reset during probe time | |
1861 | * (Mostly after second bus reset), skip it now | |
1862 | */ | |
1863 | if (adev->gmc.xgmi.pending_reset) | |
1864 | return 0; | |
b82e65a9 GC |
1865 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1866 | /* | |
1867 | * This calling fails when exc_err_limit is true or | |
1868 | * ret != 0. | |
1869 | */ | |
1870 | if (exc_err_limit || ret) | |
1a6fc071 | 1871 | goto free; |
78ad00c9 | 1872 | |
0771b0bf | 1873 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1874 | ret = amdgpu_ras_load_bad_pages(adev); |
1875 | if (ret) | |
1a6fc071 | 1876 | goto free; |
78ad00c9 | 1877 | } |
c030f2e4 | 1878 | |
1879 | return 0; | |
1a6fc071 | 1880 | |
1a6fc071 | 1881 | free: |
1a6fc071 | 1882 | kfree((*data)->bps); |
1a6fc071 | 1883 | kfree(*data); |
1995b3a3 | 1884 | con->eh_data = NULL; |
1a6fc071 | 1885 | out: |
6952e99c | 1886 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1887 | |
b82e65a9 GC |
1888 | /* |
1889 | * Except error threshold exceeding case, other failure cases in this | |
1890 | * function would not fail amdgpu driver init. | |
1891 | */ | |
1892 | if (!exc_err_limit) | |
1893 | ret = 0; | |
1894 | else | |
1895 | ret = -EINVAL; | |
1896 | ||
1a6fc071 | 1897 | return ret; |
c030f2e4 | 1898 | } |
1899 | ||
1900 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1901 | { | |
1902 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1903 | struct ras_err_handler_data *data = con->eh_data; | |
1904 | ||
1a6fc071 TZ |
1905 | /* recovery_init failed to init it, fini is useless */ |
1906 | if (!data) | |
1907 | return 0; | |
1908 | ||
c030f2e4 | 1909 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1910 | |
1911 | mutex_lock(&con->recovery_lock); | |
1912 | con->eh_data = NULL; | |
1913 | kfree(data->bps); | |
1914 | kfree(data); | |
1915 | mutex_unlock(&con->recovery_lock); | |
1916 | ||
1917 | return 0; | |
1918 | } | |
1919 | /* recovery end */ | |
1920 | ||
a564808e | 1921 | /* return 0 if ras will reset gpu and repost.*/ |
1922 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1923 | unsigned int block) | |
1924 | { | |
1925 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1926 | ||
1927 | if (!ras) | |
1928 | return -EINVAL; | |
1929 | ||
1930 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1931 | return 0; | |
1932 | } | |
1933 | ||
084e2640 | 1934 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 1935 | { |
084e2640 LT |
1936 | return adev->asic_type == CHIP_VEGA10 || |
1937 | adev->asic_type == CHIP_VEGA20 || | |
1938 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 1939 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 1940 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
1941 | } |
1942 | ||
5caf466a | 1943 | /* |
1944 | * check hardware's ras ability which will be saved in hw_supported. | |
1945 | * if hardware does not support ras, we can skip some ras initializtion and | |
1946 | * forbid some ras operations from IP. | |
1947 | * if software itself, say boot parameter, limit the ras ability. We still | |
1948 | * need allow IP do some limited operations, like disable. In such case, | |
1949 | * we have to initialize ras as normal. but need check if operation is | |
1950 | * allowed or not in each function. | |
1951 | */ | |
1952 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1953 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1954 | { |
5caf466a | 1955 | *hw_supported = 0; |
1956 | *supported = 0; | |
c030f2e4 | 1957 | |
88474cca | 1958 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 1959 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 1960 | return; |
b404ae82 | 1961 | |
75f06251 HZ |
1962 | if (!adev->gmc.xgmi.connected_to_cpu) { |
1963 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
1964 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
1965 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | | |
1966 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1967 | } else { | |
1968 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
1969 | } | |
88474cca | 1970 | |
75f06251 HZ |
1971 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
1972 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
1973 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | | |
1974 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1975 | } else { | |
1976 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
1977 | } | |
1978 | } else { | |
1979 | /* driver only manages a few IP blocks RAS feature | |
1980 | * when GPU is connected cpu through XGMI */ | |
1981 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX | | |
1982 | 1 << AMDGPU_RAS_BLOCK__SDMA | | |
1983 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
1984 | } | |
88474cca GC |
1985 | |
1986 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1987 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1988 | |
5caf466a | 1989 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1990 | 0 : *hw_supported & amdgpu_ras_mask; |
5436ab94 | 1991 | adev->ras_features = *supported; |
c030f2e4 | 1992 | } |
1993 | ||
1994 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1995 | { | |
1996 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1997 | int r; |
c030f2e4 | 1998 | |
b404ae82 | 1999 | if (con) |
c030f2e4 | 2000 | return 0; |
2001 | ||
2002 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
2003 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
2004 | GFP_KERNEL|__GFP_ZERO); | |
2005 | if (!con) | |
2006 | return -ENOMEM; | |
2007 | ||
2008 | con->objs = (struct ras_manager *)(con + 1); | |
2009 | ||
2010 | amdgpu_ras_set_context(adev, con); | |
2011 | ||
5caf466a | 2012 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
2013 | &con->supported); | |
5436ab94 | 2014 | if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) { |
970fd197 SY |
2015 | /* set gfx block ras context feature for VEGA20 Gaming |
2016 | * send ras disable cmd to ras ta during ras late init. | |
2017 | */ | |
2018 | if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) { | |
2019 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); | |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
5e91160a | 2024 | r = 0; |
5436ab94 | 2025 | goto release_con; |
fb2a3607 HZ |
2026 | } |
2027 | ||
c030f2e4 | 2028 | con->features = 0; |
2029 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2030 | /* Might need get this flag from vbios. */ |
2031 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2032 | |
4e644fff HZ |
2033 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
2034 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
2035 | if (r) | |
5436ab94 | 2036 | goto release_con; |
4e644fff HZ |
2037 | } |
2038 | ||
2039 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
2040 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
2041 | if (r) | |
5436ab94 | 2042 | goto release_con; |
4e644fff HZ |
2043 | } |
2044 | ||
5e91160a GC |
2045 | if (amdgpu_ras_fs_init(adev)) { |
2046 | r = -EINVAL; | |
5436ab94 | 2047 | goto release_con; |
5e91160a | 2048 | } |
c030f2e4 | 2049 | |
6952e99c | 2050 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 2051 | "hardware ability[%x] ras_mask[%x]\n", |
2052 | con->hw_supported, con->supported); | |
c030f2e4 | 2053 | return 0; |
5436ab94 | 2054 | release_con: |
c030f2e4 | 2055 | amdgpu_ras_set_context(adev, NULL); |
2056 | kfree(con); | |
2057 | ||
5e91160a | 2058 | return r; |
c030f2e4 | 2059 | } |
2060 | ||
b293e891 HZ |
2061 | /* helper function to handle common stuff in ip late init phase */ |
2062 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2063 | struct ras_common_if *ras_block, | |
2064 | struct ras_fs_if *fs_info, | |
2065 | struct ras_ih_if *ih_info) | |
2066 | { | |
2067 | int r; | |
2068 | ||
2069 | /* disable RAS feature per IP block if it is not supported */ | |
2070 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2071 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2072 | return 0; | |
2073 | } | |
2074 | ||
2075 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2076 | if (r) { | |
2077 | if (r == -EAGAIN) { | |
2078 | /* request gpu reset. will run again */ | |
2079 | amdgpu_ras_request_reset_on_boot(adev, | |
2080 | ras_block->block); | |
2081 | return 0; | |
53b3f8f4 | 2082 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2083 | /* in resume phase, if fail to enable ras, |
2084 | * clean up all ras fs nodes, and disable ras */ | |
2085 | goto cleanup; | |
2086 | } else | |
2087 | return r; | |
2088 | } | |
2089 | ||
2090 | /* in resume phase, no need to create ras fs node */ | |
53b3f8f4 | 2091 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2092 | return 0; |
2093 | ||
2094 | if (ih_info->cb) { | |
2095 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2096 | if (r) | |
2097 | goto interrupt; | |
2098 | } | |
2099 | ||
b293e891 HZ |
2100 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2101 | if (r) | |
2102 | goto sysfs; | |
2103 | ||
2104 | return 0; | |
2105 | cleanup: | |
2106 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2107 | sysfs: | |
b293e891 HZ |
2108 | if (ih_info->cb) |
2109 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2110 | interrupt: | |
2111 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2112 | return r; | |
2113 | } | |
2114 | ||
2115 | /* helper function to remove ras fs node and interrupt handler */ | |
2116 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2117 | struct ras_common_if *ras_block, | |
2118 | struct ras_ih_if *ih_info) | |
2119 | { | |
2120 | if (!ras_block || !ih_info) | |
2121 | return; | |
2122 | ||
2123 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2124 | if (ih_info->cb) |
f3729f7b | 2125 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2126 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2127 | } | |
2128 | ||
a564808e | 2129 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2130 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2131 | */ |
511fdbc3 | 2132 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2133 | { |
2134 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2135 | struct ras_manager *obj, *tmp; | |
2136 | ||
970fd197 SY |
2137 | if (!adev->ras_features || !con) { |
2138 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ | |
2139 | amdgpu_release_ras_context(adev); | |
2140 | ||
108c6a63 | 2141 | return; |
970fd197 | 2142 | } |
108c6a63 | 2143 | |
108c6a63 | 2144 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2145 | /* Set up all other IPs which are not implemented. There is a |
2146 | * tricky thing that IP's actual ras error type should be | |
2147 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2148 | * ERROR_NONE make sense anyway. | |
2149 | */ | |
2150 | amdgpu_ras_enable_all_features(adev, 1); | |
2151 | ||
2152 | /* We enable ras on all hw_supported block, but as boot | |
2153 | * parameter might disable some of them and one or more IP has | |
2154 | * not implemented yet. So we disable them on behalf. | |
2155 | */ | |
108c6a63 | 2156 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2157 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2158 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2159 | /* there should be no any reference. */ | |
2160 | WARN_ON(alive_obj(obj)); | |
2161 | } | |
191051a1 | 2162 | } |
108c6a63 | 2163 | } |
a564808e | 2164 | |
2165 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2166 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2167 | /* setup ras obj state as disabled. | |
2168 | * for init_by_vbios case. | |
2169 | * if we want to enable ras, just enable it in a normal way. | |
2170 | * If we want do disable it, need setup ras obj as enabled, | |
2171 | * then issue another TA disable cmd. | |
2172 | * See feature_enable_on_boot | |
2173 | */ | |
2174 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2175 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2176 | } |
108c6a63 | 2177 | } |
2178 | ||
511fdbc3 | 2179 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2180 | { | |
2181 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2182 | ||
970fd197 | 2183 | if (!adev->ras_features || !con) |
511fdbc3 | 2184 | return; |
2185 | ||
2186 | amdgpu_ras_disable_all_features(adev, 0); | |
2187 | /* Make sure all ras objects are disabled. */ | |
2188 | if (con->features) | |
2189 | amdgpu_ras_disable_all_features(adev, 1); | |
2190 | } | |
2191 | ||
c030f2e4 | 2192 | /* do some fini work before IP fini as dependence */ |
2193 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2194 | { | |
2195 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2196 | ||
970fd197 | 2197 | if (!adev->ras_features || !con) |
c030f2e4 | 2198 | return 0; |
2199 | ||
2200 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2201 | amdgpu_ras_disable_all_features(adev, 0); | |
2202 | amdgpu_ras_recovery_fini(adev); | |
2203 | return 0; | |
2204 | } | |
2205 | ||
2206 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2207 | { | |
2208 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2209 | ||
970fd197 | 2210 | if (!adev->ras_features || !con) |
c030f2e4 | 2211 | return 0; |
2212 | ||
2213 | amdgpu_ras_fs_fini(adev); | |
2214 | amdgpu_ras_interrupt_remove_all(adev); | |
2215 | ||
2216 | WARN(con->features, "Feature mask is not cleared"); | |
2217 | ||
2218 | if (con->features) | |
2219 | amdgpu_ras_disable_all_features(adev, 1); | |
2220 | ||
2221 | amdgpu_ras_set_context(adev, NULL); | |
2222 | kfree(con); | |
2223 | ||
2224 | return 0; | |
2225 | } | |
7c6e68c7 AG |
2226 | |
2227 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2228 | { | |
ed606f8a AG |
2229 | uint32_t hw_supported, supported; |
2230 | ||
2231 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2232 | if (!hw_supported) | |
2233 | return; | |
2234 | ||
7c6e68c7 | 2235 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2236 | dev_info(adev->dev, "uncorrectable hardware error" |
2237 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2238 | |
61934624 | 2239 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2240 | } |
2241 | } | |
bb5c7235 WS |
2242 | |
2243 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2244 | { | |
2245 | if (adev->asic_type == CHIP_VEGA20 && | |
2246 | adev->pm.fw_version <= 0x283400) { | |
2247 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2248 | amdgpu_ras_intr_triggered(); | |
2249 | } | |
2250 | ||
2251 | return false; | |
2252 | } | |
970fd197 SY |
2253 | |
2254 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2255 | { | |
2256 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2257 | ||
2258 | if (!con) | |
2259 | return; | |
2260 | ||
2261 | if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { | |
2262 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); | |
2263 | amdgpu_ras_set_context(adev, NULL); | |
2264 | kfree(con); | |
2265 | } | |
2266 | } |