Commit | Line | Data |
---|---|---|
c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
eb0c3cd4 GC |
37 | static const char *RAS_FS_NAME = "ras"; |
38 | ||
c030f2e4 | 39 | const char *ras_error_string[] = { |
40 | "none", | |
41 | "parity", | |
42 | "single_correctable", | |
43 | "multi_uncorrectable", | |
44 | "poison", | |
45 | }; | |
46 | ||
47 | const char *ras_block_string[] = { | |
48 | "umc", | |
49 | "sdma", | |
50 | "gfx", | |
51 | "mmhub", | |
52 | "athub", | |
53 | "pcie_bif", | |
54 | "hdp", | |
55 | "xgmi_wafl", | |
56 | "df", | |
57 | "smn", | |
58 | "sem", | |
59 | "mp0", | |
60 | "mp1", | |
61 | "fuse", | |
62 | }; | |
63 | ||
64 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
65 | #define ras_block_str(i) (ras_block_string[i]) | |
66 | ||
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
c84d4670 GC |
72 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
73 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
74 | ||
52dd95f2 GC |
75 | enum amdgpu_ras_retire_page_reservation { |
76 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
77 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
78 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
79 | }; | |
7c6e68c7 AG |
80 | |
81 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
82 | ||
676deb38 DL |
83 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
84 | uint64_t addr); | |
6e4be987 TZ |
85 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
86 | uint64_t addr); | |
87 | ||
61380faa JC |
88 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
89 | { | |
a9d82d2f | 90 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
91 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
92 | } | |
93 | ||
f3167919 | 94 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 95 | { |
a9d82d2f | 96 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
97 | return amdgpu_ras_get_context(adev)->error_query_ready; |
98 | ||
99 | return false; | |
100 | } | |
101 | ||
cbb8f989 JC |
102 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
103 | { | |
104 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
105 | struct eeprom_table_record err_rec; | |
106 | ||
107 | if ((address >= adev->gmc.mc_vram_size) || | |
108 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
109 | dev_warn(adev->dev, | |
110 | "RAS WARN: input address 0x%llx is invalid.\n", | |
111 | address); | |
112 | return -EINVAL; | |
113 | } | |
114 | ||
115 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
116 | dev_warn(adev->dev, | |
80b0cd0f | 117 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
118 | address); |
119 | return 0; | |
120 | } | |
121 | ||
122 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
123 | ||
124 | err_rec.address = address; | |
125 | err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT; | |
126 | err_rec.ts = (uint64_t)ktime_get_real_seconds(); | |
127 | err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; | |
128 | ||
129 | err_data.err_addr = &err_rec; | |
130 | err_data.err_addr_cnt = 1; | |
131 | ||
132 | if (amdgpu_bad_page_threshold != 0) { | |
133 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
134 | err_data.err_addr_cnt); | |
135 | amdgpu_ras_save_bad_pages(adev); | |
136 | } | |
137 | ||
138 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
139 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
140 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
141 | ||
142 | return 0; | |
143 | } | |
144 | ||
c030f2e4 | 145 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
146 | size_t size, loff_t *pos) | |
147 | { | |
148 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
149 | struct ras_query_if info = { | |
150 | .head = obj->head, | |
151 | }; | |
152 | ssize_t s; | |
153 | char val[128]; | |
154 | ||
761d86d3 | 155 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 156 | return -EINVAL; |
157 | ||
158 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
159 | "ue", info.ue_count, | |
160 | "ce", info.ce_count); | |
161 | if (*pos >= s) | |
162 | return 0; | |
163 | ||
164 | s -= *pos; | |
165 | s = min_t(u64, s, size); | |
166 | ||
167 | ||
168 | if (copy_to_user(buf, &val[*pos], s)) | |
169 | return -EINVAL; | |
170 | ||
171 | *pos += s; | |
172 | ||
173 | return s; | |
174 | } | |
175 | ||
c030f2e4 | 176 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
177 | .owner = THIS_MODULE, | |
178 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 179 | .write = NULL, |
c030f2e4 | 180 | .llseek = default_llseek |
181 | }; | |
182 | ||
96ebb307 | 183 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
184 | { | |
185 | int i; | |
186 | ||
187 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
188 | *block_id = i; | |
189 | if (strcmp(name, ras_block_str(i)) == 0) | |
190 | return 0; | |
191 | } | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
195 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
196 | const char __user *buf, size_t size, | |
197 | loff_t *pos, struct ras_debug_if *data) | |
198 | { | |
199 | ssize_t s = min_t(u64, 64, size); | |
200 | char str[65]; | |
201 | char block_name[33]; | |
202 | char err[9] = "ue"; | |
203 | int op = -1; | |
204 | int block_id; | |
44494f96 | 205 | uint32_t sub_block; |
96ebb307 | 206 | u64 address, value; |
207 | ||
208 | if (*pos) | |
209 | return -EINVAL; | |
210 | *pos = size; | |
211 | ||
212 | memset(str, 0, sizeof(str)); | |
213 | memset(data, 0, sizeof(*data)); | |
214 | ||
215 | if (copy_from_user(str, buf, s)) | |
216 | return -EINVAL; | |
217 | ||
218 | if (sscanf(str, "disable %32s", block_name) == 1) | |
219 | op = 0; | |
220 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
221 | op = 1; | |
222 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
223 | op = 2; | |
cbb8f989 JC |
224 | else if (sscanf(str, "retire_page") == 0) |
225 | op = 3; | |
b076296b | 226 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 227 | /* ascii string, but commands are not matched. */ |
228 | return -EINVAL; | |
229 | ||
230 | if (op != -1) { | |
cbb8f989 | 231 | if (op == 3) { |
6cb7a1d4 LT |
232 | if (sscanf(str, "%*s %llx", &address) != 1) |
233 | return -EINVAL; | |
cbb8f989 JC |
234 | |
235 | data->op = op; | |
236 | data->inject.address = address; | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
96ebb307 | 241 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
242 | return -EINVAL; | |
243 | ||
244 | data->head.block = block_id; | |
e1063493 TZ |
245 | /* only ue and ce errors are supported */ |
246 | if (!memcmp("ue", err, 2)) | |
247 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
248 | else if (!memcmp("ce", err, 2)) | |
249 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
250 | else | |
251 | return -EINVAL; | |
252 | ||
96ebb307 | 253 | data->op = op; |
254 | ||
255 | if (op == 2) { | |
6cb7a1d4 LT |
256 | if (sscanf(str, "%*s %*s %*s %x %llx %llx", |
257 | &sub_block, &address, &value) != 3) | |
258 | return -EINVAL; | |
44494f96 | 259 | data->head.sub_block_index = sub_block; |
96ebb307 | 260 | data->inject.address = address; |
261 | data->inject.value = value; | |
262 | } | |
263 | } else { | |
73aa8e1a | 264 | if (size < sizeof(*data)) |
96ebb307 | 265 | return -EINVAL; |
266 | ||
267 | if (copy_from_user(data, buf, sizeof(*data))) | |
268 | return -EINVAL; | |
269 | } | |
270 | ||
271 | return 0; | |
272 | } | |
7c6e68c7 | 273 | |
74abc221 TSD |
274 | /** |
275 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 276 | * |
277 | * It accepts struct ras_debug_if who has two members. | |
278 | * | |
279 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 280 | * |
281 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 282 | * |
283 | * head has four members, they are block, type, sub_block_index, name. | |
284 | * block: which IP will be under control. | |
285 | * type: what kind of error will be enabled/disabled/injected. | |
286 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
287 | * name: the name of IP. | |
288 | * | |
289 | * inject has two more members than head, they are address, value. | |
290 | * As their names indicate, inject operation will write the | |
291 | * value to the address. | |
292 | * | |
ef177d11 | 293 | * The second member: struct ras_debug_if::op. |
c688a06b | 294 | * It has three kinds of operations. |
879e723d AZ |
295 | * |
296 | * - 0: disable RAS on the block. Take ::head as its data. | |
297 | * - 1: enable RAS on the block. Take ::head as its data. | |
298 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 299 | * |
96ebb307 | 300 | * How to use the interface? |
ef177d11 AD |
301 | * |
302 | * Programs | |
303 | * | |
304 | * Copy the struct ras_debug_if in your codes and initialize it. | |
305 | * Write the struct to the control node. | |
306 | * | |
307 | * Shells | |
96ebb307 | 308 | * |
879e723d AZ |
309 | * .. code-block:: bash |
310 | * | |
a20bfd0f | 311 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 312 | * |
ef177d11 AD |
313 | * Parameters: |
314 | * | |
879e723d AZ |
315 | * op: disable, enable, inject |
316 | * disable: only block is needed | |
317 | * enable: block and error are needed | |
318 | * inject: error, address, value are needed | |
a20bfd0f | 319 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
320 | * see ras_block_string[] for details |
321 | * error: ue, ce | |
322 | * ue: multi_uncorrectable | |
323 | * ce: single_correctable | |
324 | * sub_block: | |
325 | * sub block index, pass 0 if there is no sub block | |
326 | * | |
327 | * here are some examples for bash commands: | |
328 | * | |
329 | * .. code-block:: bash | |
96ebb307 | 330 | * |
44494f96 TZ |
331 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
332 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 333 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
334 | * | |
36ea1bd2 | 335 | * How to check the result? |
336 | * | |
337 | * For disable/enable, please check ras features at | |
338 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
339 | * | |
340 | * For inject, please check corresponding err count at | |
341 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
342 | * | |
879e723d | 343 | * .. note:: |
ef177d11 | 344 | * Operations are only allowed on blocks which are supported. |
879e723d | 345 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
346 | * to see which blocks support RAS on a particular asic. |
347 | * | |
36ea1bd2 | 348 | */ |
349 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
350 | size_t size, loff_t *pos) | |
351 | { | |
352 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
353 | struct ras_debug_if data; | |
354 | int ret = 0; | |
355 | ||
61380faa | 356 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
357 | dev_warn(adev->dev, "RAS WARN: error injection " |
358 | "currently inaccessible\n"); | |
43c4d576 JC |
359 | return size; |
360 | } | |
361 | ||
96ebb307 | 362 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
363 | if (ret) | |
36ea1bd2 | 364 | return -EINVAL; |
365 | ||
80b0cd0f | 366 | if (data.op == 3) { |
cbb8f989 | 367 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 368 | if (!ret) |
cbb8f989 JC |
369 | return size; |
370 | else | |
371 | return ret; | |
372 | } | |
373 | ||
36ea1bd2 | 374 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
375 | return -EINVAL; | |
376 | ||
377 | switch (data.op) { | |
378 | case 0: | |
379 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
380 | break; | |
381 | case 1: | |
382 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
383 | break; | |
384 | case 2: | |
7cdc2ee3 TZ |
385 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
386 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
387 | dev_warn(adev->dev, "RAS WARN: input address " |
388 | "0x%llx is invalid.", | |
389 | data.inject.address); | |
7cdc2ee3 TZ |
390 | ret = -EINVAL; |
391 | break; | |
392 | } | |
393 | ||
6e4be987 TZ |
394 | /* umc ce/ue error injection for a bad page is not allowed */ |
395 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
396 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
397 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
398 | "as bad before error injection!\n", | |
6e4be987 TZ |
399 | data.inject.address); |
400 | break; | |
401 | } | |
402 | ||
7cdc2ee3 | 403 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 404 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
405 | break; | |
96ebb307 | 406 | default: |
407 | ret = -EINVAL; | |
408 | break; | |
374bf7bd | 409 | } |
36ea1bd2 | 410 | |
411 | if (ret) | |
412 | return -EINVAL; | |
413 | ||
414 | return size; | |
415 | } | |
416 | ||
084fe13b AG |
417 | /** |
418 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
419 | * | |
f77c7109 | 420 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 421 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
422 | * a way to reset the EEPROM, e.g., after testing error injection. |
423 | * | |
424 | * Usage: | |
425 | * | |
426 | * .. code-block:: bash | |
427 | * | |
428 | * echo 1 > ../ras/ras_eeprom_reset | |
429 | * | |
430 | * will reset EEPROM table to 0 entries. | |
431 | * | |
084fe13b AG |
432 | */ |
433 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
434 | size_t size, loff_t *pos) | |
435 | { | |
bf0b91b7 GC |
436 | struct amdgpu_device *adev = |
437 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
438 | int ret; |
439 | ||
bf0b91b7 GC |
440 | ret = amdgpu_ras_eeprom_reset_table( |
441 | &(amdgpu_ras_get_context(adev)->eeprom_control)); | |
084fe13b | 442 | |
bf0b91b7 GC |
443 | if (ret == 1) { |
444 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; | |
445 | return size; | |
446 | } else { | |
447 | return -EIO; | |
448 | } | |
084fe13b AG |
449 | } |
450 | ||
36ea1bd2 | 451 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
452 | .owner = THIS_MODULE, | |
453 | .read = NULL, | |
454 | .write = amdgpu_ras_debugfs_ctrl_write, | |
455 | .llseek = default_llseek | |
456 | }; | |
457 | ||
084fe13b AG |
458 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
459 | .owner = THIS_MODULE, | |
460 | .read = NULL, | |
461 | .write = amdgpu_ras_debugfs_eeprom_write, | |
462 | .llseek = default_llseek | |
463 | }; | |
464 | ||
f77c7109 AD |
465 | /** |
466 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
467 | * | |
ef177d11 | 468 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
469 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
470 | * | |
471 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
472 | * (ce) error counts. | |
473 | * | |
474 | * The format of one line is below, | |
475 | * | |
476 | * [ce|ue]: count | |
477 | * | |
478 | * Example: | |
479 | * | |
480 | * .. code-block:: bash | |
481 | * | |
482 | * ue: 0 | |
483 | * ce: 1 | |
484 | * | |
485 | */ | |
c030f2e4 | 486 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
487 | struct device_attribute *attr, char *buf) | |
488 | { | |
489 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
490 | struct ras_query_if info = { | |
491 | .head = obj->head, | |
492 | }; | |
493 | ||
61380faa | 494 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 495 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 496 | |
761d86d3 | 497 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 498 | return -EINVAL; |
499 | ||
36000c7a TT |
500 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
501 | "ce", info.ce_count); | |
c030f2e4 | 502 | } |
503 | ||
504 | /* obj begin */ | |
505 | ||
506 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
507 | #define alive_obj(obj) ((obj)->use) | |
508 | ||
509 | static inline void put_obj(struct ras_manager *obj) | |
510 | { | |
f0872686 | 511 | if (obj && (--obj->use == 0)) |
c030f2e4 | 512 | list_del(&obj->node); |
f0872686 BZ |
513 | if (obj && (obj->use < 0)) |
514 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
c030f2e4 | 515 | } |
516 | ||
517 | /* make one obj and return it. */ | |
518 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
519 | struct ras_common_if *head) | |
520 | { | |
521 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
522 | struct ras_manager *obj; | |
523 | ||
970fd197 | 524 | if (!adev->ras_features || !con) |
c030f2e4 | 525 | return NULL; |
526 | ||
527 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
528 | return NULL; | |
529 | ||
530 | obj = &con->objs[head->block]; | |
531 | /* already exist. return obj? */ | |
532 | if (alive_obj(obj)) | |
533 | return NULL; | |
534 | ||
535 | obj->head = *head; | |
536 | obj->adev = adev; | |
537 | list_add(&obj->node, &con->head); | |
538 | get_obj(obj); | |
539 | ||
540 | return obj; | |
541 | } | |
542 | ||
543 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 544 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 545 | struct ras_common_if *head) |
546 | { | |
547 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
548 | struct ras_manager *obj; | |
549 | int i; | |
550 | ||
970fd197 | 551 | if (!adev->ras_features || !con) |
c030f2e4 | 552 | return NULL; |
553 | ||
554 | if (head) { | |
555 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
556 | return NULL; | |
557 | ||
558 | obj = &con->objs[head->block]; | |
559 | ||
560 | if (alive_obj(obj)) { | |
561 | WARN_ON(head->block != obj->head.block); | |
562 | return obj; | |
563 | } | |
564 | } else { | |
565 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
566 | obj = &con->objs[i]; | |
567 | if (alive_obj(obj)) { | |
568 | WARN_ON(i != obj->head.block); | |
569 | return obj; | |
570 | } | |
571 | } | |
572 | } | |
573 | ||
574 | return NULL; | |
575 | } | |
576 | /* obj end */ | |
577 | ||
f3167919 | 578 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
f3729f7b DV |
579 | const char* invoke_type, |
580 | const char* block_name, | |
581 | enum ta_ras_status ret) | |
a200034b JC |
582 | { |
583 | switch (ret) { | |
584 | case TA_RAS_STATUS__SUCCESS: | |
585 | return; | |
586 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
587 | dev_warn(adev->dev, | |
588 | "RAS WARN: %s %s currently unavailable\n", | |
589 | invoke_type, | |
590 | block_name); | |
591 | break; | |
592 | default: | |
593 | dev_err(adev->dev, | |
594 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
595 | invoke_type, | |
596 | block_name, | |
597 | ret); | |
598 | } | |
599 | } | |
600 | ||
c030f2e4 | 601 | /* feature ctl begin */ |
602 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
603 | struct ras_common_if *head) | |
604 | { | |
5caf466a | 605 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
606 | ||
607 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 608 | } |
609 | ||
610 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
611 | struct ras_common_if *head) | |
612 | { | |
613 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
614 | ||
615 | return con->features & BIT(head->block); | |
616 | } | |
617 | ||
618 | /* | |
619 | * if obj is not created, then create one. | |
620 | * set feature enable flag. | |
621 | */ | |
622 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
623 | struct ras_common_if *head, int enable) | |
624 | { | |
625 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
626 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
627 | ||
5caf466a | 628 | /* If hardware does not support ras, then do not create obj. |
629 | * But if hardware support ras, we can create the obj. | |
630 | * Ras framework checks con->hw_supported to see if it need do | |
631 | * corresponding initialization. | |
632 | * IP checks con->support to see if it need disable ras. | |
633 | */ | |
c030f2e4 | 634 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
635 | return 0; | |
636 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
637 | return 0; | |
638 | ||
639 | if (enable) { | |
640 | if (!obj) { | |
641 | obj = amdgpu_ras_create_obj(adev, head); | |
642 | if (!obj) | |
643 | return -EINVAL; | |
644 | } else { | |
645 | /* In case we create obj somewhere else */ | |
646 | get_obj(obj); | |
647 | } | |
648 | con->features |= BIT(head->block); | |
649 | } else { | |
650 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
970fd197 SY |
651 | /* skip clean gfx ras context feature for VEGA20 Gaming. |
652 | * will clean later | |
653 | */ | |
654 | if (!(!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX))) | |
655 | con->features &= ~BIT(head->block); | |
c030f2e4 | 656 | put_obj(obj); |
657 | } | |
658 | } | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | /* wrapper of psp_ras_enable_features */ | |
664 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
665 | struct ras_common_if *head, bool enable) | |
666 | { | |
667 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 668 | union ta_ras_cmd_input *info; |
c030f2e4 | 669 | int ret; |
670 | ||
671 | if (!con) | |
672 | return -EINVAL; | |
673 | ||
f3729f7b | 674 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
675 | if (!info) |
676 | return -ENOMEM; | |
677 | ||
c030f2e4 | 678 | if (!enable) { |
7fcffecf | 679 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 680 | .block_id = amdgpu_ras_block_to_ta(head->block), |
681 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 682 | }; |
683 | } else { | |
7fcffecf | 684 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 685 | .block_id = amdgpu_ras_block_to_ta(head->block), |
686 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 687 | }; |
688 | } | |
689 | ||
690 | /* Do not enable if it is not allowed. */ | |
691 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
692 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
693 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
694 | ret = 0; | |
695 | goto out; | |
696 | } | |
c030f2e4 | 697 | |
bff77e86 | 698 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 699 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 700 | if (ret) { |
a200034b JC |
701 | amdgpu_ras_parse_status_code(adev, |
702 | enable ? "enable":"disable", | |
703 | ras_block_str(head->block), | |
704 | (enum ta_ras_status)ret); | |
bff77e86 | 705 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
706 | ret = -EAGAIN; |
707 | else | |
708 | ret = -EINVAL; | |
709 | ||
710 | goto out; | |
bff77e86 | 711 | } |
c030f2e4 | 712 | } |
713 | ||
714 | /* setup the obj */ | |
715 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
716 | ret = 0; |
717 | out: | |
718 | kfree(info); | |
719 | return ret; | |
c030f2e4 | 720 | } |
721 | ||
77de502b | 722 | /* Only used in device probe stage and called only once. */ |
723 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
724 | struct ras_common_if *head, bool enable) | |
725 | { | |
726 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
727 | int ret; | |
728 | ||
729 | if (!con) | |
730 | return -EINVAL; | |
731 | ||
732 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 733 | if (enable) { |
734 | /* There is no harm to issue a ras TA cmd regardless of | |
735 | * the currecnt ras state. | |
736 | * If current state == target state, it will do nothing | |
737 | * But sometimes it requests driver to reset and repost | |
738 | * with error code -EAGAIN. | |
739 | */ | |
740 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
741 | /* With old ras TA, we might fail to enable ras. | |
742 | * Log it and just setup the object. | |
743 | * TODO need remove this WA in the future. | |
744 | */ | |
745 | if (ret == -EINVAL) { | |
746 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
747 | if (!ret) | |
6952e99c GC |
748 | dev_info(adev->dev, |
749 | "RAS INFO: %s setup object\n", | |
7af23ebe | 750 | ras_block_str(head->block)); |
751 | } | |
752 | } else { | |
753 | /* setup the object then issue a ras TA disable cmd.*/ | |
754 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
755 | if (ret) | |
756 | return ret; | |
77de502b | 757 | |
970fd197 SY |
758 | /* gfx block ras dsiable cmd must send to ras-ta */ |
759 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
760 | con->features |= BIT(head->block); | |
761 | ||
77de502b | 762 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 763 | } |
77de502b | 764 | } else |
765 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
766 | ||
767 | return ret; | |
768 | } | |
769 | ||
c030f2e4 | 770 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
771 | bool bypass) | |
772 | { | |
773 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
774 | struct ras_manager *obj, *tmp; | |
775 | ||
776 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
777 | /* bypass psp. | |
778 | * aka just release the obj and corresponding flags | |
779 | */ | |
780 | if (bypass) { | |
781 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
782 | break; | |
783 | } else { | |
784 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
785 | break; | |
786 | } | |
289d513b | 787 | } |
c030f2e4 | 788 | |
789 | return con->features; | |
790 | } | |
791 | ||
792 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
793 | bool bypass) | |
794 | { | |
795 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
796 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
797 | int i; | |
191051a1 | 798 | const enum amdgpu_ras_error_type default_ras_type = |
799 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 800 | |
801 | for (i = 0; i < ras_block_count; i++) { | |
802 | struct ras_common_if head = { | |
803 | .block = i, | |
191051a1 | 804 | .type = default_ras_type, |
c030f2e4 | 805 | .sub_block_index = 0, |
806 | }; | |
807 | strcpy(head.name, ras_block_str(i)); | |
808 | if (bypass) { | |
809 | /* | |
810 | * bypass psp. vbios enable ras for us. | |
811 | * so just create the obj | |
812 | */ | |
813 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
814 | break; | |
815 | } else { | |
816 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
817 | break; | |
818 | } | |
289d513b | 819 | } |
c030f2e4 | 820 | |
821 | return con->features; | |
822 | } | |
823 | /* feature ctl end */ | |
824 | ||
825 | /* query/inject/cure begin */ | |
761d86d3 DL |
826 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
827 | struct ras_query_if *info) | |
c030f2e4 | 828 | { |
829 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 830 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 831 | int i; |
c030f2e4 | 832 | |
833 | if (!obj) | |
834 | return -EINVAL; | |
c030f2e4 | 835 | |
939e2258 HZ |
836 | switch (info->head.block) { |
837 | case AMDGPU_RAS_BLOCK__UMC: | |
49070c4e HZ |
838 | if (adev->umc.ras_funcs && |
839 | adev->umc.ras_funcs->query_ras_error_count) | |
840 | adev->umc.ras_funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
841 | /* umc query_ras_error_address is also responsible for clearing |
842 | * error status | |
843 | */ | |
49070c4e HZ |
844 | if (adev->umc.ras_funcs && |
845 | adev->umc.ras_funcs->query_ras_error_address) | |
846 | adev->umc.ras_funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 847 | break; |
3e81ee9a HZ |
848 | case AMDGPU_RAS_BLOCK__SDMA: |
849 | if (adev->sdma.funcs->query_ras_error_count) { | |
850 | for (i = 0; i < adev->sdma.num_instances; i++) | |
851 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
852 | &err_data); | |
853 | } | |
854 | break; | |
83b0582c | 855 | case AMDGPU_RAS_BLOCK__GFX: |
719a9b33 HZ |
856 | if (adev->gfx.ras_funcs && |
857 | adev->gfx.ras_funcs->query_ras_error_count) | |
858 | adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 859 | |
719a9b33 HZ |
860 | if (adev->gfx.ras_funcs && |
861 | adev->gfx.ras_funcs->query_ras_error_status) | |
862 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
83b0582c | 863 | break; |
9fb2d8de | 864 | case AMDGPU_RAS_BLOCK__MMHUB: |
8bc7b360 HZ |
865 | if (adev->mmhub.ras_funcs && |
866 | adev->mmhub.ras_funcs->query_ras_error_count) | |
867 | adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 868 | |
8bc7b360 HZ |
869 | if (adev->mmhub.ras_funcs && |
870 | adev->mmhub.ras_funcs->query_ras_error_status) | |
871 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
9fb2d8de | 872 | break; |
d7bd680d | 873 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
6e36f231 HZ |
874 | if (adev->nbio.ras_funcs && |
875 | adev->nbio.ras_funcs->query_ras_error_count) | |
876 | adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data); | |
d7bd680d | 877 | break; |
ec01fe2d | 878 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
52137ca8 HZ |
879 | if (adev->gmc.xgmi.ras_funcs && |
880 | adev->gmc.xgmi.ras_funcs->query_ras_error_count) | |
881 | adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data); | |
ec01fe2d | 882 | break; |
939e2258 HZ |
883 | default: |
884 | break; | |
885 | } | |
05a58345 TZ |
886 | |
887 | obj->err_data.ue_count += err_data.ue_count; | |
888 | obj->err_data.ce_count += err_data.ce_count; | |
889 | ||
c030f2e4 | 890 | info->ue_count = obj->err_data.ue_count; |
891 | info->ce_count = obj->err_data.ce_count; | |
892 | ||
7c6e68c7 | 893 | if (err_data.ce_count) { |
6952e99c GC |
894 | dev_info(adev->dev, "%ld correctable hardware errors " |
895 | "detected in %s block, no user " | |
896 | "action is needed.\n", | |
897 | obj->err_data.ce_count, | |
898 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
899 | } |
900 | if (err_data.ue_count) { | |
6952e99c GC |
901 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
902 | "detected in %s block\n", | |
903 | obj->err_data.ue_count, | |
904 | ras_block_str(info->head.block)); | |
7c6e68c7 | 905 | } |
05a58345 | 906 | |
c030f2e4 | 907 | return 0; |
908 | } | |
909 | ||
761d86d3 DL |
910 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
911 | enum amdgpu_ras_block block) | |
912 | { | |
913 | if (!amdgpu_ras_is_supported(adev, block)) | |
914 | return -EINVAL; | |
915 | ||
916 | switch (block) { | |
917 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
918 | if (adev->gfx.ras_funcs && |
919 | adev->gfx.ras_funcs->reset_ras_error_count) | |
920 | adev->gfx.ras_funcs->reset_ras_error_count(adev); | |
761d86d3 | 921 | |
719a9b33 HZ |
922 | if (adev->gfx.ras_funcs && |
923 | adev->gfx.ras_funcs->reset_ras_error_status) | |
924 | adev->gfx.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
925 | break; |
926 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
927 | if (adev->mmhub.ras_funcs && |
928 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
929 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
761d86d3 DL |
930 | break; |
931 | case AMDGPU_RAS_BLOCK__SDMA: | |
932 | if (adev->sdma.funcs->reset_ras_error_count) | |
933 | adev->sdma.funcs->reset_ras_error_count(adev); | |
934 | break; | |
935 | default: | |
936 | break; | |
937 | } | |
938 | ||
939 | return 0; | |
940 | } | |
941 | ||
5c23e9e0 | 942 | /* Trigger XGMI/WAFL error */ |
f3167919 | 943 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
944 | struct ta_ras_trigger_error_input *block_info) |
945 | { | |
946 | int ret; | |
947 | ||
948 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
949 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
950 | ||
951 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
952 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
953 | ||
954 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
955 | ||
956 | if (amdgpu_ras_intr_triggered()) | |
957 | return ret; | |
958 | ||
959 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
960 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
961 | ||
fe2d9f5a | 962 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) |
5c23e9e0 JC |
963 | dev_warn(adev->dev, "Failed to allow df cstate"); |
964 | ||
965 | return ret; | |
966 | } | |
967 | ||
c030f2e4 | 968 | /* wrapper of psp_ras_trigger_error */ |
969 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
970 | struct ras_inject_if *info) | |
971 | { | |
972 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
973 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 974 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
975 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 976 | .sub_block_index = info->head.sub_block_index, |
977 | .address = info->address, | |
978 | .value = info->value, | |
979 | }; | |
980 | int ret = 0; | |
981 | ||
982 | if (!obj) | |
983 | return -EINVAL; | |
984 | ||
a6c44d25 JC |
985 | /* Calculate XGMI relative offset */ |
986 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
987 | block_info.address = |
988 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
989 | block_info.address); | |
a6c44d25 JC |
990 | } |
991 | ||
83b0582c DL |
992 | switch (info->head.block) { |
993 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
994 | if (adev->gfx.ras_funcs && |
995 | adev->gfx.ras_funcs->ras_error_inject) | |
996 | ret = adev->gfx.ras_funcs->ras_error_inject(adev, info); | |
83b0582c DL |
997 | else |
998 | ret = -EINVAL; | |
999 | break; | |
1000 | case AMDGPU_RAS_BLOCK__UMC: | |
5a434527 | 1001 | case AMDGPU_RAS_BLOCK__SDMA: |
9fb2d8de | 1002 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 1003 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
1004 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
1005 | break; | |
5c23e9e0 JC |
1006 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
1007 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
1008 | break; | |
83b0582c | 1009 | default: |
6952e99c | 1010 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 1011 | ras_block_str(info->head.block)); |
83b0582c | 1012 | ret = -EINVAL; |
a5dd40ca HZ |
1013 | } |
1014 | ||
a200034b JC |
1015 | amdgpu_ras_parse_status_code(adev, |
1016 | "inject", | |
1017 | ras_block_str(info->head.block), | |
1018 | (enum ta_ras_status)ret); | |
c030f2e4 | 1019 | |
1020 | return ret; | |
1021 | } | |
1022 | ||
c030f2e4 | 1023 | /* get the total error counts on all IPs */ |
64cc5414 | 1024 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 1025 | bool is_ce) |
1026 | { | |
1027 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1028 | struct ras_manager *obj; | |
1029 | struct ras_err_data data = {0, 0}; | |
1030 | ||
970fd197 | 1031 | if (!adev->ras_features || !con) |
64cc5414 | 1032 | return 0; |
c030f2e4 | 1033 | |
1034 | list_for_each_entry(obj, &con->head, node) { | |
1035 | struct ras_query_if info = { | |
1036 | .head = obj->head, | |
1037 | }; | |
1038 | ||
761d86d3 | 1039 | if (amdgpu_ras_query_error_status(adev, &info)) |
64cc5414 | 1040 | return 0; |
c030f2e4 | 1041 | |
1042 | data.ce_count += info.ce_count; | |
1043 | data.ue_count += info.ue_count; | |
1044 | } | |
1045 | ||
1046 | return is_ce ? data.ce_count : data.ue_count; | |
1047 | } | |
1048 | /* query/inject/cure end */ | |
1049 | ||
1050 | ||
1051 | /* sysfs begin */ | |
1052 | ||
466b1793 | 1053 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1054 | struct ras_badpage **bps, unsigned int *count); | |
1055 | ||
1056 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1057 | { | |
1058 | switch (flags) { | |
52dd95f2 | 1059 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1060 | return "R"; |
52dd95f2 | 1061 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1062 | return "P"; |
52dd95f2 | 1063 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1064 | default: |
1065 | return "F"; | |
aec576f9 | 1066 | } |
466b1793 | 1067 | } |
1068 | ||
f77c7109 AD |
1069 | /** |
1070 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1071 | * |
1072 | * It allows user to read the bad pages of vram on the gpu through | |
1073 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1074 | * | |
1075 | * It outputs multiple lines, and each line stands for one gpu page. | |
1076 | * | |
1077 | * The format of one line is below, | |
1078 | * gpu pfn : gpu page size : flags | |
1079 | * | |
1080 | * gpu pfn and gpu page size are printed in hex format. | |
1081 | * flags can be one of below character, | |
f77c7109 | 1082 | * |
466b1793 | 1083 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1084 | * |
466b1793 | 1085 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1086 | * in next window of page_reserve. |
1087 | * | |
466b1793 | 1088 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1089 | * | |
f77c7109 AD |
1090 | * Examples: |
1091 | * | |
1092 | * .. code-block:: bash | |
1093 | * | |
1094 | * 0x00000001 : 0x00001000 : R | |
1095 | * 0x00000002 : 0x00001000 : P | |
1096 | * | |
466b1793 | 1097 | */ |
1098 | ||
1099 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1100 | struct kobject *kobj, struct bin_attribute *attr, | |
1101 | char *buf, loff_t ppos, size_t count) | |
1102 | { | |
1103 | struct amdgpu_ras *con = | |
1104 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1105 | struct amdgpu_device *adev = con->adev; | |
1106 | const unsigned int element_size = | |
1107 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1108 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1109 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1110 | ssize_t s = 0; |
1111 | struct ras_badpage *bps = NULL; | |
1112 | unsigned int bps_count = 0; | |
1113 | ||
1114 | memset(buf, 0, count); | |
1115 | ||
1116 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1117 | return 0; | |
1118 | ||
1119 | for (; start < end && start < bps_count; start++) | |
1120 | s += scnprintf(&buf[s], element_size + 1, | |
1121 | "0x%08x : 0x%08x : %1s\n", | |
1122 | bps[start].bp, | |
1123 | bps[start].size, | |
1124 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1125 | ||
1126 | kfree(bps); | |
1127 | ||
1128 | return s; | |
1129 | } | |
1130 | ||
c030f2e4 | 1131 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1132 | struct device_attribute *attr, char *buf) | |
1133 | { | |
1134 | struct amdgpu_ras *con = | |
1135 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1136 | |
5212a3bd | 1137 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1138 | } |
1139 | ||
f848159b GC |
1140 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1141 | { | |
1142 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1143 | ||
1144 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1145 | &con->badpages_attr.attr, | |
1146 | RAS_FS_NAME); | |
1147 | } | |
1148 | ||
c030f2e4 | 1149 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1150 | { | |
1151 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1152 | struct attribute *attrs[] = { | |
1153 | &con->features_attr.attr, | |
1154 | NULL | |
1155 | }; | |
1156 | struct attribute_group group = { | |
eb0c3cd4 | 1157 | .name = RAS_FS_NAME, |
c030f2e4 | 1158 | .attrs = attrs, |
1159 | }; | |
1160 | ||
1161 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1167 | struct ras_fs_if *head) | |
1168 | { | |
1169 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1170 | ||
1171 | if (!obj || obj->attr_inuse) | |
1172 | return -EINVAL; | |
1173 | ||
1174 | get_obj(obj); | |
1175 | ||
1176 | memcpy(obj->fs_data.sysfs_name, | |
1177 | head->sysfs_name, | |
1178 | sizeof(obj->fs_data.sysfs_name)); | |
1179 | ||
1180 | obj->sysfs_attr = (struct device_attribute){ | |
1181 | .attr = { | |
1182 | .name = obj->fs_data.sysfs_name, | |
1183 | .mode = S_IRUGO, | |
1184 | }, | |
1185 | .show = amdgpu_ras_sysfs_read, | |
1186 | }; | |
163def43 | 1187 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1188 | |
1189 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1190 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1191 | RAS_FS_NAME)) { |
c030f2e4 | 1192 | put_obj(obj); |
1193 | return -EINVAL; | |
1194 | } | |
1195 | ||
1196 | obj->attr_inuse = 1; | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1202 | struct ras_common_if *head) | |
1203 | { | |
1204 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1205 | ||
1206 | if (!obj || !obj->attr_inuse) | |
1207 | return -EINVAL; | |
1208 | ||
1209 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1210 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1211 | RAS_FS_NAME); |
c030f2e4 | 1212 | obj->attr_inuse = 0; |
1213 | put_obj(obj); | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1219 | { | |
1220 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1221 | struct ras_manager *obj, *tmp; | |
1222 | ||
1223 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1224 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1225 | } | |
1226 | ||
f848159b GC |
1227 | if (amdgpu_bad_page_threshold != 0) |
1228 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1229 | ||
c030f2e4 | 1230 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | /* sysfs end */ | |
1235 | ||
ef177d11 AD |
1236 | /** |
1237 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1238 | * | |
1239 | * Normally when there is an uncorrectable error, the driver will reset | |
1240 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1241 | * the driver provides an interface to reboot the system automatically | |
1242 | * in that event. | |
1243 | * | |
1244 | * The following file in debugfs provides that interface: | |
1245 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1246 | * | |
1247 | * Usage: | |
1248 | * | |
1249 | * .. code-block:: bash | |
1250 | * | |
1251 | * echo true > .../ras/auto_reboot | |
1252 | * | |
1253 | */ | |
c030f2e4 | 1254 | /* debugfs begin */ |
ea1b8c9b | 1255 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1256 | { |
1257 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1258 | struct dentry *dir; |
4a580877 | 1259 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
36ea1bd2 | 1260 | |
88293c03 ND |
1261 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1262 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1263 | &amdgpu_ras_debugfs_ctrl_ops); | |
1264 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1265 | &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1266 | |
1267 | /* | |
1268 | * After one uncorrectable error happens, usually GPU recovery will | |
1269 | * be scheduled. But due to the known problem in GPU recovery failing | |
1270 | * to bring GPU back, below interface provides one direct way to | |
1271 | * user to reboot system automatically in such case within | |
1272 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1273 | * will never be called. | |
1274 | */ | |
88293c03 | 1275 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1276 | |
1277 | /* | |
1278 | * User could set this not to clean up hardware's error count register | |
1279 | * of RAS IPs during ras recovery. | |
1280 | */ | |
88293c03 ND |
1281 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1282 | &con->disable_ras_err_cnt_harvest); | |
1283 | return dir; | |
36ea1bd2 | 1284 | } |
1285 | ||
cedf7884 | 1286 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1287 | struct ras_fs_if *head, |
1288 | struct dentry *dir) | |
c030f2e4 | 1289 | { |
c030f2e4 | 1290 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1291 | |
88293c03 | 1292 | if (!obj || !dir) |
450f30ea | 1293 | return; |
c030f2e4 | 1294 | |
1295 | get_obj(obj); | |
1296 | ||
1297 | memcpy(obj->fs_data.debugfs_name, | |
1298 | head->debugfs_name, | |
1299 | sizeof(obj->fs_data.debugfs_name)); | |
1300 | ||
88293c03 ND |
1301 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1302 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1303 | } |
1304 | ||
f9317014 TZ |
1305 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1306 | { | |
1307 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1308 | struct dentry *dir; |
c1509f3f | 1309 | struct ras_manager *obj; |
f9317014 TZ |
1310 | struct ras_fs_if fs_info; |
1311 | ||
1312 | /* | |
1313 | * it won't be called in resume path, no need to check | |
1314 | * suspend and gpu reset status | |
1315 | */ | |
cedf7884 | 1316 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1317 | return; |
1318 | ||
88293c03 | 1319 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1320 | |
c1509f3f | 1321 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1322 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1323 | (obj->attr_inuse == 1)) { | |
1324 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1325 | ras_block_str(obj->head.block)); | |
1326 | fs_info.head = obj->head; | |
88293c03 | 1327 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1328 | } |
1329 | } | |
1330 | } | |
1331 | ||
c030f2e4 | 1332 | /* debugfs end */ |
1333 | ||
1334 | /* ras fs */ | |
c3d4d45d GC |
1335 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1336 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1337 | static DEVICE_ATTR(features, S_IRUGO, | |
1338 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1339 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1340 | { | |
c3d4d45d GC |
1341 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1342 | struct attribute_group group = { | |
1343 | .name = RAS_FS_NAME, | |
1344 | }; | |
1345 | struct attribute *attrs[] = { | |
1346 | &con->features_attr.attr, | |
1347 | NULL | |
1348 | }; | |
1349 | struct bin_attribute *bin_attrs[] = { | |
1350 | NULL, | |
1351 | NULL, | |
1352 | }; | |
a069a9eb | 1353 | int r; |
c030f2e4 | 1354 | |
c3d4d45d GC |
1355 | /* add features entry */ |
1356 | con->features_attr = dev_attr_features; | |
1357 | group.attrs = attrs; | |
1358 | sysfs_attr_init(attrs[0]); | |
1359 | ||
1360 | if (amdgpu_bad_page_threshold != 0) { | |
1361 | /* add bad_page_features entry */ | |
1362 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1363 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1364 | bin_attrs[0] = &con->badpages_attr; | |
1365 | group.bin_attrs = bin_attrs; | |
1366 | sysfs_bin_attr_init(bin_attrs[0]); | |
1367 | } | |
1368 | ||
a069a9eb AD |
1369 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1370 | if (r) | |
1371 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1372 | |
c030f2e4 | 1373 | return 0; |
1374 | } | |
1375 | ||
1376 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1377 | { | |
88293c03 ND |
1378 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1379 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1380 | ||
1381 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1382 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1383 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1384 | if (ip_obj) | |
1385 | put_obj(ip_obj); | |
1386 | } | |
1387 | } | |
1388 | ||
c030f2e4 | 1389 | amdgpu_ras_sysfs_remove_all(adev); |
1390 | return 0; | |
1391 | } | |
1392 | /* ras fs end */ | |
1393 | ||
1394 | /* ih begin */ | |
1395 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1396 | { | |
1397 | struct ras_ih_data *data = &obj->ih_data; | |
1398 | struct amdgpu_iv_entry entry; | |
1399 | int ret; | |
cf04dfd0 | 1400 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1401 | |
1402 | while (data->rptr != data->wptr) { | |
1403 | rmb(); | |
1404 | memcpy(&entry, &data->ring[data->rptr], | |
1405 | data->element_size); | |
1406 | ||
1407 | wmb(); | |
1408 | data->rptr = (data->aligned_element_size + | |
1409 | data->rptr) % data->ring_size; | |
1410 | ||
1411 | /* Let IP handle its data, maybe we need get the output | |
1412 | * from the callback to udpate the error type/count, etc | |
1413 | */ | |
1414 | if (data->cb) { | |
cf04dfd0 | 1415 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1416 | /* ue will trigger an interrupt, and in that case |
1417 | * we need do a reset to recovery the whole system. | |
1418 | * But leave IP do that recovery, here we just dispatch | |
1419 | * the error. | |
1420 | */ | |
bd2280da | 1421 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1422 | /* these counts could be left as 0 if |
1423 | * some blocks do not count error number | |
1424 | */ | |
cf04dfd0 | 1425 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1426 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1427 | } |
c030f2e4 | 1428 | } |
1429 | } | |
1430 | } | |
1431 | ||
1432 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1433 | { | |
1434 | struct ras_ih_data *data = | |
1435 | container_of(work, struct ras_ih_data, ih_work); | |
1436 | struct ras_manager *obj = | |
1437 | container_of(data, struct ras_manager, ih_data); | |
1438 | ||
1439 | amdgpu_ras_interrupt_handler(obj); | |
1440 | } | |
1441 | ||
1442 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1443 | struct ras_dispatch_if *info) | |
1444 | { | |
1445 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1446 | struct ras_ih_data *data = &obj->ih_data; | |
1447 | ||
1448 | if (!obj) | |
1449 | return -EINVAL; | |
1450 | ||
1451 | if (data->inuse == 0) | |
1452 | return 0; | |
1453 | ||
1454 | /* Might be overflow... */ | |
1455 | memcpy(&data->ring[data->wptr], info->entry, | |
1456 | data->element_size); | |
1457 | ||
1458 | wmb(); | |
1459 | data->wptr = (data->aligned_element_size + | |
1460 | data->wptr) % data->ring_size; | |
1461 | ||
1462 | schedule_work(&data->ih_work); | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
1467 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1468 | struct ras_ih_if *info) | |
1469 | { | |
1470 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1471 | struct ras_ih_data *data; | |
1472 | ||
1473 | if (!obj) | |
1474 | return -EINVAL; | |
1475 | ||
1476 | data = &obj->ih_data; | |
1477 | if (data->inuse == 0) | |
1478 | return 0; | |
1479 | ||
1480 | cancel_work_sync(&data->ih_work); | |
1481 | ||
1482 | kfree(data->ring); | |
1483 | memset(data, 0, sizeof(*data)); | |
1484 | put_obj(obj); | |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
1489 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1490 | struct ras_ih_if *info) | |
1491 | { | |
1492 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1493 | struct ras_ih_data *data; | |
1494 | ||
1495 | if (!obj) { | |
1496 | /* in case we registe the IH before enable ras feature */ | |
1497 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1498 | if (!obj) | |
1499 | return -EINVAL; | |
1500 | } else | |
1501 | get_obj(obj); | |
1502 | ||
1503 | data = &obj->ih_data; | |
1504 | /* add the callback.etc */ | |
1505 | *data = (struct ras_ih_data) { | |
1506 | .inuse = 0, | |
1507 | .cb = info->cb, | |
1508 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1509 | .rptr = 0, | |
1510 | .wptr = 0, | |
1511 | }; | |
1512 | ||
1513 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1514 | ||
1515 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1516 | /* the ring can store 64 iv entries. */ | |
1517 | data->ring_size = 64 * data->aligned_element_size; | |
1518 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1519 | if (!data->ring) { | |
1520 | put_obj(obj); | |
1521 | return -ENOMEM; | |
1522 | } | |
1523 | ||
1524 | /* IH is ready */ | |
1525 | data->inuse = 1; | |
1526 | ||
1527 | return 0; | |
1528 | } | |
1529 | ||
1530 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1531 | { | |
1532 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1533 | struct ras_manager *obj, *tmp; | |
1534 | ||
1535 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1536 | struct ras_ih_if info = { | |
1537 | .head = obj->head, | |
1538 | }; | |
1539 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1540 | } | |
1541 | ||
1542 | return 0; | |
1543 | } | |
1544 | /* ih end */ | |
1545 | ||
313c8fd3 GC |
1546 | /* traversal all IPs except NBIO to query error counter */ |
1547 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1548 | { | |
1549 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1550 | struct ras_manager *obj; | |
1551 | ||
970fd197 | 1552 | if (!adev->ras_features || !con) |
313c8fd3 GC |
1553 | return; |
1554 | ||
1555 | list_for_each_entry(obj, &con->head, node) { | |
1556 | struct ras_query_if info = { | |
1557 | .head = obj->head, | |
1558 | }; | |
1559 | ||
1560 | /* | |
1561 | * PCIE_BIF IP has one different isr by ras controller | |
1562 | * interrupt, the specific ras counter query will be | |
1563 | * done in that isr. So skip such block from common | |
1564 | * sync flood interrupt isr calling. | |
1565 | */ | |
1566 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1567 | continue; | |
1568 | ||
761d86d3 | 1569 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1570 | } |
1571 | } | |
1572 | ||
3f975d0f | 1573 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1574 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1575 | struct ras_query_if *info) | |
3f975d0f SY |
1576 | { |
1577 | /* | |
1578 | * Only two block need to query read/write | |
1579 | * RspStatus at current state | |
1580 | */ | |
1581 | switch (info->head.block) { | |
1582 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1583 | if (adev->gfx.ras_funcs && |
1584 | adev->gfx.ras_funcs->query_ras_error_status) | |
1585 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1586 | break; |
1587 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
1588 | if (adev->mmhub.ras_funcs && |
1589 | adev->mmhub.ras_funcs->query_ras_error_status) | |
1590 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1591 | break; |
1592 | default: | |
1593 | break; | |
1594 | } | |
1595 | } | |
1596 | ||
1597 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1598 | { | |
1599 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1600 | struct ras_manager *obj; | |
1601 | ||
970fd197 | 1602 | if (!adev->ras_features || !con) |
3f975d0f SY |
1603 | return; |
1604 | ||
1605 | list_for_each_entry(obj, &con->head, node) { | |
1606 | struct ras_query_if info = { | |
1607 | .head = obj->head, | |
1608 | }; | |
1609 | ||
1610 | amdgpu_ras_error_status_query(adev, &info); | |
1611 | } | |
1612 | } | |
1613 | ||
c030f2e4 | 1614 | /* recovery begin */ |
466b1793 | 1615 | |
1616 | /* return 0 on success. | |
1617 | * caller need free bps. | |
1618 | */ | |
1619 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1620 | struct ras_badpage **bps, unsigned int *count) | |
1621 | { | |
1622 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1623 | struct ras_err_handler_data *data; | |
1624 | int i = 0; | |
732f2a30 | 1625 | int ret = 0, status; |
466b1793 | 1626 | |
1627 | if (!con || !con->eh_data || !bps || !count) | |
1628 | return -EINVAL; | |
1629 | ||
1630 | mutex_lock(&con->recovery_lock); | |
1631 | data = con->eh_data; | |
1632 | if (!data || data->count == 0) { | |
1633 | *bps = NULL; | |
46cf2fec | 1634 | ret = -EINVAL; |
466b1793 | 1635 | goto out; |
1636 | } | |
1637 | ||
1638 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1639 | if (!*bps) { | |
1640 | ret = -ENOMEM; | |
1641 | goto out; | |
1642 | } | |
1643 | ||
1644 | for (; i < data->count; i++) { | |
1645 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1646 | .bp = data->bps[i].retired_page, |
466b1793 | 1647 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1648 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1649 | }; |
732f2a30 | 1650 | status = amdgpu_vram_mgr_query_page_status( |
676deb38 DL |
1651 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), |
1652 | data->bps[i].retired_page); | |
732f2a30 | 1653 | if (status == -EBUSY) |
52dd95f2 | 1654 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1655 | else if (status == -ENOENT) |
52dd95f2 | 1656 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1657 | } |
1658 | ||
1659 | *count = data->count; | |
1660 | out: | |
1661 | mutex_unlock(&con->recovery_lock); | |
1662 | return ret; | |
1663 | } | |
1664 | ||
c030f2e4 | 1665 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1666 | { | |
1667 | struct amdgpu_ras *ras = | |
1668 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1669 | struct amdgpu_device *remote_adev = NULL; |
1670 | struct amdgpu_device *adev = ras->adev; | |
1671 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1672 | |
f75e94d8 | 1673 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1674 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1675 | ||
f75e94d8 GC |
1676 | /* Build list of devices to query RAS related errors */ |
1677 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1678 | device_list_handle = &hive->device_list; | |
1679 | } else { | |
1680 | INIT_LIST_HEAD(&device_list); | |
1681 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1682 | device_list_handle = &device_list; | |
1683 | } | |
c030f2e4 | 1684 | |
f75e94d8 | 1685 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1686 | device_list_handle, gmc.xgmi.head) { |
1687 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1688 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1689 | } |
d95e8e97 DL |
1690 | |
1691 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1692 | } |
313c8fd3 | 1693 | |
93af20f7 | 1694 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1695 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1696 | atomic_set(&ras->in_recovery, 0); |
1697 | } | |
1698 | ||
c030f2e4 | 1699 | /* alloc/realloc bps array */ |
1700 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1701 | struct ras_err_handler_data *data, int pages) | |
1702 | { | |
1703 | unsigned int old_space = data->count + data->space_left; | |
1704 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1705 | unsigned int align_space = ALIGN(new_space, 512); |
1706 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1707 | |
676deb38 | 1708 | if (!bps) { |
9dc23a63 | 1709 | kfree(bps); |
c030f2e4 | 1710 | return -ENOMEM; |
9dc23a63 | 1711 | } |
c030f2e4 | 1712 | |
1713 | if (data->bps) { | |
9dc23a63 | 1714 | memcpy(bps, data->bps, |
c030f2e4 | 1715 | data->count * sizeof(*data->bps)); |
1716 | kfree(data->bps); | |
1717 | } | |
1718 | ||
9dc23a63 | 1719 | data->bps = bps; |
c030f2e4 | 1720 | data->space_left += align_space - old_space; |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | /* it deal with vram only. */ | |
1725 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1726 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1727 | { |
1728 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1729 | struct ras_err_handler_data *data; |
c030f2e4 | 1730 | int ret = 0; |
676deb38 | 1731 | uint32_t i; |
c030f2e4 | 1732 | |
73aa8e1a | 1733 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1734 | return 0; |
1735 | ||
1736 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1737 | data = con->eh_data; |
c030f2e4 | 1738 | if (!data) |
1739 | goto out; | |
1740 | ||
676deb38 DL |
1741 | for (i = 0; i < pages; i++) { |
1742 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1743 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1744 | continue; | |
1745 | ||
1746 | if (!data->space_left && | |
1747 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1748 | ret = -ENOMEM; |
1749 | goto out; | |
1750 | } | |
1751 | ||
676deb38 DL |
1752 | amdgpu_vram_mgr_reserve_range( |
1753 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1754 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1755 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1756 | |
676deb38 DL |
1757 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1758 | data->count++; | |
1759 | data->space_left--; | |
1760 | } | |
c030f2e4 | 1761 | out: |
1762 | mutex_unlock(&con->recovery_lock); | |
1763 | ||
1764 | return ret; | |
1765 | } | |
1766 | ||
78ad00c9 TZ |
1767 | /* |
1768 | * write error record array to eeprom, the function should be | |
1769 | * protected by recovery_lock | |
1770 | */ | |
22503d80 | 1771 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1772 | { |
1773 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1774 | struct ras_err_handler_data *data; | |
8a3e801f | 1775 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1776 | int save_count; |
1777 | ||
1778 | if (!con || !con->eh_data) | |
1779 | return 0; | |
1780 | ||
8a3e801f | 1781 | control = &con->eeprom_control; |
78ad00c9 TZ |
1782 | data = con->eh_data; |
1783 | save_count = data->count - control->num_recs; | |
1784 | /* only new entries are saved */ | |
b1628425 | 1785 | if (save_count > 0) { |
0771b0bf | 1786 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1787 | &data->bps[control->num_recs], |
1788 | true, | |
1789 | save_count)) { | |
6952e99c | 1790 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1791 | return -EIO; |
1792 | } | |
1793 | ||
b1628425 GC |
1794 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1795 | } | |
1796 | ||
78ad00c9 TZ |
1797 | return 0; |
1798 | } | |
1799 | ||
1800 | /* | |
1801 | * read error record array in eeprom and reserve enough space for | |
1802 | * storing new bad pages | |
1803 | */ | |
1804 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1805 | { | |
1806 | struct amdgpu_ras_eeprom_control *control = | |
1807 | &adev->psp.ras.ras->eeprom_control; | |
1808 | struct eeprom_table_record *bps = NULL; | |
1809 | int ret = 0; | |
1810 | ||
1811 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1812 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1813 | return ret; |
1814 | ||
1815 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1816 | if (!bps) | |
1817 | return -ENOMEM; | |
1818 | ||
1819 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1820 | control->num_recs)) { | |
6952e99c | 1821 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1822 | ret = -EIO; |
1823 | goto out; | |
1824 | } | |
1825 | ||
1826 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1827 | ||
1828 | out: | |
1829 | kfree(bps); | |
1830 | return ret; | |
1831 | } | |
1832 | ||
676deb38 DL |
1833 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1834 | uint64_t addr) | |
1835 | { | |
1836 | struct ras_err_handler_data *data = con->eh_data; | |
1837 | int i; | |
1838 | ||
1839 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1840 | for (i = 0; i < data->count; i++) | |
1841 | if (addr == data->bps[i].retired_page) | |
1842 | return true; | |
1843 | ||
1844 | return false; | |
1845 | } | |
1846 | ||
6e4be987 TZ |
1847 | /* |
1848 | * check if an address belongs to bad page | |
1849 | * | |
1850 | * Note: this check is only for umc block | |
1851 | */ | |
1852 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1853 | uint64_t addr) | |
1854 | { | |
1855 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1856 | bool ret = false; |
1857 | ||
1858 | if (!con || !con->eh_data) | |
1859 | return ret; | |
1860 | ||
1861 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1862 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1863 | mutex_unlock(&con->recovery_lock); |
1864 | return ret; | |
1865 | } | |
1866 | ||
e5c04edf CK |
1867 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1868 | uint32_t max_length) | |
c84d4670 | 1869 | { |
e5c04edf | 1870 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
1871 | int tmp_threshold = amdgpu_bad_page_threshold; |
1872 | u64 val; | |
1873 | ||
1874 | /* | |
1875 | * Justification of value bad_page_cnt_threshold in ras structure | |
1876 | * | |
1877 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1878 | * in eeprom, and introduce two scenarios accordingly. | |
1879 | * | |
1880 | * Bad page retirement enablement: | |
1881 | * - If amdgpu_bad_page_threshold = -1, | |
1882 | * bad_page_cnt_threshold = typical value by formula. | |
1883 | * | |
1884 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1885 | * max record length in eeprom, use it directly. | |
1886 | * | |
1887 | * Bad page retirement disablement: | |
1888 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1889 | * functionality is disabled, and bad_page_cnt_threshold will | |
1890 | * take no effect. | |
1891 | */ | |
1892 | ||
1893 | if (tmp_threshold < -1) | |
1894 | tmp_threshold = -1; | |
1895 | else if (tmp_threshold > max_length) | |
1896 | tmp_threshold = max_length; | |
1897 | ||
1898 | if (tmp_threshold == -1) { | |
e5c04edf | 1899 | val = adev->gmc.mc_vram_size; |
c84d4670 | 1900 | do_div(val, RAS_BAD_PAGE_RATE); |
e5c04edf CK |
1901 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
1902 | max_length); | |
1903 | } else { | |
1904 | con->bad_page_cnt_threshold = tmp_threshold; | |
c84d4670 GC |
1905 | } |
1906 | } | |
1907 | ||
1a6fc071 | 1908 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1909 | { |
1910 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1911 | struct ras_err_handler_data **data; |
e5c04edf | 1912 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1913 | bool exc_err_limit = false; |
78ad00c9 | 1914 | int ret; |
c030f2e4 | 1915 | |
970fd197 | 1916 | if (adev->ras_features && con) |
4d1337d2 AG |
1917 | data = &con->eh_data; |
1918 | else | |
1919 | return 0; | |
1920 | ||
1a6fc071 TZ |
1921 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1922 | if (!*data) { | |
1923 | ret = -ENOMEM; | |
1924 | goto out; | |
1925 | } | |
c030f2e4 | 1926 | |
1927 | mutex_init(&con->recovery_lock); | |
1928 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1929 | atomic_set(&con->in_recovery, 0); | |
1930 | con->adev = adev; | |
1931 | ||
e5c04edf CK |
1932 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1933 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
c84d4670 | 1934 | |
e5086659 | 1935 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
1936 | * when the GPU is pending on XGMI reset during probe time | |
1937 | * (Mostly after second bus reset), skip it now | |
1938 | */ | |
1939 | if (adev->gmc.xgmi.pending_reset) | |
1940 | return 0; | |
b82e65a9 GC |
1941 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1942 | /* | |
1943 | * This calling fails when exc_err_limit is true or | |
1944 | * ret != 0. | |
1945 | */ | |
1946 | if (exc_err_limit || ret) | |
1a6fc071 | 1947 | goto free; |
78ad00c9 | 1948 | |
0771b0bf | 1949 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1950 | ret = amdgpu_ras_load_bad_pages(adev); |
1951 | if (ret) | |
1a6fc071 | 1952 | goto free; |
78ad00c9 | 1953 | } |
c030f2e4 | 1954 | |
1955 | return 0; | |
1a6fc071 | 1956 | |
1a6fc071 | 1957 | free: |
1a6fc071 | 1958 | kfree((*data)->bps); |
1a6fc071 | 1959 | kfree(*data); |
1995b3a3 | 1960 | con->eh_data = NULL; |
1a6fc071 | 1961 | out: |
6952e99c | 1962 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1963 | |
b82e65a9 GC |
1964 | /* |
1965 | * Except error threshold exceeding case, other failure cases in this | |
1966 | * function would not fail amdgpu driver init. | |
1967 | */ | |
1968 | if (!exc_err_limit) | |
1969 | ret = 0; | |
1970 | else | |
1971 | ret = -EINVAL; | |
1972 | ||
1a6fc071 | 1973 | return ret; |
c030f2e4 | 1974 | } |
1975 | ||
1976 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1977 | { | |
1978 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1979 | struct ras_err_handler_data *data = con->eh_data; | |
1980 | ||
1a6fc071 TZ |
1981 | /* recovery_init failed to init it, fini is useless */ |
1982 | if (!data) | |
1983 | return 0; | |
1984 | ||
c030f2e4 | 1985 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1986 | |
1987 | mutex_lock(&con->recovery_lock); | |
1988 | con->eh_data = NULL; | |
1989 | kfree(data->bps); | |
1990 | kfree(data); | |
1991 | mutex_unlock(&con->recovery_lock); | |
1992 | ||
1993 | return 0; | |
1994 | } | |
1995 | /* recovery end */ | |
1996 | ||
a564808e | 1997 | /* return 0 if ras will reset gpu and repost.*/ |
1998 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1999 | unsigned int block) | |
2000 | { | |
2001 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2002 | ||
2003 | if (!ras) | |
2004 | return -EINVAL; | |
2005 | ||
2006 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2007 | return 0; | |
2008 | } | |
2009 | ||
084e2640 | 2010 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2011 | { |
084e2640 LT |
2012 | return adev->asic_type == CHIP_VEGA10 || |
2013 | adev->asic_type == CHIP_VEGA20 || | |
2014 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2015 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2016 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2017 | } |
2018 | ||
5caf466a | 2019 | /* |
2020 | * check hardware's ras ability which will be saved in hw_supported. | |
2021 | * if hardware does not support ras, we can skip some ras initializtion and | |
2022 | * forbid some ras operations from IP. | |
2023 | * if software itself, say boot parameter, limit the ras ability. We still | |
2024 | * need allow IP do some limited operations, like disable. In such case, | |
2025 | * we have to initialize ras as normal. but need check if operation is | |
2026 | * allowed or not in each function. | |
2027 | */ | |
2028 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
2029 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 2030 | { |
5caf466a | 2031 | *hw_supported = 0; |
2032 | *supported = 0; | |
c030f2e4 | 2033 | |
88474cca | 2034 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 2035 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 2036 | return; |
b404ae82 | 2037 | |
75f06251 HZ |
2038 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2039 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2040 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
2041 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | | |
2042 | 1 << AMDGPU_RAS_BLOCK__DF); | |
2043 | } else { | |
2044 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2045 | } | |
88474cca | 2046 | |
75f06251 HZ |
2047 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2048 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
2049 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | | |
2050 | 1 << AMDGPU_RAS_BLOCK__DF); | |
2051 | } else { | |
2052 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2053 | } | |
2054 | } else { | |
2055 | /* driver only manages a few IP blocks RAS feature | |
2056 | * when GPU is connected cpu through XGMI */ | |
2057 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__GFX | | |
2058 | 1 << AMDGPU_RAS_BLOCK__SDMA | | |
2059 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
2060 | } | |
88474cca GC |
2061 | |
2062 | /* hw_supported needs to be aligned with RAS block mask. */ | |
2063 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 2064 | |
5caf466a | 2065 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 2066 | 0 : *hw_supported & amdgpu_ras_mask; |
5436ab94 | 2067 | adev->ras_features = *supported; |
c030f2e4 | 2068 | } |
2069 | ||
2070 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
2071 | { | |
2072 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2073 | int r; |
c030f2e4 | 2074 | |
b404ae82 | 2075 | if (con) |
c030f2e4 | 2076 | return 0; |
2077 | ||
2078 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
2079 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
2080 | GFP_KERNEL|__GFP_ZERO); | |
2081 | if (!con) | |
2082 | return -ENOMEM; | |
2083 | ||
2084 | con->objs = (struct ras_manager *)(con + 1); | |
2085 | ||
2086 | amdgpu_ras_set_context(adev, con); | |
2087 | ||
5caf466a | 2088 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
2089 | &con->supported); | |
5436ab94 | 2090 | if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) { |
970fd197 SY |
2091 | /* set gfx block ras context feature for VEGA20 Gaming |
2092 | * send ras disable cmd to ras ta during ras late init. | |
2093 | */ | |
2094 | if (!adev->ras_features && adev->asic_type == CHIP_VEGA20) { | |
2095 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); | |
2096 | ||
2097 | return 0; | |
2098 | } | |
2099 | ||
5e91160a | 2100 | r = 0; |
5436ab94 | 2101 | goto release_con; |
fb2a3607 HZ |
2102 | } |
2103 | ||
c030f2e4 | 2104 | con->features = 0; |
2105 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2106 | /* Might need get this flag from vbios. */ |
2107 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2108 | |
6e36f231 HZ |
2109 | /* initialize nbio ras function ahead of any other |
2110 | * ras functions so hardware fatal error interrupt | |
2111 | * can be enabled as early as possible */ | |
2112 | switch (adev->asic_type) { | |
2113 | case CHIP_VEGA20: | |
2114 | case CHIP_ARCTURUS: | |
2115 | case CHIP_ALDEBARAN: | |
2116 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2117 | adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs; | |
2118 | break; | |
2119 | default: | |
2120 | /* nbio ras is not available */ | |
2121 | break; | |
2122 | } | |
2123 | ||
2124 | if (adev->nbio.ras_funcs && | |
2125 | adev->nbio.ras_funcs->init_ras_controller_interrupt) { | |
2126 | r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev); | |
4e644fff | 2127 | if (r) |
5436ab94 | 2128 | goto release_con; |
4e644fff HZ |
2129 | } |
2130 | ||
6e36f231 HZ |
2131 | if (adev->nbio.ras_funcs && |
2132 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) { | |
2133 | r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2134 | if (r) |
5436ab94 | 2135 | goto release_con; |
4e644fff HZ |
2136 | } |
2137 | ||
5e91160a GC |
2138 | if (amdgpu_ras_fs_init(adev)) { |
2139 | r = -EINVAL; | |
5436ab94 | 2140 | goto release_con; |
5e91160a | 2141 | } |
c030f2e4 | 2142 | |
6952e99c | 2143 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 2144 | "hardware ability[%x] ras_mask[%x]\n", |
2145 | con->hw_supported, con->supported); | |
c030f2e4 | 2146 | return 0; |
5436ab94 | 2147 | release_con: |
c030f2e4 | 2148 | amdgpu_ras_set_context(adev, NULL); |
2149 | kfree(con); | |
2150 | ||
5e91160a | 2151 | return r; |
c030f2e4 | 2152 | } |
2153 | ||
134d16d5 JC |
2154 | static int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
2155 | { | |
2156 | if (adev->gmc.xgmi.connected_to_cpu) | |
2157 | return 1; | |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2162 | struct ras_common_if *ras_block) | |
2163 | { | |
2164 | struct ras_query_if info = { | |
2165 | .head = *ras_block, | |
2166 | }; | |
2167 | ||
2168 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2169 | return 0; | |
2170 | ||
2171 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2172 | DRM_WARN("RAS init harvest failure"); | |
2173 | ||
2174 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2175 | DRM_WARN("RAS init harvest reset failure"); | |
2176 | ||
2177 | return 0; | |
2178 | } | |
2179 | ||
b293e891 HZ |
2180 | /* helper function to handle common stuff in ip late init phase */ |
2181 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2182 | struct ras_common_if *ras_block, | |
2183 | struct ras_fs_if *fs_info, | |
2184 | struct ras_ih_if *ih_info) | |
2185 | { | |
2186 | int r; | |
2187 | ||
2188 | /* disable RAS feature per IP block if it is not supported */ | |
2189 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2190 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2191 | return 0; | |
2192 | } | |
2193 | ||
2194 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2195 | if (r) { | |
2196 | if (r == -EAGAIN) { | |
2197 | /* request gpu reset. will run again */ | |
2198 | amdgpu_ras_request_reset_on_boot(adev, | |
2199 | ras_block->block); | |
2200 | return 0; | |
53b3f8f4 | 2201 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2202 | /* in resume phase, if fail to enable ras, |
2203 | * clean up all ras fs nodes, and disable ras */ | |
2204 | goto cleanup; | |
2205 | } else | |
2206 | return r; | |
2207 | } | |
2208 | ||
134d16d5 JC |
2209 | /* check for errors on warm reset edc persisant supported ASIC */ |
2210 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2211 | ||
b293e891 | 2212 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2213 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2214 | return 0; |
2215 | ||
2216 | if (ih_info->cb) { | |
2217 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2218 | if (r) | |
2219 | goto interrupt; | |
2220 | } | |
2221 | ||
b293e891 HZ |
2222 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2223 | if (r) | |
2224 | goto sysfs; | |
2225 | ||
2226 | return 0; | |
2227 | cleanup: | |
2228 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2229 | sysfs: | |
b293e891 HZ |
2230 | if (ih_info->cb) |
2231 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2232 | interrupt: | |
2233 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2234 | return r; | |
2235 | } | |
2236 | ||
2237 | /* helper function to remove ras fs node and interrupt handler */ | |
2238 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2239 | struct ras_common_if *ras_block, | |
2240 | struct ras_ih_if *ih_info) | |
2241 | { | |
2242 | if (!ras_block || !ih_info) | |
2243 | return; | |
2244 | ||
2245 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2246 | if (ih_info->cb) |
f3729f7b | 2247 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2248 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2249 | } | |
2250 | ||
a564808e | 2251 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2252 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2253 | */ |
511fdbc3 | 2254 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2255 | { |
2256 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2257 | struct ras_manager *obj, *tmp; | |
2258 | ||
970fd197 SY |
2259 | if (!adev->ras_features || !con) { |
2260 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ | |
2261 | amdgpu_release_ras_context(adev); | |
2262 | ||
108c6a63 | 2263 | return; |
970fd197 | 2264 | } |
108c6a63 | 2265 | |
108c6a63 | 2266 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2267 | /* Set up all other IPs which are not implemented. There is a |
2268 | * tricky thing that IP's actual ras error type should be | |
2269 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2270 | * ERROR_NONE make sense anyway. | |
2271 | */ | |
2272 | amdgpu_ras_enable_all_features(adev, 1); | |
2273 | ||
2274 | /* We enable ras on all hw_supported block, but as boot | |
2275 | * parameter might disable some of them and one or more IP has | |
2276 | * not implemented yet. So we disable them on behalf. | |
2277 | */ | |
108c6a63 | 2278 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2279 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2280 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2281 | /* there should be no any reference. */ | |
2282 | WARN_ON(alive_obj(obj)); | |
2283 | } | |
191051a1 | 2284 | } |
108c6a63 | 2285 | } |
a564808e | 2286 | |
2287 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2288 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2289 | /* setup ras obj state as disabled. | |
2290 | * for init_by_vbios case. | |
2291 | * if we want to enable ras, just enable it in a normal way. | |
2292 | * If we want do disable it, need setup ras obj as enabled, | |
2293 | * then issue another TA disable cmd. | |
2294 | * See feature_enable_on_boot | |
2295 | */ | |
2296 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2297 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2298 | } |
108c6a63 | 2299 | } |
2300 | ||
511fdbc3 | 2301 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2302 | { | |
2303 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2304 | ||
970fd197 | 2305 | if (!adev->ras_features || !con) |
511fdbc3 | 2306 | return; |
2307 | ||
2308 | amdgpu_ras_disable_all_features(adev, 0); | |
2309 | /* Make sure all ras objects are disabled. */ | |
2310 | if (con->features) | |
2311 | amdgpu_ras_disable_all_features(adev, 1); | |
2312 | } | |
2313 | ||
c030f2e4 | 2314 | /* do some fini work before IP fini as dependence */ |
2315 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2316 | { | |
2317 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2318 | ||
970fd197 | 2319 | if (!adev->ras_features || !con) |
c030f2e4 | 2320 | return 0; |
2321 | ||
2322 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2323 | amdgpu_ras_disable_all_features(adev, 0); | |
2324 | amdgpu_ras_recovery_fini(adev); | |
2325 | return 0; | |
2326 | } | |
2327 | ||
2328 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2329 | { | |
2330 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2331 | ||
970fd197 | 2332 | if (!adev->ras_features || !con) |
c030f2e4 | 2333 | return 0; |
2334 | ||
2335 | amdgpu_ras_fs_fini(adev); | |
2336 | amdgpu_ras_interrupt_remove_all(adev); | |
2337 | ||
2338 | WARN(con->features, "Feature mask is not cleared"); | |
2339 | ||
2340 | if (con->features) | |
2341 | amdgpu_ras_disable_all_features(adev, 1); | |
2342 | ||
2343 | amdgpu_ras_set_context(adev, NULL); | |
2344 | kfree(con); | |
2345 | ||
2346 | return 0; | |
2347 | } | |
7c6e68c7 AG |
2348 | |
2349 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2350 | { | |
ed606f8a AG |
2351 | uint32_t hw_supported, supported; |
2352 | ||
2353 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2354 | if (!hw_supported) | |
2355 | return; | |
2356 | ||
7c6e68c7 | 2357 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2358 | dev_info(adev->dev, "uncorrectable hardware error" |
2359 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2360 | |
61934624 | 2361 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2362 | } |
2363 | } | |
bb5c7235 WS |
2364 | |
2365 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2366 | { | |
2367 | if (adev->asic_type == CHIP_VEGA20 && | |
2368 | adev->pm.fw_version <= 0x283400) { | |
2369 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2370 | amdgpu_ras_intr_triggered(); | |
2371 | } | |
2372 | ||
2373 | return false; | |
2374 | } | |
970fd197 SY |
2375 | |
2376 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2377 | { | |
2378 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2379 | ||
2380 | if (!con) | |
2381 | return; | |
2382 | ||
2383 | if (!adev->ras_features && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { | |
2384 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); | |
2385 | amdgpu_ras_set_context(adev, NULL); | |
2386 | kfree(con); | |
2387 | } | |
2388 | } |