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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
f50160cf | 37 | #include "atom.h" |
c030f2e4 | 38 | |
eb0c3cd4 GC |
39 | static const char *RAS_FS_NAME = "ras"; |
40 | ||
c030f2e4 | 41 | const char *ras_error_string[] = { |
42 | "none", | |
43 | "parity", | |
44 | "single_correctable", | |
45 | "multi_uncorrectable", | |
46 | "poison", | |
47 | }; | |
48 | ||
49 | const char *ras_block_string[] = { | |
50 | "umc", | |
51 | "sdma", | |
52 | "gfx", | |
53 | "mmhub", | |
54 | "athub", | |
55 | "pcie_bif", | |
56 | "hdp", | |
57 | "xgmi_wafl", | |
58 | "df", | |
59 | "smn", | |
60 | "sem", | |
61 | "mp0", | |
62 | "mp1", | |
63 | "fuse", | |
64 | }; | |
65 | ||
66 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
67 | #define ras_block_str(i) (ras_block_string[i]) | |
68 | ||
108c6a63 | 69 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
70 | ||
7cdc2ee3 TZ |
71 | /* inject address is 52 bits */ |
72 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
73 | ||
c84d4670 GC |
74 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
75 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
76 | ||
52dd95f2 GC |
77 | enum amdgpu_ras_retire_page_reservation { |
78 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
79 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
80 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
81 | }; | |
7c6e68c7 AG |
82 | |
83 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
84 | ||
676deb38 DL |
85 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
86 | uint64_t addr); | |
6e4be987 TZ |
87 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
88 | uint64_t addr); | |
89 | ||
61380faa JC |
90 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
91 | { | |
a9d82d2f | 92 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
93 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
94 | } | |
95 | ||
f3167919 | 96 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 97 | { |
a9d82d2f | 98 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
99 | return amdgpu_ras_get_context(adev)->error_query_ready; |
100 | ||
101 | return false; | |
102 | } | |
103 | ||
cbb8f989 JC |
104 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
105 | { | |
106 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
107 | struct eeprom_table_record err_rec; | |
108 | ||
109 | if ((address >= adev->gmc.mc_vram_size) || | |
110 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
111 | dev_warn(adev->dev, | |
112 | "RAS WARN: input address 0x%llx is invalid.\n", | |
113 | address); | |
114 | return -EINVAL; | |
115 | } | |
116 | ||
117 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
118 | dev_warn(adev->dev, | |
80b0cd0f | 119 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
120 | address); |
121 | return 0; | |
122 | } | |
123 | ||
124 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
125 | ||
126 | err_rec.address = address; | |
127 | err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT; | |
128 | err_rec.ts = (uint64_t)ktime_get_real_seconds(); | |
129 | err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; | |
130 | ||
131 | err_data.err_addr = &err_rec; | |
132 | err_data.err_addr_cnt = 1; | |
133 | ||
134 | if (amdgpu_bad_page_threshold != 0) { | |
135 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
136 | err_data.err_addr_cnt); | |
137 | amdgpu_ras_save_bad_pages(adev); | |
138 | } | |
139 | ||
140 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
141 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
142 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
c030f2e4 | 147 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
148 | size_t size, loff_t *pos) | |
149 | { | |
150 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
151 | struct ras_query_if info = { | |
152 | .head = obj->head, | |
153 | }; | |
154 | ssize_t s; | |
155 | char val[128]; | |
156 | ||
761d86d3 | 157 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 158 | return -EINVAL; |
159 | ||
160 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
161 | "ue", info.ue_count, | |
162 | "ce", info.ce_count); | |
163 | if (*pos >= s) | |
164 | return 0; | |
165 | ||
166 | s -= *pos; | |
167 | s = min_t(u64, s, size); | |
168 | ||
169 | ||
170 | if (copy_to_user(buf, &val[*pos], s)) | |
171 | return -EINVAL; | |
172 | ||
173 | *pos += s; | |
174 | ||
175 | return s; | |
176 | } | |
177 | ||
c030f2e4 | 178 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
179 | .owner = THIS_MODULE, | |
180 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 181 | .write = NULL, |
c030f2e4 | 182 | .llseek = default_llseek |
183 | }; | |
184 | ||
96ebb307 | 185 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
186 | { | |
187 | int i; | |
188 | ||
189 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
190 | *block_id = i; | |
191 | if (strcmp(name, ras_block_str(i)) == 0) | |
192 | return 0; | |
193 | } | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
198 | const char __user *buf, size_t size, | |
199 | loff_t *pos, struct ras_debug_if *data) | |
200 | { | |
201 | ssize_t s = min_t(u64, 64, size); | |
202 | char str[65]; | |
203 | char block_name[33]; | |
204 | char err[9] = "ue"; | |
205 | int op = -1; | |
206 | int block_id; | |
44494f96 | 207 | uint32_t sub_block; |
96ebb307 | 208 | u64 address, value; |
209 | ||
210 | if (*pos) | |
211 | return -EINVAL; | |
212 | *pos = size; | |
213 | ||
214 | memset(str, 0, sizeof(str)); | |
215 | memset(data, 0, sizeof(*data)); | |
216 | ||
217 | if (copy_from_user(str, buf, s)) | |
218 | return -EINVAL; | |
219 | ||
220 | if (sscanf(str, "disable %32s", block_name) == 1) | |
221 | op = 0; | |
222 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
223 | op = 1; | |
224 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
225 | op = 2; | |
6df23f4c | 226 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 227 | op = 3; |
b076296b | 228 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 229 | /* ascii string, but commands are not matched. */ |
230 | return -EINVAL; | |
231 | ||
232 | if (op != -1) { | |
cbb8f989 | 233 | if (op == 3) { |
546aa546 LT |
234 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
235 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 236 | return -EINVAL; |
cbb8f989 JC |
237 | |
238 | data->op = op; | |
239 | data->inject.address = address; | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
96ebb307 | 244 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
245 | return -EINVAL; | |
246 | ||
247 | data->head.block = block_id; | |
e1063493 TZ |
248 | /* only ue and ce errors are supported */ |
249 | if (!memcmp("ue", err, 2)) | |
250 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
251 | else if (!memcmp("ce", err, 2)) | |
252 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
253 | else | |
254 | return -EINVAL; | |
255 | ||
96ebb307 | 256 | data->op = op; |
257 | ||
258 | if (op == 2) { | |
546aa546 LT |
259 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", |
260 | &sub_block, &address, &value) != 3 && | |
261 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
262 | &sub_block, &address, &value) != 3) |
263 | return -EINVAL; | |
44494f96 | 264 | data->head.sub_block_index = sub_block; |
96ebb307 | 265 | data->inject.address = address; |
266 | data->inject.value = value; | |
267 | } | |
268 | } else { | |
73aa8e1a | 269 | if (size < sizeof(*data)) |
96ebb307 | 270 | return -EINVAL; |
271 | ||
272 | if (copy_from_user(data, buf, sizeof(*data))) | |
273 | return -EINVAL; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
7c6e68c7 | 278 | |
74abc221 TSD |
279 | /** |
280 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 281 | * |
737c375b | 282 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 283 | * |
284 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 285 | * |
286 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 287 | * |
288 | * head has four members, they are block, type, sub_block_index, name. | |
289 | * block: which IP will be under control. | |
290 | * type: what kind of error will be enabled/disabled/injected. | |
291 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
292 | * name: the name of IP. | |
293 | * | |
294 | * inject has two more members than head, they are address, value. | |
295 | * As their names indicate, inject operation will write the | |
296 | * value to the address. | |
297 | * | |
ef177d11 | 298 | * The second member: struct ras_debug_if::op. |
c688a06b | 299 | * It has three kinds of operations. |
879e723d AZ |
300 | * |
301 | * - 0: disable RAS on the block. Take ::head as its data. | |
302 | * - 1: enable RAS on the block. Take ::head as its data. | |
303 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 304 | * |
96ebb307 | 305 | * How to use the interface? |
ef177d11 | 306 | * |
737c375b | 307 | * In a program |
ef177d11 | 308 | * |
737c375b LT |
309 | * Copy the struct ras_debug_if in your code and initialize it. |
310 | * Write the struct to the control interface. | |
ef177d11 | 311 | * |
737c375b | 312 | * From shell |
96ebb307 | 313 | * |
879e723d AZ |
314 | * .. code-block:: bash |
315 | * | |
737c375b LT |
316 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
317 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
318 | * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
879e723d | 319 | * |
737c375b | 320 | * Where N, is the card which you want to affect. |
ef177d11 | 321 | * |
737c375b LT |
322 | * "disable" requires only the block. |
323 | * "enable" requires the block and error type. | |
324 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 325 | * |
737c375b | 326 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 327 | * see ras_block_string[] for details |
c666bbf0 | 328 | * |
737c375b LT |
329 | * The error type is one of: ue, ce, where, |
330 | * ue is multi-uncorrectable | |
331 | * ce is single-correctable | |
c666bbf0 | 332 | * |
737c375b LT |
333 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
334 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
879e723d | 335 | * |
737c375b | 336 | * For instance, |
879e723d AZ |
337 | * |
338 | * .. code-block:: bash | |
96ebb307 | 339 | * |
44494f96 TZ |
340 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
341 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 342 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
343 | * | |
737c375b | 344 | * How to check the result of the operation? |
36ea1bd2 | 345 | * |
737c375b | 346 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 347 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
348 | * | |
737c375b LT |
349 | * To check inject, see the corresponding error count at, |
350 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 351 | * |
879e723d | 352 | * .. note:: |
ef177d11 | 353 | * Operations are only allowed on blocks which are supported. |
737c375b | 354 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
355 | * to see which blocks support RAS on a particular asic. |
356 | * | |
36ea1bd2 | 357 | */ |
cf696091 LT |
358 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
359 | const char __user *buf, | |
360 | size_t size, loff_t *pos) | |
36ea1bd2 | 361 | { |
362 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
363 | struct ras_debug_if data; | |
364 | int ret = 0; | |
365 | ||
61380faa | 366 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
367 | dev_warn(adev->dev, "RAS WARN: error injection " |
368 | "currently inaccessible\n"); | |
43c4d576 JC |
369 | return size; |
370 | } | |
371 | ||
96ebb307 | 372 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
373 | if (ret) | |
cf696091 | 374 | return ret; |
36ea1bd2 | 375 | |
80b0cd0f | 376 | if (data.op == 3) { |
cbb8f989 | 377 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 378 | if (!ret) |
cbb8f989 JC |
379 | return size; |
380 | else | |
381 | return ret; | |
382 | } | |
383 | ||
36ea1bd2 | 384 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
385 | return -EINVAL; | |
386 | ||
387 | switch (data.op) { | |
388 | case 0: | |
389 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
390 | break; | |
391 | case 1: | |
392 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
393 | break; | |
394 | case 2: | |
7cdc2ee3 TZ |
395 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
396 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
397 | dev_warn(adev->dev, "RAS WARN: input address " |
398 | "0x%llx is invalid.", | |
399 | data.inject.address); | |
7cdc2ee3 TZ |
400 | ret = -EINVAL; |
401 | break; | |
402 | } | |
403 | ||
6e4be987 TZ |
404 | /* umc ce/ue error injection for a bad page is not allowed */ |
405 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
406 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
407 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
408 | "as bad before error injection!\n", | |
6e4be987 TZ |
409 | data.inject.address); |
410 | break; | |
411 | } | |
412 | ||
7cdc2ee3 | 413 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 414 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
415 | break; | |
96ebb307 | 416 | default: |
417 | ret = -EINVAL; | |
418 | break; | |
374bf7bd | 419 | } |
36ea1bd2 | 420 | |
421 | if (ret) | |
422 | return -EINVAL; | |
423 | ||
424 | return size; | |
425 | } | |
426 | ||
084fe13b AG |
427 | /** |
428 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
429 | * | |
f77c7109 | 430 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 431 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
432 | * a way to reset the EEPROM, e.g., after testing error injection. |
433 | * | |
434 | * Usage: | |
435 | * | |
436 | * .. code-block:: bash | |
437 | * | |
438 | * echo 1 > ../ras/ras_eeprom_reset | |
439 | * | |
440 | * will reset EEPROM table to 0 entries. | |
441 | * | |
084fe13b | 442 | */ |
cf696091 LT |
443 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
444 | const char __user *buf, | |
445 | size_t size, loff_t *pos) | |
084fe13b | 446 | { |
bf0b91b7 GC |
447 | struct amdgpu_device *adev = |
448 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
449 | int ret; |
450 | ||
bf0b91b7 | 451 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 452 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 453 | |
cf696091 LT |
454 | if (ret > 0) { |
455 | /* Something was written to EEPROM. | |
456 | */ | |
bf0b91b7 GC |
457 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
458 | return size; | |
459 | } else { | |
cf696091 | 460 | return ret; |
bf0b91b7 | 461 | } |
084fe13b AG |
462 | } |
463 | ||
36ea1bd2 | 464 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
465 | .owner = THIS_MODULE, | |
466 | .read = NULL, | |
467 | .write = amdgpu_ras_debugfs_ctrl_write, | |
468 | .llseek = default_llseek | |
469 | }; | |
470 | ||
084fe13b AG |
471 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
472 | .owner = THIS_MODULE, | |
473 | .read = NULL, | |
474 | .write = amdgpu_ras_debugfs_eeprom_write, | |
475 | .llseek = default_llseek | |
476 | }; | |
477 | ||
f77c7109 AD |
478 | /** |
479 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
480 | * | |
ef177d11 | 481 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
482 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
483 | * | |
484 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
485 | * (ce) error counts. | |
486 | * | |
487 | * The format of one line is below, | |
488 | * | |
489 | * [ce|ue]: count | |
490 | * | |
491 | * Example: | |
492 | * | |
493 | * .. code-block:: bash | |
494 | * | |
495 | * ue: 0 | |
496 | * ce: 1 | |
497 | * | |
498 | */ | |
c030f2e4 | 499 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
500 | struct device_attribute *attr, char *buf) | |
501 | { | |
502 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
503 | struct ras_query_if info = { | |
504 | .head = obj->head, | |
505 | }; | |
506 | ||
61380faa | 507 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 508 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 509 | |
761d86d3 | 510 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 511 | return -EINVAL; |
512 | ||
1f0d8e37 MJ |
513 | |
514 | if (obj->adev->asic_type == CHIP_ALDEBARAN) { | |
515 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) | |
516 | DRM_WARN("Failed to reset error counter and error status"); | |
517 | } | |
518 | ||
36000c7a TT |
519 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
520 | "ce", info.ce_count); | |
c030f2e4 | 521 | } |
522 | ||
523 | /* obj begin */ | |
524 | ||
525 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
526 | #define alive_obj(obj) ((obj)->use) | |
527 | ||
528 | static inline void put_obj(struct ras_manager *obj) | |
529 | { | |
f0872686 | 530 | if (obj && (--obj->use == 0)) |
c030f2e4 | 531 | list_del(&obj->node); |
f0872686 BZ |
532 | if (obj && (obj->use < 0)) |
533 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
c030f2e4 | 534 | } |
535 | ||
536 | /* make one obj and return it. */ | |
537 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
538 | struct ras_common_if *head) | |
539 | { | |
540 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
541 | struct ras_manager *obj; | |
542 | ||
8ab0d6f0 | 543 | if (!adev->ras_enabled || !con) |
c030f2e4 | 544 | return NULL; |
545 | ||
546 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
547 | return NULL; | |
548 | ||
549 | obj = &con->objs[head->block]; | |
550 | /* already exist. return obj? */ | |
551 | if (alive_obj(obj)) | |
552 | return NULL; | |
553 | ||
554 | obj->head = *head; | |
555 | obj->adev = adev; | |
556 | list_add(&obj->node, &con->head); | |
557 | get_obj(obj); | |
558 | ||
559 | return obj; | |
560 | } | |
561 | ||
562 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 563 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 564 | struct ras_common_if *head) |
565 | { | |
566 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
567 | struct ras_manager *obj; | |
568 | int i; | |
569 | ||
8ab0d6f0 | 570 | if (!adev->ras_enabled || !con) |
c030f2e4 | 571 | return NULL; |
572 | ||
573 | if (head) { | |
574 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
575 | return NULL; | |
576 | ||
577 | obj = &con->objs[head->block]; | |
578 | ||
579 | if (alive_obj(obj)) { | |
580 | WARN_ON(head->block != obj->head.block); | |
581 | return obj; | |
582 | } | |
583 | } else { | |
584 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
585 | obj = &con->objs[i]; | |
586 | if (alive_obj(obj)) { | |
587 | WARN_ON(i != obj->head.block); | |
588 | return obj; | |
589 | } | |
590 | } | |
591 | } | |
592 | ||
593 | return NULL; | |
594 | } | |
595 | /* obj end */ | |
596 | ||
597 | /* feature ctl begin */ | |
598 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 599 | struct ras_common_if *head) |
c030f2e4 | 600 | { |
8ab0d6f0 | 601 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 602 | } |
603 | ||
604 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
605 | struct ras_common_if *head) | |
606 | { | |
607 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
608 | ||
609 | return con->features & BIT(head->block); | |
610 | } | |
611 | ||
612 | /* | |
613 | * if obj is not created, then create one. | |
614 | * set feature enable flag. | |
615 | */ | |
616 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
617 | struct ras_common_if *head, int enable) | |
618 | { | |
619 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
620 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
621 | ||
5caf466a | 622 | /* If hardware does not support ras, then do not create obj. |
623 | * But if hardware support ras, we can create the obj. | |
624 | * Ras framework checks con->hw_supported to see if it need do | |
625 | * corresponding initialization. | |
626 | * IP checks con->support to see if it need disable ras. | |
627 | */ | |
c030f2e4 | 628 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
629 | return 0; | |
630 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
631 | return 0; | |
632 | ||
633 | if (enable) { | |
634 | if (!obj) { | |
635 | obj = amdgpu_ras_create_obj(adev, head); | |
636 | if (!obj) | |
637 | return -EINVAL; | |
638 | } else { | |
639 | /* In case we create obj somewhere else */ | |
640 | get_obj(obj); | |
641 | } | |
642 | con->features |= BIT(head->block); | |
643 | } else { | |
644 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 645 | con->features &= ~BIT(head->block); |
c030f2e4 | 646 | put_obj(obj); |
647 | } | |
648 | } | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | /* wrapper of psp_ras_enable_features */ | |
654 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
655 | struct ras_common_if *head, bool enable) | |
656 | { | |
657 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 658 | union ta_ras_cmd_input *info; |
c030f2e4 | 659 | int ret; |
660 | ||
661 | if (!con) | |
662 | return -EINVAL; | |
663 | ||
f3729f7b | 664 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
665 | if (!info) |
666 | return -ENOMEM; | |
667 | ||
c030f2e4 | 668 | if (!enable) { |
7fcffecf | 669 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 670 | .block_id = amdgpu_ras_block_to_ta(head->block), |
671 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 672 | }; |
673 | } else { | |
7fcffecf | 674 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 675 | .block_id = amdgpu_ras_block_to_ta(head->block), |
676 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 677 | }; |
678 | } | |
679 | ||
680 | /* Do not enable if it is not allowed. */ | |
681 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
682 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
683 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
684 | ret = 0; | |
685 | goto out; | |
686 | } | |
c030f2e4 | 687 | |
bff77e86 | 688 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 689 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 690 | if (ret) { |
011907fd DL |
691 | dev_err(adev->dev, "ras %s %s failed %d\n", |
692 | enable ? "enable":"disable", | |
693 | ras_block_str(head->block), | |
694 | ret); | |
7fcffecf | 695 | goto out; |
bff77e86 | 696 | } |
c030f2e4 | 697 | } |
698 | ||
699 | /* setup the obj */ | |
700 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
701 | ret = 0; |
702 | out: | |
703 | kfree(info); | |
704 | return ret; | |
c030f2e4 | 705 | } |
706 | ||
77de502b | 707 | /* Only used in device probe stage and called only once. */ |
708 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
709 | struct ras_common_if *head, bool enable) | |
710 | { | |
711 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
712 | int ret; | |
713 | ||
714 | if (!con) | |
715 | return -EINVAL; | |
716 | ||
717 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 718 | if (enable) { |
719 | /* There is no harm to issue a ras TA cmd regardless of | |
720 | * the currecnt ras state. | |
721 | * If current state == target state, it will do nothing | |
722 | * But sometimes it requests driver to reset and repost | |
723 | * with error code -EAGAIN. | |
724 | */ | |
725 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
726 | /* With old ras TA, we might fail to enable ras. | |
727 | * Log it and just setup the object. | |
728 | * TODO need remove this WA in the future. | |
729 | */ | |
730 | if (ret == -EINVAL) { | |
731 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
732 | if (!ret) | |
6952e99c GC |
733 | dev_info(adev->dev, |
734 | "RAS INFO: %s setup object\n", | |
7af23ebe | 735 | ras_block_str(head->block)); |
736 | } | |
737 | } else { | |
738 | /* setup the object then issue a ras TA disable cmd.*/ | |
739 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
740 | if (ret) | |
741 | return ret; | |
77de502b | 742 | |
970fd197 SY |
743 | /* gfx block ras dsiable cmd must send to ras-ta */ |
744 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
745 | con->features |= BIT(head->block); | |
746 | ||
77de502b | 747 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
748 | |
749 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 750 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 751 | con->features &= ~BIT(head->block); |
7af23ebe | 752 | } |
77de502b | 753 | } else |
754 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
755 | ||
756 | return ret; | |
757 | } | |
758 | ||
c030f2e4 | 759 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
760 | bool bypass) | |
761 | { | |
762 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
763 | struct ras_manager *obj, *tmp; | |
764 | ||
765 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
766 | /* bypass psp. | |
767 | * aka just release the obj and corresponding flags | |
768 | */ | |
769 | if (bypass) { | |
770 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
771 | break; | |
772 | } else { | |
773 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
774 | break; | |
775 | } | |
289d513b | 776 | } |
c030f2e4 | 777 | |
778 | return con->features; | |
779 | } | |
780 | ||
781 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
782 | bool bypass) | |
783 | { | |
784 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
785 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
786 | int i; | |
191051a1 | 787 | const enum amdgpu_ras_error_type default_ras_type = |
788 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 789 | |
790 | for (i = 0; i < ras_block_count; i++) { | |
791 | struct ras_common_if head = { | |
792 | .block = i, | |
191051a1 | 793 | .type = default_ras_type, |
c030f2e4 | 794 | .sub_block_index = 0, |
795 | }; | |
796 | strcpy(head.name, ras_block_str(i)); | |
797 | if (bypass) { | |
798 | /* | |
799 | * bypass psp. vbios enable ras for us. | |
800 | * so just create the obj | |
801 | */ | |
802 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
803 | break; | |
804 | } else { | |
805 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
806 | break; | |
807 | } | |
289d513b | 808 | } |
c030f2e4 | 809 | |
810 | return con->features; | |
811 | } | |
812 | /* feature ctl end */ | |
813 | ||
814 | /* query/inject/cure begin */ | |
761d86d3 DL |
815 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
816 | struct ras_query_if *info) | |
c030f2e4 | 817 | { |
818 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 819 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 820 | int i; |
c030f2e4 | 821 | |
822 | if (!obj) | |
823 | return -EINVAL; | |
c030f2e4 | 824 | |
939e2258 HZ |
825 | switch (info->head.block) { |
826 | case AMDGPU_RAS_BLOCK__UMC: | |
49070c4e HZ |
827 | if (adev->umc.ras_funcs && |
828 | adev->umc.ras_funcs->query_ras_error_count) | |
829 | adev->umc.ras_funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
830 | /* umc query_ras_error_address is also responsible for clearing |
831 | * error status | |
832 | */ | |
49070c4e HZ |
833 | if (adev->umc.ras_funcs && |
834 | adev->umc.ras_funcs->query_ras_error_address) | |
835 | adev->umc.ras_funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 836 | break; |
3e81ee9a HZ |
837 | case AMDGPU_RAS_BLOCK__SDMA: |
838 | if (adev->sdma.funcs->query_ras_error_count) { | |
839 | for (i = 0; i < adev->sdma.num_instances; i++) | |
840 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
841 | &err_data); | |
842 | } | |
843 | break; | |
83b0582c | 844 | case AMDGPU_RAS_BLOCK__GFX: |
719a9b33 HZ |
845 | if (adev->gfx.ras_funcs && |
846 | adev->gfx.ras_funcs->query_ras_error_count) | |
847 | adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 848 | |
719a9b33 HZ |
849 | if (adev->gfx.ras_funcs && |
850 | adev->gfx.ras_funcs->query_ras_error_status) | |
851 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
83b0582c | 852 | break; |
9fb2d8de | 853 | case AMDGPU_RAS_BLOCK__MMHUB: |
8bc7b360 HZ |
854 | if (adev->mmhub.ras_funcs && |
855 | adev->mmhub.ras_funcs->query_ras_error_count) | |
856 | adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 857 | |
8bc7b360 HZ |
858 | if (adev->mmhub.ras_funcs && |
859 | adev->mmhub.ras_funcs->query_ras_error_status) | |
860 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
9fb2d8de | 861 | break; |
d7bd680d | 862 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
6e36f231 HZ |
863 | if (adev->nbio.ras_funcs && |
864 | adev->nbio.ras_funcs->query_ras_error_count) | |
865 | adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data); | |
d7bd680d | 866 | break; |
ec01fe2d | 867 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
52137ca8 HZ |
868 | if (adev->gmc.xgmi.ras_funcs && |
869 | adev->gmc.xgmi.ras_funcs->query_ras_error_count) | |
870 | adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data); | |
ec01fe2d | 871 | break; |
78871b6c HZ |
872 | case AMDGPU_RAS_BLOCK__HDP: |
873 | if (adev->hdp.ras_funcs && | |
874 | adev->hdp.ras_funcs->query_ras_error_count) | |
875 | adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data); | |
876 | break; | |
939e2258 HZ |
877 | default: |
878 | break; | |
879 | } | |
05a58345 TZ |
880 | |
881 | obj->err_data.ue_count += err_data.ue_count; | |
882 | obj->err_data.ce_count += err_data.ce_count; | |
883 | ||
c030f2e4 | 884 | info->ue_count = obj->err_data.ue_count; |
885 | info->ce_count = obj->err_data.ce_count; | |
886 | ||
7c6e68c7 | 887 | if (err_data.ce_count) { |
a30f1286 HZ |
888 | if (adev->smuio.funcs && |
889 | adev->smuio.funcs->get_socket_id && | |
890 | adev->smuio.funcs->get_die_id) { | |
891 | dev_info(adev->dev, "socket: %d, die: %d " | |
892 | "%ld correctable hardware errors " | |
6952e99c GC |
893 | "detected in %s block, no user " |
894 | "action is needed.\n", | |
a30f1286 HZ |
895 | adev->smuio.funcs->get_socket_id(adev), |
896 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c GC |
897 | obj->err_data.ce_count, |
898 | ras_block_str(info->head.block)); | |
a30f1286 HZ |
899 | } else { |
900 | dev_info(adev->dev, "%ld correctable hardware errors " | |
6952e99c GC |
901 | "detected in %s block, no user " |
902 | "action is needed.\n", | |
903 | obj->err_data.ce_count, | |
904 | ras_block_str(info->head.block)); | |
a30f1286 | 905 | } |
7c6e68c7 AG |
906 | } |
907 | if (err_data.ue_count) { | |
a30f1286 HZ |
908 | if (adev->smuio.funcs && |
909 | adev->smuio.funcs->get_socket_id && | |
910 | adev->smuio.funcs->get_die_id) { | |
911 | dev_info(adev->dev, "socket: %d, die: %d " | |
912 | "%ld uncorrectable hardware errors " | |
6952e99c | 913 | "detected in %s block\n", |
a30f1286 HZ |
914 | adev->smuio.funcs->get_socket_id(adev), |
915 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c GC |
916 | obj->err_data.ue_count, |
917 | ras_block_str(info->head.block)); | |
a30f1286 HZ |
918 | } else { |
919 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
6952e99c GC |
920 | "detected in %s block\n", |
921 | obj->err_data.ue_count, | |
922 | ras_block_str(info->head.block)); | |
a30f1286 | 923 | } |
7c6e68c7 | 924 | } |
05a58345 | 925 | |
c030f2e4 | 926 | return 0; |
927 | } | |
928 | ||
761d86d3 DL |
929 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
930 | enum amdgpu_ras_block block) | |
931 | { | |
932 | if (!amdgpu_ras_is_supported(adev, block)) | |
933 | return -EINVAL; | |
934 | ||
935 | switch (block) { | |
936 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
937 | if (adev->gfx.ras_funcs && |
938 | adev->gfx.ras_funcs->reset_ras_error_count) | |
939 | adev->gfx.ras_funcs->reset_ras_error_count(adev); | |
761d86d3 | 940 | |
719a9b33 HZ |
941 | if (adev->gfx.ras_funcs && |
942 | adev->gfx.ras_funcs->reset_ras_error_status) | |
943 | adev->gfx.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
944 | break; |
945 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
946 | if (adev->mmhub.ras_funcs && |
947 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
948 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
7780f503 DL |
949 | |
950 | if (adev->mmhub.ras_funcs && | |
951 | adev->mmhub.ras_funcs->reset_ras_error_status) | |
952 | adev->mmhub.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
953 | break; |
954 | case AMDGPU_RAS_BLOCK__SDMA: | |
955 | if (adev->sdma.funcs->reset_ras_error_count) | |
956 | adev->sdma.funcs->reset_ras_error_count(adev); | |
957 | break; | |
78871b6c HZ |
958 | case AMDGPU_RAS_BLOCK__HDP: |
959 | if (adev->hdp.ras_funcs && | |
960 | adev->hdp.ras_funcs->reset_ras_error_count) | |
961 | adev->hdp.ras_funcs->reset_ras_error_count(adev); | |
962 | break; | |
761d86d3 DL |
963 | default: |
964 | break; | |
965 | } | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
5c23e9e0 | 970 | /* Trigger XGMI/WAFL error */ |
f3167919 | 971 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
972 | struct ta_ras_trigger_error_input *block_info) |
973 | { | |
974 | int ret; | |
975 | ||
976 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
977 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
978 | ||
979 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
980 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
981 | ||
982 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
983 | ||
984 | if (amdgpu_ras_intr_triggered()) | |
985 | return ret; | |
986 | ||
987 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
988 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
989 | ||
fe2d9f5a | 990 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) |
5c23e9e0 JC |
991 | dev_warn(adev->dev, "Failed to allow df cstate"); |
992 | ||
993 | return ret; | |
994 | } | |
995 | ||
c030f2e4 | 996 | /* wrapper of psp_ras_trigger_error */ |
997 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
998 | struct ras_inject_if *info) | |
999 | { | |
1000 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1001 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1002 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1003 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1004 | .sub_block_index = info->head.sub_block_index, |
1005 | .address = info->address, | |
1006 | .value = info->value, | |
1007 | }; | |
1008 | int ret = 0; | |
1009 | ||
1010 | if (!obj) | |
1011 | return -EINVAL; | |
1012 | ||
a6c44d25 JC |
1013 | /* Calculate XGMI relative offset */ |
1014 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
1015 | block_info.address = |
1016 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1017 | block_info.address); | |
a6c44d25 JC |
1018 | } |
1019 | ||
83b0582c DL |
1020 | switch (info->head.block) { |
1021 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1022 | if (adev->gfx.ras_funcs && |
1023 | adev->gfx.ras_funcs->ras_error_inject) | |
1024 | ret = adev->gfx.ras_funcs->ras_error_inject(adev, info); | |
83b0582c DL |
1025 | else |
1026 | ret = -EINVAL; | |
1027 | break; | |
1028 | case AMDGPU_RAS_BLOCK__UMC: | |
5a434527 | 1029 | case AMDGPU_RAS_BLOCK__SDMA: |
9fb2d8de | 1030 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 1031 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
1032 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
1033 | break; | |
5c23e9e0 JC |
1034 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
1035 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
1036 | break; | |
83b0582c | 1037 | default: |
6952e99c | 1038 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 1039 | ras_block_str(info->head.block)); |
83b0582c | 1040 | ret = -EINVAL; |
a5dd40ca HZ |
1041 | } |
1042 | ||
011907fd DL |
1043 | if (ret) |
1044 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
1045 | ras_block_str(info->head.block), ret); | |
c030f2e4 | 1046 | |
1047 | return ret; | |
1048 | } | |
1049 | ||
c030f2e4 | 1050 | /* get the total error counts on all IPs */ |
a46751fb LT |
1051 | void amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
1052 | unsigned long *ce_count, | |
1053 | unsigned long *ue_count) | |
c030f2e4 | 1054 | { |
1055 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1056 | struct ras_manager *obj; | |
a46751fb | 1057 | unsigned long ce, ue; |
c030f2e4 | 1058 | |
8ab0d6f0 | 1059 | if (!adev->ras_enabled || !con) |
a46751fb | 1060 | return; |
c030f2e4 | 1061 | |
a46751fb LT |
1062 | ce = 0; |
1063 | ue = 0; | |
c030f2e4 | 1064 | list_for_each_entry(obj, &con->head, node) { |
1065 | struct ras_query_if info = { | |
1066 | .head = obj->head, | |
1067 | }; | |
1068 | ||
761d86d3 | 1069 | if (amdgpu_ras_query_error_status(adev, &info)) |
a46751fb | 1070 | return; |
c030f2e4 | 1071 | |
a46751fb LT |
1072 | ce += info.ce_count; |
1073 | ue += info.ue_count; | |
c030f2e4 | 1074 | } |
1075 | ||
a46751fb LT |
1076 | if (ce_count) |
1077 | *ce_count = ce; | |
1078 | ||
1079 | if (ue_count) | |
1080 | *ue_count = ue; | |
c030f2e4 | 1081 | } |
1082 | /* query/inject/cure end */ | |
1083 | ||
1084 | ||
1085 | /* sysfs begin */ | |
1086 | ||
466b1793 | 1087 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1088 | struct ras_badpage **bps, unsigned int *count); | |
1089 | ||
1090 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1091 | { | |
1092 | switch (flags) { | |
52dd95f2 | 1093 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1094 | return "R"; |
52dd95f2 | 1095 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1096 | return "P"; |
52dd95f2 | 1097 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1098 | default: |
1099 | return "F"; | |
aec576f9 | 1100 | } |
466b1793 | 1101 | } |
1102 | ||
f77c7109 AD |
1103 | /** |
1104 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1105 | * |
1106 | * It allows user to read the bad pages of vram on the gpu through | |
1107 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1108 | * | |
1109 | * It outputs multiple lines, and each line stands for one gpu page. | |
1110 | * | |
1111 | * The format of one line is below, | |
1112 | * gpu pfn : gpu page size : flags | |
1113 | * | |
1114 | * gpu pfn and gpu page size are printed in hex format. | |
1115 | * flags can be one of below character, | |
f77c7109 | 1116 | * |
466b1793 | 1117 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1118 | * |
466b1793 | 1119 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1120 | * in next window of page_reserve. |
1121 | * | |
466b1793 | 1122 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1123 | * | |
f77c7109 AD |
1124 | * Examples: |
1125 | * | |
1126 | * .. code-block:: bash | |
1127 | * | |
1128 | * 0x00000001 : 0x00001000 : R | |
1129 | * 0x00000002 : 0x00001000 : P | |
1130 | * | |
466b1793 | 1131 | */ |
1132 | ||
1133 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1134 | struct kobject *kobj, struct bin_attribute *attr, | |
1135 | char *buf, loff_t ppos, size_t count) | |
1136 | { | |
1137 | struct amdgpu_ras *con = | |
1138 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1139 | struct amdgpu_device *adev = con->adev; | |
1140 | const unsigned int element_size = | |
1141 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1142 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1143 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1144 | ssize_t s = 0; |
1145 | struct ras_badpage *bps = NULL; | |
1146 | unsigned int bps_count = 0; | |
1147 | ||
1148 | memset(buf, 0, count); | |
1149 | ||
1150 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1151 | return 0; | |
1152 | ||
1153 | for (; start < end && start < bps_count; start++) | |
1154 | s += scnprintf(&buf[s], element_size + 1, | |
1155 | "0x%08x : 0x%08x : %1s\n", | |
1156 | bps[start].bp, | |
1157 | bps[start].size, | |
1158 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1159 | ||
1160 | kfree(bps); | |
1161 | ||
1162 | return s; | |
1163 | } | |
1164 | ||
c030f2e4 | 1165 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1166 | struct device_attribute *attr, char *buf) | |
1167 | { | |
1168 | struct amdgpu_ras *con = | |
1169 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1170 | |
5212a3bd | 1171 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1172 | } |
1173 | ||
f848159b GC |
1174 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1175 | { | |
1176 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1177 | ||
1178 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1179 | &con->badpages_attr.attr, | |
1180 | RAS_FS_NAME); | |
1181 | } | |
1182 | ||
c030f2e4 | 1183 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1184 | { | |
1185 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1186 | struct attribute *attrs[] = { | |
1187 | &con->features_attr.attr, | |
1188 | NULL | |
1189 | }; | |
1190 | struct attribute_group group = { | |
eb0c3cd4 | 1191 | .name = RAS_FS_NAME, |
c030f2e4 | 1192 | .attrs = attrs, |
1193 | }; | |
1194 | ||
1195 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1201 | struct ras_fs_if *head) | |
1202 | { | |
1203 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1204 | ||
1205 | if (!obj || obj->attr_inuse) | |
1206 | return -EINVAL; | |
1207 | ||
1208 | get_obj(obj); | |
1209 | ||
1210 | memcpy(obj->fs_data.sysfs_name, | |
1211 | head->sysfs_name, | |
1212 | sizeof(obj->fs_data.sysfs_name)); | |
1213 | ||
1214 | obj->sysfs_attr = (struct device_attribute){ | |
1215 | .attr = { | |
1216 | .name = obj->fs_data.sysfs_name, | |
1217 | .mode = S_IRUGO, | |
1218 | }, | |
1219 | .show = amdgpu_ras_sysfs_read, | |
1220 | }; | |
163def43 | 1221 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1222 | |
1223 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1224 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1225 | RAS_FS_NAME)) { |
c030f2e4 | 1226 | put_obj(obj); |
1227 | return -EINVAL; | |
1228 | } | |
1229 | ||
1230 | obj->attr_inuse = 1; | |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1236 | struct ras_common_if *head) | |
1237 | { | |
1238 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1239 | ||
1240 | if (!obj || !obj->attr_inuse) | |
1241 | return -EINVAL; | |
1242 | ||
1243 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1244 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1245 | RAS_FS_NAME); |
c030f2e4 | 1246 | obj->attr_inuse = 0; |
1247 | put_obj(obj); | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1253 | { | |
1254 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1255 | struct ras_manager *obj, *tmp; | |
1256 | ||
1257 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1258 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1259 | } | |
1260 | ||
f848159b GC |
1261 | if (amdgpu_bad_page_threshold != 0) |
1262 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1263 | ||
c030f2e4 | 1264 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1265 | ||
1266 | return 0; | |
1267 | } | |
1268 | /* sysfs end */ | |
1269 | ||
ef177d11 AD |
1270 | /** |
1271 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1272 | * | |
1273 | * Normally when there is an uncorrectable error, the driver will reset | |
1274 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1275 | * the driver provides an interface to reboot the system automatically | |
1276 | * in that event. | |
1277 | * | |
1278 | * The following file in debugfs provides that interface: | |
1279 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1280 | * | |
1281 | * Usage: | |
1282 | * | |
1283 | * .. code-block:: bash | |
1284 | * | |
1285 | * echo true > .../ras/auto_reboot | |
1286 | * | |
1287 | */ | |
c030f2e4 | 1288 | /* debugfs begin */ |
ea1b8c9b | 1289 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1290 | { |
1291 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
ef0d7d20 LT |
1292 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1293 | struct dentry *dir; | |
36ea1bd2 | 1294 | |
88293c03 ND |
1295 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1296 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1297 | &amdgpu_ras_debugfs_ctrl_ops); | |
1298 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1299 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1300 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1301 | &con->bad_page_cnt_threshold); | |
ef0d7d20 LT |
1302 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1303 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c688a06b GC |
1304 | |
1305 | /* | |
1306 | * After one uncorrectable error happens, usually GPU recovery will | |
1307 | * be scheduled. But due to the known problem in GPU recovery failing | |
1308 | * to bring GPU back, below interface provides one direct way to | |
1309 | * user to reboot system automatically in such case within | |
1310 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1311 | * will never be called. | |
1312 | */ | |
88293c03 | 1313 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1314 | |
1315 | /* | |
1316 | * User could set this not to clean up hardware's error count register | |
1317 | * of RAS IPs during ras recovery. | |
1318 | */ | |
88293c03 ND |
1319 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1320 | &con->disable_ras_err_cnt_harvest); | |
1321 | return dir; | |
36ea1bd2 | 1322 | } |
1323 | ||
cedf7884 | 1324 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1325 | struct ras_fs_if *head, |
1326 | struct dentry *dir) | |
c030f2e4 | 1327 | { |
c030f2e4 | 1328 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1329 | |
88293c03 | 1330 | if (!obj || !dir) |
450f30ea | 1331 | return; |
c030f2e4 | 1332 | |
1333 | get_obj(obj); | |
1334 | ||
1335 | memcpy(obj->fs_data.debugfs_name, | |
1336 | head->debugfs_name, | |
1337 | sizeof(obj->fs_data.debugfs_name)); | |
1338 | ||
88293c03 ND |
1339 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1340 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1341 | } |
1342 | ||
f9317014 TZ |
1343 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1344 | { | |
1345 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1346 | struct dentry *dir; |
c1509f3f | 1347 | struct ras_manager *obj; |
f9317014 TZ |
1348 | struct ras_fs_if fs_info; |
1349 | ||
1350 | /* | |
1351 | * it won't be called in resume path, no need to check | |
1352 | * suspend and gpu reset status | |
1353 | */ | |
cedf7884 | 1354 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1355 | return; |
1356 | ||
88293c03 | 1357 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1358 | |
c1509f3f | 1359 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1360 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1361 | (obj->attr_inuse == 1)) { | |
1362 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1363 | ras_block_str(obj->head.block)); | |
1364 | fs_info.head = obj->head; | |
88293c03 | 1365 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1366 | } |
1367 | } | |
1368 | } | |
1369 | ||
c030f2e4 | 1370 | /* debugfs end */ |
1371 | ||
1372 | /* ras fs */ | |
c3d4d45d GC |
1373 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1374 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1375 | static DEVICE_ATTR(features, S_IRUGO, | |
1376 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1377 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1378 | { | |
c3d4d45d GC |
1379 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1380 | struct attribute_group group = { | |
1381 | .name = RAS_FS_NAME, | |
1382 | }; | |
1383 | struct attribute *attrs[] = { | |
1384 | &con->features_attr.attr, | |
1385 | NULL | |
1386 | }; | |
1387 | struct bin_attribute *bin_attrs[] = { | |
1388 | NULL, | |
1389 | NULL, | |
1390 | }; | |
a069a9eb | 1391 | int r; |
c030f2e4 | 1392 | |
c3d4d45d GC |
1393 | /* add features entry */ |
1394 | con->features_attr = dev_attr_features; | |
1395 | group.attrs = attrs; | |
1396 | sysfs_attr_init(attrs[0]); | |
1397 | ||
1398 | if (amdgpu_bad_page_threshold != 0) { | |
1399 | /* add bad_page_features entry */ | |
1400 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1401 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1402 | bin_attrs[0] = &con->badpages_attr; | |
1403 | group.bin_attrs = bin_attrs; | |
1404 | sysfs_bin_attr_init(bin_attrs[0]); | |
1405 | } | |
1406 | ||
a069a9eb AD |
1407 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1408 | if (r) | |
1409 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1410 | |
c030f2e4 | 1411 | return 0; |
1412 | } | |
1413 | ||
1414 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1415 | { | |
88293c03 ND |
1416 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1417 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1418 | ||
1419 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1420 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1421 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1422 | if (ip_obj) | |
1423 | put_obj(ip_obj); | |
1424 | } | |
1425 | } | |
1426 | ||
c030f2e4 | 1427 | amdgpu_ras_sysfs_remove_all(adev); |
1428 | return 0; | |
1429 | } | |
1430 | /* ras fs end */ | |
1431 | ||
1432 | /* ih begin */ | |
1433 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1434 | { | |
1435 | struct ras_ih_data *data = &obj->ih_data; | |
1436 | struct amdgpu_iv_entry entry; | |
1437 | int ret; | |
cf04dfd0 | 1438 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1439 | |
1440 | while (data->rptr != data->wptr) { | |
1441 | rmb(); | |
1442 | memcpy(&entry, &data->ring[data->rptr], | |
1443 | data->element_size); | |
1444 | ||
1445 | wmb(); | |
1446 | data->rptr = (data->aligned_element_size + | |
1447 | data->rptr) % data->ring_size; | |
1448 | ||
1449 | /* Let IP handle its data, maybe we need get the output | |
1450 | * from the callback to udpate the error type/count, etc | |
1451 | */ | |
1452 | if (data->cb) { | |
cf04dfd0 | 1453 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1454 | /* ue will trigger an interrupt, and in that case |
1455 | * we need do a reset to recovery the whole system. | |
1456 | * But leave IP do that recovery, here we just dispatch | |
1457 | * the error. | |
1458 | */ | |
bd2280da | 1459 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1460 | /* these counts could be left as 0 if |
1461 | * some blocks do not count error number | |
1462 | */ | |
cf04dfd0 | 1463 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1464 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1465 | } |
c030f2e4 | 1466 | } |
1467 | } | |
1468 | } | |
1469 | ||
1470 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1471 | { | |
1472 | struct ras_ih_data *data = | |
1473 | container_of(work, struct ras_ih_data, ih_work); | |
1474 | struct ras_manager *obj = | |
1475 | container_of(data, struct ras_manager, ih_data); | |
1476 | ||
1477 | amdgpu_ras_interrupt_handler(obj); | |
1478 | } | |
1479 | ||
1480 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1481 | struct ras_dispatch_if *info) | |
1482 | { | |
1483 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1484 | struct ras_ih_data *data = &obj->ih_data; | |
1485 | ||
1486 | if (!obj) | |
1487 | return -EINVAL; | |
1488 | ||
1489 | if (data->inuse == 0) | |
1490 | return 0; | |
1491 | ||
1492 | /* Might be overflow... */ | |
1493 | memcpy(&data->ring[data->wptr], info->entry, | |
1494 | data->element_size); | |
1495 | ||
1496 | wmb(); | |
1497 | data->wptr = (data->aligned_element_size + | |
1498 | data->wptr) % data->ring_size; | |
1499 | ||
1500 | schedule_work(&data->ih_work); | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1506 | struct ras_ih_if *info) | |
1507 | { | |
1508 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1509 | struct ras_ih_data *data; | |
1510 | ||
1511 | if (!obj) | |
1512 | return -EINVAL; | |
1513 | ||
1514 | data = &obj->ih_data; | |
1515 | if (data->inuse == 0) | |
1516 | return 0; | |
1517 | ||
1518 | cancel_work_sync(&data->ih_work); | |
1519 | ||
1520 | kfree(data->ring); | |
1521 | memset(data, 0, sizeof(*data)); | |
1522 | put_obj(obj); | |
1523 | ||
1524 | return 0; | |
1525 | } | |
1526 | ||
1527 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1528 | struct ras_ih_if *info) | |
1529 | { | |
1530 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1531 | struct ras_ih_data *data; | |
1532 | ||
1533 | if (!obj) { | |
1534 | /* in case we registe the IH before enable ras feature */ | |
1535 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1536 | if (!obj) | |
1537 | return -EINVAL; | |
1538 | } else | |
1539 | get_obj(obj); | |
1540 | ||
1541 | data = &obj->ih_data; | |
1542 | /* add the callback.etc */ | |
1543 | *data = (struct ras_ih_data) { | |
1544 | .inuse = 0, | |
1545 | .cb = info->cb, | |
1546 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1547 | .rptr = 0, | |
1548 | .wptr = 0, | |
1549 | }; | |
1550 | ||
1551 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1552 | ||
1553 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1554 | /* the ring can store 64 iv entries. */ | |
1555 | data->ring_size = 64 * data->aligned_element_size; | |
1556 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1557 | if (!data->ring) { | |
1558 | put_obj(obj); | |
1559 | return -ENOMEM; | |
1560 | } | |
1561 | ||
1562 | /* IH is ready */ | |
1563 | data->inuse = 1; | |
1564 | ||
1565 | return 0; | |
1566 | } | |
1567 | ||
1568 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1569 | { | |
1570 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1571 | struct ras_manager *obj, *tmp; | |
1572 | ||
1573 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1574 | struct ras_ih_if info = { | |
1575 | .head = obj->head, | |
1576 | }; | |
1577 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | /* ih end */ | |
1583 | ||
313c8fd3 GC |
1584 | /* traversal all IPs except NBIO to query error counter */ |
1585 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1586 | { | |
1587 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1588 | struct ras_manager *obj; | |
1589 | ||
8ab0d6f0 | 1590 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
1591 | return; |
1592 | ||
1593 | list_for_each_entry(obj, &con->head, node) { | |
1594 | struct ras_query_if info = { | |
1595 | .head = obj->head, | |
1596 | }; | |
1597 | ||
1598 | /* | |
1599 | * PCIE_BIF IP has one different isr by ras controller | |
1600 | * interrupt, the specific ras counter query will be | |
1601 | * done in that isr. So skip such block from common | |
1602 | * sync flood interrupt isr calling. | |
1603 | */ | |
1604 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1605 | continue; | |
1606 | ||
761d86d3 | 1607 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1608 | } |
1609 | } | |
1610 | ||
3f975d0f | 1611 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1612 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1613 | struct ras_query_if *info) | |
3f975d0f SY |
1614 | { |
1615 | /* | |
1616 | * Only two block need to query read/write | |
1617 | * RspStatus at current state | |
1618 | */ | |
1619 | switch (info->head.block) { | |
1620 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1621 | if (adev->gfx.ras_funcs && |
1622 | adev->gfx.ras_funcs->query_ras_error_status) | |
1623 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1624 | break; |
1625 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
1626 | if (adev->mmhub.ras_funcs && |
1627 | adev->mmhub.ras_funcs->query_ras_error_status) | |
1628 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1629 | break; |
1630 | default: | |
1631 | break; | |
1632 | } | |
1633 | } | |
1634 | ||
1635 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1636 | { | |
1637 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1638 | struct ras_manager *obj; | |
1639 | ||
8ab0d6f0 | 1640 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
1641 | return; |
1642 | ||
1643 | list_for_each_entry(obj, &con->head, node) { | |
1644 | struct ras_query_if info = { | |
1645 | .head = obj->head, | |
1646 | }; | |
1647 | ||
1648 | amdgpu_ras_error_status_query(adev, &info); | |
1649 | } | |
1650 | } | |
1651 | ||
c030f2e4 | 1652 | /* recovery begin */ |
466b1793 | 1653 | |
1654 | /* return 0 on success. | |
1655 | * caller need free bps. | |
1656 | */ | |
1657 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1658 | struct ras_badpage **bps, unsigned int *count) | |
1659 | { | |
1660 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1661 | struct ras_err_handler_data *data; | |
1662 | int i = 0; | |
732f2a30 | 1663 | int ret = 0, status; |
466b1793 | 1664 | |
1665 | if (!con || !con->eh_data || !bps || !count) | |
1666 | return -EINVAL; | |
1667 | ||
1668 | mutex_lock(&con->recovery_lock); | |
1669 | data = con->eh_data; | |
1670 | if (!data || data->count == 0) { | |
1671 | *bps = NULL; | |
46cf2fec | 1672 | ret = -EINVAL; |
466b1793 | 1673 | goto out; |
1674 | } | |
1675 | ||
1676 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1677 | if (!*bps) { | |
1678 | ret = -ENOMEM; | |
1679 | goto out; | |
1680 | } | |
1681 | ||
1682 | for (; i < data->count; i++) { | |
1683 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1684 | .bp = data->bps[i].retired_page, |
466b1793 | 1685 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1686 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1687 | }; |
732f2a30 | 1688 | status = amdgpu_vram_mgr_query_page_status( |
676deb38 DL |
1689 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), |
1690 | data->bps[i].retired_page); | |
732f2a30 | 1691 | if (status == -EBUSY) |
52dd95f2 | 1692 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1693 | else if (status == -ENOENT) |
52dd95f2 | 1694 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1695 | } |
1696 | ||
1697 | *count = data->count; | |
1698 | out: | |
1699 | mutex_unlock(&con->recovery_lock); | |
1700 | return ret; | |
1701 | } | |
1702 | ||
c030f2e4 | 1703 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1704 | { | |
1705 | struct amdgpu_ras *ras = | |
1706 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1707 | struct amdgpu_device *remote_adev = NULL; |
1708 | struct amdgpu_device *adev = ras->adev; | |
1709 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1710 | |
f75e94d8 | 1711 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1712 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1713 | ||
f75e94d8 GC |
1714 | /* Build list of devices to query RAS related errors */ |
1715 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1716 | device_list_handle = &hive->device_list; | |
1717 | } else { | |
1718 | INIT_LIST_HEAD(&device_list); | |
1719 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1720 | device_list_handle = &device_list; | |
1721 | } | |
c030f2e4 | 1722 | |
f75e94d8 | 1723 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1724 | device_list_handle, gmc.xgmi.head) { |
1725 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1726 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1727 | } |
d95e8e97 DL |
1728 | |
1729 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1730 | } |
313c8fd3 | 1731 | |
93af20f7 | 1732 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1733 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1734 | atomic_set(&ras->in_recovery, 0); |
1735 | } | |
1736 | ||
c030f2e4 | 1737 | /* alloc/realloc bps array */ |
1738 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1739 | struct ras_err_handler_data *data, int pages) | |
1740 | { | |
1741 | unsigned int old_space = data->count + data->space_left; | |
1742 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1743 | unsigned int align_space = ALIGN(new_space, 512); |
1744 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1745 | |
676deb38 | 1746 | if (!bps) { |
9dc23a63 | 1747 | kfree(bps); |
c030f2e4 | 1748 | return -ENOMEM; |
9dc23a63 | 1749 | } |
c030f2e4 | 1750 | |
1751 | if (data->bps) { | |
9dc23a63 | 1752 | memcpy(bps, data->bps, |
c030f2e4 | 1753 | data->count * sizeof(*data->bps)); |
1754 | kfree(data->bps); | |
1755 | } | |
1756 | ||
9dc23a63 | 1757 | data->bps = bps; |
c030f2e4 | 1758 | data->space_left += align_space - old_space; |
1759 | return 0; | |
1760 | } | |
1761 | ||
1762 | /* it deal with vram only. */ | |
1763 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1764 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1765 | { |
1766 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1767 | struct ras_err_handler_data *data; |
c030f2e4 | 1768 | int ret = 0; |
676deb38 | 1769 | uint32_t i; |
c030f2e4 | 1770 | |
73aa8e1a | 1771 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1772 | return 0; |
1773 | ||
1774 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1775 | data = con->eh_data; |
c030f2e4 | 1776 | if (!data) |
1777 | goto out; | |
1778 | ||
676deb38 DL |
1779 | for (i = 0; i < pages; i++) { |
1780 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1781 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1782 | continue; | |
1783 | ||
1784 | if (!data->space_left && | |
1785 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1786 | ret = -ENOMEM; |
1787 | goto out; | |
1788 | } | |
1789 | ||
676deb38 DL |
1790 | amdgpu_vram_mgr_reserve_range( |
1791 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1792 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1793 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1794 | |
676deb38 DL |
1795 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1796 | data->count++; | |
1797 | data->space_left--; | |
1798 | } | |
c030f2e4 | 1799 | out: |
1800 | mutex_unlock(&con->recovery_lock); | |
1801 | ||
1802 | return ret; | |
1803 | } | |
1804 | ||
78ad00c9 TZ |
1805 | /* |
1806 | * write error record array to eeprom, the function should be | |
1807 | * protected by recovery_lock | |
1808 | */ | |
22503d80 | 1809 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1810 | { |
1811 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1812 | struct ras_err_handler_data *data; | |
8a3e801f | 1813 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1814 | int save_count; |
1815 | ||
1816 | if (!con || !con->eh_data) | |
1817 | return 0; | |
1818 | ||
8a3e801f | 1819 | control = &con->eeprom_control; |
78ad00c9 TZ |
1820 | data = con->eh_data; |
1821 | save_count = data->count - control->num_recs; | |
1822 | /* only new entries are saved */ | |
b1628425 | 1823 | if (save_count > 0) { |
1fab841f LT |
1824 | if (amdgpu_ras_eeprom_write(control, |
1825 | &data->bps[control->num_recs], | |
1826 | save_count)) { | |
6952e99c | 1827 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1828 | return -EIO; |
1829 | } | |
1830 | ||
b1628425 GC |
1831 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1832 | } | |
1833 | ||
78ad00c9 TZ |
1834 | return 0; |
1835 | } | |
1836 | ||
1837 | /* | |
1838 | * read error record array in eeprom and reserve enough space for | |
1839 | * storing new bad pages | |
1840 | */ | |
1841 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1842 | { | |
1843 | struct amdgpu_ras_eeprom_control *control = | |
1844 | &adev->psp.ras.ras->eeprom_control; | |
1845 | struct eeprom_table_record *bps = NULL; | |
1846 | int ret = 0; | |
1847 | ||
1848 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1849 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1850 | return ret; |
1851 | ||
1852 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1853 | if (!bps) | |
1854 | return -ENOMEM; | |
1855 | ||
1fab841f | 1856 | if (amdgpu_ras_eeprom_read(control, bps, control->num_recs)) { |
6952e99c | 1857 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1858 | ret = -EIO; |
1859 | goto out; | |
1860 | } | |
1861 | ||
1862 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1863 | ||
1864 | out: | |
1865 | kfree(bps); | |
1866 | return ret; | |
1867 | } | |
1868 | ||
676deb38 DL |
1869 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1870 | uint64_t addr) | |
1871 | { | |
1872 | struct ras_err_handler_data *data = con->eh_data; | |
1873 | int i; | |
1874 | ||
1875 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1876 | for (i = 0; i < data->count; i++) | |
1877 | if (addr == data->bps[i].retired_page) | |
1878 | return true; | |
1879 | ||
1880 | return false; | |
1881 | } | |
1882 | ||
6e4be987 TZ |
1883 | /* |
1884 | * check if an address belongs to bad page | |
1885 | * | |
1886 | * Note: this check is only for umc block | |
1887 | */ | |
1888 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1889 | uint64_t addr) | |
1890 | { | |
1891 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1892 | bool ret = false; |
1893 | ||
1894 | if (!con || !con->eh_data) | |
1895 | return ret; | |
1896 | ||
1897 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1898 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1899 | mutex_unlock(&con->recovery_lock); |
1900 | return ret; | |
1901 | } | |
1902 | ||
e5c04edf CK |
1903 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1904 | uint32_t max_length) | |
c84d4670 | 1905 | { |
e5c04edf | 1906 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
1907 | int tmp_threshold = amdgpu_bad_page_threshold; |
1908 | u64 val; | |
1909 | ||
1910 | /* | |
1911 | * Justification of value bad_page_cnt_threshold in ras structure | |
1912 | * | |
1913 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1914 | * in eeprom, and introduce two scenarios accordingly. | |
1915 | * | |
1916 | * Bad page retirement enablement: | |
1917 | * - If amdgpu_bad_page_threshold = -1, | |
1918 | * bad_page_cnt_threshold = typical value by formula. | |
1919 | * | |
1920 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1921 | * max record length in eeprom, use it directly. | |
1922 | * | |
1923 | * Bad page retirement disablement: | |
1924 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1925 | * functionality is disabled, and bad_page_cnt_threshold will | |
1926 | * take no effect. | |
1927 | */ | |
1928 | ||
1929 | if (tmp_threshold < -1) | |
1930 | tmp_threshold = -1; | |
1931 | else if (tmp_threshold > max_length) | |
1932 | tmp_threshold = max_length; | |
1933 | ||
1934 | if (tmp_threshold == -1) { | |
e5c04edf | 1935 | val = adev->gmc.mc_vram_size; |
c84d4670 | 1936 | do_div(val, RAS_BAD_PAGE_RATE); |
e5c04edf CK |
1937 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
1938 | max_length); | |
1939 | } else { | |
1940 | con->bad_page_cnt_threshold = tmp_threshold; | |
c84d4670 GC |
1941 | } |
1942 | } | |
1943 | ||
1a6fc071 | 1944 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1945 | { |
1946 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1947 | struct ras_err_handler_data **data; |
e5c04edf | 1948 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1949 | bool exc_err_limit = false; |
78ad00c9 | 1950 | int ret; |
c030f2e4 | 1951 | |
8ab0d6f0 | 1952 | if (adev->ras_enabled && con) |
4d1337d2 AG |
1953 | data = &con->eh_data; |
1954 | else | |
1955 | return 0; | |
1956 | ||
1a6fc071 TZ |
1957 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1958 | if (!*data) { | |
1959 | ret = -ENOMEM; | |
1960 | goto out; | |
1961 | } | |
c030f2e4 | 1962 | |
1963 | mutex_init(&con->recovery_lock); | |
1964 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1965 | atomic_set(&con->in_recovery, 0); | |
1966 | con->adev = adev; | |
1967 | ||
e5c04edf CK |
1968 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1969 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
c84d4670 | 1970 | |
e5086659 | 1971 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
1972 | * when the GPU is pending on XGMI reset during probe time | |
1973 | * (Mostly after second bus reset), skip it now | |
1974 | */ | |
1975 | if (adev->gmc.xgmi.pending_reset) | |
1976 | return 0; | |
b82e65a9 GC |
1977 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1978 | /* | |
1979 | * This calling fails when exc_err_limit is true or | |
1980 | * ret != 0. | |
1981 | */ | |
1982 | if (exc_err_limit || ret) | |
1a6fc071 | 1983 | goto free; |
78ad00c9 | 1984 | |
0771b0bf | 1985 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1986 | ret = amdgpu_ras_load_bad_pages(adev); |
1987 | if (ret) | |
1a6fc071 | 1988 | goto free; |
513befa6 SY |
1989 | |
1990 | if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) | |
1991 | adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); | |
78ad00c9 | 1992 | } |
c030f2e4 | 1993 | |
1994 | return 0; | |
1a6fc071 | 1995 | |
1a6fc071 | 1996 | free: |
1a6fc071 | 1997 | kfree((*data)->bps); |
1a6fc071 | 1998 | kfree(*data); |
1995b3a3 | 1999 | con->eh_data = NULL; |
1a6fc071 | 2000 | out: |
cf696091 | 2001 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2002 | |
b82e65a9 GC |
2003 | /* |
2004 | * Except error threshold exceeding case, other failure cases in this | |
2005 | * function would not fail amdgpu driver init. | |
2006 | */ | |
2007 | if (!exc_err_limit) | |
2008 | ret = 0; | |
2009 | else | |
2010 | ret = -EINVAL; | |
2011 | ||
1a6fc071 | 2012 | return ret; |
c030f2e4 | 2013 | } |
2014 | ||
2015 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2016 | { | |
2017 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2018 | struct ras_err_handler_data *data = con->eh_data; | |
2019 | ||
1a6fc071 TZ |
2020 | /* recovery_init failed to init it, fini is useless */ |
2021 | if (!data) | |
2022 | return 0; | |
2023 | ||
c030f2e4 | 2024 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2025 | |
2026 | mutex_lock(&con->recovery_lock); | |
2027 | con->eh_data = NULL; | |
2028 | kfree(data->bps); | |
2029 | kfree(data); | |
2030 | mutex_unlock(&con->recovery_lock); | |
2031 | ||
2032 | return 0; | |
2033 | } | |
2034 | /* recovery end */ | |
2035 | ||
a564808e | 2036 | /* return 0 if ras will reset gpu and repost.*/ |
2037 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
2038 | unsigned int block) | |
2039 | { | |
2040 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2041 | ||
2042 | if (!ras) | |
2043 | return -EINVAL; | |
2044 | ||
2045 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2046 | return 0; | |
2047 | } | |
2048 | ||
084e2640 | 2049 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2050 | { |
084e2640 LT |
2051 | return adev->asic_type == CHIP_VEGA10 || |
2052 | adev->asic_type == CHIP_VEGA20 || | |
2053 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2054 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2055 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2056 | } |
2057 | ||
f50160cf SY |
2058 | /* |
2059 | * this is workaround for vega20 workstation sku, | |
2060 | * force enable gfx ras, ignore vbios gfx ras flag | |
2061 | * due to GC EDC can not write | |
2062 | */ | |
e509965e | 2063 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2064 | { |
2065 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2066 | ||
2067 | if (!ctx) | |
2068 | return; | |
2069 | ||
2070 | if (strnstr(ctx->vbios_version, "D16406", | |
e11d5e0d SY |
2071 | sizeof(ctx->vbios_version)) || |
2072 | strnstr(ctx->vbios_version, "D36002", | |
2073 | sizeof(ctx->vbios_version))) | |
8ab0d6f0 | 2074 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2075 | } |
2076 | ||
5caf466a | 2077 | /* |
2078 | * check hardware's ras ability which will be saved in hw_supported. | |
2079 | * if hardware does not support ras, we can skip some ras initializtion and | |
2080 | * forbid some ras operations from IP. | |
2081 | * if software itself, say boot parameter, limit the ras ability. We still | |
2082 | * need allow IP do some limited operations, like disable. In such case, | |
2083 | * we have to initialize ras as normal. but need check if operation is | |
2084 | * allowed or not in each function. | |
2085 | */ | |
e509965e | 2086 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2087 | { |
8ab0d6f0 | 2088 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2089 | |
88474cca | 2090 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 2091 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 2092 | return; |
b404ae82 | 2093 | |
75f06251 HZ |
2094 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2095 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2096 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2097 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2098 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2099 | } else { |
2100 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2101 | } | |
88474cca | 2102 | |
75f06251 HZ |
2103 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2104 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
8ab0d6f0 | 2105 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2106 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2107 | } else { |
2108 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2109 | } | |
2110 | } else { | |
2111 | /* driver only manages a few IP blocks RAS feature | |
2112 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2113 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2114 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2115 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2116 | } |
88474cca | 2117 | |
e509965e | 2118 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2119 | |
88474cca | 2120 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2121 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2122 | |
8ab0d6f0 LT |
2123 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2124 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2125 | } |
2126 | ||
05adfd80 LT |
2127 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2128 | { | |
2129 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2130 | ras_counte_delay_work.work); | |
2131 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2132 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2133 | unsigned long ce_count, ue_count; |
2134 | int res; | |
2135 | ||
2136 | res = pm_runtime_get_sync(dev->dev); | |
2137 | if (res < 0) | |
2138 | goto Out; | |
2139 | ||
2140 | /* Cache new values. | |
2141 | */ | |
2142 | amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
2143 | atomic_set(&con->ras_ce_count, ce_count); | |
2144 | atomic_set(&con->ras_ue_count, ue_count); | |
2145 | ||
2146 | pm_runtime_mark_last_busy(dev->dev); | |
2147 | Out: | |
2148 | pm_runtime_put_autosuspend(dev->dev); | |
2149 | } | |
2150 | ||
c030f2e4 | 2151 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2152 | { | |
2153 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2154 | int r; |
c030f2e4 | 2155 | |
b404ae82 | 2156 | if (con) |
c030f2e4 | 2157 | return 0; |
2158 | ||
2159 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
2160 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
2161 | GFP_KERNEL|__GFP_ZERO); | |
2162 | if (!con) | |
2163 | return -ENOMEM; | |
2164 | ||
05adfd80 LT |
2165 | con->adev = adev; |
2166 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2167 | atomic_set(&con->ras_ce_count, 0); | |
2168 | atomic_set(&con->ras_ue_count, 0); | |
2169 | ||
c030f2e4 | 2170 | con->objs = (struct ras_manager *)(con + 1); |
2171 | ||
2172 | amdgpu_ras_set_context(adev, con); | |
2173 | ||
e509965e LT |
2174 | amdgpu_ras_check_supported(adev); |
2175 | ||
7ddd9770 | 2176 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2177 | /* set gfx block ras context feature for VEGA20 Gaming |
2178 | * send ras disable cmd to ras ta during ras late init. | |
2179 | */ | |
8ab0d6f0 | 2180 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2181 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2182 | ||
2183 | return 0; | |
2184 | } | |
2185 | ||
5e91160a | 2186 | r = 0; |
5436ab94 | 2187 | goto release_con; |
fb2a3607 HZ |
2188 | } |
2189 | ||
c030f2e4 | 2190 | con->features = 0; |
2191 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2192 | /* Might need get this flag from vbios. */ |
2193 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2194 | |
6e36f231 HZ |
2195 | /* initialize nbio ras function ahead of any other |
2196 | * ras functions so hardware fatal error interrupt | |
2197 | * can be enabled as early as possible */ | |
2198 | switch (adev->asic_type) { | |
2199 | case CHIP_VEGA20: | |
2200 | case CHIP_ARCTURUS: | |
2201 | case CHIP_ALDEBARAN: | |
2202 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2203 | adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs; | |
2204 | break; | |
2205 | default: | |
2206 | /* nbio ras is not available */ | |
2207 | break; | |
2208 | } | |
2209 | ||
2210 | if (adev->nbio.ras_funcs && | |
2211 | adev->nbio.ras_funcs->init_ras_controller_interrupt) { | |
2212 | r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev); | |
4e644fff | 2213 | if (r) |
5436ab94 | 2214 | goto release_con; |
4e644fff HZ |
2215 | } |
2216 | ||
6e36f231 HZ |
2217 | if (adev->nbio.ras_funcs && |
2218 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) { | |
2219 | r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2220 | if (r) |
5436ab94 | 2221 | goto release_con; |
4e644fff HZ |
2222 | } |
2223 | ||
5e91160a GC |
2224 | if (amdgpu_ras_fs_init(adev)) { |
2225 | r = -EINVAL; | |
5436ab94 | 2226 | goto release_con; |
5e91160a | 2227 | } |
c030f2e4 | 2228 | |
6952e99c | 2229 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2230 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2231 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2232 | |
c030f2e4 | 2233 | return 0; |
5436ab94 | 2234 | release_con: |
c030f2e4 | 2235 | amdgpu_ras_set_context(adev, NULL); |
2236 | kfree(con); | |
2237 | ||
5e91160a | 2238 | return r; |
c030f2e4 | 2239 | } |
2240 | ||
8f6368a9 | 2241 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 JC |
2242 | { |
2243 | if (adev->gmc.xgmi.connected_to_cpu) | |
2244 | return 1; | |
2245 | return 0; | |
2246 | } | |
2247 | ||
2248 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2249 | struct ras_common_if *ras_block) | |
2250 | { | |
2251 | struct ras_query_if info = { | |
2252 | .head = *ras_block, | |
2253 | }; | |
2254 | ||
2255 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2256 | return 0; | |
2257 | ||
2258 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2259 | DRM_WARN("RAS init harvest failure"); | |
2260 | ||
2261 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2262 | DRM_WARN("RAS init harvest reset failure"); | |
2263 | ||
2264 | return 0; | |
2265 | } | |
2266 | ||
b293e891 HZ |
2267 | /* helper function to handle common stuff in ip late init phase */ |
2268 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2269 | struct ras_common_if *ras_block, | |
2270 | struct ras_fs_if *fs_info, | |
2271 | struct ras_ih_if *ih_info) | |
2272 | { | |
05adfd80 LT |
2273 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2274 | unsigned long ue_count, ce_count; | |
b293e891 HZ |
2275 | int r; |
2276 | ||
2277 | /* disable RAS feature per IP block if it is not supported */ | |
2278 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2279 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2284 | if (r) { | |
2285 | if (r == -EAGAIN) { | |
2286 | /* request gpu reset. will run again */ | |
2287 | amdgpu_ras_request_reset_on_boot(adev, | |
2288 | ras_block->block); | |
2289 | return 0; | |
53b3f8f4 | 2290 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2291 | /* in resume phase, if fail to enable ras, |
2292 | * clean up all ras fs nodes, and disable ras */ | |
2293 | goto cleanup; | |
2294 | } else | |
2295 | return r; | |
2296 | } | |
2297 | ||
134d16d5 JC |
2298 | /* check for errors on warm reset edc persisant supported ASIC */ |
2299 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2300 | ||
b293e891 | 2301 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2302 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2303 | return 0; |
2304 | ||
2305 | if (ih_info->cb) { | |
2306 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2307 | if (r) | |
2308 | goto interrupt; | |
2309 | } | |
2310 | ||
b293e891 HZ |
2311 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2312 | if (r) | |
2313 | goto sysfs; | |
2314 | ||
05adfd80 LT |
2315 | /* Those are the cached values at init. |
2316 | */ | |
2317 | amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
2318 | atomic_set(&con->ras_ce_count, ce_count); | |
2319 | atomic_set(&con->ras_ue_count, ue_count); | |
2320 | ||
b293e891 HZ |
2321 | return 0; |
2322 | cleanup: | |
2323 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2324 | sysfs: | |
b293e891 HZ |
2325 | if (ih_info->cb) |
2326 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2327 | interrupt: | |
2328 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2329 | return r; | |
2330 | } | |
2331 | ||
2332 | /* helper function to remove ras fs node and interrupt handler */ | |
2333 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2334 | struct ras_common_if *ras_block, | |
2335 | struct ras_ih_if *ih_info) | |
2336 | { | |
2337 | if (!ras_block || !ih_info) | |
2338 | return; | |
2339 | ||
2340 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2341 | if (ih_info->cb) |
f3729f7b | 2342 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2343 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2344 | } | |
2345 | ||
a564808e | 2346 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2347 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2348 | */ |
511fdbc3 | 2349 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2350 | { |
2351 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2352 | struct ras_manager *obj, *tmp; | |
2353 | ||
8ab0d6f0 | 2354 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2355 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2356 | amdgpu_release_ras_context(adev); | |
2357 | ||
108c6a63 | 2358 | return; |
970fd197 | 2359 | } |
108c6a63 | 2360 | |
108c6a63 | 2361 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2362 | /* Set up all other IPs which are not implemented. There is a |
2363 | * tricky thing that IP's actual ras error type should be | |
2364 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2365 | * ERROR_NONE make sense anyway. | |
2366 | */ | |
2367 | amdgpu_ras_enable_all_features(adev, 1); | |
2368 | ||
2369 | /* We enable ras on all hw_supported block, but as boot | |
2370 | * parameter might disable some of them and one or more IP has | |
2371 | * not implemented yet. So we disable them on behalf. | |
2372 | */ | |
108c6a63 | 2373 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2374 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2375 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2376 | /* there should be no any reference. */ | |
2377 | WARN_ON(alive_obj(obj)); | |
2378 | } | |
191051a1 | 2379 | } |
108c6a63 | 2380 | } |
a564808e | 2381 | |
2382 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2383 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2384 | /* setup ras obj state as disabled. | |
2385 | * for init_by_vbios case. | |
2386 | * if we want to enable ras, just enable it in a normal way. | |
2387 | * If we want do disable it, need setup ras obj as enabled, | |
2388 | * then issue another TA disable cmd. | |
2389 | * See feature_enable_on_boot | |
2390 | */ | |
2391 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2392 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2393 | } |
108c6a63 | 2394 | } |
2395 | ||
511fdbc3 | 2396 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2397 | { | |
2398 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2399 | ||
8ab0d6f0 | 2400 | if (!adev->ras_enabled || !con) |
511fdbc3 | 2401 | return; |
2402 | ||
2403 | amdgpu_ras_disable_all_features(adev, 0); | |
2404 | /* Make sure all ras objects are disabled. */ | |
2405 | if (con->features) | |
2406 | amdgpu_ras_disable_all_features(adev, 1); | |
2407 | } | |
2408 | ||
c030f2e4 | 2409 | /* do some fini work before IP fini as dependence */ |
2410 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2411 | { | |
2412 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2413 | ||
8ab0d6f0 | 2414 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2415 | return 0; |
2416 | ||
72c8c97b | 2417 | |
c030f2e4 | 2418 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
2419 | amdgpu_ras_disable_all_features(adev, 0); | |
2420 | amdgpu_ras_recovery_fini(adev); | |
2421 | return 0; | |
2422 | } | |
2423 | ||
2424 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2425 | { | |
2426 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2427 | ||
8ab0d6f0 | 2428 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2429 | return 0; |
2430 | ||
2431 | amdgpu_ras_fs_fini(adev); | |
2432 | amdgpu_ras_interrupt_remove_all(adev); | |
2433 | ||
2434 | WARN(con->features, "Feature mask is not cleared"); | |
2435 | ||
2436 | if (con->features) | |
2437 | amdgpu_ras_disable_all_features(adev, 1); | |
2438 | ||
05adfd80 LT |
2439 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
2440 | ||
c030f2e4 | 2441 | amdgpu_ras_set_context(adev, NULL); |
2442 | kfree(con); | |
2443 | ||
2444 | return 0; | |
2445 | } | |
7c6e68c7 AG |
2446 | |
2447 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2448 | { | |
e509965e | 2449 | amdgpu_ras_check_supported(adev); |
8ab0d6f0 | 2450 | if (!adev->ras_hw_enabled) |
ed606f8a AG |
2451 | return; |
2452 | ||
7c6e68c7 | 2453 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2454 | dev_info(adev->dev, "uncorrectable hardware error" |
2455 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2456 | |
61934624 | 2457 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2458 | } |
2459 | } | |
bb5c7235 WS |
2460 | |
2461 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2462 | { | |
2463 | if (adev->asic_type == CHIP_VEGA20 && | |
2464 | adev->pm.fw_version <= 0x283400) { | |
2465 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2466 | amdgpu_ras_intr_triggered(); | |
2467 | } | |
2468 | ||
2469 | return false; | |
2470 | } | |
970fd197 SY |
2471 | |
2472 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2473 | { | |
2474 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2475 | ||
2476 | if (!con) | |
2477 | return; | |
2478 | ||
8ab0d6f0 | 2479 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
2480 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
2481 | amdgpu_ras_set_context(adev, NULL); | |
2482 | kfree(con); | |
2483 | } | |
2484 | } |