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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
f50160cf | 37 | #include "atom.h" |
c030f2e4 | 38 | |
eb0c3cd4 GC |
39 | static const char *RAS_FS_NAME = "ras"; |
40 | ||
c030f2e4 | 41 | const char *ras_error_string[] = { |
42 | "none", | |
43 | "parity", | |
44 | "single_correctable", | |
45 | "multi_uncorrectable", | |
46 | "poison", | |
47 | }; | |
48 | ||
49 | const char *ras_block_string[] = { | |
50 | "umc", | |
51 | "sdma", | |
52 | "gfx", | |
53 | "mmhub", | |
54 | "athub", | |
55 | "pcie_bif", | |
56 | "hdp", | |
57 | "xgmi_wafl", | |
58 | "df", | |
59 | "smn", | |
60 | "sem", | |
61 | "mp0", | |
62 | "mp1", | |
63 | "fuse", | |
640ae42e | 64 | "mca", |
c030f2e4 | 65 | }; |
66 | ||
640ae42e JC |
67 | const char *ras_mca_block_string[] = { |
68 | "mca_mp0", | |
69 | "mca_mp1", | |
70 | "mca_mpio", | |
71 | "mca_iohc", | |
72 | }; | |
73 | ||
74 | const char *get_ras_block_str(struct ras_common_if *ras_block) | |
75 | { | |
76 | if (!ras_block) | |
77 | return "NULL"; | |
78 | ||
79 | if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) | |
80 | return "OUT OF RANGE"; | |
81 | ||
82 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) | |
83 | return ras_mca_block_string[ras_block->sub_block_index]; | |
84 | ||
85 | return ras_block_string[ras_block->block]; | |
86 | } | |
87 | ||
c030f2e4 | 88 | #define ras_err_str(i) (ras_error_string[ffs(i)]) |
c030f2e4 | 89 | |
108c6a63 | 90 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
91 | ||
7cdc2ee3 TZ |
92 | /* inject address is 52 bits */ |
93 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
94 | ||
e4e6a589 LT |
95 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
96 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) | |
c84d4670 | 97 | |
52dd95f2 GC |
98 | enum amdgpu_ras_retire_page_reservation { |
99 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
100 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
101 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
102 | }; | |
7c6e68c7 AG |
103 | |
104 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
105 | ||
676deb38 DL |
106 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
107 | uint64_t addr); | |
6e4be987 TZ |
108 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
109 | uint64_t addr); | |
110 | ||
61380faa JC |
111 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
112 | { | |
a9d82d2f | 113 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
114 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
115 | } | |
116 | ||
f3167919 | 117 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 118 | { |
a9d82d2f | 119 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
120 | return amdgpu_ras_get_context(adev)->error_query_ready; |
121 | ||
122 | return false; | |
123 | } | |
124 | ||
cbb8f989 JC |
125 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
126 | { | |
127 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
128 | struct eeprom_table_record err_rec; | |
129 | ||
130 | if ((address >= adev->gmc.mc_vram_size) || | |
131 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
132 | dev_warn(adev->dev, | |
133 | "RAS WARN: input address 0x%llx is invalid.\n", | |
134 | address); | |
135 | return -EINVAL; | |
136 | } | |
137 | ||
138 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
139 | dev_warn(adev->dev, | |
80b0cd0f | 140 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
141 | address); |
142 | return 0; | |
143 | } | |
144 | ||
145 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
146 | ||
147 | err_rec.address = address; | |
148 | err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT; | |
149 | err_rec.ts = (uint64_t)ktime_get_real_seconds(); | |
150 | err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; | |
151 | ||
152 | err_data.err_addr = &err_rec; | |
153 | err_data.err_addr_cnt = 1; | |
154 | ||
155 | if (amdgpu_bad_page_threshold != 0) { | |
156 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
157 | err_data.err_addr_cnt); | |
158 | amdgpu_ras_save_bad_pages(adev); | |
159 | } | |
160 | ||
161 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
162 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
163 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
c030f2e4 | 168 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
169 | size_t size, loff_t *pos) | |
170 | { | |
171 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
172 | struct ras_query_if info = { | |
173 | .head = obj->head, | |
174 | }; | |
175 | ssize_t s; | |
176 | char val[128]; | |
177 | ||
761d86d3 | 178 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 179 | return -EINVAL; |
180 | ||
181 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
182 | "ue", info.ue_count, | |
183 | "ce", info.ce_count); | |
184 | if (*pos >= s) | |
185 | return 0; | |
186 | ||
187 | s -= *pos; | |
188 | s = min_t(u64, s, size); | |
189 | ||
190 | ||
191 | if (copy_to_user(buf, &val[*pos], s)) | |
192 | return -EINVAL; | |
193 | ||
194 | *pos += s; | |
195 | ||
196 | return s; | |
197 | } | |
198 | ||
c030f2e4 | 199 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
200 | .owner = THIS_MODULE, | |
201 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 202 | .write = NULL, |
c030f2e4 | 203 | .llseek = default_llseek |
204 | }; | |
205 | ||
96ebb307 | 206 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
207 | { | |
208 | int i; | |
209 | ||
210 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
211 | *block_id = i; | |
640ae42e | 212 | if (strcmp(name, ras_block_string[i]) == 0) |
96ebb307 | 213 | return 0; |
214 | } | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
219 | const char __user *buf, size_t size, | |
220 | loff_t *pos, struct ras_debug_if *data) | |
221 | { | |
222 | ssize_t s = min_t(u64, 64, size); | |
223 | char str[65]; | |
224 | char block_name[33]; | |
225 | char err[9] = "ue"; | |
226 | int op = -1; | |
227 | int block_id; | |
44494f96 | 228 | uint32_t sub_block; |
96ebb307 | 229 | u64 address, value; |
230 | ||
231 | if (*pos) | |
232 | return -EINVAL; | |
233 | *pos = size; | |
234 | ||
235 | memset(str, 0, sizeof(str)); | |
236 | memset(data, 0, sizeof(*data)); | |
237 | ||
238 | if (copy_from_user(str, buf, s)) | |
239 | return -EINVAL; | |
240 | ||
241 | if (sscanf(str, "disable %32s", block_name) == 1) | |
242 | op = 0; | |
243 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
244 | op = 1; | |
245 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
246 | op = 2; | |
6df23f4c | 247 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 248 | op = 3; |
b076296b | 249 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 250 | /* ascii string, but commands are not matched. */ |
251 | return -EINVAL; | |
252 | ||
253 | if (op != -1) { | |
cbb8f989 | 254 | if (op == 3) { |
546aa546 LT |
255 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
256 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 257 | return -EINVAL; |
cbb8f989 JC |
258 | |
259 | data->op = op; | |
260 | data->inject.address = address; | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
96ebb307 | 265 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
266 | return -EINVAL; | |
267 | ||
268 | data->head.block = block_id; | |
e1063493 TZ |
269 | /* only ue and ce errors are supported */ |
270 | if (!memcmp("ue", err, 2)) | |
271 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
272 | else if (!memcmp("ce", err, 2)) | |
273 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
274 | else | |
275 | return -EINVAL; | |
276 | ||
96ebb307 | 277 | data->op = op; |
278 | ||
279 | if (op == 2) { | |
546aa546 LT |
280 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", |
281 | &sub_block, &address, &value) != 3 && | |
282 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
283 | &sub_block, &address, &value) != 3) |
284 | return -EINVAL; | |
44494f96 | 285 | data->head.sub_block_index = sub_block; |
96ebb307 | 286 | data->inject.address = address; |
287 | data->inject.value = value; | |
288 | } | |
289 | } else { | |
73aa8e1a | 290 | if (size < sizeof(*data)) |
96ebb307 | 291 | return -EINVAL; |
292 | ||
293 | if (copy_from_user(data, buf, sizeof(*data))) | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
7c6e68c7 | 299 | |
74abc221 TSD |
300 | /** |
301 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 302 | * |
737c375b | 303 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 304 | * |
305 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 306 | * |
307 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 308 | * |
309 | * head has four members, they are block, type, sub_block_index, name. | |
310 | * block: which IP will be under control. | |
311 | * type: what kind of error will be enabled/disabled/injected. | |
312 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
313 | * name: the name of IP. | |
314 | * | |
315 | * inject has two more members than head, they are address, value. | |
316 | * As their names indicate, inject operation will write the | |
317 | * value to the address. | |
318 | * | |
ef177d11 | 319 | * The second member: struct ras_debug_if::op. |
c688a06b | 320 | * It has three kinds of operations. |
879e723d AZ |
321 | * |
322 | * - 0: disable RAS on the block. Take ::head as its data. | |
323 | * - 1: enable RAS on the block. Take ::head as its data. | |
324 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 325 | * |
96ebb307 | 326 | * How to use the interface? |
ef177d11 | 327 | * |
737c375b | 328 | * In a program |
ef177d11 | 329 | * |
737c375b LT |
330 | * Copy the struct ras_debug_if in your code and initialize it. |
331 | * Write the struct to the control interface. | |
ef177d11 | 332 | * |
737c375b | 333 | * From shell |
96ebb307 | 334 | * |
879e723d AZ |
335 | * .. code-block:: bash |
336 | * | |
737c375b LT |
337 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
338 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
339 | * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
879e723d | 340 | * |
737c375b | 341 | * Where N, is the card which you want to affect. |
ef177d11 | 342 | * |
737c375b LT |
343 | * "disable" requires only the block. |
344 | * "enable" requires the block and error type. | |
345 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 346 | * |
737c375b | 347 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 348 | * see ras_block_string[] for details |
c666bbf0 | 349 | * |
737c375b LT |
350 | * The error type is one of: ue, ce, where, |
351 | * ue is multi-uncorrectable | |
352 | * ce is single-correctable | |
c666bbf0 | 353 | * |
737c375b LT |
354 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
355 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
879e723d | 356 | * |
737c375b | 357 | * For instance, |
879e723d AZ |
358 | * |
359 | * .. code-block:: bash | |
96ebb307 | 360 | * |
44494f96 TZ |
361 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
362 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 363 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
364 | * | |
737c375b | 365 | * How to check the result of the operation? |
36ea1bd2 | 366 | * |
737c375b | 367 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 368 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
369 | * | |
737c375b LT |
370 | * To check inject, see the corresponding error count at, |
371 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 372 | * |
879e723d | 373 | * .. note:: |
ef177d11 | 374 | * Operations are only allowed on blocks which are supported. |
737c375b | 375 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
376 | * to see which blocks support RAS on a particular asic. |
377 | * | |
36ea1bd2 | 378 | */ |
cf696091 LT |
379 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
380 | const char __user *buf, | |
381 | size_t size, loff_t *pos) | |
36ea1bd2 | 382 | { |
383 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
384 | struct ras_debug_if data; | |
385 | int ret = 0; | |
386 | ||
61380faa | 387 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
388 | dev_warn(adev->dev, "RAS WARN: error injection " |
389 | "currently inaccessible\n"); | |
43c4d576 JC |
390 | return size; |
391 | } | |
392 | ||
96ebb307 | 393 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
394 | if (ret) | |
cf696091 | 395 | return ret; |
36ea1bd2 | 396 | |
80b0cd0f | 397 | if (data.op == 3) { |
cbb8f989 | 398 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 399 | if (!ret) |
cbb8f989 JC |
400 | return size; |
401 | else | |
402 | return ret; | |
403 | } | |
404 | ||
36ea1bd2 | 405 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
406 | return -EINVAL; | |
407 | ||
408 | switch (data.op) { | |
409 | case 0: | |
410 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
411 | break; | |
412 | case 1: | |
413 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
414 | break; | |
415 | case 2: | |
7cdc2ee3 TZ |
416 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
417 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
418 | dev_warn(adev->dev, "RAS WARN: input address " |
419 | "0x%llx is invalid.", | |
420 | data.inject.address); | |
7cdc2ee3 TZ |
421 | ret = -EINVAL; |
422 | break; | |
423 | } | |
424 | ||
6e4be987 TZ |
425 | /* umc ce/ue error injection for a bad page is not allowed */ |
426 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
427 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
c65b0805 LT |
428 | dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " |
429 | "already been marked as bad!\n", | |
430 | data.inject.address); | |
6e4be987 TZ |
431 | break; |
432 | } | |
433 | ||
7cdc2ee3 | 434 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 435 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
436 | break; | |
96ebb307 | 437 | default: |
438 | ret = -EINVAL; | |
439 | break; | |
374bf7bd | 440 | } |
36ea1bd2 | 441 | |
442 | if (ret) | |
443 | return -EINVAL; | |
444 | ||
445 | return size; | |
446 | } | |
447 | ||
084fe13b AG |
448 | /** |
449 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
450 | * | |
f77c7109 | 451 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 452 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
453 | * a way to reset the EEPROM, e.g., after testing error injection. |
454 | * | |
455 | * Usage: | |
456 | * | |
457 | * .. code-block:: bash | |
458 | * | |
459 | * echo 1 > ../ras/ras_eeprom_reset | |
460 | * | |
461 | * will reset EEPROM table to 0 entries. | |
462 | * | |
084fe13b | 463 | */ |
cf696091 LT |
464 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
465 | const char __user *buf, | |
466 | size_t size, loff_t *pos) | |
084fe13b | 467 | { |
bf0b91b7 GC |
468 | struct amdgpu_device *adev = |
469 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
470 | int ret; |
471 | ||
bf0b91b7 | 472 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 473 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 474 | |
63d4c081 | 475 | if (!ret) { |
cf696091 LT |
476 | /* Something was written to EEPROM. |
477 | */ | |
bf0b91b7 GC |
478 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
479 | return size; | |
480 | } else { | |
cf696091 | 481 | return ret; |
bf0b91b7 | 482 | } |
084fe13b AG |
483 | } |
484 | ||
36ea1bd2 | 485 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
486 | .owner = THIS_MODULE, | |
487 | .read = NULL, | |
488 | .write = amdgpu_ras_debugfs_ctrl_write, | |
489 | .llseek = default_llseek | |
490 | }; | |
491 | ||
084fe13b AG |
492 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
493 | .owner = THIS_MODULE, | |
494 | .read = NULL, | |
495 | .write = amdgpu_ras_debugfs_eeprom_write, | |
496 | .llseek = default_llseek | |
497 | }; | |
498 | ||
f77c7109 AD |
499 | /** |
500 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
501 | * | |
ef177d11 | 502 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
503 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
504 | * | |
505 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
506 | * (ce) error counts. | |
507 | * | |
508 | * The format of one line is below, | |
509 | * | |
510 | * [ce|ue]: count | |
511 | * | |
512 | * Example: | |
513 | * | |
514 | * .. code-block:: bash | |
515 | * | |
516 | * ue: 0 | |
517 | * ce: 1 | |
518 | * | |
519 | */ | |
c030f2e4 | 520 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
521 | struct device_attribute *attr, char *buf) | |
522 | { | |
523 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
524 | struct ras_query_if info = { | |
525 | .head = obj->head, | |
526 | }; | |
527 | ||
61380faa | 528 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 529 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 530 | |
761d86d3 | 531 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 532 | return -EINVAL; |
533 | ||
1f0d8e37 MJ |
534 | if (obj->adev->asic_type == CHIP_ALDEBARAN) { |
535 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) | |
536 | DRM_WARN("Failed to reset error counter and error status"); | |
537 | } | |
538 | ||
36000c7a TT |
539 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
540 | "ce", info.ce_count); | |
c030f2e4 | 541 | } |
542 | ||
543 | /* obj begin */ | |
544 | ||
545 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
546 | #define alive_obj(obj) ((obj)->use) | |
547 | ||
548 | static inline void put_obj(struct ras_manager *obj) | |
549 | { | |
f0872686 | 550 | if (obj && (--obj->use == 0)) |
c030f2e4 | 551 | list_del(&obj->node); |
f0872686 | 552 | if (obj && (obj->use < 0)) |
640ae42e | 553 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); |
c030f2e4 | 554 | } |
555 | ||
556 | /* make one obj and return it. */ | |
557 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
558 | struct ras_common_if *head) | |
559 | { | |
560 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
561 | struct ras_manager *obj; | |
562 | ||
8ab0d6f0 | 563 | if (!adev->ras_enabled || !con) |
c030f2e4 | 564 | return NULL; |
565 | ||
566 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
567 | return NULL; | |
568 | ||
640ae42e JC |
569 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
570 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
571 | return NULL; | |
572 | ||
573 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
574 | } else | |
575 | obj = &con->objs[head->block]; | |
576 | ||
c030f2e4 | 577 | /* already exist. return obj? */ |
578 | if (alive_obj(obj)) | |
579 | return NULL; | |
580 | ||
581 | obj->head = *head; | |
582 | obj->adev = adev; | |
583 | list_add(&obj->node, &con->head); | |
584 | get_obj(obj); | |
585 | ||
586 | return obj; | |
587 | } | |
588 | ||
589 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 590 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 591 | struct ras_common_if *head) |
592 | { | |
593 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
594 | struct ras_manager *obj; | |
595 | int i; | |
596 | ||
8ab0d6f0 | 597 | if (!adev->ras_enabled || !con) |
c030f2e4 | 598 | return NULL; |
599 | ||
600 | if (head) { | |
601 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
602 | return NULL; | |
603 | ||
640ae42e JC |
604 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
605 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
606 | return NULL; | |
607 | ||
608 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
609 | } else | |
610 | obj = &con->objs[head->block]; | |
c030f2e4 | 611 | |
640ae42e | 612 | if (alive_obj(obj)) |
c030f2e4 | 613 | return obj; |
c030f2e4 | 614 | } else { |
640ae42e | 615 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { |
c030f2e4 | 616 | obj = &con->objs[i]; |
640ae42e | 617 | if (alive_obj(obj)) |
c030f2e4 | 618 | return obj; |
c030f2e4 | 619 | } |
620 | } | |
621 | ||
622 | return NULL; | |
623 | } | |
624 | /* obj end */ | |
625 | ||
626 | /* feature ctl begin */ | |
627 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 628 | struct ras_common_if *head) |
c030f2e4 | 629 | { |
8ab0d6f0 | 630 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 631 | } |
632 | ||
633 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
634 | struct ras_common_if *head) | |
635 | { | |
636 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
637 | ||
638 | return con->features & BIT(head->block); | |
639 | } | |
640 | ||
641 | /* | |
642 | * if obj is not created, then create one. | |
643 | * set feature enable flag. | |
644 | */ | |
645 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
646 | struct ras_common_if *head, int enable) | |
647 | { | |
648 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
649 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
650 | ||
5caf466a | 651 | /* If hardware does not support ras, then do not create obj. |
652 | * But if hardware support ras, we can create the obj. | |
653 | * Ras framework checks con->hw_supported to see if it need do | |
654 | * corresponding initialization. | |
655 | * IP checks con->support to see if it need disable ras. | |
656 | */ | |
c030f2e4 | 657 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
658 | return 0; | |
c030f2e4 | 659 | |
660 | if (enable) { | |
661 | if (!obj) { | |
662 | obj = amdgpu_ras_create_obj(adev, head); | |
663 | if (!obj) | |
664 | return -EINVAL; | |
665 | } else { | |
666 | /* In case we create obj somewhere else */ | |
667 | get_obj(obj); | |
668 | } | |
669 | con->features |= BIT(head->block); | |
670 | } else { | |
671 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 672 | con->features &= ~BIT(head->block); |
c030f2e4 | 673 | put_obj(obj); |
674 | } | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
680 | /* wrapper of psp_ras_enable_features */ | |
681 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
682 | struct ras_common_if *head, bool enable) | |
683 | { | |
684 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 685 | union ta_ras_cmd_input *info; |
c030f2e4 | 686 | int ret; |
687 | ||
688 | if (!con) | |
689 | return -EINVAL; | |
690 | ||
f3729f7b | 691 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
692 | if (!info) |
693 | return -ENOMEM; | |
694 | ||
c030f2e4 | 695 | if (!enable) { |
7fcffecf | 696 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 697 | .block_id = amdgpu_ras_block_to_ta(head->block), |
698 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 699 | }; |
700 | } else { | |
7fcffecf | 701 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 702 | .block_id = amdgpu_ras_block_to_ta(head->block), |
703 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 704 | }; |
705 | } | |
706 | ||
707 | /* Do not enable if it is not allowed. */ | |
708 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
c030f2e4 | 709 | |
bff77e86 | 710 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 711 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 712 | if (ret) { |
011907fd DL |
713 | dev_err(adev->dev, "ras %s %s failed %d\n", |
714 | enable ? "enable":"disable", | |
640ae42e | 715 | get_ras_block_str(head), |
011907fd | 716 | ret); |
7fcffecf | 717 | goto out; |
bff77e86 | 718 | } |
c030f2e4 | 719 | } |
720 | ||
721 | /* setup the obj */ | |
722 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
723 | ret = 0; |
724 | out: | |
725 | kfree(info); | |
726 | return ret; | |
c030f2e4 | 727 | } |
728 | ||
77de502b | 729 | /* Only used in device probe stage and called only once. */ |
730 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
731 | struct ras_common_if *head, bool enable) | |
732 | { | |
733 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
734 | int ret; | |
735 | ||
736 | if (!con) | |
737 | return -EINVAL; | |
738 | ||
739 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 740 | if (enable) { |
741 | /* There is no harm to issue a ras TA cmd regardless of | |
742 | * the currecnt ras state. | |
743 | * If current state == target state, it will do nothing | |
744 | * But sometimes it requests driver to reset and repost | |
745 | * with error code -EAGAIN. | |
746 | */ | |
747 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
748 | /* With old ras TA, we might fail to enable ras. | |
749 | * Log it and just setup the object. | |
750 | * TODO need remove this WA in the future. | |
751 | */ | |
752 | if (ret == -EINVAL) { | |
753 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
754 | if (!ret) | |
6952e99c GC |
755 | dev_info(adev->dev, |
756 | "RAS INFO: %s setup object\n", | |
640ae42e | 757 | get_ras_block_str(head)); |
7af23ebe | 758 | } |
759 | } else { | |
760 | /* setup the object then issue a ras TA disable cmd.*/ | |
761 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
762 | if (ret) | |
763 | return ret; | |
77de502b | 764 | |
970fd197 SY |
765 | /* gfx block ras dsiable cmd must send to ras-ta */ |
766 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
767 | con->features |= BIT(head->block); | |
768 | ||
77de502b | 769 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
770 | |
771 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 772 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 773 | con->features &= ~BIT(head->block); |
7af23ebe | 774 | } |
77de502b | 775 | } else |
776 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
777 | ||
778 | return ret; | |
779 | } | |
780 | ||
c030f2e4 | 781 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
782 | bool bypass) | |
783 | { | |
784 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
785 | struct ras_manager *obj, *tmp; | |
786 | ||
787 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
788 | /* bypass psp. | |
789 | * aka just release the obj and corresponding flags | |
790 | */ | |
791 | if (bypass) { | |
792 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
793 | break; | |
794 | } else { | |
795 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
796 | break; | |
797 | } | |
289d513b | 798 | } |
c030f2e4 | 799 | |
800 | return con->features; | |
801 | } | |
802 | ||
803 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
804 | bool bypass) | |
805 | { | |
806 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 807 | int i; |
640ae42e | 808 | const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; |
c030f2e4 | 809 | |
640ae42e | 810 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { |
c030f2e4 | 811 | struct ras_common_if head = { |
812 | .block = i, | |
191051a1 | 813 | .type = default_ras_type, |
c030f2e4 | 814 | .sub_block_index = 0, |
815 | }; | |
640ae42e JC |
816 | |
817 | if (i == AMDGPU_RAS_BLOCK__MCA) | |
818 | continue; | |
819 | ||
820 | if (bypass) { | |
821 | /* | |
822 | * bypass psp. vbios enable ras for us. | |
823 | * so just create the obj | |
824 | */ | |
825 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
826 | break; | |
827 | } else { | |
828 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
829 | break; | |
830 | } | |
831 | } | |
832 | ||
833 | for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { | |
834 | struct ras_common_if head = { | |
835 | .block = AMDGPU_RAS_BLOCK__MCA, | |
836 | .type = default_ras_type, | |
837 | .sub_block_index = i, | |
838 | }; | |
839 | ||
c030f2e4 | 840 | if (bypass) { |
841 | /* | |
842 | * bypass psp. vbios enable ras for us. | |
843 | * so just create the obj | |
844 | */ | |
845 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
846 | break; | |
847 | } else { | |
848 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
849 | break; | |
850 | } | |
289d513b | 851 | } |
c030f2e4 | 852 | |
853 | return con->features; | |
854 | } | |
855 | /* feature ctl end */ | |
856 | ||
640ae42e JC |
857 | |
858 | void amdgpu_ras_mca_query_error_status(struct amdgpu_device *adev, | |
859 | struct ras_common_if *ras_block, | |
860 | struct ras_err_data *err_data) | |
861 | { | |
862 | switch (ras_block->sub_block_index) { | |
863 | case AMDGPU_RAS_MCA_BLOCK__MP0: | |
864 | if (adev->mca.mp0.ras_funcs && | |
865 | adev->mca.mp0.ras_funcs->query_ras_error_count) | |
866 | adev->mca.mp0.ras_funcs->query_ras_error_count(adev, &err_data); | |
867 | break; | |
868 | case AMDGPU_RAS_MCA_BLOCK__MP1: | |
869 | if (adev->mca.mp1.ras_funcs && | |
870 | adev->mca.mp1.ras_funcs->query_ras_error_count) | |
871 | adev->mca.mp1.ras_funcs->query_ras_error_count(adev, &err_data); | |
872 | break; | |
873 | case AMDGPU_RAS_MCA_BLOCK__MPIO: | |
874 | if (adev->mca.mpio.ras_funcs && | |
875 | adev->mca.mpio.ras_funcs->query_ras_error_count) | |
876 | adev->mca.mpio.ras_funcs->query_ras_error_count(adev, &err_data); | |
877 | break; | |
878 | default: | |
879 | break; | |
880 | } | |
881 | } | |
882 | ||
c030f2e4 | 883 | /* query/inject/cure begin */ |
761d86d3 | 884 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
4d9f771e | 885 | struct ras_query_if *info) |
c030f2e4 | 886 | { |
887 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 888 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 889 | int i; |
c030f2e4 | 890 | |
891 | if (!obj) | |
892 | return -EINVAL; | |
c030f2e4 | 893 | |
939e2258 HZ |
894 | switch (info->head.block) { |
895 | case AMDGPU_RAS_BLOCK__UMC: | |
49070c4e HZ |
896 | if (adev->umc.ras_funcs && |
897 | adev->umc.ras_funcs->query_ras_error_count) | |
898 | adev->umc.ras_funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
899 | /* umc query_ras_error_address is also responsible for clearing |
900 | * error status | |
901 | */ | |
49070c4e HZ |
902 | if (adev->umc.ras_funcs && |
903 | adev->umc.ras_funcs->query_ras_error_address) | |
904 | adev->umc.ras_funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 905 | break; |
3e81ee9a HZ |
906 | case AMDGPU_RAS_BLOCK__SDMA: |
907 | if (adev->sdma.funcs->query_ras_error_count) { | |
908 | for (i = 0; i < adev->sdma.num_instances; i++) | |
909 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
910 | &err_data); | |
911 | } | |
912 | break; | |
83b0582c | 913 | case AMDGPU_RAS_BLOCK__GFX: |
719a9b33 HZ |
914 | if (adev->gfx.ras_funcs && |
915 | adev->gfx.ras_funcs->query_ras_error_count) | |
916 | adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 917 | |
719a9b33 HZ |
918 | if (adev->gfx.ras_funcs && |
919 | adev->gfx.ras_funcs->query_ras_error_status) | |
920 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
83b0582c | 921 | break; |
9fb2d8de | 922 | case AMDGPU_RAS_BLOCK__MMHUB: |
8bc7b360 HZ |
923 | if (adev->mmhub.ras_funcs && |
924 | adev->mmhub.ras_funcs->query_ras_error_count) | |
925 | adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 926 | |
8bc7b360 HZ |
927 | if (adev->mmhub.ras_funcs && |
928 | adev->mmhub.ras_funcs->query_ras_error_status) | |
929 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
9fb2d8de | 930 | break; |
d7bd680d | 931 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
6e36f231 HZ |
932 | if (adev->nbio.ras_funcs && |
933 | adev->nbio.ras_funcs->query_ras_error_count) | |
934 | adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data); | |
d7bd680d | 935 | break; |
ec01fe2d | 936 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
52137ca8 HZ |
937 | if (adev->gmc.xgmi.ras_funcs && |
938 | adev->gmc.xgmi.ras_funcs->query_ras_error_count) | |
939 | adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data); | |
ec01fe2d | 940 | break; |
78871b6c HZ |
941 | case AMDGPU_RAS_BLOCK__HDP: |
942 | if (adev->hdp.ras_funcs && | |
943 | adev->hdp.ras_funcs->query_ras_error_count) | |
944 | adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data); | |
945 | break; | |
640ae42e JC |
946 | case AMDGPU_RAS_BLOCK__MCA: |
947 | amdgpu_ras_mca_query_error_status(adev, &info->head, &err_data); | |
948 | break; | |
939e2258 HZ |
949 | default: |
950 | break; | |
951 | } | |
05a58345 TZ |
952 | |
953 | obj->err_data.ue_count += err_data.ue_count; | |
954 | obj->err_data.ce_count += err_data.ce_count; | |
955 | ||
c030f2e4 | 956 | info->ue_count = obj->err_data.ue_count; |
957 | info->ce_count = obj->err_data.ce_count; | |
958 | ||
7c6e68c7 | 959 | if (err_data.ce_count) { |
a30f1286 HZ |
960 | if (adev->smuio.funcs && |
961 | adev->smuio.funcs->get_socket_id && | |
962 | adev->smuio.funcs->get_die_id) { | |
963 | dev_info(adev->dev, "socket: %d, die: %d " | |
964 | "%ld correctable hardware errors " | |
6952e99c GC |
965 | "detected in %s block, no user " |
966 | "action is needed.\n", | |
a30f1286 HZ |
967 | adev->smuio.funcs->get_socket_id(adev), |
968 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 969 | obj->err_data.ce_count, |
640ae42e | 970 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
971 | } else { |
972 | dev_info(adev->dev, "%ld correctable hardware errors " | |
6952e99c GC |
973 | "detected in %s block, no user " |
974 | "action is needed.\n", | |
975 | obj->err_data.ce_count, | |
640ae42e | 976 | get_ras_block_str(&info->head)); |
a30f1286 | 977 | } |
7c6e68c7 AG |
978 | } |
979 | if (err_data.ue_count) { | |
a30f1286 HZ |
980 | if (adev->smuio.funcs && |
981 | adev->smuio.funcs->get_socket_id && | |
982 | adev->smuio.funcs->get_die_id) { | |
983 | dev_info(adev->dev, "socket: %d, die: %d " | |
984 | "%ld uncorrectable hardware errors " | |
6952e99c | 985 | "detected in %s block\n", |
a30f1286 HZ |
986 | adev->smuio.funcs->get_socket_id(adev), |
987 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 988 | obj->err_data.ue_count, |
640ae42e | 989 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
990 | } else { |
991 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
6952e99c GC |
992 | "detected in %s block\n", |
993 | obj->err_data.ue_count, | |
640ae42e | 994 | get_ras_block_str(&info->head)); |
a30f1286 | 995 | } |
7c6e68c7 | 996 | } |
05a58345 | 997 | |
c030f2e4 | 998 | return 0; |
999 | } | |
1000 | ||
761d86d3 DL |
1001 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
1002 | enum amdgpu_ras_block block) | |
1003 | { | |
1004 | if (!amdgpu_ras_is_supported(adev, block)) | |
1005 | return -EINVAL; | |
1006 | ||
1007 | switch (block) { | |
1008 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1009 | if (adev->gfx.ras_funcs && |
1010 | adev->gfx.ras_funcs->reset_ras_error_count) | |
1011 | adev->gfx.ras_funcs->reset_ras_error_count(adev); | |
761d86d3 | 1012 | |
719a9b33 HZ |
1013 | if (adev->gfx.ras_funcs && |
1014 | adev->gfx.ras_funcs->reset_ras_error_status) | |
1015 | adev->gfx.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
1016 | break; |
1017 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
1018 | if (adev->mmhub.ras_funcs && |
1019 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
1020 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
7780f503 DL |
1021 | |
1022 | if (adev->mmhub.ras_funcs && | |
1023 | adev->mmhub.ras_funcs->reset_ras_error_status) | |
1024 | adev->mmhub.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
1025 | break; |
1026 | case AMDGPU_RAS_BLOCK__SDMA: | |
1027 | if (adev->sdma.funcs->reset_ras_error_count) | |
1028 | adev->sdma.funcs->reset_ras_error_count(adev); | |
1029 | break; | |
78871b6c HZ |
1030 | case AMDGPU_RAS_BLOCK__HDP: |
1031 | if (adev->hdp.ras_funcs && | |
1032 | adev->hdp.ras_funcs->reset_ras_error_count) | |
1033 | adev->hdp.ras_funcs->reset_ras_error_count(adev); | |
1034 | break; | |
761d86d3 DL |
1035 | default: |
1036 | break; | |
1037 | } | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | ||
5c23e9e0 | 1042 | /* Trigger XGMI/WAFL error */ |
f3167919 | 1043 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
1044 | struct ta_ras_trigger_error_input *block_info) |
1045 | { | |
1046 | int ret; | |
1047 | ||
1048 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
1049 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
1050 | ||
1051 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
1052 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
1053 | ||
1054 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
1055 | ||
1056 | if (amdgpu_ras_intr_triggered()) | |
1057 | return ret; | |
1058 | ||
1059 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
1060 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
1061 | ||
fe2d9f5a | 1062 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) |
5c23e9e0 JC |
1063 | dev_warn(adev->dev, "Failed to allow df cstate"); |
1064 | ||
1065 | return ret; | |
1066 | } | |
1067 | ||
c030f2e4 | 1068 | /* wrapper of psp_ras_trigger_error */ |
1069 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
1070 | struct ras_inject_if *info) | |
1071 | { | |
1072 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1073 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1074 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1075 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1076 | .sub_block_index = info->head.sub_block_index, |
1077 | .address = info->address, | |
1078 | .value = info->value, | |
1079 | }; | |
1080 | int ret = 0; | |
1081 | ||
1082 | if (!obj) | |
1083 | return -EINVAL; | |
1084 | ||
a6c44d25 JC |
1085 | /* Calculate XGMI relative offset */ |
1086 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
1087 | block_info.address = |
1088 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1089 | block_info.address); | |
a6c44d25 JC |
1090 | } |
1091 | ||
83b0582c DL |
1092 | switch (info->head.block) { |
1093 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1094 | if (adev->gfx.ras_funcs && |
1095 | adev->gfx.ras_funcs->ras_error_inject) | |
1096 | ret = adev->gfx.ras_funcs->ras_error_inject(adev, info); | |
83b0582c DL |
1097 | else |
1098 | ret = -EINVAL; | |
1099 | break; | |
1100 | case AMDGPU_RAS_BLOCK__UMC: | |
5a434527 | 1101 | case AMDGPU_RAS_BLOCK__SDMA: |
9fb2d8de | 1102 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 1103 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
640ae42e | 1104 | case AMDGPU_RAS_BLOCK__MCA: |
83b0582c DL |
1105 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
1106 | break; | |
5c23e9e0 JC |
1107 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
1108 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
1109 | break; | |
83b0582c | 1110 | default: |
6952e99c | 1111 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
640ae42e | 1112 | get_ras_block_str(&info->head)); |
83b0582c | 1113 | ret = -EINVAL; |
a5dd40ca HZ |
1114 | } |
1115 | ||
011907fd DL |
1116 | if (ret) |
1117 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
640ae42e | 1118 | get_ras_block_str(&info->head), ret); |
c030f2e4 | 1119 | |
1120 | return ret; | |
1121 | } | |
1122 | ||
4d9f771e LT |
1123 | /** |
1124 | * amdgpu_ras_query_error_count -- Get error counts of all IPs | |
1125 | * adev: pointer to AMD GPU device | |
1126 | * ce_count: pointer to an integer to be set to the count of correctible errors. | |
1127 | * ue_count: pointer to an integer to be set to the count of uncorrectible | |
1128 | * errors. | |
1129 | * | |
1130 | * If set, @ce_count or @ue_count, count and return the corresponding | |
1131 | * error counts in those integer pointers. Return 0 if the device | |
1132 | * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
1133 | */ | |
1134 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
1135 | unsigned long *ce_count, | |
1136 | unsigned long *ue_count) | |
c030f2e4 | 1137 | { |
1138 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1139 | struct ras_manager *obj; | |
a46751fb | 1140 | unsigned long ce, ue; |
c030f2e4 | 1141 | |
8ab0d6f0 | 1142 | if (!adev->ras_enabled || !con) |
4d9f771e LT |
1143 | return -EOPNOTSUPP; |
1144 | ||
1145 | /* Don't count since no reporting. | |
1146 | */ | |
1147 | if (!ce_count && !ue_count) | |
1148 | return 0; | |
c030f2e4 | 1149 | |
a46751fb LT |
1150 | ce = 0; |
1151 | ue = 0; | |
c030f2e4 | 1152 | list_for_each_entry(obj, &con->head, node) { |
1153 | struct ras_query_if info = { | |
1154 | .head = obj->head, | |
1155 | }; | |
4d9f771e | 1156 | int res; |
c030f2e4 | 1157 | |
4d9f771e LT |
1158 | res = amdgpu_ras_query_error_status(adev, &info); |
1159 | if (res) | |
1160 | return res; | |
c030f2e4 | 1161 | |
a46751fb LT |
1162 | ce += info.ce_count; |
1163 | ue += info.ue_count; | |
c030f2e4 | 1164 | } |
1165 | ||
a46751fb LT |
1166 | if (ce_count) |
1167 | *ce_count = ce; | |
1168 | ||
1169 | if (ue_count) | |
1170 | *ue_count = ue; | |
4d9f771e LT |
1171 | |
1172 | return 0; | |
c030f2e4 | 1173 | } |
1174 | /* query/inject/cure end */ | |
1175 | ||
1176 | ||
1177 | /* sysfs begin */ | |
1178 | ||
466b1793 | 1179 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1180 | struct ras_badpage **bps, unsigned int *count); | |
1181 | ||
1182 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1183 | { | |
1184 | switch (flags) { | |
52dd95f2 | 1185 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1186 | return "R"; |
52dd95f2 | 1187 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1188 | return "P"; |
52dd95f2 | 1189 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1190 | default: |
1191 | return "F"; | |
aec576f9 | 1192 | } |
466b1793 | 1193 | } |
1194 | ||
f77c7109 AD |
1195 | /** |
1196 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1197 | * |
1198 | * It allows user to read the bad pages of vram on the gpu through | |
1199 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1200 | * | |
1201 | * It outputs multiple lines, and each line stands for one gpu page. | |
1202 | * | |
1203 | * The format of one line is below, | |
1204 | * gpu pfn : gpu page size : flags | |
1205 | * | |
1206 | * gpu pfn and gpu page size are printed in hex format. | |
1207 | * flags can be one of below character, | |
f77c7109 | 1208 | * |
466b1793 | 1209 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1210 | * |
466b1793 | 1211 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1212 | * in next window of page_reserve. |
1213 | * | |
466b1793 | 1214 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1215 | * | |
f77c7109 AD |
1216 | * Examples: |
1217 | * | |
1218 | * .. code-block:: bash | |
1219 | * | |
1220 | * 0x00000001 : 0x00001000 : R | |
1221 | * 0x00000002 : 0x00001000 : P | |
1222 | * | |
466b1793 | 1223 | */ |
1224 | ||
1225 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1226 | struct kobject *kobj, struct bin_attribute *attr, | |
1227 | char *buf, loff_t ppos, size_t count) | |
1228 | { | |
1229 | struct amdgpu_ras *con = | |
1230 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1231 | struct amdgpu_device *adev = con->adev; | |
1232 | const unsigned int element_size = | |
1233 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1234 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1235 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1236 | ssize_t s = 0; |
1237 | struct ras_badpage *bps = NULL; | |
1238 | unsigned int bps_count = 0; | |
1239 | ||
1240 | memset(buf, 0, count); | |
1241 | ||
1242 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1243 | return 0; | |
1244 | ||
1245 | for (; start < end && start < bps_count; start++) | |
1246 | s += scnprintf(&buf[s], element_size + 1, | |
1247 | "0x%08x : 0x%08x : %1s\n", | |
1248 | bps[start].bp, | |
1249 | bps[start].size, | |
1250 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1251 | ||
1252 | kfree(bps); | |
1253 | ||
1254 | return s; | |
1255 | } | |
1256 | ||
c030f2e4 | 1257 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1258 | struct device_attribute *attr, char *buf) | |
1259 | { | |
1260 | struct amdgpu_ras *con = | |
1261 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1262 | |
5212a3bd | 1263 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1264 | } |
1265 | ||
f848159b GC |
1266 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1267 | { | |
1268 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1269 | ||
1270 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1271 | &con->badpages_attr.attr, | |
1272 | RAS_FS_NAME); | |
1273 | } | |
1274 | ||
c030f2e4 | 1275 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1276 | { | |
1277 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1278 | struct attribute *attrs[] = { | |
1279 | &con->features_attr.attr, | |
1280 | NULL | |
1281 | }; | |
1282 | struct attribute_group group = { | |
eb0c3cd4 | 1283 | .name = RAS_FS_NAME, |
c030f2e4 | 1284 | .attrs = attrs, |
1285 | }; | |
1286 | ||
1287 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1293 | struct ras_fs_if *head) | |
1294 | { | |
1295 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1296 | ||
1297 | if (!obj || obj->attr_inuse) | |
1298 | return -EINVAL; | |
1299 | ||
1300 | get_obj(obj); | |
1301 | ||
1302 | memcpy(obj->fs_data.sysfs_name, | |
1303 | head->sysfs_name, | |
1304 | sizeof(obj->fs_data.sysfs_name)); | |
1305 | ||
1306 | obj->sysfs_attr = (struct device_attribute){ | |
1307 | .attr = { | |
1308 | .name = obj->fs_data.sysfs_name, | |
1309 | .mode = S_IRUGO, | |
1310 | }, | |
1311 | .show = amdgpu_ras_sysfs_read, | |
1312 | }; | |
163def43 | 1313 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1314 | |
1315 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1316 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1317 | RAS_FS_NAME)) { |
c030f2e4 | 1318 | put_obj(obj); |
1319 | return -EINVAL; | |
1320 | } | |
1321 | ||
1322 | obj->attr_inuse = 1; | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1328 | struct ras_common_if *head) | |
1329 | { | |
1330 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1331 | ||
1332 | if (!obj || !obj->attr_inuse) | |
1333 | return -EINVAL; | |
1334 | ||
1335 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1336 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1337 | RAS_FS_NAME); |
c030f2e4 | 1338 | obj->attr_inuse = 0; |
1339 | put_obj(obj); | |
1340 | ||
1341 | return 0; | |
1342 | } | |
1343 | ||
1344 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1345 | { | |
1346 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1347 | struct ras_manager *obj, *tmp; | |
1348 | ||
1349 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1350 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1351 | } | |
1352 | ||
f848159b GC |
1353 | if (amdgpu_bad_page_threshold != 0) |
1354 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1355 | ||
c030f2e4 | 1356 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | /* sysfs end */ | |
1361 | ||
ef177d11 AD |
1362 | /** |
1363 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1364 | * | |
1365 | * Normally when there is an uncorrectable error, the driver will reset | |
1366 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1367 | * the driver provides an interface to reboot the system automatically | |
1368 | * in that event. | |
1369 | * | |
1370 | * The following file in debugfs provides that interface: | |
1371 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1372 | * | |
1373 | * Usage: | |
1374 | * | |
1375 | * .. code-block:: bash | |
1376 | * | |
1377 | * echo true > .../ras/auto_reboot | |
1378 | * | |
1379 | */ | |
c030f2e4 | 1380 | /* debugfs begin */ |
ea1b8c9b | 1381 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1382 | { |
1383 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
ef0d7d20 LT |
1384 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1385 | struct dentry *dir; | |
36ea1bd2 | 1386 | |
88293c03 ND |
1387 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1388 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1389 | &amdgpu_ras_debugfs_ctrl_ops); | |
1390 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1391 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1392 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1393 | &con->bad_page_cnt_threshold); | |
ef0d7d20 LT |
1394 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1395 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c65b0805 LT |
1396 | debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, |
1397 | &amdgpu_ras_debugfs_eeprom_size_ops); | |
1398 | con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", | |
1399 | S_IRUGO, dir, adev, | |
1400 | &amdgpu_ras_debugfs_eeprom_table_ops); | |
1401 | amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); | |
c688a06b GC |
1402 | |
1403 | /* | |
1404 | * After one uncorrectable error happens, usually GPU recovery will | |
1405 | * be scheduled. But due to the known problem in GPU recovery failing | |
1406 | * to bring GPU back, below interface provides one direct way to | |
1407 | * user to reboot system automatically in such case within | |
1408 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1409 | * will never be called. | |
1410 | */ | |
88293c03 | 1411 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1412 | |
1413 | /* | |
1414 | * User could set this not to clean up hardware's error count register | |
1415 | * of RAS IPs during ras recovery. | |
1416 | */ | |
88293c03 ND |
1417 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1418 | &con->disable_ras_err_cnt_harvest); | |
1419 | return dir; | |
36ea1bd2 | 1420 | } |
1421 | ||
cedf7884 | 1422 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1423 | struct ras_fs_if *head, |
1424 | struct dentry *dir) | |
c030f2e4 | 1425 | { |
c030f2e4 | 1426 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1427 | |
88293c03 | 1428 | if (!obj || !dir) |
450f30ea | 1429 | return; |
c030f2e4 | 1430 | |
1431 | get_obj(obj); | |
1432 | ||
1433 | memcpy(obj->fs_data.debugfs_name, | |
1434 | head->debugfs_name, | |
1435 | sizeof(obj->fs_data.debugfs_name)); | |
1436 | ||
88293c03 ND |
1437 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1438 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1439 | } |
1440 | ||
f9317014 TZ |
1441 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1442 | { | |
1443 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1444 | struct dentry *dir; |
c1509f3f | 1445 | struct ras_manager *obj; |
f9317014 TZ |
1446 | struct ras_fs_if fs_info; |
1447 | ||
1448 | /* | |
1449 | * it won't be called in resume path, no need to check | |
1450 | * suspend and gpu reset status | |
1451 | */ | |
cedf7884 | 1452 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1453 | return; |
1454 | ||
88293c03 | 1455 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1456 | |
c1509f3f | 1457 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1458 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1459 | (obj->attr_inuse == 1)) { | |
1460 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
640ae42e | 1461 | get_ras_block_str(&obj->head)); |
f9317014 | 1462 | fs_info.head = obj->head; |
88293c03 | 1463 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1464 | } |
1465 | } | |
1466 | } | |
1467 | ||
c030f2e4 | 1468 | /* debugfs end */ |
1469 | ||
1470 | /* ras fs */ | |
c3d4d45d GC |
1471 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1472 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1473 | static DEVICE_ATTR(features, S_IRUGO, | |
1474 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1475 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1476 | { | |
c3d4d45d GC |
1477 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1478 | struct attribute_group group = { | |
1479 | .name = RAS_FS_NAME, | |
1480 | }; | |
1481 | struct attribute *attrs[] = { | |
1482 | &con->features_attr.attr, | |
1483 | NULL | |
1484 | }; | |
1485 | struct bin_attribute *bin_attrs[] = { | |
1486 | NULL, | |
1487 | NULL, | |
1488 | }; | |
a069a9eb | 1489 | int r; |
c030f2e4 | 1490 | |
c3d4d45d GC |
1491 | /* add features entry */ |
1492 | con->features_attr = dev_attr_features; | |
1493 | group.attrs = attrs; | |
1494 | sysfs_attr_init(attrs[0]); | |
1495 | ||
1496 | if (amdgpu_bad_page_threshold != 0) { | |
1497 | /* add bad_page_features entry */ | |
1498 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1499 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1500 | bin_attrs[0] = &con->badpages_attr; | |
1501 | group.bin_attrs = bin_attrs; | |
1502 | sysfs_bin_attr_init(bin_attrs[0]); | |
1503 | } | |
1504 | ||
a069a9eb AD |
1505 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1506 | if (r) | |
1507 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1508 | |
c030f2e4 | 1509 | return 0; |
1510 | } | |
1511 | ||
1512 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1513 | { | |
88293c03 ND |
1514 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1515 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1516 | ||
1517 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1518 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1519 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1520 | if (ip_obj) | |
1521 | put_obj(ip_obj); | |
1522 | } | |
1523 | } | |
1524 | ||
c030f2e4 | 1525 | amdgpu_ras_sysfs_remove_all(adev); |
1526 | return 0; | |
1527 | } | |
1528 | /* ras fs end */ | |
1529 | ||
1530 | /* ih begin */ | |
1531 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1532 | { | |
1533 | struct ras_ih_data *data = &obj->ih_data; | |
1534 | struct amdgpu_iv_entry entry; | |
1535 | int ret; | |
cf04dfd0 | 1536 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1537 | |
1538 | while (data->rptr != data->wptr) { | |
1539 | rmb(); | |
1540 | memcpy(&entry, &data->ring[data->rptr], | |
1541 | data->element_size); | |
1542 | ||
1543 | wmb(); | |
1544 | data->rptr = (data->aligned_element_size + | |
1545 | data->rptr) % data->ring_size; | |
1546 | ||
1547 | /* Let IP handle its data, maybe we need get the output | |
1548 | * from the callback to udpate the error type/count, etc | |
1549 | */ | |
1550 | if (data->cb) { | |
cf04dfd0 | 1551 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1552 | /* ue will trigger an interrupt, and in that case |
1553 | * we need do a reset to recovery the whole system. | |
1554 | * But leave IP do that recovery, here we just dispatch | |
1555 | * the error. | |
1556 | */ | |
bd2280da | 1557 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1558 | /* these counts could be left as 0 if |
1559 | * some blocks do not count error number | |
1560 | */ | |
cf04dfd0 | 1561 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1562 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1563 | } |
c030f2e4 | 1564 | } |
1565 | } | |
1566 | } | |
1567 | ||
1568 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1569 | { | |
1570 | struct ras_ih_data *data = | |
1571 | container_of(work, struct ras_ih_data, ih_work); | |
1572 | struct ras_manager *obj = | |
1573 | container_of(data, struct ras_manager, ih_data); | |
1574 | ||
1575 | amdgpu_ras_interrupt_handler(obj); | |
1576 | } | |
1577 | ||
1578 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1579 | struct ras_dispatch_if *info) | |
1580 | { | |
1581 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1582 | struct ras_ih_data *data = &obj->ih_data; | |
1583 | ||
1584 | if (!obj) | |
1585 | return -EINVAL; | |
1586 | ||
1587 | if (data->inuse == 0) | |
1588 | return 0; | |
1589 | ||
1590 | /* Might be overflow... */ | |
1591 | memcpy(&data->ring[data->wptr], info->entry, | |
1592 | data->element_size); | |
1593 | ||
1594 | wmb(); | |
1595 | data->wptr = (data->aligned_element_size + | |
1596 | data->wptr) % data->ring_size; | |
1597 | ||
1598 | schedule_work(&data->ih_work); | |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
1603 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1604 | struct ras_ih_if *info) | |
1605 | { | |
1606 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1607 | struct ras_ih_data *data; | |
1608 | ||
1609 | if (!obj) | |
1610 | return -EINVAL; | |
1611 | ||
1612 | data = &obj->ih_data; | |
1613 | if (data->inuse == 0) | |
1614 | return 0; | |
1615 | ||
1616 | cancel_work_sync(&data->ih_work); | |
1617 | ||
1618 | kfree(data->ring); | |
1619 | memset(data, 0, sizeof(*data)); | |
1620 | put_obj(obj); | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1626 | struct ras_ih_if *info) | |
1627 | { | |
1628 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1629 | struct ras_ih_data *data; | |
1630 | ||
1631 | if (!obj) { | |
1632 | /* in case we registe the IH before enable ras feature */ | |
1633 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1634 | if (!obj) | |
1635 | return -EINVAL; | |
1636 | } else | |
1637 | get_obj(obj); | |
1638 | ||
1639 | data = &obj->ih_data; | |
1640 | /* add the callback.etc */ | |
1641 | *data = (struct ras_ih_data) { | |
1642 | .inuse = 0, | |
1643 | .cb = info->cb, | |
1644 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1645 | .rptr = 0, | |
1646 | .wptr = 0, | |
1647 | }; | |
1648 | ||
1649 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1650 | ||
1651 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1652 | /* the ring can store 64 iv entries. */ | |
1653 | data->ring_size = 64 * data->aligned_element_size; | |
1654 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1655 | if (!data->ring) { | |
1656 | put_obj(obj); | |
1657 | return -ENOMEM; | |
1658 | } | |
1659 | ||
1660 | /* IH is ready */ | |
1661 | data->inuse = 1; | |
1662 | ||
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1667 | { | |
1668 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1669 | struct ras_manager *obj, *tmp; | |
1670 | ||
1671 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1672 | struct ras_ih_if info = { | |
1673 | .head = obj->head, | |
1674 | }; | |
1675 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1676 | } | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | /* ih end */ | |
1681 | ||
313c8fd3 GC |
1682 | /* traversal all IPs except NBIO to query error counter */ |
1683 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1684 | { | |
1685 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1686 | struct ras_manager *obj; | |
1687 | ||
8ab0d6f0 | 1688 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
1689 | return; |
1690 | ||
1691 | list_for_each_entry(obj, &con->head, node) { | |
1692 | struct ras_query_if info = { | |
1693 | .head = obj->head, | |
1694 | }; | |
1695 | ||
1696 | /* | |
1697 | * PCIE_BIF IP has one different isr by ras controller | |
1698 | * interrupt, the specific ras counter query will be | |
1699 | * done in that isr. So skip such block from common | |
1700 | * sync flood interrupt isr calling. | |
1701 | */ | |
1702 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1703 | continue; | |
1704 | ||
761d86d3 | 1705 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1706 | } |
1707 | } | |
1708 | ||
3f975d0f | 1709 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1710 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1711 | struct ras_query_if *info) | |
3f975d0f SY |
1712 | { |
1713 | /* | |
1714 | * Only two block need to query read/write | |
1715 | * RspStatus at current state | |
1716 | */ | |
1717 | switch (info->head.block) { | |
1718 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1719 | if (adev->gfx.ras_funcs && |
1720 | adev->gfx.ras_funcs->query_ras_error_status) | |
1721 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1722 | break; |
1723 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
1724 | if (adev->mmhub.ras_funcs && |
1725 | adev->mmhub.ras_funcs->query_ras_error_status) | |
1726 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1727 | break; |
1728 | default: | |
1729 | break; | |
1730 | } | |
1731 | } | |
1732 | ||
1733 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1734 | { | |
1735 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1736 | struct ras_manager *obj; | |
1737 | ||
8ab0d6f0 | 1738 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
1739 | return; |
1740 | ||
1741 | list_for_each_entry(obj, &con->head, node) { | |
1742 | struct ras_query_if info = { | |
1743 | .head = obj->head, | |
1744 | }; | |
1745 | ||
1746 | amdgpu_ras_error_status_query(adev, &info); | |
1747 | } | |
1748 | } | |
1749 | ||
c030f2e4 | 1750 | /* recovery begin */ |
466b1793 | 1751 | |
1752 | /* return 0 on success. | |
1753 | * caller need free bps. | |
1754 | */ | |
1755 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1756 | struct ras_badpage **bps, unsigned int *count) | |
1757 | { | |
1758 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1759 | struct ras_err_handler_data *data; | |
1760 | int i = 0; | |
732f2a30 | 1761 | int ret = 0, status; |
466b1793 | 1762 | |
1763 | if (!con || !con->eh_data || !bps || !count) | |
1764 | return -EINVAL; | |
1765 | ||
1766 | mutex_lock(&con->recovery_lock); | |
1767 | data = con->eh_data; | |
1768 | if (!data || data->count == 0) { | |
1769 | *bps = NULL; | |
46cf2fec | 1770 | ret = -EINVAL; |
466b1793 | 1771 | goto out; |
1772 | } | |
1773 | ||
1774 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1775 | if (!*bps) { | |
1776 | ret = -ENOMEM; | |
1777 | goto out; | |
1778 | } | |
1779 | ||
1780 | for (; i < data->count; i++) { | |
1781 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1782 | .bp = data->bps[i].retired_page, |
466b1793 | 1783 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1784 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1785 | }; |
732f2a30 | 1786 | status = amdgpu_vram_mgr_query_page_status( |
676deb38 DL |
1787 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), |
1788 | data->bps[i].retired_page); | |
732f2a30 | 1789 | if (status == -EBUSY) |
52dd95f2 | 1790 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1791 | else if (status == -ENOENT) |
52dd95f2 | 1792 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1793 | } |
1794 | ||
1795 | *count = data->count; | |
1796 | out: | |
1797 | mutex_unlock(&con->recovery_lock); | |
1798 | return ret; | |
1799 | } | |
1800 | ||
c030f2e4 | 1801 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1802 | { | |
1803 | struct amdgpu_ras *ras = | |
1804 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1805 | struct amdgpu_device *remote_adev = NULL; |
1806 | struct amdgpu_device *adev = ras->adev; | |
1807 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1808 | |
f75e94d8 | 1809 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1810 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1811 | ||
f75e94d8 GC |
1812 | /* Build list of devices to query RAS related errors */ |
1813 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1814 | device_list_handle = &hive->device_list; | |
1815 | } else { | |
1816 | INIT_LIST_HEAD(&device_list); | |
1817 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1818 | device_list_handle = &device_list; | |
1819 | } | |
c030f2e4 | 1820 | |
f75e94d8 | 1821 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1822 | device_list_handle, gmc.xgmi.head) { |
1823 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1824 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1825 | } |
d95e8e97 DL |
1826 | |
1827 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1828 | } |
313c8fd3 | 1829 | |
93af20f7 | 1830 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1831 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1832 | atomic_set(&ras->in_recovery, 0); |
1833 | } | |
1834 | ||
c030f2e4 | 1835 | /* alloc/realloc bps array */ |
1836 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1837 | struct ras_err_handler_data *data, int pages) | |
1838 | { | |
1839 | unsigned int old_space = data->count + data->space_left; | |
1840 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1841 | unsigned int align_space = ALIGN(new_space, 512); |
1842 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1843 | |
676deb38 | 1844 | if (!bps) { |
9dc23a63 | 1845 | kfree(bps); |
c030f2e4 | 1846 | return -ENOMEM; |
9dc23a63 | 1847 | } |
c030f2e4 | 1848 | |
1849 | if (data->bps) { | |
9dc23a63 | 1850 | memcpy(bps, data->bps, |
c030f2e4 | 1851 | data->count * sizeof(*data->bps)); |
1852 | kfree(data->bps); | |
1853 | } | |
1854 | ||
9dc23a63 | 1855 | data->bps = bps; |
c030f2e4 | 1856 | data->space_left += align_space - old_space; |
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | /* it deal with vram only. */ | |
1861 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1862 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1863 | { |
1864 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1865 | struct ras_err_handler_data *data; |
c030f2e4 | 1866 | int ret = 0; |
676deb38 | 1867 | uint32_t i; |
c030f2e4 | 1868 | |
73aa8e1a | 1869 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1870 | return 0; |
1871 | ||
1872 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1873 | data = con->eh_data; |
c030f2e4 | 1874 | if (!data) |
1875 | goto out; | |
1876 | ||
676deb38 DL |
1877 | for (i = 0; i < pages; i++) { |
1878 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1879 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1880 | continue; | |
1881 | ||
1882 | if (!data->space_left && | |
1883 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1884 | ret = -ENOMEM; |
1885 | goto out; | |
1886 | } | |
1887 | ||
676deb38 DL |
1888 | amdgpu_vram_mgr_reserve_range( |
1889 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1890 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1891 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1892 | |
676deb38 DL |
1893 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1894 | data->count++; | |
1895 | data->space_left--; | |
1896 | } | |
c030f2e4 | 1897 | out: |
1898 | mutex_unlock(&con->recovery_lock); | |
1899 | ||
1900 | return ret; | |
1901 | } | |
1902 | ||
78ad00c9 TZ |
1903 | /* |
1904 | * write error record array to eeprom, the function should be | |
1905 | * protected by recovery_lock | |
1906 | */ | |
22503d80 | 1907 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1908 | { |
1909 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1910 | struct ras_err_handler_data *data; | |
8a3e801f | 1911 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1912 | int save_count; |
1913 | ||
1914 | if (!con || !con->eh_data) | |
1915 | return 0; | |
1916 | ||
8a3e801f | 1917 | control = &con->eeprom_control; |
78ad00c9 | 1918 | data = con->eh_data; |
0686627b | 1919 | save_count = data->count - control->ras_num_recs; |
78ad00c9 | 1920 | /* only new entries are saved */ |
b1628425 | 1921 | if (save_count > 0) { |
63d4c081 LT |
1922 | if (amdgpu_ras_eeprom_append(control, |
1923 | &data->bps[control->ras_num_recs], | |
1924 | save_count)) { | |
6952e99c | 1925 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1926 | return -EIO; |
1927 | } | |
1928 | ||
b1628425 GC |
1929 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1930 | } | |
1931 | ||
78ad00c9 TZ |
1932 | return 0; |
1933 | } | |
1934 | ||
1935 | /* | |
1936 | * read error record array in eeprom and reserve enough space for | |
1937 | * storing new bad pages | |
1938 | */ | |
1939 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1940 | { | |
1941 | struct amdgpu_ras_eeprom_control *control = | |
6457205c | 1942 | &adev->psp.ras_context.ras->eeprom_control; |
e4e6a589 LT |
1943 | struct eeprom_table_record *bps; |
1944 | int ret; | |
78ad00c9 TZ |
1945 | |
1946 | /* no bad page record, skip eeprom access */ | |
0686627b | 1947 | if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) |
e4e6a589 | 1948 | return 0; |
78ad00c9 | 1949 | |
0686627b | 1950 | bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); |
78ad00c9 TZ |
1951 | if (!bps) |
1952 | return -ENOMEM; | |
1953 | ||
0686627b | 1954 | ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); |
e4e6a589 | 1955 | if (ret) |
6952e99c | 1956 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
e4e6a589 | 1957 | else |
0686627b | 1958 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); |
78ad00c9 | 1959 | |
78ad00c9 TZ |
1960 | kfree(bps); |
1961 | return ret; | |
1962 | } | |
1963 | ||
676deb38 DL |
1964 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1965 | uint64_t addr) | |
1966 | { | |
1967 | struct ras_err_handler_data *data = con->eh_data; | |
1968 | int i; | |
1969 | ||
1970 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1971 | for (i = 0; i < data->count; i++) | |
1972 | if (addr == data->bps[i].retired_page) | |
1973 | return true; | |
1974 | ||
1975 | return false; | |
1976 | } | |
1977 | ||
6e4be987 TZ |
1978 | /* |
1979 | * check if an address belongs to bad page | |
1980 | * | |
1981 | * Note: this check is only for umc block | |
1982 | */ | |
1983 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1984 | uint64_t addr) | |
1985 | { | |
1986 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1987 | bool ret = false; |
1988 | ||
1989 | if (!con || !con->eh_data) | |
1990 | return ret; | |
1991 | ||
1992 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1993 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1994 | mutex_unlock(&con->recovery_lock); |
1995 | return ret; | |
1996 | } | |
1997 | ||
e5c04edf | 1998 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
e4e6a589 | 1999 | uint32_t max_count) |
c84d4670 | 2000 | { |
e5c04edf | 2001 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
2002 | |
2003 | /* | |
2004 | * Justification of value bad_page_cnt_threshold in ras structure | |
2005 | * | |
2006 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
2007 | * in eeprom, and introduce two scenarios accordingly. | |
2008 | * | |
2009 | * Bad page retirement enablement: | |
2010 | * - If amdgpu_bad_page_threshold = -1, | |
2011 | * bad_page_cnt_threshold = typical value by formula. | |
2012 | * | |
2013 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
2014 | * max record length in eeprom, use it directly. | |
2015 | * | |
2016 | * Bad page retirement disablement: | |
2017 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
2018 | * functionality is disabled, and bad_page_cnt_threshold will | |
2019 | * take no effect. | |
2020 | */ | |
2021 | ||
e4e6a589 LT |
2022 | if (amdgpu_bad_page_threshold < 0) { |
2023 | u64 val = adev->gmc.mc_vram_size; | |
c84d4670 | 2024 | |
e4e6a589 | 2025 | do_div(val, RAS_BAD_PAGE_COVER); |
e5c04edf | 2026 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
e4e6a589 | 2027 | max_count); |
e5c04edf | 2028 | } else { |
e4e6a589 LT |
2029 | con->bad_page_cnt_threshold = min_t(int, max_count, |
2030 | amdgpu_bad_page_threshold); | |
c84d4670 GC |
2031 | } |
2032 | } | |
2033 | ||
1a6fc071 | 2034 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 2035 | { |
2036 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 2037 | struct ras_err_handler_data **data; |
e4e6a589 | 2038 | u32 max_eeprom_records_count = 0; |
b82e65a9 | 2039 | bool exc_err_limit = false; |
78ad00c9 | 2040 | int ret; |
c030f2e4 | 2041 | |
1d9d2ca8 LT |
2042 | if (!con) |
2043 | return 0; | |
2044 | ||
2045 | /* Allow access to RAS EEPROM via debugfs, when the ASIC | |
2046 | * supports RAS and debugfs is enabled, but when | |
2047 | * adev->ras_enabled is unset, i.e. when "ras_enable" | |
2048 | * module parameter is set to 0. | |
2049 | */ | |
2050 | con->adev = adev; | |
2051 | ||
2052 | if (!adev->ras_enabled) | |
4d1337d2 AG |
2053 | return 0; |
2054 | ||
1d9d2ca8 | 2055 | data = &con->eh_data; |
1a6fc071 TZ |
2056 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
2057 | if (!*data) { | |
2058 | ret = -ENOMEM; | |
2059 | goto out; | |
2060 | } | |
c030f2e4 | 2061 | |
2062 | mutex_init(&con->recovery_lock); | |
2063 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
2064 | atomic_set(&con->in_recovery, 0); | |
c030f2e4 | 2065 | |
e4e6a589 LT |
2066 | max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(); |
2067 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); | |
c84d4670 | 2068 | |
e5086659 | 2069 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
2070 | * when the GPU is pending on XGMI reset during probe time | |
2071 | * (Mostly after second bus reset), skip it now | |
2072 | */ | |
2073 | if (adev->gmc.xgmi.pending_reset) | |
2074 | return 0; | |
b82e65a9 GC |
2075 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
2076 | /* | |
2077 | * This calling fails when exc_err_limit is true or | |
2078 | * ret != 0. | |
2079 | */ | |
2080 | if (exc_err_limit || ret) | |
1a6fc071 | 2081 | goto free; |
78ad00c9 | 2082 | |
0686627b | 2083 | if (con->eeprom_control.ras_num_recs) { |
78ad00c9 TZ |
2084 | ret = amdgpu_ras_load_bad_pages(adev); |
2085 | if (ret) | |
1a6fc071 | 2086 | goto free; |
513befa6 SY |
2087 | |
2088 | if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) | |
0686627b | 2089 | adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs); |
78ad00c9 | 2090 | } |
c030f2e4 | 2091 | |
2092 | return 0; | |
1a6fc071 | 2093 | |
1a6fc071 | 2094 | free: |
1a6fc071 | 2095 | kfree((*data)->bps); |
1a6fc071 | 2096 | kfree(*data); |
1995b3a3 | 2097 | con->eh_data = NULL; |
1a6fc071 | 2098 | out: |
cf696091 | 2099 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2100 | |
b82e65a9 GC |
2101 | /* |
2102 | * Except error threshold exceeding case, other failure cases in this | |
2103 | * function would not fail amdgpu driver init. | |
2104 | */ | |
2105 | if (!exc_err_limit) | |
2106 | ret = 0; | |
2107 | else | |
2108 | ret = -EINVAL; | |
2109 | ||
1a6fc071 | 2110 | return ret; |
c030f2e4 | 2111 | } |
2112 | ||
2113 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2114 | { | |
2115 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2116 | struct ras_err_handler_data *data = con->eh_data; | |
2117 | ||
1a6fc071 TZ |
2118 | /* recovery_init failed to init it, fini is useless */ |
2119 | if (!data) | |
2120 | return 0; | |
2121 | ||
c030f2e4 | 2122 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2123 | |
2124 | mutex_lock(&con->recovery_lock); | |
2125 | con->eh_data = NULL; | |
2126 | kfree(data->bps); | |
2127 | kfree(data); | |
2128 | mutex_unlock(&con->recovery_lock); | |
2129 | ||
2130 | return 0; | |
2131 | } | |
2132 | /* recovery end */ | |
2133 | ||
a564808e | 2134 | /* return 0 if ras will reset gpu and repost.*/ |
2135 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
2136 | unsigned int block) | |
2137 | { | |
2138 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2139 | ||
2140 | if (!ras) | |
2141 | return -EINVAL; | |
2142 | ||
2143 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2144 | return 0; | |
2145 | } | |
2146 | ||
084e2640 | 2147 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2148 | { |
084e2640 LT |
2149 | return adev->asic_type == CHIP_VEGA10 || |
2150 | adev->asic_type == CHIP_VEGA20 || | |
2151 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2152 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2153 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2154 | } |
2155 | ||
f50160cf SY |
2156 | /* |
2157 | * this is workaround for vega20 workstation sku, | |
2158 | * force enable gfx ras, ignore vbios gfx ras flag | |
2159 | * due to GC EDC can not write | |
2160 | */ | |
e509965e | 2161 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2162 | { |
2163 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2164 | ||
2165 | if (!ctx) | |
2166 | return; | |
2167 | ||
2168 | if (strnstr(ctx->vbios_version, "D16406", | |
e11d5e0d SY |
2169 | sizeof(ctx->vbios_version)) || |
2170 | strnstr(ctx->vbios_version, "D36002", | |
2171 | sizeof(ctx->vbios_version))) | |
8ab0d6f0 | 2172 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2173 | } |
2174 | ||
5caf466a | 2175 | /* |
2176 | * check hardware's ras ability which will be saved in hw_supported. | |
2177 | * if hardware does not support ras, we can skip some ras initializtion and | |
2178 | * forbid some ras operations from IP. | |
2179 | * if software itself, say boot parameter, limit the ras ability. We still | |
2180 | * need allow IP do some limited operations, like disable. In such case, | |
2181 | * we have to initialize ras as normal. but need check if operation is | |
2182 | * allowed or not in each function. | |
2183 | */ | |
e509965e | 2184 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2185 | { |
8ab0d6f0 | 2186 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2187 | |
88474cca | 2188 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 2189 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 2190 | return; |
b404ae82 | 2191 | |
75f06251 HZ |
2192 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2193 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2194 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2195 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2196 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2197 | } else { |
2198 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2199 | } | |
88474cca | 2200 | |
75f06251 HZ |
2201 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2202 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
8ab0d6f0 | 2203 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2204 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2205 | } else { |
2206 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2207 | } | |
2208 | } else { | |
2209 | /* driver only manages a few IP blocks RAS feature | |
2210 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2211 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2212 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2213 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2214 | } |
88474cca | 2215 | |
e509965e | 2216 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2217 | |
88474cca | 2218 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2219 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2220 | |
8ab0d6f0 LT |
2221 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2222 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2223 | } |
2224 | ||
05adfd80 LT |
2225 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2226 | { | |
2227 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2228 | ras_counte_delay_work.work); | |
2229 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2230 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2231 | unsigned long ce_count, ue_count; |
2232 | int res; | |
2233 | ||
2234 | res = pm_runtime_get_sync(dev->dev); | |
2235 | if (res < 0) | |
2236 | goto Out; | |
2237 | ||
2238 | /* Cache new values. | |
2239 | */ | |
4d9f771e LT |
2240 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { |
2241 | atomic_set(&con->ras_ce_count, ce_count); | |
2242 | atomic_set(&con->ras_ue_count, ue_count); | |
2243 | } | |
05adfd80 LT |
2244 | |
2245 | pm_runtime_mark_last_busy(dev->dev); | |
2246 | Out: | |
2247 | pm_runtime_put_autosuspend(dev->dev); | |
2248 | } | |
2249 | ||
c030f2e4 | 2250 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2251 | { | |
2252 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2253 | int r; |
c030f2e4 | 2254 | |
b404ae82 | 2255 | if (con) |
c030f2e4 | 2256 | return 0; |
2257 | ||
2258 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
640ae42e JC |
2259 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + |
2260 | sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, | |
c030f2e4 | 2261 | GFP_KERNEL|__GFP_ZERO); |
2262 | if (!con) | |
2263 | return -ENOMEM; | |
2264 | ||
05adfd80 LT |
2265 | con->adev = adev; |
2266 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2267 | atomic_set(&con->ras_ce_count, 0); | |
2268 | atomic_set(&con->ras_ue_count, 0); | |
2269 | ||
c030f2e4 | 2270 | con->objs = (struct ras_manager *)(con + 1); |
2271 | ||
2272 | amdgpu_ras_set_context(adev, con); | |
2273 | ||
e509965e LT |
2274 | amdgpu_ras_check_supported(adev); |
2275 | ||
7ddd9770 | 2276 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2277 | /* set gfx block ras context feature for VEGA20 Gaming |
2278 | * send ras disable cmd to ras ta during ras late init. | |
2279 | */ | |
8ab0d6f0 | 2280 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2281 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2282 | ||
2283 | return 0; | |
2284 | } | |
2285 | ||
5e91160a | 2286 | r = 0; |
5436ab94 | 2287 | goto release_con; |
fb2a3607 HZ |
2288 | } |
2289 | ||
c030f2e4 | 2290 | con->features = 0; |
2291 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2292 | /* Might need get this flag from vbios. */ |
2293 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2294 | |
6e36f231 HZ |
2295 | /* initialize nbio ras function ahead of any other |
2296 | * ras functions so hardware fatal error interrupt | |
2297 | * can be enabled as early as possible */ | |
2298 | switch (adev->asic_type) { | |
2299 | case CHIP_VEGA20: | |
2300 | case CHIP_ARCTURUS: | |
2301 | case CHIP_ALDEBARAN: | |
2302 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2303 | adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs; | |
2304 | break; | |
2305 | default: | |
2306 | /* nbio ras is not available */ | |
2307 | break; | |
2308 | } | |
2309 | ||
2310 | if (adev->nbio.ras_funcs && | |
2311 | adev->nbio.ras_funcs->init_ras_controller_interrupt) { | |
2312 | r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev); | |
4e644fff | 2313 | if (r) |
5436ab94 | 2314 | goto release_con; |
4e644fff HZ |
2315 | } |
2316 | ||
6e36f231 HZ |
2317 | if (adev->nbio.ras_funcs && |
2318 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) { | |
2319 | r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2320 | if (r) |
5436ab94 | 2321 | goto release_con; |
4e644fff HZ |
2322 | } |
2323 | ||
5e91160a GC |
2324 | if (amdgpu_ras_fs_init(adev)) { |
2325 | r = -EINVAL; | |
5436ab94 | 2326 | goto release_con; |
5e91160a | 2327 | } |
c030f2e4 | 2328 | |
6952e99c | 2329 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2330 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2331 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2332 | |
c030f2e4 | 2333 | return 0; |
5436ab94 | 2334 | release_con: |
c030f2e4 | 2335 | amdgpu_ras_set_context(adev, NULL); |
2336 | kfree(con); | |
2337 | ||
5e91160a | 2338 | return r; |
c030f2e4 | 2339 | } |
2340 | ||
8f6368a9 | 2341 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 JC |
2342 | { |
2343 | if (adev->gmc.xgmi.connected_to_cpu) | |
2344 | return 1; | |
2345 | return 0; | |
2346 | } | |
2347 | ||
2348 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2349 | struct ras_common_if *ras_block) | |
2350 | { | |
2351 | struct ras_query_if info = { | |
2352 | .head = *ras_block, | |
2353 | }; | |
2354 | ||
2355 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2356 | return 0; | |
2357 | ||
2358 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2359 | DRM_WARN("RAS init harvest failure"); | |
2360 | ||
2361 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2362 | DRM_WARN("RAS init harvest reset failure"); | |
2363 | ||
2364 | return 0; | |
2365 | } | |
2366 | ||
b293e891 HZ |
2367 | /* helper function to handle common stuff in ip late init phase */ |
2368 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2369 | struct ras_common_if *ras_block, | |
2370 | struct ras_fs_if *fs_info, | |
2371 | struct ras_ih_if *ih_info) | |
2372 | { | |
05adfd80 LT |
2373 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2374 | unsigned long ue_count, ce_count; | |
b293e891 HZ |
2375 | int r; |
2376 | ||
2377 | /* disable RAS feature per IP block if it is not supported */ | |
2378 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2379 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2380 | return 0; | |
2381 | } | |
2382 | ||
2383 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2384 | if (r) { | |
2385 | if (r == -EAGAIN) { | |
2386 | /* request gpu reset. will run again */ | |
2387 | amdgpu_ras_request_reset_on_boot(adev, | |
2388 | ras_block->block); | |
2389 | return 0; | |
53b3f8f4 | 2390 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2391 | /* in resume phase, if fail to enable ras, |
2392 | * clean up all ras fs nodes, and disable ras */ | |
2393 | goto cleanup; | |
2394 | } else | |
2395 | return r; | |
2396 | } | |
2397 | ||
134d16d5 JC |
2398 | /* check for errors on warm reset edc persisant supported ASIC */ |
2399 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2400 | ||
b293e891 | 2401 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2402 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2403 | return 0; |
2404 | ||
2405 | if (ih_info->cb) { | |
2406 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2407 | if (r) | |
2408 | goto interrupt; | |
2409 | } | |
2410 | ||
b293e891 HZ |
2411 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2412 | if (r) | |
2413 | goto sysfs; | |
2414 | ||
05adfd80 LT |
2415 | /* Those are the cached values at init. |
2416 | */ | |
4d9f771e LT |
2417 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) { |
2418 | atomic_set(&con->ras_ce_count, ce_count); | |
2419 | atomic_set(&con->ras_ue_count, ue_count); | |
2420 | } | |
05adfd80 | 2421 | |
b293e891 HZ |
2422 | return 0; |
2423 | cleanup: | |
2424 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2425 | sysfs: | |
b293e891 HZ |
2426 | if (ih_info->cb) |
2427 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2428 | interrupt: | |
2429 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2430 | return r; | |
2431 | } | |
2432 | ||
2433 | /* helper function to remove ras fs node and interrupt handler */ | |
2434 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2435 | struct ras_common_if *ras_block, | |
2436 | struct ras_ih_if *ih_info) | |
2437 | { | |
2438 | if (!ras_block || !ih_info) | |
2439 | return; | |
2440 | ||
2441 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2442 | if (ih_info->cb) |
f3729f7b | 2443 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2444 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2445 | } | |
2446 | ||
a564808e | 2447 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2448 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2449 | */ |
511fdbc3 | 2450 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2451 | { |
2452 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2453 | struct ras_manager *obj, *tmp; | |
2454 | ||
8ab0d6f0 | 2455 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2456 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2457 | amdgpu_release_ras_context(adev); | |
2458 | ||
108c6a63 | 2459 | return; |
970fd197 | 2460 | } |
108c6a63 | 2461 | |
108c6a63 | 2462 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2463 | /* Set up all other IPs which are not implemented. There is a |
2464 | * tricky thing that IP's actual ras error type should be | |
2465 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2466 | * ERROR_NONE make sense anyway. | |
2467 | */ | |
2468 | amdgpu_ras_enable_all_features(adev, 1); | |
2469 | ||
2470 | /* We enable ras on all hw_supported block, but as boot | |
2471 | * parameter might disable some of them and one or more IP has | |
2472 | * not implemented yet. So we disable them on behalf. | |
2473 | */ | |
108c6a63 | 2474 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2475 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2476 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2477 | /* there should be no any reference. */ | |
2478 | WARN_ON(alive_obj(obj)); | |
2479 | } | |
191051a1 | 2480 | } |
108c6a63 | 2481 | } |
a564808e | 2482 | |
2483 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2484 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2485 | /* setup ras obj state as disabled. | |
2486 | * for init_by_vbios case. | |
2487 | * if we want to enable ras, just enable it in a normal way. | |
2488 | * If we want do disable it, need setup ras obj as enabled, | |
2489 | * then issue another TA disable cmd. | |
2490 | * See feature_enable_on_boot | |
2491 | */ | |
2492 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2493 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2494 | } |
108c6a63 | 2495 | } |
2496 | ||
511fdbc3 | 2497 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2498 | { | |
2499 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2500 | ||
8ab0d6f0 | 2501 | if (!adev->ras_enabled || !con) |
511fdbc3 | 2502 | return; |
2503 | ||
2504 | amdgpu_ras_disable_all_features(adev, 0); | |
2505 | /* Make sure all ras objects are disabled. */ | |
2506 | if (con->features) | |
2507 | amdgpu_ras_disable_all_features(adev, 1); | |
2508 | } | |
2509 | ||
c030f2e4 | 2510 | /* do some fini work before IP fini as dependence */ |
2511 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2512 | { | |
2513 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2514 | ||
8ab0d6f0 | 2515 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2516 | return 0; |
2517 | ||
72c8c97b | 2518 | |
c030f2e4 | 2519 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
2520 | amdgpu_ras_disable_all_features(adev, 0); | |
2521 | amdgpu_ras_recovery_fini(adev); | |
2522 | return 0; | |
2523 | } | |
2524 | ||
2525 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2526 | { | |
2527 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2528 | ||
8ab0d6f0 | 2529 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2530 | return 0; |
2531 | ||
2532 | amdgpu_ras_fs_fini(adev); | |
2533 | amdgpu_ras_interrupt_remove_all(adev); | |
2534 | ||
2535 | WARN(con->features, "Feature mask is not cleared"); | |
2536 | ||
2537 | if (con->features) | |
2538 | amdgpu_ras_disable_all_features(adev, 1); | |
2539 | ||
05adfd80 LT |
2540 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
2541 | ||
c030f2e4 | 2542 | amdgpu_ras_set_context(adev, NULL); |
2543 | kfree(con); | |
2544 | ||
2545 | return 0; | |
2546 | } | |
7c6e68c7 AG |
2547 | |
2548 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2549 | { | |
e509965e | 2550 | amdgpu_ras_check_supported(adev); |
8ab0d6f0 | 2551 | if (!adev->ras_hw_enabled) |
ed606f8a AG |
2552 | return; |
2553 | ||
7c6e68c7 | 2554 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2555 | dev_info(adev->dev, "uncorrectable hardware error" |
2556 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2557 | |
61934624 | 2558 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2559 | } |
2560 | } | |
bb5c7235 WS |
2561 | |
2562 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2563 | { | |
2564 | if (adev->asic_type == CHIP_VEGA20 && | |
2565 | adev->pm.fw_version <= 0x283400) { | |
2566 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2567 | amdgpu_ras_intr_triggered(); | |
2568 | } | |
2569 | ||
2570 | return false; | |
2571 | } | |
970fd197 SY |
2572 | |
2573 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2574 | { | |
2575 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2576 | ||
2577 | if (!con) | |
2578 | return; | |
2579 | ||
8ab0d6f0 | 2580 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
2581 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
2582 | amdgpu_ras_set_context(adev, NULL); | |
2583 | kfree(con); | |
2584 | } | |
2585 | } |