Commit | Line | Data |
---|---|---|
c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
dbf3850d | 31 | #include <linux/list_sort.h> |
f867723b | 32 | |
c030f2e4 | 33 | #include "amdgpu.h" |
34 | #include "amdgpu_ras.h" | |
b404ae82 | 35 | #include "amdgpu_atomfirmware.h" |
19744f5f | 36 | #include "amdgpu_xgmi.h" |
4e644fff | 37 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
9af357bc | 38 | #include "nbio_v4_3.h" |
7692e1ee | 39 | #include "nbio_v7_9.h" |
f50160cf | 40 | #include "atom.h" |
25a2b22e | 41 | #include "amdgpu_reset.h" |
4e2965bd | 42 | #include "amdgpu_psp.h" |
25a2b22e | 43 | |
12b2cab7 MJ |
44 | #ifdef CONFIG_X86_MCE_AMD |
45 | #include <asm/mce.h> | |
c030f2e4 | 46 | |
12b2cab7 MJ |
47 | static bool notifier_registered; |
48 | #endif | |
eb0c3cd4 GC |
49 | static const char *RAS_FS_NAME = "ras"; |
50 | ||
c030f2e4 | 51 | const char *ras_error_string[] = { |
52 | "none", | |
53 | "parity", | |
54 | "single_correctable", | |
55 | "multi_uncorrectable", | |
56 | "poison", | |
57 | }; | |
58 | ||
59 | const char *ras_block_string[] = { | |
60 | "umc", | |
61 | "sdma", | |
62 | "gfx", | |
63 | "mmhub", | |
64 | "athub", | |
65 | "pcie_bif", | |
66 | "hdp", | |
67 | "xgmi_wafl", | |
68 | "df", | |
69 | "smn", | |
70 | "sem", | |
71 | "mp0", | |
72 | "mp1", | |
73 | "fuse", | |
640ae42e | 74 | "mca", |
a3d63c62 MZZ |
75 | "vcn", |
76 | "jpeg", | |
7ed97155 YW |
77 | "ih", |
78 | "mpio", | |
c030f2e4 | 79 | }; |
80 | ||
640ae42e JC |
81 | const char *ras_mca_block_string[] = { |
82 | "mca_mp0", | |
83 | "mca_mp1", | |
84 | "mca_mpio", | |
85 | "mca_iohc", | |
86 | }; | |
87 | ||
d5e8ff5f | 88 | struct amdgpu_ras_block_list { |
89 | /* ras block link */ | |
90 | struct list_head node; | |
91 | ||
92 | struct amdgpu_ras_block_object *ras_obj; | |
93 | }; | |
94 | ||
640ae42e JC |
95 | const char *get_ras_block_str(struct ras_common_if *ras_block) |
96 | { | |
97 | if (!ras_block) | |
98 | return "NULL"; | |
99 | ||
7ed97155 YW |
100 | if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || |
101 | ras_block->block >= ARRAY_SIZE(ras_block_string)) | |
640ae42e JC |
102 | return "OUT OF RANGE"; |
103 | ||
104 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) | |
105 | return ras_mca_block_string[ras_block->sub_block_index]; | |
106 | ||
107 | return ras_block_string[ras_block->block]; | |
108 | } | |
109 | ||
954ea6aa | 110 | #define ras_block_str(_BLOCK_) \ |
111 | (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") | |
8b0fb0e9 | 112 | |
c030f2e4 | 113 | #define ras_err_str(i) (ras_error_string[ffs(i)]) |
c030f2e4 | 114 | |
108c6a63 | 115 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
116 | ||
7cdc2ee3 TZ |
117 | /* inject address is 52 bits */ |
118 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
119 | ||
e4e6a589 LT |
120 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
121 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) | |
c84d4670 | 122 | |
6c23f3d1 YC |
123 | #define MAX_UMC_POISON_POLLING_TIME_ASYNC 100 //ms |
124 | ||
52dd95f2 GC |
125 | enum amdgpu_ras_retire_page_reservation { |
126 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
127 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
128 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
129 | }; | |
7c6e68c7 AG |
130 | |
131 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
132 | ||
676deb38 DL |
133 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
134 | uint64_t addr); | |
6e4be987 TZ |
135 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
136 | uint64_t addr); | |
12b2cab7 | 137 | #ifdef CONFIG_X86_MCE_AMD |
91a1a52d MJ |
138 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); |
139 | struct mce_notifier_adev_list { | |
140 | struct amdgpu_device *devs[MAX_GPU_INSTANCE]; | |
141 | int num_gpu; | |
142 | }; | |
143 | static struct mce_notifier_adev_list mce_adev_list; | |
12b2cab7 | 144 | #endif |
6e4be987 | 145 | |
61380faa JC |
146 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
147 | { | |
a9d82d2f | 148 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
149 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
150 | } | |
151 | ||
f3167919 | 152 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 153 | { |
a9d82d2f | 154 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
155 | return amdgpu_ras_get_context(adev)->error_query_ready; |
156 | ||
157 | return false; | |
158 | } | |
159 | ||
cbb8f989 JC |
160 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
161 | { | |
5b1270be | 162 | struct ras_err_data err_data; |
cbb8f989 | 163 | struct eeprom_table_record err_rec; |
5b1270be | 164 | int ret; |
cbb8f989 JC |
165 | |
166 | if ((address >= adev->gmc.mc_vram_size) || | |
167 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
168 | dev_warn(adev->dev, | |
169 | "RAS WARN: input address 0x%llx is invalid.\n", | |
170 | address); | |
171 | return -EINVAL; | |
172 | } | |
173 | ||
174 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
175 | dev_warn(adev->dev, | |
80b0cd0f | 176 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
177 | address); |
178 | return 0; | |
179 | } | |
180 | ||
5b1270be YW |
181 | ret = amdgpu_ras_error_data_init(&err_data); |
182 | if (ret) | |
183 | return ret; | |
184 | ||
cbb8f989 | 185 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); |
cbb8f989 | 186 | err_data.err_addr = &err_rec; |
71344a71 | 187 | amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0); |
cbb8f989 JC |
188 | |
189 | if (amdgpu_bad_page_threshold != 0) { | |
190 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
191 | err_data.err_addr_cnt); | |
4d33e0f1 | 192 | amdgpu_ras_save_bad_pages(adev, NULL); |
cbb8f989 JC |
193 | } |
194 | ||
5b1270be YW |
195 | amdgpu_ras_error_data_fini(&err_data); |
196 | ||
cbb8f989 JC |
197 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); |
198 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
199 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
c030f2e4 | 204 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
205 | size_t size, loff_t *pos) | |
206 | { | |
207 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
208 | struct ras_query_if info = { | |
209 | .head = obj->head, | |
210 | }; | |
211 | ssize_t s; | |
212 | char val[128]; | |
213 | ||
761d86d3 | 214 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 215 | return -EINVAL; |
216 | ||
2a460963 | 217 | /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */ |
4e8303cf LL |
218 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
219 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
2a460963 CL |
220 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
221 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); | |
222 | } | |
223 | ||
c030f2e4 | 224 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", |
225 | "ue", info.ue_count, | |
226 | "ce", info.ce_count); | |
227 | if (*pos >= s) | |
228 | return 0; | |
229 | ||
230 | s -= *pos; | |
231 | s = min_t(u64, s, size); | |
232 | ||
233 | ||
234 | if (copy_to_user(buf, &val[*pos], s)) | |
235 | return -EINVAL; | |
236 | ||
237 | *pos += s; | |
238 | ||
239 | return s; | |
240 | } | |
241 | ||
c030f2e4 | 242 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
243 | .owner = THIS_MODULE, | |
244 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 245 | .write = NULL, |
c030f2e4 | 246 | .llseek = default_llseek |
247 | }; | |
248 | ||
96ebb307 | 249 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
250 | { | |
251 | int i; | |
252 | ||
253 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
254 | *block_id = i; | |
640ae42e | 255 | if (strcmp(name, ras_block_string[i]) == 0) |
96ebb307 | 256 | return 0; |
257 | } | |
258 | return -EINVAL; | |
259 | } | |
260 | ||
261 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
262 | const char __user *buf, size_t size, | |
263 | loff_t *pos, struct ras_debug_if *data) | |
264 | { | |
265 | ssize_t s = min_t(u64, 64, size); | |
266 | char str[65]; | |
267 | char block_name[33]; | |
268 | char err[9] = "ue"; | |
269 | int op = -1; | |
270 | int block_id; | |
44494f96 | 271 | uint32_t sub_block; |
96ebb307 | 272 | u64 address, value; |
2c22ed0b TZ |
273 | /* default value is 0 if the mask is not set by user */ |
274 | u32 instance_mask = 0; | |
96ebb307 | 275 | |
276 | if (*pos) | |
277 | return -EINVAL; | |
278 | *pos = size; | |
279 | ||
280 | memset(str, 0, sizeof(str)); | |
281 | memset(data, 0, sizeof(*data)); | |
282 | ||
283 | if (copy_from_user(str, buf, s)) | |
284 | return -EINVAL; | |
285 | ||
286 | if (sscanf(str, "disable %32s", block_name) == 1) | |
287 | op = 0; | |
288 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
289 | op = 1; | |
290 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
291 | op = 2; | |
6df23f4c | 292 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 293 | op = 3; |
b076296b | 294 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 295 | /* ascii string, but commands are not matched. */ |
296 | return -EINVAL; | |
297 | ||
298 | if (op != -1) { | |
cbb8f989 | 299 | if (op == 3) { |
546aa546 LT |
300 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
301 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 302 | return -EINVAL; |
cbb8f989 JC |
303 | |
304 | data->op = op; | |
305 | data->inject.address = address; | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
96ebb307 | 310 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
311 | return -EINVAL; | |
312 | ||
313 | data->head.block = block_id; | |
fb1e9171 | 314 | /* only ue, ce and poison errors are supported */ |
e1063493 TZ |
315 | if (!memcmp("ue", err, 2)) |
316 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
317 | else if (!memcmp("ce", err, 2)) | |
318 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
fb1e9171 CL |
319 | else if (!memcmp("poison", err, 6)) |
320 | data->head.type = AMDGPU_RAS_ERROR__POISON; | |
e1063493 TZ |
321 | else |
322 | return -EINVAL; | |
323 | ||
96ebb307 | 324 | data->op = op; |
325 | ||
326 | if (op == 2) { | |
2c22ed0b TZ |
327 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x", |
328 | &sub_block, &address, &value, &instance_mask) != 4 && | |
329 | sscanf(str, "%*s %*s %*s %u %llu %llu %u", | |
330 | &sub_block, &address, &value, &instance_mask) != 4 && | |
331 | sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
546aa546 LT |
332 | &sub_block, &address, &value) != 3 && |
333 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
334 | &sub_block, &address, &value) != 3) |
335 | return -EINVAL; | |
44494f96 | 336 | data->head.sub_block_index = sub_block; |
96ebb307 | 337 | data->inject.address = address; |
338 | data->inject.value = value; | |
2c22ed0b | 339 | data->inject.instance_mask = instance_mask; |
96ebb307 | 340 | } |
341 | } else { | |
73aa8e1a | 342 | if (size < sizeof(*data)) |
96ebb307 | 343 | return -EINVAL; |
344 | ||
345 | if (copy_from_user(data, buf, sizeof(*data))) | |
346 | return -EINVAL; | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
7c6e68c7 | 351 | |
f464c5dd TZ |
352 | static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev, |
353 | struct ras_debug_if *data) | |
354 | { | |
355 | int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; | |
356 | uint32_t mask, inst_mask = data->inject.instance_mask; | |
357 | ||
358 | /* no need to set instance mask if there is only one instance */ | |
359 | if (num_xcc <= 1 && inst_mask) { | |
360 | data->inject.instance_mask = 0; | |
361 | dev_dbg(adev->dev, | |
362 | "RAS inject mask(0x%x) isn't supported and force it to 0.\n", | |
363 | inst_mask); | |
364 | ||
365 | return; | |
366 | } | |
367 | ||
368 | switch (data->head.block) { | |
369 | case AMDGPU_RAS_BLOCK__GFX: | |
370 | mask = GENMASK(num_xcc - 1, 0); | |
371 | break; | |
372 | case AMDGPU_RAS_BLOCK__SDMA: | |
373 | mask = GENMASK(adev->sdma.num_instances - 1, 0); | |
374 | break; | |
e3959cb5 SY |
375 | case AMDGPU_RAS_BLOCK__VCN: |
376 | case AMDGPU_RAS_BLOCK__JPEG: | |
377 | mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); | |
378 | break; | |
f464c5dd | 379 | default: |
e3959cb5 | 380 | mask = inst_mask; |
f464c5dd TZ |
381 | break; |
382 | } | |
383 | ||
384 | /* remove invalid bits in instance mask */ | |
385 | data->inject.instance_mask &= mask; | |
386 | if (inst_mask != data->inject.instance_mask) | |
387 | dev_dbg(adev->dev, | |
388 | "Adjust RAS inject mask 0x%x to 0x%x\n", | |
389 | inst_mask, data->inject.instance_mask); | |
390 | } | |
391 | ||
74abc221 TSD |
392 | /** |
393 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 394 | * |
737c375b | 395 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 396 | * |
397 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 398 | * |
399 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 400 | * |
401 | * head has four members, they are block, type, sub_block_index, name. | |
402 | * block: which IP will be under control. | |
403 | * type: what kind of error will be enabled/disabled/injected. | |
404 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
405 | * name: the name of IP. | |
406 | * | |
2c22ed0b | 407 | * inject has three more members than head, they are address, value and mask. |
36ea1bd2 | 408 | * As their names indicate, inject operation will write the |
409 | * value to the address. | |
410 | * | |
ef177d11 | 411 | * The second member: struct ras_debug_if::op. |
c688a06b | 412 | * It has three kinds of operations. |
879e723d AZ |
413 | * |
414 | * - 0: disable RAS on the block. Take ::head as its data. | |
415 | * - 1: enable RAS on the block. Take ::head as its data. | |
416 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 417 | * |
96ebb307 | 418 | * How to use the interface? |
ef177d11 | 419 | * |
737c375b | 420 | * In a program |
ef177d11 | 421 | * |
737c375b LT |
422 | * Copy the struct ras_debug_if in your code and initialize it. |
423 | * Write the struct to the control interface. | |
ef177d11 | 424 | * |
737c375b | 425 | * From shell |
96ebb307 | 426 | * |
879e723d AZ |
427 | * .. code-block:: bash |
428 | * | |
737c375b LT |
429 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
430 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
2c22ed0b | 431 | * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
879e723d | 432 | * |
737c375b | 433 | * Where N, is the card which you want to affect. |
ef177d11 | 434 | * |
737c375b LT |
435 | * "disable" requires only the block. |
436 | * "enable" requires the block and error type. | |
437 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 438 | * |
737c375b | 439 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 440 | * see ras_block_string[] for details |
c666bbf0 | 441 | * |
fb1e9171 | 442 | * The error type is one of: ue, ce and poison where, |
737c375b LT |
443 | * ue is multi-uncorrectable |
444 | * ce is single-correctable | |
fb1e9171 | 445 | * poison is poison |
c666bbf0 | 446 | * |
737c375b LT |
447 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
448 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
2c22ed0b | 449 | * The mask means instance mask, is optional, default value is 0x1. |
879e723d | 450 | * |
737c375b | 451 | * For instance, |
879e723d AZ |
452 | * |
453 | * .. code-block:: bash | |
96ebb307 | 454 | * |
44494f96 | 455 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
2c22ed0b | 456 | * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
96ebb307 | 457 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
458 | * | |
737c375b | 459 | * How to check the result of the operation? |
36ea1bd2 | 460 | * |
737c375b | 461 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 462 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
463 | * | |
737c375b LT |
464 | * To check inject, see the corresponding error count at, |
465 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 466 | * |
879e723d | 467 | * .. note:: |
ef177d11 | 468 | * Operations are only allowed on blocks which are supported. |
737c375b | 469 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
470 | * to see which blocks support RAS on a particular asic. |
471 | * | |
36ea1bd2 | 472 | */ |
cf696091 LT |
473 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
474 | const char __user *buf, | |
475 | size_t size, loff_t *pos) | |
36ea1bd2 | 476 | { |
477 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
478 | struct ras_debug_if data; | |
479 | int ret = 0; | |
480 | ||
61380faa | 481 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
482 | dev_warn(adev->dev, "RAS WARN: error injection " |
483 | "currently inaccessible\n"); | |
43c4d576 JC |
484 | return size; |
485 | } | |
486 | ||
96ebb307 | 487 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
488 | if (ret) | |
cf696091 | 489 | return ret; |
36ea1bd2 | 490 | |
80b0cd0f | 491 | if (data.op == 3) { |
cbb8f989 | 492 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 493 | if (!ret) |
cbb8f989 JC |
494 | return size; |
495 | else | |
496 | return ret; | |
497 | } | |
498 | ||
36ea1bd2 | 499 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
500 | return -EINVAL; | |
501 | ||
502 | switch (data.op) { | |
503 | case 0: | |
504 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
505 | break; | |
506 | case 1: | |
507 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
508 | break; | |
509 | case 2: | |
43aedbf4 SY |
510 | if ((data.inject.address >= adev->gmc.mc_vram_size && |
511 | adev->gmc.mc_vram_size) || | |
7cdc2ee3 | 512 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { |
b0d4783a GC |
513 | dev_warn(adev->dev, "RAS WARN: input address " |
514 | "0x%llx is invalid.", | |
515 | data.inject.address); | |
7cdc2ee3 TZ |
516 | ret = -EINVAL; |
517 | break; | |
518 | } | |
519 | ||
6e4be987 TZ |
520 | /* umc ce/ue error injection for a bad page is not allowed */ |
521 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
522 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
c65b0805 LT |
523 | dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " |
524 | "already been marked as bad!\n", | |
525 | data.inject.address); | |
6e4be987 TZ |
526 | break; |
527 | } | |
528 | ||
f464c5dd TZ |
529 | amdgpu_ras_instance_mask_check(adev, &data); |
530 | ||
7cdc2ee3 | 531 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 532 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
533 | break; | |
96ebb307 | 534 | default: |
535 | ret = -EINVAL; | |
536 | break; | |
374bf7bd | 537 | } |
36ea1bd2 | 538 | |
539 | if (ret) | |
79c04621 | 540 | return ret; |
36ea1bd2 | 541 | |
542 | return size; | |
543 | } | |
544 | ||
084fe13b AG |
545 | /** |
546 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
547 | * | |
f77c7109 | 548 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 549 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
550 | * a way to reset the EEPROM, e.g., after testing error injection. |
551 | * | |
552 | * Usage: | |
553 | * | |
554 | * .. code-block:: bash | |
555 | * | |
556 | * echo 1 > ../ras/ras_eeprom_reset | |
557 | * | |
558 | * will reset EEPROM table to 0 entries. | |
559 | * | |
084fe13b | 560 | */ |
cf696091 LT |
561 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
562 | const char __user *buf, | |
563 | size_t size, loff_t *pos) | |
084fe13b | 564 | { |
bf0b91b7 GC |
565 | struct amdgpu_device *adev = |
566 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
567 | int ret; |
568 | ||
bf0b91b7 | 569 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 570 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 571 | |
63d4c081 | 572 | if (!ret) { |
cf696091 LT |
573 | /* Something was written to EEPROM. |
574 | */ | |
bf0b91b7 GC |
575 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
576 | return size; | |
577 | } else { | |
cf696091 | 578 | return ret; |
bf0b91b7 | 579 | } |
084fe13b AG |
580 | } |
581 | ||
36ea1bd2 | 582 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
583 | .owner = THIS_MODULE, | |
584 | .read = NULL, | |
585 | .write = amdgpu_ras_debugfs_ctrl_write, | |
586 | .llseek = default_llseek | |
587 | }; | |
588 | ||
084fe13b AG |
589 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
590 | .owner = THIS_MODULE, | |
591 | .read = NULL, | |
592 | .write = amdgpu_ras_debugfs_eeprom_write, | |
593 | .llseek = default_llseek | |
594 | }; | |
595 | ||
f77c7109 AD |
596 | /** |
597 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
598 | * | |
ef177d11 | 599 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
600 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
601 | * | |
602 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
603 | * (ce) error counts. | |
604 | * | |
605 | * The format of one line is below, | |
606 | * | |
607 | * [ce|ue]: count | |
608 | * | |
609 | * Example: | |
610 | * | |
611 | * .. code-block:: bash | |
612 | * | |
613 | * ue: 0 | |
614 | * ce: 1 | |
615 | * | |
616 | */ | |
c030f2e4 | 617 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
618 | struct device_attribute *attr, char *buf) | |
619 | { | |
620 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
621 | struct ras_query_if info = { | |
622 | .head = obj->head, | |
623 | }; | |
624 | ||
61380faa | 625 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 626 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 627 | |
761d86d3 | 628 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 629 | return -EINVAL; |
630 | ||
4e8303cf LL |
631 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
632 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
1f0d8e37 | 633 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
2a460963 | 634 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); |
1f0d8e37 MJ |
635 | } |
636 | ||
2c7a1560 SY |
637 | if (info.head.block == AMDGPU_RAS_BLOCK__UMC) |
638 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
639 | "ce", info.ce_count, "de", info.de_count); | |
640 | else | |
641 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
642 | "ce", info.ce_count); | |
c030f2e4 | 643 | } |
644 | ||
645 | /* obj begin */ | |
646 | ||
647 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
648 | #define alive_obj(obj) ((obj)->use) | |
649 | ||
650 | static inline void put_obj(struct ras_manager *obj) | |
651 | { | |
ec3e0a91 | 652 | if (obj && (--obj->use == 0)) { |
c030f2e4 | 653 | list_del(&obj->node); |
ec3e0a91 YW |
654 | amdgpu_ras_error_data_fini(&obj->err_data); |
655 | } | |
656 | ||
f0872686 | 657 | if (obj && (obj->use < 0)) |
640ae42e | 658 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); |
c030f2e4 | 659 | } |
660 | ||
661 | /* make one obj and return it. */ | |
662 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
663 | struct ras_common_if *head) | |
664 | { | |
665 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
666 | struct ras_manager *obj; | |
667 | ||
8ab0d6f0 | 668 | if (!adev->ras_enabled || !con) |
c030f2e4 | 669 | return NULL; |
670 | ||
671 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
672 | return NULL; | |
673 | ||
640ae42e JC |
674 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
675 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
676 | return NULL; | |
677 | ||
678 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
679 | } else | |
680 | obj = &con->objs[head->block]; | |
681 | ||
c030f2e4 | 682 | /* already exist. return obj? */ |
683 | if (alive_obj(obj)) | |
684 | return NULL; | |
685 | ||
ec3e0a91 YW |
686 | if (amdgpu_ras_error_data_init(&obj->err_data)) |
687 | return NULL; | |
688 | ||
c030f2e4 | 689 | obj->head = *head; |
690 | obj->adev = adev; | |
691 | list_add(&obj->node, &con->head); | |
692 | get_obj(obj); | |
693 | ||
694 | return obj; | |
695 | } | |
696 | ||
697 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 698 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 699 | struct ras_common_if *head) |
700 | { | |
701 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
702 | struct ras_manager *obj; | |
703 | int i; | |
704 | ||
8ab0d6f0 | 705 | if (!adev->ras_enabled || !con) |
c030f2e4 | 706 | return NULL; |
707 | ||
708 | if (head) { | |
709 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
710 | return NULL; | |
711 | ||
640ae42e JC |
712 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
713 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
714 | return NULL; | |
715 | ||
716 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
717 | } else | |
718 | obj = &con->objs[head->block]; | |
c030f2e4 | 719 | |
640ae42e | 720 | if (alive_obj(obj)) |
c030f2e4 | 721 | return obj; |
c030f2e4 | 722 | } else { |
640ae42e | 723 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { |
c030f2e4 | 724 | obj = &con->objs[i]; |
640ae42e | 725 | if (alive_obj(obj)) |
c030f2e4 | 726 | return obj; |
c030f2e4 | 727 | } |
728 | } | |
729 | ||
730 | return NULL; | |
731 | } | |
732 | /* obj end */ | |
733 | ||
734 | /* feature ctl begin */ | |
735 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 736 | struct ras_common_if *head) |
c030f2e4 | 737 | { |
8ab0d6f0 | 738 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 739 | } |
740 | ||
741 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
742 | struct ras_common_if *head) | |
743 | { | |
744 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
745 | ||
746 | return con->features & BIT(head->block); | |
747 | } | |
748 | ||
749 | /* | |
750 | * if obj is not created, then create one. | |
751 | * set feature enable flag. | |
752 | */ | |
753 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
754 | struct ras_common_if *head, int enable) | |
755 | { | |
756 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
757 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
758 | ||
5caf466a | 759 | /* If hardware does not support ras, then do not create obj. |
760 | * But if hardware support ras, we can create the obj. | |
761 | * Ras framework checks con->hw_supported to see if it need do | |
762 | * corresponding initialization. | |
763 | * IP checks con->support to see if it need disable ras. | |
764 | */ | |
c030f2e4 | 765 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
766 | return 0; | |
c030f2e4 | 767 | |
768 | if (enable) { | |
769 | if (!obj) { | |
770 | obj = amdgpu_ras_create_obj(adev, head); | |
771 | if (!obj) | |
772 | return -EINVAL; | |
773 | } else { | |
774 | /* In case we create obj somewhere else */ | |
775 | get_obj(obj); | |
776 | } | |
777 | con->features |= BIT(head->block); | |
778 | } else { | |
779 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 780 | con->features &= ~BIT(head->block); |
c030f2e4 | 781 | put_obj(obj); |
782 | } | |
783 | } | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | /* wrapper of psp_ras_enable_features */ | |
789 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
790 | struct ras_common_if *head, bool enable) | |
791 | { | |
792 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 793 | union ta_ras_cmd_input *info; |
bf7aa8be | 794 | int ret; |
c030f2e4 | 795 | |
796 | if (!con) | |
797 | return -EINVAL; | |
798 | ||
ec70578c HZ |
799 | /* For non-gfx ip, do not enable ras feature if it is not allowed */ |
800 | /* For gfx ip, regardless of feature support status, */ | |
801 | /* Force issue enable or disable ras feature commands */ | |
802 | if (head->block != AMDGPU_RAS_BLOCK__GFX && | |
6fc9d92c | 803 | !amdgpu_ras_is_feature_allowed(adev, head)) |
bf7aa8be | 804 | return 0; |
6fc9d92c HZ |
805 | |
806 | /* Only enable gfx ras feature from host side */ | |
807 | if (head->block == AMDGPU_RAS_BLOCK__GFX && | |
808 | !amdgpu_sriov_vf(adev) && | |
809 | !amdgpu_ras_intr_triggered()) { | |
26093ce1 SY |
810 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
811 | if (!info) | |
812 | return -ENOMEM; | |
813 | ||
814 | if (!enable) { | |
815 | info->disable_features = (struct ta_ras_disable_features_input) { | |
816 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
817 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
818 | }; | |
819 | } else { | |
820 | info->enable_features = (struct ta_ras_enable_features_input) { | |
821 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
822 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
823 | }; | |
824 | } | |
c030f2e4 | 825 | |
7fcffecf | 826 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 827 | if (ret) { |
e4348849 | 828 | dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", |
011907fd | 829 | enable ? "enable":"disable", |
640ae42e | 830 | get_ras_block_str(head), |
e4348849 | 831 | amdgpu_ras_is_poison_mode_supported(adev), ret); |
5838f74c | 832 | kfree(info); |
bf7aa8be | 833 | return ret; |
bff77e86 | 834 | } |
bf7aa8be HZ |
835 | |
836 | kfree(info); | |
c030f2e4 | 837 | } |
838 | ||
839 | /* setup the obj */ | |
840 | __amdgpu_ras_feature_enable(adev, head, enable); | |
bf7aa8be HZ |
841 | |
842 | return 0; | |
c030f2e4 | 843 | } |
844 | ||
77de502b | 845 | /* Only used in device probe stage and called only once. */ |
846 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
847 | struct ras_common_if *head, bool enable) | |
848 | { | |
849 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
850 | int ret; | |
851 | ||
852 | if (!con) | |
853 | return -EINVAL; | |
854 | ||
855 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 856 | if (enable) { |
857 | /* There is no harm to issue a ras TA cmd regardless of | |
858 | * the currecnt ras state. | |
859 | * If current state == target state, it will do nothing | |
860 | * But sometimes it requests driver to reset and repost | |
861 | * with error code -EAGAIN. | |
862 | */ | |
863 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
864 | /* With old ras TA, we might fail to enable ras. | |
865 | * Log it and just setup the object. | |
866 | * TODO need remove this WA in the future. | |
867 | */ | |
868 | if (ret == -EINVAL) { | |
869 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
870 | if (!ret) | |
6952e99c GC |
871 | dev_info(adev->dev, |
872 | "RAS INFO: %s setup object\n", | |
640ae42e | 873 | get_ras_block_str(head)); |
7af23ebe | 874 | } |
875 | } else { | |
876 | /* setup the object then issue a ras TA disable cmd.*/ | |
877 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
878 | if (ret) | |
879 | return ret; | |
77de502b | 880 | |
970fd197 SY |
881 | /* gfx block ras dsiable cmd must send to ras-ta */ |
882 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
883 | con->features |= BIT(head->block); | |
884 | ||
77de502b | 885 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
886 | |
887 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 888 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 889 | con->features &= ~BIT(head->block); |
7af23ebe | 890 | } |
77de502b | 891 | } else |
892 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
893 | ||
894 | return ret; | |
895 | } | |
896 | ||
c030f2e4 | 897 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
898 | bool bypass) | |
899 | { | |
900 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
901 | struct ras_manager *obj, *tmp; | |
902 | ||
903 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
904 | /* bypass psp. | |
905 | * aka just release the obj and corresponding flags | |
906 | */ | |
907 | if (bypass) { | |
908 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
909 | break; | |
910 | } else { | |
911 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
912 | break; | |
913 | } | |
289d513b | 914 | } |
c030f2e4 | 915 | |
916 | return con->features; | |
917 | } | |
918 | ||
919 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
920 | bool bypass) | |
921 | { | |
922 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 923 | int i; |
640ae42e | 924 | const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; |
c030f2e4 | 925 | |
640ae42e | 926 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { |
c030f2e4 | 927 | struct ras_common_if head = { |
928 | .block = i, | |
191051a1 | 929 | .type = default_ras_type, |
c030f2e4 | 930 | .sub_block_index = 0, |
931 | }; | |
640ae42e JC |
932 | |
933 | if (i == AMDGPU_RAS_BLOCK__MCA) | |
934 | continue; | |
935 | ||
936 | if (bypass) { | |
937 | /* | |
938 | * bypass psp. vbios enable ras for us. | |
939 | * so just create the obj | |
940 | */ | |
941 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
942 | break; | |
943 | } else { | |
944 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
945 | break; | |
946 | } | |
947 | } | |
948 | ||
949 | for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { | |
950 | struct ras_common_if head = { | |
951 | .block = AMDGPU_RAS_BLOCK__MCA, | |
952 | .type = default_ras_type, | |
953 | .sub_block_index = i, | |
954 | }; | |
955 | ||
c030f2e4 | 956 | if (bypass) { |
957 | /* | |
958 | * bypass psp. vbios enable ras for us. | |
959 | * so just create the obj | |
960 | */ | |
961 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
962 | break; | |
963 | } else { | |
964 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
965 | break; | |
966 | } | |
289d513b | 967 | } |
c030f2e4 | 968 | |
969 | return con->features; | |
970 | } | |
971 | /* feature ctl end */ | |
972 | ||
e3d833f4 | 973 | static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, |
974 | enum amdgpu_ras_block block) | |
6492e1b0 | 975 | { |
b6efdb02 | 976 | if (!block_obj) |
6492e1b0 | 977 | return -EINVAL; |
978 | ||
bdb3489c | 979 | if (block_obj->ras_comm.block == block) |
6492e1b0 | 980 | return 0; |
640ae42e | 981 | |
6492e1b0 | 982 | return -EINVAL; |
983 | } | |
984 | ||
b6efdb02 | 985 | static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, |
6492e1b0 | 986 | enum amdgpu_ras_block block, uint32_t sub_block_index) |
640ae42e | 987 | { |
d5e8ff5f | 988 | struct amdgpu_ras_block_list *node, *tmp; |
989 | struct amdgpu_ras_block_object *obj; | |
6492e1b0 | 990 | |
991 | if (block >= AMDGPU_RAS_BLOCK__LAST) | |
992 | return NULL; | |
993 | ||
d5e8ff5f | 994 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
995 | if (!node->ras_obj) { | |
996 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
997 | continue; | |
998 | } | |
999 | ||
1000 | obj = node->ras_obj; | |
6492e1b0 | 1001 | if (obj->ras_block_match) { |
1002 | if (obj->ras_block_match(obj, block, sub_block_index) == 0) | |
1003 | return obj; | |
1004 | } else { | |
1005 | if (amdgpu_ras_block_match_default(obj, block) == 0) | |
1006 | return obj; | |
1007 | } | |
640ae42e | 1008 | } |
6492e1b0 | 1009 | |
1010 | return NULL; | |
640ae42e JC |
1011 | } |
1012 | ||
fdcb279d SY |
1013 | static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) |
1014 | { | |
1015 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1016 | int ret = 0; | |
1017 | ||
1018 | /* | |
1019 | * choosing right query method according to | |
1020 | * whether smu support query error information | |
1021 | */ | |
bc143d8b | 1022 | ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); |
fdcb279d | 1023 | if (ret == -EOPNOTSUPP) { |
efe17d5a | 1024 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
1025 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count) | |
1026 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); | |
fdcb279d SY |
1027 | |
1028 | /* umc query_ras_error_address is also responsible for clearing | |
1029 | * error status | |
1030 | */ | |
efe17d5a | 1031 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
1032 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address) | |
1033 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); | |
fdcb279d | 1034 | } else if (!ret) { |
efe17d5a | 1035 | if (adev->umc.ras && |
1036 | adev->umc.ras->ecc_info_query_ras_error_count) | |
1037 | adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); | |
fdcb279d | 1038 | |
efe17d5a | 1039 | if (adev->umc.ras && |
1040 | adev->umc.ras->ecc_info_query_ras_error_address) | |
1041 | adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); | |
fdcb279d SY |
1042 | } |
1043 | } | |
1044 | ||
5b1270be | 1045 | static void amdgpu_ras_error_print_error_data(struct amdgpu_device *adev, |
ec3e0a91 | 1046 | struct ras_manager *ras_mgr, |
5b1270be | 1047 | struct ras_err_data *err_data, |
ec3e0a91 | 1048 | const char *blk_name, |
46e2231c CL |
1049 | bool is_ue, |
1050 | bool is_de) | |
5b1270be | 1051 | { |
5b1270be YW |
1052 | struct amdgpu_smuio_mcm_config_info *mcm_info; |
1053 | struct ras_err_node *err_node; | |
1054 | struct ras_err_info *err_info; | |
1055 | ||
ec3e0a91 YW |
1056 | if (is_ue) { |
1057 | for_each_ras_error(err_node, err_data) { | |
1058 | err_info = &err_node->err_info; | |
1059 | mcm_info = &err_info->mcm_info; | |
1060 | if (err_info->ue_count) { | |
1061 | dev_info(adev->dev, "socket: %d, die: %d, " | |
1062 | "%lld new uncorrectable hardware errors detected in %s block\n", | |
1063 | mcm_info->socket_id, | |
1064 | mcm_info->die_id, | |
1065 | err_info->ue_count, | |
1066 | blk_name); | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | for_each_ras_error(err_node, &ras_mgr->err_data) { | |
1071 | err_info = &err_node->err_info; | |
1072 | mcm_info = &err_info->mcm_info; | |
1073 | dev_info(adev->dev, "socket: %d, die: %d, " | |
1074 | "%lld uncorrectable hardware errors detected in total in %s block\n", | |
1075 | mcm_info->socket_id, mcm_info->die_id, err_info->ue_count, blk_name); | |
1076 | } | |
1077 | ||
1078 | } else { | |
46e2231c CL |
1079 | if (is_de) { |
1080 | for_each_ras_error(err_node, err_data) { | |
1081 | err_info = &err_node->err_info; | |
1082 | mcm_info = &err_info->mcm_info; | |
1083 | if (err_info->de_count) { | |
1084 | dev_info(adev->dev, "socket: %d, die: %d, " | |
1085 | "%lld new deferred hardware errors detected in %s block\n", | |
1086 | mcm_info->socket_id, | |
1087 | mcm_info->die_id, | |
1088 | err_info->de_count, | |
1089 | blk_name); | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | for_each_ras_error(err_node, &ras_mgr->err_data) { | |
1094 | err_info = &err_node->err_info; | |
1095 | mcm_info = &err_info->mcm_info; | |
ec3e0a91 | 1096 | dev_info(adev->dev, "socket: %d, die: %d, " |
46e2231c CL |
1097 | "%lld deferred hardware errors detected in total in %s block\n", |
1098 | mcm_info->socket_id, mcm_info->die_id, | |
1099 | err_info->de_count, blk_name); | |
1100 | } | |
1101 | } else { | |
1102 | for_each_ras_error(err_node, err_data) { | |
1103 | err_info = &err_node->err_info; | |
1104 | mcm_info = &err_info->mcm_info; | |
1105 | if (err_info->ce_count) { | |
1106 | dev_info(adev->dev, "socket: %d, die: %d, " | |
1107 | "%lld new correctable hardware errors detected in %s block\n", | |
1108 | mcm_info->socket_id, | |
1109 | mcm_info->die_id, | |
1110 | err_info->ce_count, | |
1111 | blk_name); | |
1112 | } | |
ec3e0a91 | 1113 | } |
ec3e0a91 | 1114 | |
46e2231c CL |
1115 | for_each_ras_error(err_node, &ras_mgr->err_data) { |
1116 | err_info = &err_node->err_info; | |
1117 | mcm_info = &err_info->mcm_info; | |
1118 | dev_info(adev->dev, "socket: %d, die: %d, " | |
1119 | "%lld correctable hardware errors detected in total in %s block\n", | |
1120 | mcm_info->socket_id, mcm_info->die_id, | |
1121 | err_info->ce_count, blk_name); | |
1122 | } | |
5b1270be YW |
1123 | } |
1124 | } | |
1125 | } | |
1126 | ||
ec3e0a91 YW |
1127 | static inline bool err_data_has_source_info(struct ras_err_data *data) |
1128 | { | |
1129 | return !list_empty(&data->err_node_list); | |
1130 | } | |
1131 | ||
5b1270be YW |
1132 | static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, |
1133 | struct ras_query_if *query_if, | |
1134 | struct ras_err_data *err_data) | |
1135 | { | |
1136 | struct ras_manager *ras_mgr = amdgpu_ras_find_obj(adev, &query_if->head); | |
1137 | const char *blk_name = get_ras_block_str(&query_if->head); | |
1138 | ||
1139 | if (err_data->ce_count) { | |
ec3e0a91 | 1140 | if (err_data_has_source_info(err_data)) { |
46e2231c CL |
1141 | amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, |
1142 | blk_name, false, false); | |
5b1270be YW |
1143 | } else if (!adev->aid_mask && |
1144 | adev->smuio.funcs && | |
1145 | adev->smuio.funcs->get_socket_id && | |
1146 | adev->smuio.funcs->get_die_id) { | |
1147 | dev_info(adev->dev, "socket: %d, die: %d " | |
1148 | "%ld correctable hardware errors " | |
90bd0147 | 1149 | "detected in %s block\n", |
5b1270be YW |
1150 | adev->smuio.funcs->get_socket_id(adev), |
1151 | adev->smuio.funcs->get_die_id(adev), | |
1152 | ras_mgr->err_data.ce_count, | |
1153 | blk_name); | |
1154 | } else { | |
1155 | dev_info(adev->dev, "%ld correctable hardware errors " | |
90bd0147 | 1156 | "detected in %s block\n", |
5b1270be YW |
1157 | ras_mgr->err_data.ce_count, |
1158 | blk_name); | |
1159 | } | |
1160 | } | |
1161 | ||
1162 | if (err_data->ue_count) { | |
ec3e0a91 | 1163 | if (err_data_has_source_info(err_data)) { |
46e2231c CL |
1164 | amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, |
1165 | blk_name, true, false); | |
5b1270be YW |
1166 | } else if (!adev->aid_mask && |
1167 | adev->smuio.funcs && | |
1168 | adev->smuio.funcs->get_socket_id && | |
1169 | adev->smuio.funcs->get_die_id) { | |
1170 | dev_info(adev->dev, "socket: %d, die: %d " | |
1171 | "%ld uncorrectable hardware errors " | |
1172 | "detected in %s block\n", | |
1173 | adev->smuio.funcs->get_socket_id(adev), | |
1174 | adev->smuio.funcs->get_die_id(adev), | |
1175 | ras_mgr->err_data.ue_count, | |
1176 | blk_name); | |
1177 | } else { | |
1178 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
1179 | "detected in %s block\n", | |
1180 | ras_mgr->err_data.ue_count, | |
1181 | blk_name); | |
1182 | } | |
1183 | } | |
1184 | ||
46e2231c CL |
1185 | if (err_data->de_count) { |
1186 | if (err_data_has_source_info(err_data)) { | |
1187 | amdgpu_ras_error_print_error_data(adev, ras_mgr, err_data, | |
1188 | blk_name, false, true); | |
1189 | } else if (!adev->aid_mask && | |
1190 | adev->smuio.funcs && | |
1191 | adev->smuio.funcs->get_socket_id && | |
1192 | adev->smuio.funcs->get_die_id) { | |
1193 | dev_info(adev->dev, "socket: %d, die: %d " | |
1194 | "%ld deferred hardware errors " | |
1195 | "detected in %s block\n", | |
1196 | adev->smuio.funcs->get_socket_id(adev), | |
1197 | adev->smuio.funcs->get_die_id(adev), | |
1198 | ras_mgr->err_data.de_count, | |
1199 | blk_name); | |
1200 | } else { | |
1201 | dev_info(adev->dev, "%ld deferred hardware errors " | |
1202 | "detected in %s block\n", | |
1203 | ras_mgr->err_data.de_count, | |
1204 | blk_name); | |
1205 | } | |
1206 | } | |
5b1270be YW |
1207 | } |
1208 | ||
ec3e0a91 YW |
1209 | static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data) |
1210 | { | |
1211 | struct ras_err_node *err_node; | |
1212 | struct ras_err_info *err_info; | |
1213 | ||
1214 | if (err_data_has_source_info(err_data)) { | |
1215 | for_each_ras_error(err_node, err_data) { | |
1216 | err_info = &err_node->err_info; | |
46e2231c CL |
1217 | amdgpu_ras_error_statistic_de_count(&obj->err_data, |
1218 | &err_info->mcm_info, NULL, err_info->de_count); | |
9f91e983 YC |
1219 | amdgpu_ras_error_statistic_ce_count(&obj->err_data, |
1220 | &err_info->mcm_info, NULL, err_info->ce_count); | |
1221 | amdgpu_ras_error_statistic_ue_count(&obj->err_data, | |
1222 | &err_info->mcm_info, NULL, err_info->ue_count); | |
ec3e0a91 YW |
1223 | } |
1224 | } else { | |
1225 | /* for legacy asic path which doesn't has error source info */ | |
1226 | obj->err_data.ue_count += err_data->ue_count; | |
1227 | obj->err_data.ce_count += err_data->ce_count; | |
46e2231c | 1228 | obj->err_data.de_count += err_data->de_count; |
ec3e0a91 YW |
1229 | } |
1230 | } | |
1231 | ||
04c4fcd2 YW |
1232 | static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk) |
1233 | { | |
1234 | struct ras_common_if head; | |
1235 | ||
1236 | memset(&head, 0, sizeof(head)); | |
1237 | head.block = blk; | |
1238 | ||
1239 | return amdgpu_ras_find_obj(adev, &head); | |
1240 | } | |
1241 | ||
1242 | int amdgpu_ras_bind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk, | |
1243 | const struct aca_info *aca_info, void *data) | |
1244 | { | |
1245 | struct ras_manager *obj; | |
1246 | ||
1247 | obj = get_ras_manager(adev, blk); | |
1248 | if (!obj) | |
1249 | return -EINVAL; | |
1250 | ||
1251 | return amdgpu_aca_add_handle(adev, &obj->aca_handle, ras_block_str(blk), aca_info, data); | |
1252 | } | |
1253 | ||
1254 | int amdgpu_ras_unbind_aca(struct amdgpu_device *adev, enum amdgpu_ras_block blk) | |
1255 | { | |
1256 | struct ras_manager *obj; | |
1257 | ||
1258 | obj = get_ras_manager(adev, blk); | |
1259 | if (!obj) | |
1260 | return -EINVAL; | |
1261 | ||
1262 | amdgpu_aca_remove_handle(&obj->aca_handle); | |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
1267 | static int amdgpu_aca_log_ras_error_data(struct amdgpu_device *adev, enum amdgpu_ras_block blk, | |
1268 | enum aca_error_type type, struct ras_err_data *err_data) | |
1269 | { | |
1270 | struct ras_manager *obj; | |
1271 | ||
1272 | obj = get_ras_manager(adev, blk); | |
1273 | if (!obj) | |
1274 | return -EINVAL; | |
1275 | ||
1276 | return amdgpu_aca_get_error_data(adev, &obj->aca_handle, type, err_data); | |
1277 | } | |
1278 | ||
37973b69 YW |
1279 | ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *attr, |
1280 | struct aca_handle *handle, char *buf, void *data) | |
1281 | { | |
1282 | struct ras_manager *obj = container_of(handle, struct ras_manager, aca_handle); | |
1283 | struct ras_query_if info = { | |
1284 | .head = obj->head, | |
1285 | }; | |
1286 | ||
1287 | if (amdgpu_ras_query_error_status(obj->adev, &info)) | |
1288 | return -EINVAL; | |
1289 | ||
1290 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, | |
1291 | "ce", info.ce_count); | |
1292 | } | |
1293 | ||
8cc0f566 HZ |
1294 | static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, |
1295 | struct ras_query_if *info, | |
1296 | struct ras_err_data *err_data, | |
1297 | unsigned int error_query_mode) | |
c030f2e4 | 1298 | { |
8cc0f566 | 1299 | enum amdgpu_ras_block blk = info ? info->head.block : AMDGPU_RAS_BLOCK_COUNT; |
b6efdb02 | 1300 | struct amdgpu_ras_block_object *block_obj = NULL; |
04c4fcd2 | 1301 | int ret; |
8cc0f566 | 1302 | |
b8d55a90 SS |
1303 | if (blk == AMDGPU_RAS_BLOCK_COUNT) |
1304 | return -EINVAL; | |
1305 | ||
8cc0f566 HZ |
1306 | if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY) |
1307 | return -EINVAL; | |
1308 | ||
1309 | if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { | |
1310 | if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { | |
1311 | amdgpu_ras_get_ecc_info(adev, err_data); | |
1312 | } else { | |
1313 | block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); | |
1314 | if (!block_obj || !block_obj->hw_ops) { | |
1315 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", | |
1316 | get_ras_block_str(&info->head)); | |
1317 | return -EINVAL; | |
1318 | } | |
1319 | ||
1320 | if (block_obj->hw_ops->query_ras_error_count) | |
07ee43fa | 1321 | block_obj->hw_ops->query_ras_error_count(adev, err_data); |
8cc0f566 HZ |
1322 | |
1323 | if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || | |
1324 | (info->head.block == AMDGPU_RAS_BLOCK__GFX) || | |
1325 | (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
1326 | if (block_obj->hw_ops->query_ras_error_status) | |
1327 | block_obj->hw_ops->query_ras_error_status(adev); | |
1328 | } | |
1329 | } | |
1330 | } else { | |
04c4fcd2 YW |
1331 | if (amdgpu_aca_is_enabled(adev)) { |
1332 | ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_UE, err_data); | |
1333 | if (ret) | |
1334 | return ret; | |
1335 | ||
1336 | ret = amdgpu_aca_log_ras_error_data(adev, blk, ACA_ERROR_TYPE_CE, err_data); | |
1337 | if (ret) | |
1338 | return ret; | |
1339 | } else { | |
1340 | /* FIXME: add code to check return value later */ | |
1341 | amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_UE, err_data); | |
1342 | amdgpu_mca_smu_log_ras_error(adev, blk, AMDGPU_MCA_ERROR_TYPE_CE, err_data); | |
1343 | } | |
8cc0f566 HZ |
1344 | } |
1345 | ||
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | /* query/inject/cure begin */ | |
1350 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, struct ras_query_if *info) | |
1351 | { | |
c030f2e4 | 1352 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); |
5b1270be | 1353 | struct ras_err_data err_data; |
8cc0f566 | 1354 | unsigned int error_query_mode; |
5b1270be | 1355 | int ret; |
c030f2e4 | 1356 | |
1357 | if (!obj) | |
1358 | return -EINVAL; | |
c030f2e4 | 1359 | |
5b1270be YW |
1360 | ret = amdgpu_ras_error_data_init(&err_data); |
1361 | if (ret) | |
1362 | return ret; | |
1363 | ||
8cc0f566 HZ |
1364 | if (!amdgpu_ras_get_error_query_mode(adev, &error_query_mode)) |
1365 | return -EINVAL; | |
7389a5b8 | 1366 | |
8cc0f566 HZ |
1367 | ret = amdgpu_ras_query_error_status_helper(adev, info, |
1368 | &err_data, | |
1369 | error_query_mode); | |
1370 | if (ret) | |
1371 | goto out_fini_err_data; | |
05a58345 | 1372 | |
ec3e0a91 | 1373 | amdgpu_rasmgr_error_data_statistic_update(obj, &err_data); |
05a58345 | 1374 | |
c030f2e4 | 1375 | info->ue_count = obj->err_data.ue_count; |
1376 | info->ce_count = obj->err_data.ce_count; | |
46e2231c | 1377 | info->de_count = obj->err_data.de_count; |
c030f2e4 | 1378 | |
5b1270be | 1379 | amdgpu_ras_error_generate_report(adev, info, &err_data); |
05a58345 | 1380 | |
5b1270be YW |
1381 | out_fini_err_data: |
1382 | amdgpu_ras_error_data_fini(&err_data); | |
1383 | ||
1384 | return ret; | |
c030f2e4 | 1385 | } |
1386 | ||
472c5fb2 | 1387 | int amdgpu_ras_reset_error_count(struct amdgpu_device *adev, |
761d86d3 DL |
1388 | enum amdgpu_ras_block block) |
1389 | { | |
b6efdb02 | 1390 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); |
73582be1 TZ |
1391 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
1392 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; | |
04c4fcd2 | 1393 | const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; |
18eae367 TZ |
1394 | struct amdgpu_hive_info *hive; |
1395 | int hive_ras_recovery = 0; | |
8b0fb0e9 | 1396 | |
a83f2bf1 | 1397 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 | 1398 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
472c5fb2 TZ |
1399 | ras_block_str(block)); |
1400 | return -EOPNOTSUPP; | |
761d86d3 DL |
1401 | } |
1402 | ||
d1d4c0b7 | 1403 | if (!amdgpu_ras_is_supported(adev, block) || |
04c4fcd2 | 1404 | !amdgpu_ras_get_aca_debug_mode(adev)) |
d1d4c0b7 TZ |
1405 | return -EOPNOTSUPP; |
1406 | ||
18eae367 TZ |
1407 | hive = amdgpu_get_xgmi_hive(adev); |
1408 | if (hive) { | |
1409 | hive_ras_recovery = atomic_read(&hive->ras_recovery); | |
1410 | amdgpu_put_xgmi_hive(hive); | |
1411 | } | |
1412 | ||
73582be1 | 1413 | /* skip ras error reset in gpu reset */ |
18eae367 TZ |
1414 | if ((amdgpu_in_reset(adev) || atomic_read(&ras->in_recovery) || |
1415 | hive_ras_recovery) && | |
04c4fcd2 YW |
1416 | ((smu_funcs && smu_funcs->set_debug_mode) || |
1417 | (mca_funcs && mca_funcs->mca_set_debug_mode))) | |
73582be1 TZ |
1418 | return -EOPNOTSUPP; |
1419 | ||
7389a5b8 | 1420 | if (block_obj->hw_ops->reset_ras_error_count) |
1421 | block_obj->hw_ops->reset_ras_error_count(adev); | |
5c23e9e0 | 1422 | |
472c5fb2 TZ |
1423 | return 0; |
1424 | } | |
1425 | ||
1426 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, | |
1427 | enum amdgpu_ras_block block) | |
1428 | { | |
1429 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); | |
1430 | ||
1431 | if (amdgpu_ras_reset_error_count(adev, block) == -EOPNOTSUPP) | |
1432 | return 0; | |
1433 | ||
7389a5b8 | 1434 | if ((block == AMDGPU_RAS_BLOCK__GFX) || |
1435 | (block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
8b0fb0e9 | 1436 | if (block_obj->hw_ops->reset_ras_error_status) |
1437 | block_obj->hw_ops->reset_ras_error_status(adev); | |
761d86d3 | 1438 | } |
5c23e9e0 | 1439 | |
761d86d3 | 1440 | return 0; |
5c23e9e0 JC |
1441 | } |
1442 | ||
c030f2e4 | 1443 | /* wrapper of psp_ras_trigger_error */ |
1444 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
1445 | struct ras_inject_if *info) | |
1446 | { | |
1447 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1448 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1449 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1450 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1451 | .sub_block_index = info->head.sub_block_index, |
1452 | .address = info->address, | |
1453 | .value = info->value, | |
1454 | }; | |
ab3b9de6 YL |
1455 | int ret = -EINVAL; |
1456 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, | |
1457 | info->head.block, | |
1458 | info->head.sub_block_index); | |
c030f2e4 | 1459 | |
248c9635 TZ |
1460 | /* inject on guest isn't allowed, return success directly */ |
1461 | if (amdgpu_sriov_vf(adev)) | |
1462 | return 0; | |
1463 | ||
c030f2e4 | 1464 | if (!obj) |
1465 | return -EINVAL; | |
1466 | ||
22d4ba53 | 1467 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1468 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1469 | get_ras_block_str(&info->head)); | |
22d4ba53 | 1470 | return -EINVAL; |
1471 | } | |
1472 | ||
a6c44d25 | 1473 | /* Calculate XGMI relative offset */ |
a80fe1a6 TZ |
1474 | if (adev->gmc.xgmi.num_physical_nodes > 1 && |
1475 | info->head.block != AMDGPU_RAS_BLOCK__GFX) { | |
19744f5f HZ |
1476 | block_info.address = |
1477 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1478 | block_info.address); | |
a6c44d25 JC |
1479 | } |
1480 | ||
27c5f295 TZ |
1481 | if (block_obj->hw_ops->ras_error_inject) { |
1482 | if (info->head.block == AMDGPU_RAS_BLOCK__GFX) | |
2c22ed0b | 1483 | ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask); |
27c5f295 | 1484 | else /* Special ras_error_inject is defined (e.g: xgmi) */ |
2c22ed0b TZ |
1485 | ret = block_obj->hw_ops->ras_error_inject(adev, &block_info, |
1486 | info->instance_mask); | |
27c5f295 TZ |
1487 | } else { |
1488 | /* default path */ | |
1489 | ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask); | |
a5dd40ca HZ |
1490 | } |
1491 | ||
011907fd DL |
1492 | if (ret) |
1493 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
640ae42e | 1494 | get_ras_block_str(&info->head), ret); |
c030f2e4 | 1495 | |
1496 | return ret; | |
1497 | } | |
1498 | ||
4d9f771e | 1499 | /** |
4a1c9a44 HZ |
1500 | * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP |
1501 | * @adev: pointer to AMD GPU device | |
1502 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1503 | * @ue_count: pointer to an integer to be set to the count of uncorrectible errors. | |
1504 | * @query_info: pointer to ras_query_if | |
1505 | * | |
1506 | * Return 0 for query success or do nothing, otherwise return an error | |
1507 | * on failures | |
1508 | */ | |
1509 | static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev, | |
1510 | unsigned long *ce_count, | |
1511 | unsigned long *ue_count, | |
1512 | struct ras_query_if *query_info) | |
1513 | { | |
1514 | int ret; | |
1515 | ||
1516 | if (!query_info) | |
1517 | /* do nothing if query_info is not specified */ | |
1518 | return 0; | |
1519 | ||
1520 | ret = amdgpu_ras_query_error_status(adev, query_info); | |
1521 | if (ret) | |
1522 | return ret; | |
1523 | ||
1524 | *ce_count += query_info->ce_count; | |
1525 | *ue_count += query_info->ue_count; | |
1526 | ||
1527 | /* some hardware/IP supports read to clear | |
1528 | * no need to explictly reset the err status after the query call */ | |
4e8303cf LL |
1529 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
1530 | amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
4a1c9a44 HZ |
1531 | if (amdgpu_ras_reset_error_status(adev, query_info->head.block)) |
1532 | dev_warn(adev->dev, | |
1533 | "Failed to reset error counter and error status\n"); | |
1534 | } | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | /** | |
1540 | * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP | |
bbe04dec IB |
1541 | * @adev: pointer to AMD GPU device |
1542 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1543 | * @ue_count: pointer to an integer to be set to the count of uncorrectible | |
4d9f771e | 1544 | * errors. |
4a1c9a44 HZ |
1545 | * @query_info: pointer to ras_query_if if the query request is only for |
1546 | * specific ip block; if info is NULL, then the qurey request is for | |
1547 | * all the ip blocks that support query ras error counters/status | |
4d9f771e LT |
1548 | * |
1549 | * If set, @ce_count or @ue_count, count and return the corresponding | |
1550 | * error counts in those integer pointers. Return 0 if the device | |
1551 | * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
1552 | */ | |
1553 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
1554 | unsigned long *ce_count, | |
4a1c9a44 HZ |
1555 | unsigned long *ue_count, |
1556 | struct ras_query_if *query_info) | |
c030f2e4 | 1557 | { |
1558 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1559 | struct ras_manager *obj; | |
a46751fb | 1560 | unsigned long ce, ue; |
4a1c9a44 | 1561 | int ret; |
c030f2e4 | 1562 | |
8ab0d6f0 | 1563 | if (!adev->ras_enabled || !con) |
4d9f771e LT |
1564 | return -EOPNOTSUPP; |
1565 | ||
1566 | /* Don't count since no reporting. | |
1567 | */ | |
1568 | if (!ce_count && !ue_count) | |
1569 | return 0; | |
c030f2e4 | 1570 | |
a46751fb LT |
1571 | ce = 0; |
1572 | ue = 0; | |
4a1c9a44 HZ |
1573 | if (!query_info) { |
1574 | /* query all the ip blocks that support ras query interface */ | |
1575 | list_for_each_entry(obj, &con->head, node) { | |
1576 | struct ras_query_if info = { | |
1577 | .head = obj->head, | |
1578 | }; | |
c030f2e4 | 1579 | |
4a1c9a44 | 1580 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info); |
2a460963 | 1581 | } |
4a1c9a44 HZ |
1582 | } else { |
1583 | /* query specific ip block */ | |
1584 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info); | |
c030f2e4 | 1585 | } |
1586 | ||
4a1c9a44 HZ |
1587 | if (ret) |
1588 | return ret; | |
1589 | ||
a46751fb LT |
1590 | if (ce_count) |
1591 | *ce_count = ce; | |
1592 | ||
1593 | if (ue_count) | |
1594 | *ue_count = ue; | |
4d9f771e LT |
1595 | |
1596 | return 0; | |
c030f2e4 | 1597 | } |
1598 | /* query/inject/cure end */ | |
1599 | ||
1600 | ||
1601 | /* sysfs begin */ | |
1602 | ||
466b1793 | 1603 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1604 | struct ras_badpage **bps, unsigned int *count); | |
1605 | ||
1606 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1607 | { | |
1608 | switch (flags) { | |
52dd95f2 | 1609 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1610 | return "R"; |
52dd95f2 | 1611 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1612 | return "P"; |
52dd95f2 | 1613 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1614 | default: |
1615 | return "F"; | |
aec576f9 | 1616 | } |
466b1793 | 1617 | } |
1618 | ||
f77c7109 AD |
1619 | /** |
1620 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1621 | * |
1622 | * It allows user to read the bad pages of vram on the gpu through | |
1623 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1624 | * | |
1625 | * It outputs multiple lines, and each line stands for one gpu page. | |
1626 | * | |
1627 | * The format of one line is below, | |
1628 | * gpu pfn : gpu page size : flags | |
1629 | * | |
1630 | * gpu pfn and gpu page size are printed in hex format. | |
1631 | * flags can be one of below character, | |
f77c7109 | 1632 | * |
466b1793 | 1633 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1634 | * |
466b1793 | 1635 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1636 | * in next window of page_reserve. |
1637 | * | |
466b1793 | 1638 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1639 | * | |
f77c7109 AD |
1640 | * Examples: |
1641 | * | |
1642 | * .. code-block:: bash | |
1643 | * | |
1644 | * 0x00000001 : 0x00001000 : R | |
1645 | * 0x00000002 : 0x00001000 : P | |
1646 | * | |
466b1793 | 1647 | */ |
1648 | ||
1649 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1650 | struct kobject *kobj, struct bin_attribute *attr, | |
1651 | char *buf, loff_t ppos, size_t count) | |
1652 | { | |
1653 | struct amdgpu_ras *con = | |
1654 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1655 | struct amdgpu_device *adev = con->adev; | |
1656 | const unsigned int element_size = | |
1657 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1658 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1659 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1660 | ssize_t s = 0; |
1661 | struct ras_badpage *bps = NULL; | |
1662 | unsigned int bps_count = 0; | |
1663 | ||
1664 | memset(buf, 0, count); | |
1665 | ||
1666 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1667 | return 0; | |
1668 | ||
1669 | for (; start < end && start < bps_count; start++) | |
1670 | s += scnprintf(&buf[s], element_size + 1, | |
1671 | "0x%08x : 0x%08x : %1s\n", | |
1672 | bps[start].bp, | |
1673 | bps[start].size, | |
1674 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1675 | ||
1676 | kfree(bps); | |
1677 | ||
1678 | return s; | |
1679 | } | |
1680 | ||
c030f2e4 | 1681 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1682 | struct device_attribute *attr, char *buf) | |
1683 | { | |
1684 | struct amdgpu_ras *con = | |
1685 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1686 | |
2cffcb66 | 1687 | return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1688 | } |
1689 | ||
625e5f38 AK |
1690 | static ssize_t amdgpu_ras_sysfs_version_show(struct device *dev, |
1691 | struct device_attribute *attr, char *buf) | |
1692 | { | |
1693 | struct amdgpu_ras *con = | |
1694 | container_of(attr, struct amdgpu_ras, version_attr); | |
1695 | return sysfs_emit(buf, "table version: 0x%x\n", con->eeprom_control.tbl_hdr.version); | |
1696 | } | |
1697 | ||
1698 | static ssize_t amdgpu_ras_sysfs_schema_show(struct device *dev, | |
1699 | struct device_attribute *attr, char *buf) | |
1700 | { | |
1701 | struct amdgpu_ras *con = | |
1702 | container_of(attr, struct amdgpu_ras, schema_attr); | |
1703 | return sysfs_emit(buf, "schema: 0x%x\n", con->schema); | |
1704 | } | |
1705 | ||
f848159b GC |
1706 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1707 | { | |
1708 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1709 | ||
4638e0c2 VP |
1710 | if (adev->dev->kobj.sd) |
1711 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
f848159b GC |
1712 | &con->badpages_attr.attr, |
1713 | RAS_FS_NAME); | |
1714 | } | |
1715 | ||
625e5f38 | 1716 | static int amdgpu_ras_sysfs_remove_dev_attr_node(struct amdgpu_device *adev) |
c030f2e4 | 1717 | { |
1718 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1719 | struct attribute *attrs[] = { | |
1720 | &con->features_attr.attr, | |
625e5f38 AK |
1721 | &con->version_attr.attr, |
1722 | &con->schema_attr.attr, | |
c030f2e4 | 1723 | NULL |
1724 | }; | |
1725 | struct attribute_group group = { | |
eb0c3cd4 | 1726 | .name = RAS_FS_NAME, |
c030f2e4 | 1727 | .attrs = attrs, |
1728 | }; | |
1729 | ||
4638e0c2 VP |
1730 | if (adev->dev->kobj.sd) |
1731 | sysfs_remove_group(&adev->dev->kobj, &group); | |
c030f2e4 | 1732 | |
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
9252d33d | 1737 | struct ras_common_if *head) |
c030f2e4 | 1738 | { |
9252d33d | 1739 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1740 | |
1741 | if (!obj || obj->attr_inuse) | |
1742 | return -EINVAL; | |
1743 | ||
1744 | get_obj(obj); | |
1745 | ||
9252d33d | 1746 | snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), |
1747 | "%s_err_count", head->name); | |
c030f2e4 | 1748 | |
1749 | obj->sysfs_attr = (struct device_attribute){ | |
1750 | .attr = { | |
1751 | .name = obj->fs_data.sysfs_name, | |
1752 | .mode = S_IRUGO, | |
1753 | }, | |
1754 | .show = amdgpu_ras_sysfs_read, | |
1755 | }; | |
163def43 | 1756 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1757 | |
1758 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1759 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1760 | RAS_FS_NAME)) { |
c030f2e4 | 1761 | put_obj(obj); |
1762 | return -EINVAL; | |
1763 | } | |
1764 | ||
1765 | obj->attr_inuse = 1; | |
1766 | ||
1767 | return 0; | |
1768 | } | |
1769 | ||
1770 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1771 | struct ras_common_if *head) | |
1772 | { | |
1773 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1774 | ||
1775 | if (!obj || !obj->attr_inuse) | |
1776 | return -EINVAL; | |
1777 | ||
4638e0c2 VP |
1778 | if (adev->dev->kobj.sd) |
1779 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
c030f2e4 | 1780 | &obj->sysfs_attr.attr, |
eb0c3cd4 | 1781 | RAS_FS_NAME); |
c030f2e4 | 1782 | obj->attr_inuse = 0; |
1783 | put_obj(obj); | |
1784 | ||
1785 | return 0; | |
1786 | } | |
1787 | ||
1788 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1789 | { | |
1790 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1791 | struct ras_manager *obj, *tmp; | |
1792 | ||
1793 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1794 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1795 | } | |
1796 | ||
f848159b GC |
1797 | if (amdgpu_bad_page_threshold != 0) |
1798 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1799 | ||
625e5f38 | 1800 | amdgpu_ras_sysfs_remove_dev_attr_node(adev); |
c030f2e4 | 1801 | |
1802 | return 0; | |
1803 | } | |
1804 | /* sysfs end */ | |
1805 | ||
ef177d11 AD |
1806 | /** |
1807 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1808 | * | |
1809 | * Normally when there is an uncorrectable error, the driver will reset | |
1810 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1811 | * the driver provides an interface to reboot the system automatically | |
1812 | * in that event. | |
1813 | * | |
1814 | * The following file in debugfs provides that interface: | |
1815 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1816 | * | |
1817 | * Usage: | |
1818 | * | |
1819 | * .. code-block:: bash | |
1820 | * | |
1821 | * echo true > .../ras/auto_reboot | |
1822 | * | |
1823 | */ | |
c030f2e4 | 1824 | /* debugfs begin */ |
ea1b8c9b | 1825 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1826 | { |
1827 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
740f42a2 | 1828 | struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control; |
ef0d7d20 LT |
1829 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1830 | struct dentry *dir; | |
36ea1bd2 | 1831 | |
88293c03 ND |
1832 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1833 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1834 | &amdgpu_ras_debugfs_ctrl_ops); | |
1835 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1836 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1837 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1838 | &con->bad_page_cnt_threshold); | |
740f42a2 | 1839 | debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs); |
ef0d7d20 LT |
1840 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1841 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c65b0805 LT |
1842 | debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, |
1843 | &amdgpu_ras_debugfs_eeprom_size_ops); | |
1844 | con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", | |
1845 | S_IRUGO, dir, adev, | |
1846 | &amdgpu_ras_debugfs_eeprom_table_ops); | |
1847 | amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); | |
c688a06b GC |
1848 | |
1849 | /* | |
1850 | * After one uncorrectable error happens, usually GPU recovery will | |
1851 | * be scheduled. But due to the known problem in GPU recovery failing | |
1852 | * to bring GPU back, below interface provides one direct way to | |
1853 | * user to reboot system automatically in such case within | |
1854 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1855 | * will never be called. | |
1856 | */ | |
88293c03 | 1857 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1858 | |
1859 | /* | |
1860 | * User could set this not to clean up hardware's error count register | |
1861 | * of RAS IPs during ras recovery. | |
1862 | */ | |
88293c03 ND |
1863 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1864 | &con->disable_ras_err_cnt_harvest); | |
1865 | return dir; | |
36ea1bd2 | 1866 | } |
1867 | ||
cedf7884 | 1868 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1869 | struct ras_fs_if *head, |
1870 | struct dentry *dir) | |
c030f2e4 | 1871 | { |
c030f2e4 | 1872 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1873 | |
88293c03 | 1874 | if (!obj || !dir) |
450f30ea | 1875 | return; |
c030f2e4 | 1876 | |
1877 | get_obj(obj); | |
1878 | ||
1879 | memcpy(obj->fs_data.debugfs_name, | |
1880 | head->debugfs_name, | |
1881 | sizeof(obj->fs_data.debugfs_name)); | |
1882 | ||
88293c03 ND |
1883 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1884 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1885 | } |
1886 | ||
f9317014 TZ |
1887 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1888 | { | |
1889 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1890 | struct dentry *dir; |
c1509f3f | 1891 | struct ras_manager *obj; |
f9317014 TZ |
1892 | struct ras_fs_if fs_info; |
1893 | ||
1894 | /* | |
1895 | * it won't be called in resume path, no need to check | |
1896 | * suspend and gpu reset status | |
1897 | */ | |
cedf7884 | 1898 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1899 | return; |
1900 | ||
88293c03 | 1901 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1902 | |
c1509f3f | 1903 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1904 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1905 | (obj->attr_inuse == 1)) { | |
1906 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
640ae42e | 1907 | get_ras_block_str(&obj->head)); |
f9317014 | 1908 | fs_info.head = obj->head; |
88293c03 | 1909 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1910 | } |
1911 | } | |
4051844c | 1912 | |
04c4fcd2 YW |
1913 | if (amdgpu_aca_is_enabled(adev)) |
1914 | amdgpu_aca_smu_debugfs_init(adev, dir); | |
1915 | else | |
1916 | amdgpu_mca_smu_debugfs_init(adev, dir); | |
f9317014 TZ |
1917 | } |
1918 | ||
c030f2e4 | 1919 | /* debugfs end */ |
1920 | ||
1921 | /* ras fs */ | |
c3d4d45d GC |
1922 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1923 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1924 | static DEVICE_ATTR(features, S_IRUGO, | |
1925 | amdgpu_ras_sysfs_features_read, NULL); | |
625e5f38 AK |
1926 | static DEVICE_ATTR(version, 0444, |
1927 | amdgpu_ras_sysfs_version_show, NULL); | |
1928 | static DEVICE_ATTR(schema, 0444, | |
1929 | amdgpu_ras_sysfs_schema_show, NULL); | |
c030f2e4 | 1930 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1931 | { | |
c3d4d45d GC |
1932 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1933 | struct attribute_group group = { | |
1934 | .name = RAS_FS_NAME, | |
1935 | }; | |
1936 | struct attribute *attrs[] = { | |
1937 | &con->features_attr.attr, | |
625e5f38 AK |
1938 | &con->version_attr.attr, |
1939 | &con->schema_attr.attr, | |
c3d4d45d GC |
1940 | NULL |
1941 | }; | |
1942 | struct bin_attribute *bin_attrs[] = { | |
1943 | NULL, | |
1944 | NULL, | |
1945 | }; | |
a069a9eb | 1946 | int r; |
c030f2e4 | 1947 | |
625e5f38 AK |
1948 | group.attrs = attrs; |
1949 | ||
c3d4d45d GC |
1950 | /* add features entry */ |
1951 | con->features_attr = dev_attr_features; | |
c3d4d45d GC |
1952 | sysfs_attr_init(attrs[0]); |
1953 | ||
625e5f38 AK |
1954 | /* add version entry */ |
1955 | con->version_attr = dev_attr_version; | |
1956 | sysfs_attr_init(attrs[1]); | |
1957 | ||
1958 | /* add schema entry */ | |
1959 | con->schema_attr = dev_attr_schema; | |
1960 | sysfs_attr_init(attrs[2]); | |
1961 | ||
c3d4d45d GC |
1962 | if (amdgpu_bad_page_threshold != 0) { |
1963 | /* add bad_page_features entry */ | |
1964 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1965 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1966 | bin_attrs[0] = &con->badpages_attr; | |
1967 | group.bin_attrs = bin_attrs; | |
1968 | sysfs_bin_attr_init(bin_attrs[0]); | |
1969 | } | |
1970 | ||
a069a9eb AD |
1971 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1972 | if (r) | |
1973 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1974 | |
c030f2e4 | 1975 | return 0; |
1976 | } | |
1977 | ||
1978 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1979 | { | |
88293c03 ND |
1980 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1981 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1982 | ||
1983 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1984 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1985 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1986 | if (ip_obj) | |
1987 | put_obj(ip_obj); | |
1988 | } | |
1989 | } | |
1990 | ||
c030f2e4 | 1991 | amdgpu_ras_sysfs_remove_all(adev); |
1992 | return 0; | |
1993 | } | |
1994 | /* ras fs end */ | |
1995 | ||
1996 | /* ih begin */ | |
b3c76814 TZ |
1997 | |
1998 | /* For the hardware that cannot enable bif ring for both ras_controller_irq | |
1999 | * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status | |
2000 | * register to check whether the interrupt is triggered or not, and properly | |
2001 | * ack the interrupt if it is there | |
2002 | */ | |
2003 | void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) | |
2004 | { | |
950d6425 | 2005 | /* Fatal error events are handled on host side */ |
8eba7205 | 2006 | if (amdgpu_sriov_vf(adev)) |
b3c76814 TZ |
2007 | return; |
2008 | ||
2009 | if (adev->nbio.ras && | |
2010 | adev->nbio.ras->handle_ras_controller_intr_no_bifring) | |
2011 | adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); | |
2012 | ||
2013 | if (adev->nbio.ras && | |
2014 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) | |
2015 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); | |
2016 | } | |
2017 | ||
66f87949 TZ |
2018 | static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj, |
2019 | struct amdgpu_iv_entry *entry) | |
2020 | { | |
b63ac5d3 | 2021 | bool poison_stat = false; |
66f87949 | 2022 | struct amdgpu_device *adev = obj->adev; |
66f87949 TZ |
2023 | struct amdgpu_ras_block_object *block_obj = |
2024 | amdgpu_ras_get_ras_block(adev, obj->head.block, 0); | |
2025 | ||
ac7b25d9 | 2026 | if (!block_obj) |
b63ac5d3 | 2027 | return; |
66f87949 | 2028 | |
b63ac5d3 TZ |
2029 | /* both query_poison_status and handle_poison_consumption are optional, |
2030 | * but at least one of them should be implemented if we need poison | |
2031 | * consumption handler | |
2032 | */ | |
ac7b25d9 | 2033 | if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { |
b63ac5d3 TZ |
2034 | poison_stat = block_obj->hw_ops->query_poison_status(adev); |
2035 | if (!poison_stat) { | |
2036 | /* Not poison consumption interrupt, no need to handle it */ | |
2037 | dev_info(adev->dev, "No RAS poison status in %s poison IH.\n", | |
2038 | block_obj->ras_comm.name); | |
2039 | ||
2040 | return; | |
66f87949 TZ |
2041 | } |
2042 | } | |
2043 | ||
38298ce6 | 2044 | amdgpu_umc_poison_handler(adev, false); |
b63ac5d3 | 2045 | |
ac7b25d9 | 2046 | if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) |
b63ac5d3 TZ |
2047 | poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); |
2048 | ||
2049 | /* gpu reset is fallback for failed and default cases */ | |
2050 | if (poison_stat) { | |
2051 | dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n", | |
2052 | block_obj->ras_comm.name); | |
66f87949 | 2053 | amdgpu_ras_reset_gpu(adev); |
ac7b25d9 YC |
2054 | } else { |
2055 | amdgpu_gfx_poison_consumption_handler(adev, entry); | |
b63ac5d3 | 2056 | } |
66f87949 TZ |
2057 | } |
2058 | ||
50a7d025 TZ |
2059 | static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj, |
2060 | struct amdgpu_iv_entry *entry) | |
2061 | { | |
2062 | dev_info(obj->adev->dev, | |
90bd0147 | 2063 | "Poison is created\n"); |
50a7d025 TZ |
2064 | } |
2065 | ||
2066 | static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, | |
2067 | struct amdgpu_iv_entry *entry) | |
2068 | { | |
2069 | struct ras_ih_data *data = &obj->ih_data; | |
5b1270be | 2070 | struct ras_err_data err_data; |
50a7d025 TZ |
2071 | int ret; |
2072 | ||
2073 | if (!data->cb) | |
2074 | return; | |
2075 | ||
5b1270be YW |
2076 | ret = amdgpu_ras_error_data_init(&err_data); |
2077 | if (ret) | |
2078 | return; | |
2079 | ||
50a7d025 TZ |
2080 | /* Let IP handle its data, maybe we need get the output |
2081 | * from the callback to update the error type/count, etc | |
2082 | */ | |
2083 | ret = data->cb(obj->adev, &err_data, entry); | |
2084 | /* ue will trigger an interrupt, and in that case | |
2085 | * we need do a reset to recovery the whole system. | |
2086 | * But leave IP do that recovery, here we just dispatch | |
2087 | * the error. | |
2088 | */ | |
2089 | if (ret == AMDGPU_RAS_SUCCESS) { | |
2090 | /* these counts could be left as 0 if | |
2091 | * some blocks do not count error number | |
2092 | */ | |
2093 | obj->err_data.ue_count += err_data.ue_count; | |
2094 | obj->err_data.ce_count += err_data.ce_count; | |
46e2231c | 2095 | obj->err_data.de_count += err_data.de_count; |
50a7d025 | 2096 | } |
5b1270be YW |
2097 | |
2098 | amdgpu_ras_error_data_fini(&err_data); | |
50a7d025 TZ |
2099 | } |
2100 | ||
c030f2e4 | 2101 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) |
2102 | { | |
2103 | struct ras_ih_data *data = &obj->ih_data; | |
2104 | struct amdgpu_iv_entry entry; | |
c030f2e4 | 2105 | |
2106 | while (data->rptr != data->wptr) { | |
2107 | rmb(); | |
2108 | memcpy(&entry, &data->ring[data->rptr], | |
2109 | data->element_size); | |
2110 | ||
2111 | wmb(); | |
2112 | data->rptr = (data->aligned_element_size + | |
2113 | data->rptr) % data->ring_size; | |
2114 | ||
50a7d025 TZ |
2115 | if (amdgpu_ras_is_poison_mode_supported(obj->adev)) { |
2116 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
2117 | amdgpu_ras_interrupt_poison_creation_handler(obj, &entry); | |
66f87949 TZ |
2118 | else |
2119 | amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry); | |
50a7d025 TZ |
2120 | } else { |
2121 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
2122 | amdgpu_ras_interrupt_umc_handler(obj, &entry); | |
2123 | else | |
2124 | dev_warn(obj->adev->dev, | |
2125 | "No RAS interrupt handler for non-UMC block with poison disabled.\n"); | |
c030f2e4 | 2126 | } |
2127 | } | |
2128 | } | |
2129 | ||
2130 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
2131 | { | |
2132 | struct ras_ih_data *data = | |
2133 | container_of(work, struct ras_ih_data, ih_work); | |
2134 | struct ras_manager *obj = | |
2135 | container_of(data, struct ras_manager, ih_data); | |
2136 | ||
2137 | amdgpu_ras_interrupt_handler(obj); | |
2138 | } | |
2139 | ||
2140 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
2141 | struct ras_dispatch_if *info) | |
2142 | { | |
2143 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
2144 | struct ras_ih_data *data = &obj->ih_data; | |
2145 | ||
2146 | if (!obj) | |
2147 | return -EINVAL; | |
2148 | ||
2149 | if (data->inuse == 0) | |
2150 | return 0; | |
2151 | ||
2152 | /* Might be overflow... */ | |
2153 | memcpy(&data->ring[data->wptr], info->entry, | |
2154 | data->element_size); | |
2155 | ||
2156 | wmb(); | |
2157 | data->wptr = (data->aligned_element_size + | |
2158 | data->wptr) % data->ring_size; | |
2159 | ||
2160 | schedule_work(&data->ih_work); | |
2161 | ||
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
9252d33d | 2166 | struct ras_common_if *head) |
c030f2e4 | 2167 | { |
9252d33d | 2168 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 2169 | struct ras_ih_data *data; |
2170 | ||
2171 | if (!obj) | |
2172 | return -EINVAL; | |
2173 | ||
2174 | data = &obj->ih_data; | |
2175 | if (data->inuse == 0) | |
2176 | return 0; | |
2177 | ||
2178 | cancel_work_sync(&data->ih_work); | |
2179 | ||
2180 | kfree(data->ring); | |
2181 | memset(data, 0, sizeof(*data)); | |
2182 | put_obj(obj); | |
2183 | ||
2184 | return 0; | |
2185 | } | |
2186 | ||
2187 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
9252d33d | 2188 | struct ras_common_if *head) |
c030f2e4 | 2189 | { |
9252d33d | 2190 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 2191 | struct ras_ih_data *data; |
9252d33d | 2192 | struct amdgpu_ras_block_object *ras_obj; |
c030f2e4 | 2193 | |
2194 | if (!obj) { | |
2195 | /* in case we registe the IH before enable ras feature */ | |
9252d33d | 2196 | obj = amdgpu_ras_create_obj(adev, head); |
c030f2e4 | 2197 | if (!obj) |
2198 | return -EINVAL; | |
2199 | } else | |
2200 | get_obj(obj); | |
2201 | ||
9252d33d | 2202 | ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); |
2203 | ||
c030f2e4 | 2204 | data = &obj->ih_data; |
2205 | /* add the callback.etc */ | |
2206 | *data = (struct ras_ih_data) { | |
2207 | .inuse = 0, | |
9252d33d | 2208 | .cb = ras_obj->ras_cb, |
c030f2e4 | 2209 | .element_size = sizeof(struct amdgpu_iv_entry), |
2210 | .rptr = 0, | |
2211 | .wptr = 0, | |
2212 | }; | |
2213 | ||
2214 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
2215 | ||
2216 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
2217 | /* the ring can store 64 iv entries. */ | |
2218 | data->ring_size = 64 * data->aligned_element_size; | |
2219 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
2220 | if (!data->ring) { | |
2221 | put_obj(obj); | |
2222 | return -ENOMEM; | |
2223 | } | |
2224 | ||
2225 | /* IH is ready */ | |
2226 | data->inuse = 1; | |
2227 | ||
2228 | return 0; | |
2229 | } | |
2230 | ||
2231 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
2232 | { | |
2233 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2234 | struct ras_manager *obj, *tmp; | |
2235 | ||
2236 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
9252d33d | 2237 | amdgpu_ras_interrupt_remove_handler(adev, &obj->head); |
c030f2e4 | 2238 | } |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | /* ih end */ | |
2243 | ||
313c8fd3 GC |
2244 | /* traversal all IPs except NBIO to query error counter */ |
2245 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
2246 | { | |
2247 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2248 | struct ras_manager *obj; | |
2249 | ||
8ab0d6f0 | 2250 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
2251 | return; |
2252 | ||
2253 | list_for_each_entry(obj, &con->head, node) { | |
2254 | struct ras_query_if info = { | |
2255 | .head = obj->head, | |
2256 | }; | |
2257 | ||
2258 | /* | |
2259 | * PCIE_BIF IP has one different isr by ras controller | |
2260 | * interrupt, the specific ras counter query will be | |
2261 | * done in that isr. So skip such block from common | |
2262 | * sync flood interrupt isr calling. | |
2263 | */ | |
2264 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
2265 | continue; | |
2266 | ||
cf63b702 SY |
2267 | /* |
2268 | * this is a workaround for aldebaran, skip send msg to | |
2269 | * smu to get ecc_info table due to smu handle get ecc | |
2270 | * info table failed temporarily. | |
2271 | * should be removed until smu fix handle ecc_info table. | |
2272 | */ | |
2273 | if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
4e8303cf LL |
2274 | (amdgpu_ip_version(adev, MP1_HWIP, 0) == |
2275 | IP_VERSION(13, 0, 2))) | |
cf63b702 SY |
2276 | continue; |
2277 | ||
761d86d3 | 2278 | amdgpu_ras_query_error_status(adev, &info); |
2a460963 | 2279 | |
4e8303cf LL |
2280 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != |
2281 | IP_VERSION(11, 0, 2) && | |
2282 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
2283 | IP_VERSION(11, 0, 4) && | |
2284 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
2285 | IP_VERSION(13, 0, 0)) { | |
2a460963 CL |
2286 | if (amdgpu_ras_reset_error_status(adev, info.head.block)) |
2287 | dev_warn(adev->dev, "Failed to reset error counter and error status"); | |
2288 | } | |
313c8fd3 GC |
2289 | } |
2290 | } | |
2291 | ||
3f975d0f | 2292 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
2293 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
2294 | struct ras_query_if *info) | |
3f975d0f | 2295 | { |
8eb53bb2 | 2296 | struct amdgpu_ras_block_object *block_obj; |
3f975d0f SY |
2297 | /* |
2298 | * Only two block need to query read/write | |
2299 | * RspStatus at current state | |
2300 | */ | |
5e67bba3 | 2301 | if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && |
2302 | (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) | |
b6efdb02 | 2303 | return; |
2304 | ||
2305 | block_obj = amdgpu_ras_get_ras_block(adev, | |
2306 | info->head.block, | |
2307 | info->head.sub_block_index); | |
5e67bba3 | 2308 | |
5e67bba3 | 2309 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
2310 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
2311 | get_ras_block_str(&info->head)); | |
b6efdb02 | 2312 | return; |
3f975d0f | 2313 | } |
5e67bba3 | 2314 | |
2315 | if (block_obj->hw_ops->query_ras_error_status) | |
ab3b9de6 | 2316 | block_obj->hw_ops->query_ras_error_status(adev); |
5e67bba3 | 2317 | |
3f975d0f SY |
2318 | } |
2319 | ||
2320 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
2321 | { | |
2322 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2323 | struct ras_manager *obj; | |
2324 | ||
8ab0d6f0 | 2325 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
2326 | return; |
2327 | ||
2328 | list_for_each_entry(obj, &con->head, node) { | |
2329 | struct ras_query_if info = { | |
2330 | .head = obj->head, | |
2331 | }; | |
2332 | ||
2333 | amdgpu_ras_error_status_query(adev, &info); | |
2334 | } | |
2335 | } | |
2336 | ||
c030f2e4 | 2337 | /* recovery begin */ |
466b1793 | 2338 | |
2339 | /* return 0 on success. | |
2340 | * caller need free bps. | |
2341 | */ | |
2342 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
2343 | struct ras_badpage **bps, unsigned int *count) | |
2344 | { | |
2345 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2346 | struct ras_err_handler_data *data; | |
2347 | int i = 0; | |
732f2a30 | 2348 | int ret = 0, status; |
466b1793 | 2349 | |
2350 | if (!con || !con->eh_data || !bps || !count) | |
2351 | return -EINVAL; | |
2352 | ||
2353 | mutex_lock(&con->recovery_lock); | |
2354 | data = con->eh_data; | |
2355 | if (!data || data->count == 0) { | |
2356 | *bps = NULL; | |
46cf2fec | 2357 | ret = -EINVAL; |
466b1793 | 2358 | goto out; |
2359 | } | |
2360 | ||
2361 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
2362 | if (!*bps) { | |
2363 | ret = -ENOMEM; | |
2364 | goto out; | |
2365 | } | |
2366 | ||
2367 | for (; i < data->count; i++) { | |
2368 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 2369 | .bp = data->bps[i].retired_page, |
466b1793 | 2370 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 2371 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 2372 | }; |
ec6aae97 | 2373 | status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, |
676deb38 | 2374 | data->bps[i].retired_page); |
732f2a30 | 2375 | if (status == -EBUSY) |
52dd95f2 | 2376 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 2377 | else if (status == -ENOENT) |
52dd95f2 | 2378 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 2379 | } |
2380 | ||
2381 | *count = data->count; | |
2382 | out: | |
2383 | mutex_unlock(&con->recovery_lock); | |
2384 | return ret; | |
2385 | } | |
2386 | ||
c030f2e4 | 2387 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
2388 | { | |
2389 | struct amdgpu_ras *ras = | |
2390 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
2391 | struct amdgpu_device *remote_adev = NULL; |
2392 | struct amdgpu_device *adev = ras->adev; | |
2393 | struct list_head device_list, *device_list_handle = NULL; | |
53dd920c | 2394 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
b3dbd6d3 | 2395 | |
53dd920c AK |
2396 | if (hive) |
2397 | atomic_set(&hive->ras_recovery, 1); | |
f75e94d8 | 2398 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 | 2399 | |
f75e94d8 GC |
2400 | /* Build list of devices to query RAS related errors */ |
2401 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
2402 | device_list_handle = &hive->device_list; | |
2403 | } else { | |
2404 | INIT_LIST_HEAD(&device_list); | |
2405 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
2406 | device_list_handle = &device_list; | |
2407 | } | |
c030f2e4 | 2408 | |
f75e94d8 | 2409 | list_for_each_entry(remote_adev, |
3f975d0f SY |
2410 | device_list_handle, gmc.xgmi.head) { |
2411 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 2412 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 2413 | } |
d95e8e97 | 2414 | |
b3dbd6d3 | 2415 | } |
313c8fd3 | 2416 | |
f1549c09 LG |
2417 | if (amdgpu_device_should_recover_gpu(ras->adev)) { |
2418 | struct amdgpu_reset_context reset_context; | |
2419 | memset(&reset_context, 0, sizeof(reset_context)); | |
2420 | ||
2421 | reset_context.method = AMD_RESET_METHOD_NONE; | |
2422 | reset_context.reset_req_dev = adev; | |
1a11a65d YC |
2423 | |
2424 | /* Perform full reset in fatal error mode */ | |
2425 | if (!amdgpu_ras_is_poison_mode_supported(ras->adev)) | |
2426 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
6c47a79b | 2427 | else { |
1a11a65d | 2428 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
f1549c09 | 2429 | |
6c47a79b YC |
2430 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) { |
2431 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
2432 | reset_context.method = AMD_RESET_METHOD_MODE2; | |
2433 | } | |
2c7cd280 YC |
2434 | |
2435 | /* Fatal error occurs in poison mode, mode1 reset is used to | |
2436 | * recover gpu. | |
2437 | */ | |
2438 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) { | |
2439 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET; | |
2440 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
1b98a5f8 YC |
2441 | |
2442 | psp_fatal_error_recovery_quirk(&adev->psp); | |
2c7cd280 | 2443 | } |
6c47a79b YC |
2444 | } |
2445 | ||
f1549c09 LG |
2446 | amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); |
2447 | } | |
c030f2e4 | 2448 | atomic_set(&ras->in_recovery, 0); |
53dd920c AK |
2449 | if (hive) { |
2450 | atomic_set(&hive->ras_recovery, 0); | |
2451 | amdgpu_put_xgmi_hive(hive); | |
2452 | } | |
c030f2e4 | 2453 | } |
2454 | ||
c030f2e4 | 2455 | /* alloc/realloc bps array */ |
2456 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
2457 | struct ras_err_handler_data *data, int pages) | |
2458 | { | |
2459 | unsigned int old_space = data->count + data->space_left; | |
2460 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
2461 | unsigned int align_space = ALIGN(new_space, 512); |
2462 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 2463 | |
676deb38 | 2464 | if (!bps) { |
c030f2e4 | 2465 | return -ENOMEM; |
9dc23a63 | 2466 | } |
c030f2e4 | 2467 | |
2468 | if (data->bps) { | |
9dc23a63 | 2469 | memcpy(bps, data->bps, |
c030f2e4 | 2470 | data->count * sizeof(*data->bps)); |
2471 | kfree(data->bps); | |
2472 | } | |
2473 | ||
9dc23a63 | 2474 | data->bps = bps; |
c030f2e4 | 2475 | data->space_left += align_space - old_space; |
2476 | return 0; | |
2477 | } | |
2478 | ||
2479 | /* it deal with vram only. */ | |
2480 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 2481 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 2482 | { |
2483 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 2484 | struct ras_err_handler_data *data; |
c030f2e4 | 2485 | int ret = 0; |
676deb38 | 2486 | uint32_t i; |
c030f2e4 | 2487 | |
73aa8e1a | 2488 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 2489 | return 0; |
2490 | ||
2491 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 2492 | data = con->eh_data; |
c030f2e4 | 2493 | if (!data) |
2494 | goto out; | |
2495 | ||
676deb38 DL |
2496 | for (i = 0; i < pages; i++) { |
2497 | if (amdgpu_ras_check_bad_page_unlock(con, | |
2498 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
2499 | continue; | |
2500 | ||
2501 | if (!data->space_left && | |
2502 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 2503 | ret = -ENOMEM; |
2504 | goto out; | |
2505 | } | |
2506 | ||
ec6aae97 | 2507 | amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, |
676deb38 DL |
2508 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, |
2509 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 2510 | |
676deb38 DL |
2511 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
2512 | data->count++; | |
2513 | data->space_left--; | |
2514 | } | |
c030f2e4 | 2515 | out: |
2516 | mutex_unlock(&con->recovery_lock); | |
2517 | ||
2518 | return ret; | |
2519 | } | |
2520 | ||
78ad00c9 TZ |
2521 | /* |
2522 | * write error record array to eeprom, the function should be | |
2523 | * protected by recovery_lock | |
4d33e0f1 | 2524 | * new_cnt: new added UE count, excluding reserved bad pages, can be NULL |
78ad00c9 | 2525 | */ |
4d33e0f1 TZ |
2526 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, |
2527 | unsigned long *new_cnt) | |
78ad00c9 TZ |
2528 | { |
2529 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2530 | struct ras_err_handler_data *data; | |
8a3e801f | 2531 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
2532 | int save_count; |
2533 | ||
4d33e0f1 TZ |
2534 | if (!con || !con->eh_data) { |
2535 | if (new_cnt) | |
2536 | *new_cnt = 0; | |
2537 | ||
78ad00c9 | 2538 | return 0; |
4d33e0f1 | 2539 | } |
78ad00c9 | 2540 | |
d9a69fe5 | 2541 | mutex_lock(&con->recovery_lock); |
8a3e801f | 2542 | control = &con->eeprom_control; |
78ad00c9 | 2543 | data = con->eh_data; |
0686627b | 2544 | save_count = data->count - control->ras_num_recs; |
d9a69fe5 | 2545 | mutex_unlock(&con->recovery_lock); |
4d33e0f1 TZ |
2546 | |
2547 | if (new_cnt) | |
2548 | *new_cnt = save_count / adev->umc.retire_unit; | |
2549 | ||
78ad00c9 | 2550 | /* only new entries are saved */ |
b1628425 | 2551 | if (save_count > 0) { |
63d4c081 LT |
2552 | if (amdgpu_ras_eeprom_append(control, |
2553 | &data->bps[control->ras_num_recs], | |
2554 | save_count)) { | |
6952e99c | 2555 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
2556 | return -EIO; |
2557 | } | |
2558 | ||
b1628425 GC |
2559 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
2560 | } | |
2561 | ||
78ad00c9 TZ |
2562 | return 0; |
2563 | } | |
2564 | ||
2565 | /* | |
2566 | * read error record array in eeprom and reserve enough space for | |
2567 | * storing new bad pages | |
2568 | */ | |
2569 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
2570 | { | |
2571 | struct amdgpu_ras_eeprom_control *control = | |
6457205c | 2572 | &adev->psp.ras_context.ras->eeprom_control; |
e4e6a589 LT |
2573 | struct eeprom_table_record *bps; |
2574 | int ret; | |
78ad00c9 TZ |
2575 | |
2576 | /* no bad page record, skip eeprom access */ | |
0686627b | 2577 | if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) |
e4e6a589 | 2578 | return 0; |
78ad00c9 | 2579 | |
0686627b | 2580 | bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); |
78ad00c9 TZ |
2581 | if (!bps) |
2582 | return -ENOMEM; | |
2583 | ||
0686627b | 2584 | ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); |
e4e6a589 | 2585 | if (ret) |
6952e99c | 2586 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
e4e6a589 | 2587 | else |
0686627b | 2588 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); |
78ad00c9 | 2589 | |
78ad00c9 TZ |
2590 | kfree(bps); |
2591 | return ret; | |
2592 | } | |
2593 | ||
676deb38 DL |
2594 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
2595 | uint64_t addr) | |
2596 | { | |
2597 | struct ras_err_handler_data *data = con->eh_data; | |
2598 | int i; | |
2599 | ||
2600 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
2601 | for (i = 0; i < data->count; i++) | |
2602 | if (addr == data->bps[i].retired_page) | |
2603 | return true; | |
2604 | ||
2605 | return false; | |
2606 | } | |
2607 | ||
6e4be987 TZ |
2608 | /* |
2609 | * check if an address belongs to bad page | |
2610 | * | |
2611 | * Note: this check is only for umc block | |
2612 | */ | |
2613 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
2614 | uint64_t addr) | |
2615 | { | |
2616 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
2617 | bool ret = false; |
2618 | ||
2619 | if (!con || !con->eh_data) | |
2620 | return ret; | |
2621 | ||
2622 | mutex_lock(&con->recovery_lock); | |
676deb38 | 2623 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
2624 | mutex_unlock(&con->recovery_lock); |
2625 | return ret; | |
2626 | } | |
2627 | ||
e5c04edf | 2628 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
e4e6a589 | 2629 | uint32_t max_count) |
c84d4670 | 2630 | { |
e5c04edf | 2631 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
2632 | |
2633 | /* | |
2634 | * Justification of value bad_page_cnt_threshold in ras structure | |
2635 | * | |
f3cbe70e TZ |
2636 | * Generally, 0 <= amdgpu_bad_page_threshold <= max record length |
2637 | * in eeprom or amdgpu_bad_page_threshold == -2, introduce two | |
2638 | * scenarios accordingly. | |
c84d4670 GC |
2639 | * |
2640 | * Bad page retirement enablement: | |
f3cbe70e | 2641 | * - If amdgpu_bad_page_threshold = -2, |
c84d4670 GC |
2642 | * bad_page_cnt_threshold = typical value by formula. |
2643 | * | |
2644 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
2645 | * max record length in eeprom, use it directly. | |
2646 | * | |
2647 | * Bad page retirement disablement: | |
2648 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
2649 | * functionality is disabled, and bad_page_cnt_threshold will | |
2650 | * take no effect. | |
2651 | */ | |
2652 | ||
e4e6a589 LT |
2653 | if (amdgpu_bad_page_threshold < 0) { |
2654 | u64 val = adev->gmc.mc_vram_size; | |
c84d4670 | 2655 | |
e4e6a589 | 2656 | do_div(val, RAS_BAD_PAGE_COVER); |
e5c04edf | 2657 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
e4e6a589 | 2658 | max_count); |
e5c04edf | 2659 | } else { |
e4e6a589 LT |
2660 | con->bad_page_cnt_threshold = min_t(int, max_count, |
2661 | amdgpu_bad_page_threshold); | |
c84d4670 GC |
2662 | } |
2663 | } | |
2664 | ||
3fdcd0a3 YC |
2665 | static int amdgpu_ras_page_retirement_thread(void *param) |
2666 | { | |
2667 | struct amdgpu_device *adev = (struct amdgpu_device *)param; | |
2668 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2669 | ||
2670 | while (!kthread_should_stop()) { | |
2671 | ||
2672 | wait_event_interruptible(con->page_retirement_wq, | |
c84a7e21 | 2673 | kthread_should_stop() || |
3fdcd0a3 YC |
2674 | atomic_read(&con->page_retirement_req_cnt)); |
2675 | ||
c84a7e21 MJ |
2676 | if (kthread_should_stop()) |
2677 | break; | |
2678 | ||
3fdcd0a3 YC |
2679 | dev_info(adev->dev, "Start processing page retirement. request:%d\n", |
2680 | atomic_read(&con->page_retirement_req_cnt)); | |
2681 | ||
2682 | atomic_dec(&con->page_retirement_req_cnt); | |
6c23f3d1 YC |
2683 | |
2684 | amdgpu_umc_bad_page_polling_timeout(adev, | |
2685 | false, MAX_UMC_POISON_POLLING_TIME_ASYNC); | |
3fdcd0a3 YC |
2686 | } |
2687 | ||
2688 | return 0; | |
2689 | } | |
2690 | ||
1a6fc071 | 2691 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 2692 | { |
2693 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 2694 | struct ras_err_handler_data **data; |
e4e6a589 | 2695 | u32 max_eeprom_records_count = 0; |
b82e65a9 | 2696 | bool exc_err_limit = false; |
78ad00c9 | 2697 | int ret; |
c030f2e4 | 2698 | |
e0e146d5 | 2699 | if (!con || amdgpu_sriov_vf(adev)) |
1d9d2ca8 LT |
2700 | return 0; |
2701 | ||
2702 | /* Allow access to RAS EEPROM via debugfs, when the ASIC | |
2703 | * supports RAS and debugfs is enabled, but when | |
2704 | * adev->ras_enabled is unset, i.e. when "ras_enable" | |
2705 | * module parameter is set to 0. | |
2706 | */ | |
2707 | con->adev = adev; | |
2708 | ||
2709 | if (!adev->ras_enabled) | |
4d1337d2 AG |
2710 | return 0; |
2711 | ||
1d9d2ca8 | 2712 | data = &con->eh_data; |
091411be | 2713 | *data = kzalloc(sizeof(**data), GFP_KERNEL); |
1a6fc071 TZ |
2714 | if (!*data) { |
2715 | ret = -ENOMEM; | |
2716 | goto out; | |
2717 | } | |
c030f2e4 | 2718 | |
2719 | mutex_init(&con->recovery_lock); | |
2720 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
2721 | atomic_set(&con->in_recovery, 0); | |
69691c82 | 2722 | con->eeprom_control.bad_channel_bitmap = 0; |
c030f2e4 | 2723 | |
7f599fed | 2724 | max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); |
e4e6a589 | 2725 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); |
c84d4670 | 2726 | |
e5086659 | 2727 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
2728 | * when the GPU is pending on XGMI reset during probe time | |
2729 | * (Mostly after second bus reset), skip it now | |
2730 | */ | |
2731 | if (adev->gmc.xgmi.pending_reset) | |
2732 | return 0; | |
b82e65a9 GC |
2733 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
2734 | /* | |
2735 | * This calling fails when exc_err_limit is true or | |
2736 | * ret != 0. | |
2737 | */ | |
2738 | if (exc_err_limit || ret) | |
1a6fc071 | 2739 | goto free; |
78ad00c9 | 2740 | |
0686627b | 2741 | if (con->eeprom_control.ras_num_recs) { |
78ad00c9 TZ |
2742 | ret = amdgpu_ras_load_bad_pages(adev); |
2743 | if (ret) | |
1a6fc071 | 2744 | goto free; |
513befa6 | 2745 | |
bc143d8b | 2746 | amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); |
69691c82 SY |
2747 | |
2748 | if (con->update_channel_flag == true) { | |
2749 | amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); | |
2750 | con->update_channel_flag = false; | |
2751 | } | |
78ad00c9 | 2752 | } |
c030f2e4 | 2753 | |
3fdcd0a3 YC |
2754 | mutex_init(&con->page_retirement_lock); |
2755 | init_waitqueue_head(&con->page_retirement_wq); | |
2756 | atomic_set(&con->page_retirement_req_cnt, 0); | |
2757 | con->page_retirement_thread = | |
2758 | kthread_run(amdgpu_ras_page_retirement_thread, adev, "umc_page_retirement"); | |
2759 | if (IS_ERR(con->page_retirement_thread)) { | |
2760 | con->page_retirement_thread = NULL; | |
2761 | dev_warn(adev->dev, "Failed to create umc_page_retirement thread!!!\n"); | |
2762 | } | |
2763 | ||
12b2cab7 MJ |
2764 | #ifdef CONFIG_X86_MCE_AMD |
2765 | if ((adev->asic_type == CHIP_ALDEBARAN) && | |
2766 | (adev->gmc.xgmi.connected_to_cpu)) | |
91a1a52d | 2767 | amdgpu_register_bad_pages_mca_notifier(adev); |
12b2cab7 | 2768 | #endif |
c030f2e4 | 2769 | return 0; |
1a6fc071 | 2770 | |
1a6fc071 | 2771 | free: |
1a6fc071 | 2772 | kfree((*data)->bps); |
1a6fc071 | 2773 | kfree(*data); |
1995b3a3 | 2774 | con->eh_data = NULL; |
1a6fc071 | 2775 | out: |
cf696091 | 2776 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2777 | |
b82e65a9 GC |
2778 | /* |
2779 | * Except error threshold exceeding case, other failure cases in this | |
2780 | * function would not fail amdgpu driver init. | |
2781 | */ | |
2782 | if (!exc_err_limit) | |
2783 | ret = 0; | |
2784 | else | |
2785 | ret = -EINVAL; | |
2786 | ||
1a6fc071 | 2787 | return ret; |
c030f2e4 | 2788 | } |
2789 | ||
2790 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2791 | { | |
2792 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2793 | struct ras_err_handler_data *data = con->eh_data; | |
2794 | ||
1a6fc071 TZ |
2795 | /* recovery_init failed to init it, fini is useless */ |
2796 | if (!data) | |
2797 | return 0; | |
2798 | ||
3fdcd0a3 YC |
2799 | if (con->page_retirement_thread) |
2800 | kthread_stop(con->page_retirement_thread); | |
2801 | ||
2802 | atomic_set(&con->page_retirement_req_cnt, 0); | |
2803 | ||
c030f2e4 | 2804 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2805 | |
2806 | mutex_lock(&con->recovery_lock); | |
2807 | con->eh_data = NULL; | |
2808 | kfree(data->bps); | |
2809 | kfree(data); | |
2810 | mutex_unlock(&con->recovery_lock); | |
2811 | ||
2812 | return 0; | |
2813 | } | |
2814 | /* recovery end */ | |
2815 | ||
084e2640 | 2816 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2817 | { |
82835055 | 2818 | if (amdgpu_sriov_vf(adev)) { |
4e8303cf | 2819 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
82835055 | 2820 | case IP_VERSION(13, 0, 2): |
80578f16 | 2821 | case IP_VERSION(13, 0, 6): |
82835055 YC |
2822 | return true; |
2823 | default: | |
2824 | return false; | |
2825 | } | |
2826 | } | |
2827 | ||
073285ef | 2828 | if (adev->asic_type == CHIP_IP_DISCOVERY) { |
4e8303cf | 2829 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
073285ef | 2830 | case IP_VERSION(13, 0, 0): |
cb906ce3 | 2831 | case IP_VERSION(13, 0, 6): |
073285ef YC |
2832 | case IP_VERSION(13, 0, 10): |
2833 | return true; | |
2834 | default: | |
2835 | return false; | |
2836 | } | |
2837 | } | |
2838 | ||
084e2640 LT |
2839 | return adev->asic_type == CHIP_VEGA10 || |
2840 | adev->asic_type == CHIP_VEGA20 || | |
2841 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2842 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2843 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2844 | } |
2845 | ||
f50160cf SY |
2846 | /* |
2847 | * this is workaround for vega20 workstation sku, | |
2848 | * force enable gfx ras, ignore vbios gfx ras flag | |
2849 | * due to GC EDC can not write | |
2850 | */ | |
e509965e | 2851 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2852 | { |
2853 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2854 | ||
2855 | if (!ctx) | |
2856 | return; | |
2857 | ||
adf64e21 ML |
2858 | if (strnstr(ctx->vbios_pn, "D16406", |
2859 | sizeof(ctx->vbios_pn)) || | |
2860 | strnstr(ctx->vbios_pn, "D36002", | |
2861 | sizeof(ctx->vbios_pn))) | |
8ab0d6f0 | 2862 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2863 | } |
2864 | ||
4e2965bd HZ |
2865 | /* Query ras capablity via atomfirmware interface */ |
2866 | static void amdgpu_ras_query_ras_capablity_from_vbios(struct amdgpu_device *adev) | |
2867 | { | |
2868 | /* mem_ecc cap */ | |
2869 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2870 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
2871 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | | |
2872 | 1 << AMDGPU_RAS_BLOCK__DF); | |
2873 | } else { | |
2874 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2875 | } | |
2876 | ||
2877 | /* sram_ecc cap */ | |
2878 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
2879 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
2880 | if (!amdgpu_sriov_vf(adev)) | |
2881 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | | |
2882 | 1 << AMDGPU_RAS_BLOCK__DF); | |
2883 | else | |
2884 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | | |
2885 | 1 << AMDGPU_RAS_BLOCK__SDMA | | |
2886 | 1 << AMDGPU_RAS_BLOCK__GFX); | |
2887 | ||
2888 | /* | |
2889 | * VCN/JPEG RAS can be supported on both bare metal and | |
2890 | * SRIOV environment | |
2891 | */ | |
2892 | if (amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(2, 6, 0) || | |
2893 | amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 0) || | |
2894 | amdgpu_ip_version(adev, VCN_HWIP, 0) == IP_VERSION(4, 0, 3)) | |
2895 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | | |
2896 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
2897 | else | |
2898 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | | |
2899 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
2900 | ||
2901 | /* | |
2902 | * XGMI RAS is not supported if xgmi num physical nodes | |
2903 | * is zero | |
2904 | */ | |
2905 | if (!adev->gmc.xgmi.num_physical_nodes) | |
2906 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); | |
2907 | } else { | |
2908 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2909 | } | |
2910 | } | |
2911 | ||
2912 | /* Query poison mode from umc/df IP callbacks */ | |
2913 | static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) | |
2914 | { | |
2915 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2916 | bool df_poison, umc_poison; | |
2917 | ||
2918 | /* poison setting is useless on SRIOV guest */ | |
2919 | if (amdgpu_sriov_vf(adev) || !con) | |
2920 | return; | |
2921 | ||
2922 | /* Init poison supported flag, the default value is false */ | |
2923 | if (adev->gmc.xgmi.connected_to_cpu || | |
2924 | adev->gmc.is_app_apu) { | |
2925 | /* enabled by default when GPU is connected to CPU */ | |
2926 | con->poison_supported = true; | |
2927 | } else if (adev->df.funcs && | |
2928 | adev->df.funcs->query_ras_poison_mode && | |
2929 | adev->umc.ras && | |
2930 | adev->umc.ras->query_ras_poison_mode) { | |
2931 | df_poison = | |
2932 | adev->df.funcs->query_ras_poison_mode(adev); | |
2933 | umc_poison = | |
2934 | adev->umc.ras->query_ras_poison_mode(adev); | |
2935 | ||
2936 | /* Only poison is set in both DF and UMC, we can support it */ | |
2937 | if (df_poison && umc_poison) | |
2938 | con->poison_supported = true; | |
2939 | else if (df_poison != umc_poison) | |
2940 | dev_warn(adev->dev, | |
2941 | "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
2942 | df_poison, umc_poison); | |
2943 | } | |
2944 | } | |
2945 | ||
5caf466a | 2946 | /* |
2947 | * check hardware's ras ability which will be saved in hw_supported. | |
2948 | * if hardware does not support ras, we can skip some ras initializtion and | |
2949 | * forbid some ras operations from IP. | |
2950 | * if software itself, say boot parameter, limit the ras ability. We still | |
2951 | * need allow IP do some limited operations, like disable. In such case, | |
2952 | * we have to initialize ras as normal. but need check if operation is | |
2953 | * allowed or not in each function. | |
2954 | */ | |
e509965e | 2955 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2956 | { |
8ab0d6f0 | 2957 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2958 | |
38298ce6 | 2959 | if (!amdgpu_ras_asic_supported(adev)) |
5caf466a | 2960 | return; |
b404ae82 | 2961 | |
4e2965bd HZ |
2962 | /* query ras capability from psp */ |
2963 | if (amdgpu_psp_get_ras_capability(&adev->psp)) | |
2964 | goto init_ras_enabled_flag; | |
58bc2a9c | 2965 | |
4e2965bd HZ |
2966 | /* query ras capablity from bios */ |
2967 | if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { | |
2968 | amdgpu_ras_query_ras_capablity_from_vbios(adev); | |
75f06251 HZ |
2969 | } else { |
2970 | /* driver only manages a few IP blocks RAS feature | |
2971 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2972 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2973 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2974 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2975 | } |
88474cca | 2976 | |
4e2965bd | 2977 | /* apply asic specific settings (vega20 only for now) */ |
e509965e | 2978 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2979 | |
4e2965bd HZ |
2980 | /* query poison mode from umc/df ip callback */ |
2981 | amdgpu_ras_query_poison_mode(adev); | |
2982 | ||
2983 | init_ras_enabled_flag: | |
88474cca | 2984 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2985 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2986 | |
66d64e4e SY |
2987 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2988 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
04c4fcd2 YW |
2989 | |
2990 | /* aca is disabled by default */ | |
2991 | adev->aca.is_enabled = false; | |
c030f2e4 | 2992 | } |
2993 | ||
05adfd80 LT |
2994 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2995 | { | |
2996 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2997 | ras_counte_delay_work.work); | |
2998 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2999 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
3000 | unsigned long ce_count, ue_count; |
3001 | int res; | |
3002 | ||
3003 | res = pm_runtime_get_sync(dev->dev); | |
3004 | if (res < 0) | |
3005 | goto Out; | |
3006 | ||
3007 | /* Cache new values. | |
3008 | */ | |
4a1c9a44 | 3009 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) { |
4d9f771e LT |
3010 | atomic_set(&con->ras_ce_count, ce_count); |
3011 | atomic_set(&con->ras_ue_count, ue_count); | |
3012 | } | |
05adfd80 LT |
3013 | |
3014 | pm_runtime_mark_last_busy(dev->dev); | |
3015 | Out: | |
3016 | pm_runtime_put_autosuspend(dev->dev); | |
3017 | } | |
3018 | ||
625e5f38 AK |
3019 | static int amdgpu_get_ras_schema(struct amdgpu_device *adev) |
3020 | { | |
3021 | return amdgpu_ras_is_poison_mode_supported(adev) ? AMDGPU_RAS_ERROR__POISON : 0 | | |
3022 | AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE | | |
3023 | AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE | | |
3024 | AMDGPU_RAS_ERROR__PARITY; | |
3025 | } | |
3026 | ||
c030f2e4 | 3027 | int amdgpu_ras_init(struct amdgpu_device *adev) |
3028 | { | |
3029 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 3030 | int r; |
c030f2e4 | 3031 | |
b404ae82 | 3032 | if (con) |
c030f2e4 | 3033 | return 0; |
3034 | ||
091411be | 3035 | con = kzalloc(sizeof(*con) + |
640ae42e JC |
3036 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + |
3037 | sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, | |
091411be | 3038 | GFP_KERNEL); |
c030f2e4 | 3039 | if (!con) |
3040 | return -ENOMEM; | |
3041 | ||
05adfd80 LT |
3042 | con->adev = adev; |
3043 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
3044 | atomic_set(&con->ras_ce_count, 0); | |
3045 | atomic_set(&con->ras_ue_count, 0); | |
3046 | ||
c030f2e4 | 3047 | con->objs = (struct ras_manager *)(con + 1); |
3048 | ||
3049 | amdgpu_ras_set_context(adev, con); | |
3050 | ||
e509965e LT |
3051 | amdgpu_ras_check_supported(adev); |
3052 | ||
7ddd9770 | 3053 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
3054 | /* set gfx block ras context feature for VEGA20 Gaming |
3055 | * send ras disable cmd to ras ta during ras late init. | |
3056 | */ | |
8ab0d6f0 | 3057 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
3058 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
3059 | ||
3060 | return 0; | |
3061 | } | |
3062 | ||
5e91160a | 3063 | r = 0; |
5436ab94 | 3064 | goto release_con; |
fb2a3607 HZ |
3065 | } |
3066 | ||
69691c82 | 3067 | con->update_channel_flag = false; |
c030f2e4 | 3068 | con->features = 0; |
625e5f38 | 3069 | con->schema = 0; |
c030f2e4 | 3070 | INIT_LIST_HEAD(&con->head); |
108c6a63 | 3071 | /* Might need get this flag from vbios. */ |
3072 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 3073 | |
6e36f231 HZ |
3074 | /* initialize nbio ras function ahead of any other |
3075 | * ras functions so hardware fatal error interrupt | |
3076 | * can be enabled as early as possible */ | |
4e8303cf | 3077 | switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { |
fdc94d3a HZ |
3078 | case IP_VERSION(7, 4, 0): |
3079 | case IP_VERSION(7, 4, 1): | |
3080 | case IP_VERSION(7, 4, 4): | |
3081 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2e54fe5d | 3082 | adev->nbio.ras = &nbio_v7_4_ras; |
6e36f231 | 3083 | break; |
9af357bc HZ |
3084 | case IP_VERSION(4, 3, 0): |
3085 | if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) | |
3086 | /* unlike other generation of nbio ras, | |
3087 | * nbio v4_3 only support fatal error interrupt | |
3088 | * to inform software that DF is freezed due to | |
3089 | * system fatal error event. driver should not | |
3090 | * enable nbio ras in such case. Instead, | |
3091 | * check DF RAS */ | |
3092 | adev->nbio.ras = &nbio_v4_3_ras; | |
3093 | break; | |
7692e1ee TZ |
3094 | case IP_VERSION(7, 9, 0): |
3095 | if (!adev->gmc.is_app_apu) | |
3096 | adev->nbio.ras = &nbio_v7_9_ras; | |
3097 | break; | |
6e36f231 HZ |
3098 | default: |
3099 | /* nbio ras is not available */ | |
3100 | break; | |
3101 | } | |
3102 | ||
fdc94d3a HZ |
3103 | /* nbio ras block needs to be enabled ahead of other ras blocks |
3104 | * to handle fatal error */ | |
3105 | r = amdgpu_nbio_ras_sw_init(adev); | |
3106 | if (r) | |
3107 | return r; | |
3108 | ||
2e54fe5d | 3109 | if (adev->nbio.ras && |
3110 | adev->nbio.ras->init_ras_controller_interrupt) { | |
3111 | r = adev->nbio.ras->init_ras_controller_interrupt(adev); | |
4e644fff | 3112 | if (r) |
5436ab94 | 3113 | goto release_con; |
4e644fff HZ |
3114 | } |
3115 | ||
2e54fe5d | 3116 | if (adev->nbio.ras && |
3117 | adev->nbio.ras->init_ras_err_event_athub_interrupt) { | |
3118 | r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 3119 | if (r) |
5436ab94 | 3120 | goto release_con; |
4e644fff HZ |
3121 | } |
3122 | ||
73cb81dc HZ |
3123 | /* Packed socket_id to ras feature mask bits[31:29] */ |
3124 | if (adev->smuio.funcs && | |
3125 | adev->smuio.funcs->get_socket_id) | |
ee9c3031 SY |
3126 | con->features |= ((adev->smuio.funcs->get_socket_id(adev)) << |
3127 | AMDGPU_RAS_FEATURES_SOCKETID_SHIFT); | |
73cb81dc | 3128 | |
625e5f38 AK |
3129 | /* Get RAS schema for particular SOC */ |
3130 | con->schema = amdgpu_get_ras_schema(adev); | |
3131 | ||
5e91160a GC |
3132 | if (amdgpu_ras_fs_init(adev)) { |
3133 | r = -EINVAL; | |
5436ab94 | 3134 | goto release_con; |
5e91160a | 3135 | } |
c030f2e4 | 3136 | |
6952e99c | 3137 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 3138 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 3139 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 3140 | |
c030f2e4 | 3141 | return 0; |
5436ab94 | 3142 | release_con: |
c030f2e4 | 3143 | amdgpu_ras_set_context(adev, NULL); |
3144 | kfree(con); | |
3145 | ||
5e91160a | 3146 | return r; |
c030f2e4 | 3147 | } |
3148 | ||
8f6368a9 | 3149 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 | 3150 | { |
8107e499 HZ |
3151 | if (adev->gmc.xgmi.connected_to_cpu || |
3152 | adev->gmc.is_app_apu) | |
134d16d5 JC |
3153 | return 1; |
3154 | return 0; | |
3155 | } | |
3156 | ||
3157 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
3158 | struct ras_common_if *ras_block) | |
3159 | { | |
3160 | struct ras_query_if info = { | |
3161 | .head = *ras_block, | |
3162 | }; | |
3163 | ||
3164 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
3165 | return 0; | |
3166 | ||
3167 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
3168 | DRM_WARN("RAS init harvest failure"); | |
3169 | ||
3170 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
3171 | DRM_WARN("RAS init harvest reset failure"); | |
3172 | ||
3173 | return 0; | |
3174 | } | |
3175 | ||
e4348849 TZ |
3176 | bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) |
3177 | { | |
3178 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3179 | ||
3180 | if (!con) | |
3181 | return false; | |
3182 | ||
3183 | return con->poison_supported; | |
3184 | } | |
3185 | ||
b293e891 | 3186 | /* helper function to handle common stuff in ip late init phase */ |
563285c8 | 3187 | int amdgpu_ras_block_late_init(struct amdgpu_device *adev, |
3188 | struct ras_common_if *ras_block) | |
b293e891 | 3189 | { |
29c9b6cd | 3190 | struct amdgpu_ras_block_object *ras_obj = NULL; |
05adfd80 | 3191 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
4a1c9a44 | 3192 | struct ras_query_if *query_info; |
05adfd80 | 3193 | unsigned long ue_count, ce_count; |
b293e891 HZ |
3194 | int r; |
3195 | ||
3196 | /* disable RAS feature per IP block if it is not supported */ | |
3197 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
3198 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
3203 | if (r) { | |
9080a18f | 3204 | if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
3205 | /* in resume phase, if fail to enable ras, |
3206 | * clean up all ras fs nodes, and disable ras */ | |
3207 | goto cleanup; | |
3208 | } else | |
3209 | return r; | |
3210 | } | |
3211 | ||
134d16d5 JC |
3212 | /* check for errors on warm reset edc persisant supported ASIC */ |
3213 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
3214 | ||
b293e891 | 3215 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 3216 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
3217 | return 0; |
3218 | ||
563285c8 | 3219 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
36780606 TZ |
3220 | if (ras_obj->ras_cb || (ras_obj->hw_ops && |
3221 | (ras_obj->hw_ops->query_poison_status || | |
3222 | ras_obj->hw_ops->handle_poison_consumption))) { | |
9252d33d | 3223 | r = amdgpu_ras_interrupt_add_handler(adev, ras_block); |
b293e891 | 3224 | if (r) |
779596ce | 3225 | goto cleanup; |
b293e891 HZ |
3226 | } |
3227 | ||
f957138c HZ |
3228 | if (ras_obj->hw_ops && |
3229 | (ras_obj->hw_ops->query_ras_error_count || | |
3230 | ras_obj->hw_ops->query_ras_error_status)) { | |
3231 | r = amdgpu_ras_sysfs_create(adev, ras_block); | |
3232 | if (r) | |
3233 | goto interrupt; | |
b293e891 | 3234 | |
f957138c HZ |
3235 | /* Those are the cached values at init. |
3236 | */ | |
3237 | query_info = kzalloc(sizeof(*query_info), GFP_KERNEL); | |
3238 | if (!query_info) | |
3239 | return -ENOMEM; | |
3240 | memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if)); | |
4a1c9a44 | 3241 | |
f957138c HZ |
3242 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) { |
3243 | atomic_set(&con->ras_ce_count, ce_count); | |
3244 | atomic_set(&con->ras_ue_count, ue_count); | |
3245 | } | |
3246 | ||
3247 | kfree(query_info); | |
4d9f771e | 3248 | } |
05adfd80 | 3249 | |
b293e891 | 3250 | return 0; |
779596ce TR |
3251 | |
3252 | interrupt: | |
563285c8 | 3253 | if (ras_obj->ras_cb) |
9252d33d | 3254 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); |
779596ce | 3255 | cleanup: |
b293e891 HZ |
3256 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
3257 | return r; | |
3258 | } | |
3259 | ||
d41ff22a | 3260 | static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev, |
418abce2 | 3261 | struct ras_common_if *ras_block) |
3262 | { | |
3263 | return amdgpu_ras_block_late_init(adev, ras_block); | |
3264 | } | |
3265 | ||
b293e891 | 3266 | /* helper function to remove ras fs node and interrupt handler */ |
bdb3489c | 3267 | void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, |
3268 | struct ras_common_if *ras_block) | |
3269 | { | |
563285c8 | 3270 | struct amdgpu_ras_block_object *ras_obj; |
bdb3489c | 3271 | if (!ras_block) |
3272 | return; | |
3273 | ||
563285c8 | 3274 | amdgpu_ras_sysfs_remove(adev, ras_block); |
bdb3489c | 3275 | |
563285c8 | 3276 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
3277 | if (ras_obj->ras_cb) | |
3278 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); | |
bdb3489c | 3279 | } |
3280 | ||
80e0c2cb | 3281 | static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev, |
3282 | struct ras_common_if *ras_block) | |
3283 | { | |
3284 | return amdgpu_ras_block_late_fini(adev, ras_block); | |
3285 | } | |
3286 | ||
a564808e | 3287 | /* do some init work after IP late init as dependence. |
511fdbc3 | 3288 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 3289 | */ |
511fdbc3 | 3290 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 3291 | { |
3292 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3293 | struct ras_manager *obj, *tmp; | |
3294 | ||
8ab0d6f0 | 3295 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
3296 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
3297 | amdgpu_release_ras_context(adev); | |
3298 | ||
108c6a63 | 3299 | return; |
970fd197 | 3300 | } |
108c6a63 | 3301 | |
108c6a63 | 3302 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 3303 | /* Set up all other IPs which are not implemented. There is a |
3304 | * tricky thing that IP's actual ras error type should be | |
3305 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
3306 | * ERROR_NONE make sense anyway. | |
3307 | */ | |
3308 | amdgpu_ras_enable_all_features(adev, 1); | |
3309 | ||
3310 | /* We enable ras on all hw_supported block, but as boot | |
3311 | * parameter might disable some of them and one or more IP has | |
3312 | * not implemented yet. So we disable them on behalf. | |
3313 | */ | |
108c6a63 | 3314 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
3315 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
3316 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
3317 | /* there should be no any reference. */ | |
3318 | WARN_ON(alive_obj(obj)); | |
3319 | } | |
191051a1 | 3320 | } |
108c6a63 | 3321 | } |
3322 | } | |
3323 | ||
511fdbc3 | 3324 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
3325 | { | |
3326 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3327 | ||
8ab0d6f0 | 3328 | if (!adev->ras_enabled || !con) |
511fdbc3 | 3329 | return; |
3330 | ||
3331 | amdgpu_ras_disable_all_features(adev, 0); | |
3332 | /* Make sure all ras objects are disabled. */ | |
ee9c3031 | 3333 | if (AMDGPU_RAS_GET_FEATURES(con->features)) |
511fdbc3 | 3334 | amdgpu_ras_disable_all_features(adev, 1); |
3335 | } | |
3336 | ||
867e24ca | 3337 | int amdgpu_ras_late_init(struct amdgpu_device *adev) |
3338 | { | |
3339 | struct amdgpu_ras_block_list *node, *tmp; | |
3340 | struct amdgpu_ras_block_object *obj; | |
3341 | int r; | |
3342 | ||
950d6425 SY |
3343 | /* Guest side doesn't need init ras feature */ |
3344 | if (amdgpu_sriov_vf(adev)) | |
3345 | return 0; | |
3346 | ||
04c4fcd2 YW |
3347 | if (amdgpu_aca_is_enabled(adev)) |
3348 | amdgpu_ras_set_aca_debug_mode(adev, false); | |
3349 | else | |
3350 | amdgpu_ras_set_mca_debug_mode(adev, false); | |
201761b5 | 3351 | |
867e24ca | 3352 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
2866a454 YW |
3353 | obj = node->ras_obj; |
3354 | if (!obj) { | |
867e24ca | 3355 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); |
3356 | continue; | |
3357 | } | |
418abce2 | 3358 | |
2866a454 YW |
3359 | if (!amdgpu_ras_is_supported(adev, obj->ras_comm.block)) |
3360 | continue; | |
3361 | ||
867e24ca | 3362 | if (obj->ras_late_init) { |
3363 | r = obj->ras_late_init(adev, &obj->ras_comm); | |
3364 | if (r) { | |
3365 | dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n", | |
3366 | obj->ras_comm.name, r); | |
3367 | return r; | |
3368 | } | |
418abce2 | 3369 | } else |
3370 | amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); | |
867e24ca | 3371 | } |
3372 | ||
3373 | return 0; | |
3374 | } | |
3375 | ||
c030f2e4 | 3376 | /* do some fini work before IP fini as dependence */ |
3377 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
3378 | { | |
3379 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3380 | ||
8ab0d6f0 | 3381 | if (!adev->ras_enabled || !con) |
c030f2e4 | 3382 | return 0; |
3383 | ||
72c8c97b | 3384 | |
c030f2e4 | 3385 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
ee9c3031 | 3386 | if (AMDGPU_RAS_GET_FEATURES(con->features)) |
642c0401 | 3387 | amdgpu_ras_disable_all_features(adev, 0); |
c030f2e4 | 3388 | amdgpu_ras_recovery_fini(adev); |
3389 | return 0; | |
3390 | } | |
3391 | ||
3392 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
3393 | { | |
d5e8ff5f | 3394 | struct amdgpu_ras_block_list *ras_node, *tmp; |
1f211a82 | 3395 | struct amdgpu_ras_block_object *obj = NULL; |
c030f2e4 | 3396 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
3397 | ||
8ab0d6f0 | 3398 | if (!adev->ras_enabled || !con) |
c030f2e4 | 3399 | return 0; |
3400 | ||
1f211a82 | 3401 | list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { |
3402 | if (ras_node->ras_obj) { | |
3403 | obj = ras_node->ras_obj; | |
3404 | if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) && | |
3405 | obj->ras_fini) | |
3406 | obj->ras_fini(adev, &obj->ras_comm); | |
80e0c2cb | 3407 | else |
3408 | amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm); | |
1f211a82 | 3409 | } |
3410 | ||
3411 | /* Clear ras blocks from ras_list and free ras block list node */ | |
3412 | list_del(&ras_node->node); | |
3413 | kfree(ras_node); | |
3414 | } | |
3415 | ||
c030f2e4 | 3416 | amdgpu_ras_fs_fini(adev); |
3417 | amdgpu_ras_interrupt_remove_all(adev); | |
3418 | ||
ee9c3031 | 3419 | WARN(AMDGPU_RAS_GET_FEATURES(con->features), "Feature mask is not cleared"); |
c030f2e4 | 3420 | |
ee9c3031 | 3421 | if (AMDGPU_RAS_GET_FEATURES(con->features)) |
c030f2e4 | 3422 | amdgpu_ras_disable_all_features(adev, 1); |
3423 | ||
05adfd80 LT |
3424 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
3425 | ||
c030f2e4 | 3426 | amdgpu_ras_set_context(adev, NULL); |
3427 | kfree(con); | |
3428 | ||
3429 | return 0; | |
3430 | } | |
7c6e68c7 AG |
3431 | |
3432 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
3433 | { | |
3434 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { | |
2c7cd280 YC |
3435 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
3436 | ||
6952e99c GC |
3437 | dev_info(adev->dev, "uncorrectable hardware error" |
3438 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 3439 | |
2c7cd280 | 3440 | ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; |
61934624 | 3441 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
3442 | } |
3443 | } | |
bb5c7235 WS |
3444 | |
3445 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
3446 | { | |
3447 | if (adev->asic_type == CHIP_VEGA20 && | |
3448 | adev->pm.fw_version <= 0x283400) { | |
3449 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
3450 | amdgpu_ras_intr_triggered(); | |
3451 | } | |
3452 | ||
3453 | return false; | |
3454 | } | |
970fd197 SY |
3455 | |
3456 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
3457 | { | |
3458 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3459 | ||
3460 | if (!con) | |
3461 | return; | |
3462 | ||
8ab0d6f0 | 3463 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
3464 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
3465 | amdgpu_ras_set_context(adev, NULL); | |
3466 | kfree(con); | |
3467 | } | |
3468 | } | |
12b2cab7 MJ |
3469 | |
3470 | #ifdef CONFIG_X86_MCE_AMD | |
3471 | static struct amdgpu_device *find_adev(uint32_t node_id) | |
3472 | { | |
12b2cab7 MJ |
3473 | int i; |
3474 | struct amdgpu_device *adev = NULL; | |
3475 | ||
91a1a52d MJ |
3476 | for (i = 0; i < mce_adev_list.num_gpu; i++) { |
3477 | adev = mce_adev_list.devs[i]; | |
12b2cab7 | 3478 | |
91a1a52d | 3479 | if (adev && adev->gmc.xgmi.connected_to_cpu && |
12b2cab7 MJ |
3480 | adev->gmc.xgmi.physical_node_id == node_id) |
3481 | break; | |
3482 | adev = NULL; | |
3483 | } | |
3484 | ||
12b2cab7 MJ |
3485 | return adev; |
3486 | } | |
3487 | ||
3488 | #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) | |
3489 | #define GET_UMC_INST(m) (((m) >> 21) & 0x7) | |
3490 | #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) | |
3491 | #define GPU_ID_OFFSET 8 | |
3492 | ||
3493 | static int amdgpu_bad_page_notifier(struct notifier_block *nb, | |
3494 | unsigned long val, void *data) | |
3495 | { | |
3496 | struct mce *m = (struct mce *)data; | |
3497 | struct amdgpu_device *adev = NULL; | |
3498 | uint32_t gpu_id = 0; | |
cd4c99f1 | 3499 | uint32_t umc_inst = 0, ch_inst = 0; |
12b2cab7 MJ |
3500 | |
3501 | /* | |
3502 | * If the error was generated in UMC_V2, which belongs to GPU UMCs, | |
3503 | * and error occurred in DramECC (Extended error code = 0) then only | |
3504 | * process the error, else bail out. | |
3505 | */ | |
91f75eb4 | 3506 | if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && |
12b2cab7 MJ |
3507 | (XEC(m->status, 0x3f) == 0x0))) |
3508 | return NOTIFY_DONE; | |
3509 | ||
3510 | /* | |
3511 | * If it is correctable error, return. | |
3512 | */ | |
3513 | if (mce_is_correctable(m)) | |
3514 | return NOTIFY_OK; | |
3515 | ||
3516 | /* | |
3517 | * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. | |
3518 | */ | |
3519 | gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; | |
3520 | ||
3521 | adev = find_adev(gpu_id); | |
3522 | if (!adev) { | |
3523 | DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, | |
3524 | gpu_id); | |
3525 | return NOTIFY_DONE; | |
3526 | } | |
3527 | ||
3528 | /* | |
3529 | * If it is uncorrectable error, then find out UMC instance and | |
3530 | * channel index. | |
3531 | */ | |
3532 | umc_inst = GET_UMC_INST(m->ipid); | |
3533 | ch_inst = GET_CHAN_INDEX(m->ipid); | |
3534 | ||
3535 | dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", | |
3536 | umc_inst, ch_inst); | |
3537 | ||
24b82292 TZ |
3538 | if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) |
3539 | return NOTIFY_OK; | |
3540 | else | |
6c0ca748 | 3541 | return NOTIFY_DONE; |
12b2cab7 MJ |
3542 | } |
3543 | ||
3544 | static struct notifier_block amdgpu_bad_page_nb = { | |
3545 | .notifier_call = amdgpu_bad_page_notifier, | |
3546 | .priority = MCE_PRIO_UC, | |
3547 | }; | |
3548 | ||
91a1a52d | 3549 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) |
12b2cab7 | 3550 | { |
91a1a52d MJ |
3551 | /* |
3552 | * Add the adev to the mce_adev_list. | |
3553 | * During mode2 reset, amdgpu device is temporarily | |
3554 | * removed from the mgpu_info list which can cause | |
3555 | * page retirement to fail. | |
3556 | * Use this list instead of mgpu_info to find the amdgpu | |
3557 | * device on which the UMC error was reported. | |
3558 | */ | |
3559 | mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; | |
3560 | ||
12b2cab7 MJ |
3561 | /* |
3562 | * Register the x86 notifier only once | |
3563 | * with MCE subsystem. | |
3564 | */ | |
3565 | if (notifier_registered == false) { | |
3566 | mce_register_decode_chain(&amdgpu_bad_page_nb); | |
3567 | notifier_registered = true; | |
3568 | } | |
3569 | } | |
3570 | #endif | |
7cab2124 | 3571 | |
b6efdb02 | 3572 | struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) |
7cab2124 | 3573 | { |
3574 | if (!adev) | |
3575 | return NULL; | |
3576 | ||
3577 | return adev->psp.ras_context.ras; | |
3578 | } | |
3579 | ||
b6efdb02 | 3580 | int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) |
7cab2124 | 3581 | { |
3582 | if (!adev) | |
69f91d32 | 3583 | return -EINVAL; |
7cab2124 | 3584 | |
3585 | adev->psp.ras_context.ras = ras_con; | |
3586 | return 0; | |
3587 | } | |
3588 | ||
3589 | /* check if ras is supported on block, say, sdma, gfx */ | |
3590 | int amdgpu_ras_is_supported(struct amdgpu_device *adev, | |
3591 | unsigned int block) | |
3592 | { | |
8f453c51 | 3593 | int ret = 0; |
7cab2124 | 3594 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
3595 | ||
3596 | if (block >= AMDGPU_RAS_BLOCK_COUNT) | |
3597 | return 0; | |
8f453c51 YC |
3598 | |
3599 | ret = ras && (adev->ras_enabled & (1 << block)); | |
3600 | ||
3601 | /* For the special asic with mem ecc enabled but sram ecc | |
3602 | * not enabled, even if the ras block is not supported on | |
3603 | * .ras_enabled, if the asic supports poison mode and the | |
3604 | * ras block has ras configuration, it can be considered | |
3605 | * that the ras block supports ras function. | |
3606 | */ | |
3607 | if (!ret && | |
bc0f8080 CL |
3608 | (block == AMDGPU_RAS_BLOCK__GFX || |
3609 | block == AMDGPU_RAS_BLOCK__SDMA || | |
3610 | block == AMDGPU_RAS_BLOCK__VCN || | |
3611 | block == AMDGPU_RAS_BLOCK__JPEG) && | |
8f453c51 YC |
3612 | amdgpu_ras_is_poison_mode_supported(adev) && |
3613 | amdgpu_ras_get_ras_block(adev, block, 0)) | |
3614 | ret = 1; | |
3615 | ||
3616 | return ret; | |
7cab2124 | 3617 | } |
3618 | ||
3619 | int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) | |
3620 | { | |
3621 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
3622 | ||
3623 | if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) | |
25a2b22e | 3624 | amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); |
7cab2124 | 3625 | return 0; |
3626 | } | |
3627 | ||
201761b5 | 3628 | int amdgpu_ras_set_mca_debug_mode(struct amdgpu_device *adev, bool enable) |
8096df76 TZ |
3629 | { |
3630 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
201761b5 | 3631 | int ret = 0; |
8096df76 | 3632 | |
201761b5 LL |
3633 | if (con) { |
3634 | ret = amdgpu_mca_smu_set_debug_mode(adev, enable); | |
3635 | if (!ret) | |
04c4fcd2 | 3636 | con->is_aca_debug_mode = enable; |
201761b5 LL |
3637 | } |
3638 | ||
3639 | return ret; | |
8096df76 TZ |
3640 | } |
3641 | ||
33dcda51 YW |
3642 | int amdgpu_ras_set_aca_debug_mode(struct amdgpu_device *adev, bool enable) |
3643 | { | |
3644 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3645 | int ret = 0; | |
3646 | ||
3647 | if (con) { | |
04c4fcd2 YW |
3648 | if (amdgpu_aca_is_enabled(adev)) |
3649 | ret = amdgpu_aca_smu_set_debug_mode(adev, enable); | |
3650 | else | |
3651 | ret = amdgpu_mca_smu_set_debug_mode(adev, enable); | |
33dcda51 | 3652 | if (!ret) |
04c4fcd2 | 3653 | con->is_aca_debug_mode = enable; |
33dcda51 YW |
3654 | } |
3655 | ||
3656 | return ret; | |
3657 | } | |
3658 | ||
04c4fcd2 | 3659 | bool amdgpu_ras_get_aca_debug_mode(struct amdgpu_device *adev) |
8096df76 TZ |
3660 | { |
3661 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
04c4fcd2 | 3662 | const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; |
8096df76 TZ |
3663 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; |
3664 | ||
3665 | if (!con) | |
3666 | return false; | |
3667 | ||
04c4fcd2 YW |
3668 | if ((amdgpu_aca_is_enabled(adev) && smu_funcs && smu_funcs->set_debug_mode) || |
3669 | (!amdgpu_aca_is_enabled(adev) && mca_funcs && mca_funcs->mca_set_debug_mode)) | |
3670 | return con->is_aca_debug_mode; | |
8096df76 TZ |
3671 | else |
3672 | return true; | |
3673 | } | |
7cab2124 | 3674 | |
8cc0f566 HZ |
3675 | bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, |
3676 | unsigned int *error_query_mode) | |
3677 | { | |
3678 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3679 | const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs; | |
04c4fcd2 | 3680 | const struct aca_smu_funcs *smu_funcs = adev->aca.smu_funcs; |
8cc0f566 HZ |
3681 | |
3682 | if (!con) { | |
3683 | *error_query_mode = AMDGPU_RAS_INVALID_ERROR_QUERY; | |
3684 | return false; | |
3685 | } | |
3686 | ||
04c4fcd2 | 3687 | if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode)) |
8cc0f566 | 3688 | *error_query_mode = |
04c4fcd2 | 3689 | (con->is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; |
8cc0f566 HZ |
3690 | else |
3691 | *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY; | |
3692 | ||
3693 | return true; | |
3694 | } | |
3695 | ||
6492e1b0 | 3696 | /* Register each ip ras block into amdgpu ras */ |
3697 | int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, | |
b6efdb02 | 3698 | struct amdgpu_ras_block_object *ras_block_obj) |
6492e1b0 | 3699 | { |
d5e8ff5f | 3700 | struct amdgpu_ras_block_list *ras_node; |
6492e1b0 | 3701 | if (!adev || !ras_block_obj) |
3702 | return -EINVAL; | |
3703 | ||
d5e8ff5f | 3704 | ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); |
3705 | if (!ras_node) | |
3706 | return -ENOMEM; | |
3707 | ||
3708 | INIT_LIST_HEAD(&ras_node->node); | |
3709 | ras_node->ras_obj = ras_block_obj; | |
3710 | list_add_tail(&ras_node->node, &adev->ras_list); | |
6492e1b0 | 3711 | |
3712 | return 0; | |
3713 | } | |
322a7e00 HZ |
3714 | |
3715 | void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name) | |
3716 | { | |
3717 | if (!err_type_name) | |
3718 | return; | |
3719 | ||
3720 | switch (err_type) { | |
3721 | case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: | |
3722 | sprintf(err_type_name, "correctable"); | |
3723 | break; | |
3724 | case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: | |
3725 | sprintf(err_type_name, "uncorrectable"); | |
3726 | break; | |
3727 | default: | |
3728 | sprintf(err_type_name, "unknown"); | |
3729 | break; | |
3730 | } | |
3731 | } | |
3732 | ||
3733 | bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, | |
3734 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3735 | uint32_t instance, | |
3736 | uint32_t *memory_id) | |
3737 | { | |
3738 | uint32_t err_status_lo_data, err_status_lo_offset; | |
3739 | ||
3740 | if (!reg_entry) | |
3741 | return false; | |
3742 | ||
3743 | err_status_lo_offset = | |
3744 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3745 | reg_entry->seg_lo, reg_entry->reg_lo); | |
3746 | err_status_lo_data = RREG32(err_status_lo_offset); | |
3747 | ||
3748 | if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && | |
3749 | !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG)) | |
3750 | return false; | |
3751 | ||
3752 | *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID); | |
3753 | ||
3754 | return true; | |
3755 | } | |
3756 | ||
3757 | bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, | |
3758 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3759 | uint32_t instance, | |
3760 | unsigned long *err_cnt) | |
3761 | { | |
3762 | uint32_t err_status_hi_data, err_status_hi_offset; | |
3763 | ||
3764 | if (!reg_entry) | |
3765 | return false; | |
3766 | ||
3767 | err_status_hi_offset = | |
3768 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3769 | reg_entry->seg_hi, reg_entry->reg_hi); | |
3770 | err_status_hi_data = RREG32(err_status_hi_offset); | |
3771 | ||
3772 | if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && | |
3773 | !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG)) | |
9b337b7d HZ |
3774 | /* keep the check here in case we need to refer to the result later */ |
3775 | dev_dbg(adev->dev, "Invalid err_info field\n"); | |
322a7e00 HZ |
3776 | |
3777 | /* read err count */ | |
3778 | *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT); | |
3779 | ||
3780 | return true; | |
3781 | } | |
3782 | ||
3783 | void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, | |
3784 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3785 | uint32_t reg_list_size, | |
3786 | const struct amdgpu_ras_memory_id_entry *mem_list, | |
3787 | uint32_t mem_list_size, | |
3788 | uint32_t instance, | |
3789 | uint32_t err_type, | |
3790 | unsigned long *err_count) | |
3791 | { | |
3792 | uint32_t memory_id; | |
3793 | unsigned long err_cnt; | |
3794 | char err_type_name[16]; | |
3795 | uint32_t i, j; | |
3796 | ||
3797 | for (i = 0; i < reg_list_size; i++) { | |
9b337b7d HZ |
3798 | /* query memory_id from err_status_lo */ |
3799 | if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i], | |
3800 | instance, &memory_id)) | |
3801 | continue; | |
3802 | ||
322a7e00 HZ |
3803 | /* query err_cnt from err_status_hi */ |
3804 | if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i], | |
3805 | instance, &err_cnt) || | |
3806 | !err_cnt) | |
3807 | continue; | |
3808 | ||
322a7e00 HZ |
3809 | *err_count += err_cnt; |
3810 | ||
3811 | /* log the errors */ | |
3812 | amdgpu_ras_get_error_type_name(err_type, err_type_name); | |
3813 | if (!mem_list) { | |
3814 | /* memory_list is not supported */ | |
3815 | dev_info(adev->dev, | |
3816 | "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n", | |
3817 | err_cnt, err_type_name, | |
3818 | reg_list[i].block_name, | |
3819 | instance, memory_id); | |
3820 | } else { | |
3821 | for (j = 0; j < mem_list_size; j++) { | |
3822 | if (memory_id == mem_list[j].memory_id) { | |
3823 | dev_info(adev->dev, | |
3824 | "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n", | |
3825 | err_cnt, err_type_name, | |
3826 | reg_list[i].block_name, | |
3827 | instance, mem_list[j].name); | |
3828 | break; | |
3829 | } | |
3830 | } | |
3831 | } | |
3832 | } | |
3833 | } | |
e53a3250 HZ |
3834 | |
3835 | void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, | |
3836 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3837 | uint32_t reg_list_size, | |
3838 | uint32_t instance) | |
3839 | { | |
3840 | uint32_t err_status_lo_offset, err_status_hi_offset; | |
3841 | uint32_t i; | |
3842 | ||
3843 | for (i = 0; i < reg_list_size; i++) { | |
3844 | err_status_lo_offset = | |
3845 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3846 | reg_list[i].seg_lo, reg_list[i].reg_lo); | |
3847 | err_status_hi_offset = | |
3848 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3849 | reg_list[i].seg_hi, reg_list[i].reg_hi); | |
3850 | WREG32(err_status_lo_offset, 0); | |
3851 | WREG32(err_status_hi_offset, 0); | |
3852 | } | |
3853 | } | |
5b1270be YW |
3854 | |
3855 | int amdgpu_ras_error_data_init(struct ras_err_data *err_data) | |
3856 | { | |
3857 | memset(err_data, 0, sizeof(*err_data)); | |
3858 | ||
3859 | INIT_LIST_HEAD(&err_data->err_node_list); | |
3860 | ||
3861 | return 0; | |
3862 | } | |
3863 | ||
3864 | static void amdgpu_ras_error_node_release(struct ras_err_node *err_node) | |
3865 | { | |
3866 | if (!err_node) | |
3867 | return; | |
3868 | ||
3869 | list_del(&err_node->node); | |
3870 | kvfree(err_node); | |
3871 | } | |
3872 | ||
3873 | void amdgpu_ras_error_data_fini(struct ras_err_data *err_data) | |
3874 | { | |
3875 | struct ras_err_node *err_node, *tmp; | |
3876 | ||
8a656611 | 3877 | list_for_each_entry_safe(err_node, tmp, &err_data->err_node_list, node) |
5b1270be | 3878 | amdgpu_ras_error_node_release(err_node); |
5b1270be YW |
3879 | } |
3880 | ||
3881 | static struct ras_err_node *amdgpu_ras_error_find_node_by_id(struct ras_err_data *err_data, | |
3882 | struct amdgpu_smuio_mcm_config_info *mcm_info) | |
3883 | { | |
3884 | struct ras_err_node *err_node; | |
3885 | struct amdgpu_smuio_mcm_config_info *ref_id; | |
3886 | ||
3887 | if (!err_data || !mcm_info) | |
3888 | return NULL; | |
3889 | ||
3890 | for_each_ras_error(err_node, err_data) { | |
3891 | ref_id = &err_node->err_info.mcm_info; | |
5b1270be | 3892 | |
53d4d779 YW |
3893 | if (mcm_info->socket_id == ref_id->socket_id && |
3894 | mcm_info->die_id == ref_id->die_id) | |
3895 | return err_node; | |
5b1270be YW |
3896 | } |
3897 | ||
3898 | return NULL; | |
3899 | } | |
3900 | ||
3901 | static struct ras_err_node *amdgpu_ras_error_node_new(void) | |
3902 | { | |
3903 | struct ras_err_node *err_node; | |
3904 | ||
3905 | err_node = kvzalloc(sizeof(*err_node), GFP_KERNEL); | |
3906 | if (!err_node) | |
3907 | return NULL; | |
3908 | ||
3909 | INIT_LIST_HEAD(&err_node->node); | |
3910 | ||
3911 | return err_node; | |
3912 | } | |
3913 | ||
dbf3850d YW |
3914 | static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) |
3915 | { | |
3916 | struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); | |
3917 | struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); | |
3918 | struct amdgpu_smuio_mcm_config_info *infoa = &nodea->err_info.mcm_info; | |
3919 | struct amdgpu_smuio_mcm_config_info *infob = &nodeb->err_info.mcm_info; | |
3920 | ||
3921 | if (unlikely(infoa->socket_id != infob->socket_id)) | |
3922 | return infoa->socket_id - infob->socket_id; | |
3923 | else | |
3924 | return infoa->die_id - infob->die_id; | |
3925 | ||
3926 | return 0; | |
3927 | } | |
3928 | ||
5b1270be | 3929 | static struct ras_err_info *amdgpu_ras_error_get_info(struct ras_err_data *err_data, |
0795b5d2 | 3930 | struct amdgpu_smuio_mcm_config_info *mcm_info) |
5b1270be YW |
3931 | { |
3932 | struct ras_err_node *err_node; | |
3933 | ||
3934 | err_node = amdgpu_ras_error_find_node_by_id(err_data, mcm_info); | |
3935 | if (err_node) | |
3936 | return &err_node->err_info; | |
3937 | ||
3938 | err_node = amdgpu_ras_error_node_new(); | |
3939 | if (!err_node) | |
3940 | return NULL; | |
3941 | ||
0795b5d2 | 3942 | INIT_LIST_HEAD(&err_node->err_info.err_addr_list); |
5b1270be | 3943 | |
0795b5d2 | 3944 | memcpy(&err_node->err_info.mcm_info, mcm_info, sizeof(*mcm_info)); |
9f91e983 | 3945 | |
5b1270be YW |
3946 | err_data->err_list_count++; |
3947 | list_add_tail(&err_node->node, &err_data->err_node_list); | |
dbf3850d | 3948 | list_sort(NULL, &err_data->err_node_list, ras_err_info_cmp); |
5b1270be YW |
3949 | |
3950 | return &err_node->err_info; | |
3951 | } | |
3952 | ||
0795b5d2 YC |
3953 | void amdgpu_ras_add_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *err_addr) |
3954 | { | |
3955 | struct ras_err_addr *mca_err_addr; | |
3956 | ||
3957 | mca_err_addr = kzalloc(sizeof(*mca_err_addr), GFP_KERNEL); | |
3958 | if (!mca_err_addr) | |
3959 | return; | |
3960 | ||
3961 | INIT_LIST_HEAD(&mca_err_addr->node); | |
3962 | ||
3963 | mca_err_addr->err_status = err_addr->err_status; | |
3964 | mca_err_addr->err_ipid = err_addr->err_ipid; | |
3965 | mca_err_addr->err_addr = err_addr->err_addr; | |
3966 | ||
3967 | list_add_tail(&mca_err_addr->node, &err_info->err_addr_list); | |
3968 | } | |
3969 | ||
3970 | void amdgpu_ras_del_mca_err_addr(struct ras_err_info *err_info, struct ras_err_addr *mca_err_addr) | |
3971 | { | |
3972 | list_del(&mca_err_addr->node); | |
3973 | kfree(mca_err_addr); | |
3974 | } | |
3975 | ||
5b1270be | 3976 | int amdgpu_ras_error_statistic_ue_count(struct ras_err_data *err_data, |
9f91e983 YC |
3977 | struct amdgpu_smuio_mcm_config_info *mcm_info, |
3978 | struct ras_err_addr *err_addr, u64 count) | |
5b1270be YW |
3979 | { |
3980 | struct ras_err_info *err_info; | |
3981 | ||
3982 | if (!err_data || !mcm_info) | |
3983 | return -EINVAL; | |
3984 | ||
3985 | if (!count) | |
3986 | return 0; | |
3987 | ||
0795b5d2 | 3988 | err_info = amdgpu_ras_error_get_info(err_data, mcm_info); |
5b1270be YW |
3989 | if (!err_info) |
3990 | return -EINVAL; | |
3991 | ||
0795b5d2 YC |
3992 | if (err_addr && err_addr->err_status) |
3993 | amdgpu_ras_add_mca_err_addr(err_info, err_addr); | |
3994 | ||
5b1270be YW |
3995 | err_info->ue_count += count; |
3996 | err_data->ue_count += count; | |
3997 | ||
3998 | return 0; | |
3999 | } | |
4000 | ||
4001 | int amdgpu_ras_error_statistic_ce_count(struct ras_err_data *err_data, | |
9f91e983 YC |
4002 | struct amdgpu_smuio_mcm_config_info *mcm_info, |
4003 | struct ras_err_addr *err_addr, u64 count) | |
5b1270be YW |
4004 | { |
4005 | struct ras_err_info *err_info; | |
4006 | ||
4007 | if (!err_data || !mcm_info) | |
4008 | return -EINVAL; | |
4009 | ||
4010 | if (!count) | |
4011 | return 0; | |
4012 | ||
0795b5d2 | 4013 | err_info = amdgpu_ras_error_get_info(err_data, mcm_info); |
5b1270be YW |
4014 | if (!err_info) |
4015 | return -EINVAL; | |
4016 | ||
4017 | err_info->ce_count += count; | |
4018 | err_data->ce_count += count; | |
4019 | ||
4020 | return 0; | |
4021 | } | |
cce4febb | 4022 | |
46e2231c CL |
4023 | int amdgpu_ras_error_statistic_de_count(struct ras_err_data *err_data, |
4024 | struct amdgpu_smuio_mcm_config_info *mcm_info, | |
4025 | struct ras_err_addr *err_addr, u64 count) | |
4026 | { | |
4027 | struct ras_err_info *err_info; | |
4028 | ||
4029 | if (!err_data || !mcm_info) | |
4030 | return -EINVAL; | |
4031 | ||
4032 | if (!count) | |
4033 | return 0; | |
4034 | ||
0795b5d2 | 4035 | err_info = amdgpu_ras_error_get_info(err_data, mcm_info); |
46e2231c CL |
4036 | if (!err_info) |
4037 | return -EINVAL; | |
4038 | ||
0795b5d2 YC |
4039 | if (err_addr && err_addr->err_status) |
4040 | amdgpu_ras_add_mca_err_addr(err_info, err_addr); | |
4041 | ||
46e2231c CL |
4042 | err_info->de_count += count; |
4043 | err_data->de_count += count; | |
4044 | ||
4045 | return 0; | |
4046 | } | |
4047 | ||
cce4febb HZ |
4048 | #define mmMP0_SMN_C2PMSG_92 0x1609C |
4049 | #define mmMP0_SMN_C2PMSG_126 0x160BE | |
4050 | static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev, | |
4051 | u32 instance, u32 boot_error) | |
4052 | { | |
4053 | u32 socket_id, aid_id, hbm_id; | |
4054 | u32 reg_data; | |
4055 | u64 reg_addr; | |
4056 | ||
4057 | socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error); | |
4058 | aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error); | |
4059 | hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error); | |
4060 | ||
4061 | /* The pattern for smn addressing in other SOC could be different from | |
4062 | * the one for aqua_vanjaram. We should revisit the code if the pattern | |
4063 | * is changed. In such case, replace the aqua_vanjaram implementation | |
4064 | * with more common helper */ | |
4065 | reg_addr = (mmMP0_SMN_C2PMSG_92 << 2) + | |
4066 | aqua_vanjaram_encode_ext_smn_addressing(instance); | |
4067 | ||
4068 | reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); | |
4069 | dev_err(adev->dev, "socket: %d, aid: %d, firmware boot failed, fw status is 0x%x\n", | |
4070 | socket_id, aid_id, reg_data); | |
4071 | ||
4072 | if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error)) | |
4073 | dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, memory training failed\n", | |
4074 | socket_id, aid_id, hbm_id); | |
4075 | ||
4076 | if (AMDGPU_RAS_GPU_ERR_FW_LOAD(boot_error)) | |
4077 | dev_info(adev->dev, "socket: %d, aid: %d, firmware load failed at boot time\n", | |
4078 | socket_id, aid_id); | |
4079 | ||
4080 | if (AMDGPU_RAS_GPU_ERR_WAFL_LINK_TRAINING(boot_error)) | |
4081 | dev_info(adev->dev, "socket: %d, aid: %d, wafl link training failed\n", | |
4082 | socket_id, aid_id); | |
4083 | ||
4084 | if (AMDGPU_RAS_GPU_ERR_XGMI_LINK_TRAINING(boot_error)) | |
4085 | dev_info(adev->dev, "socket: %d, aid: %d, xgmi link training failed\n", | |
4086 | socket_id, aid_id); | |
4087 | ||
4088 | if (AMDGPU_RAS_GPU_ERR_USR_CP_LINK_TRAINING(boot_error)) | |
4089 | dev_info(adev->dev, "socket: %d, aid: %d, usr cp link training failed\n", | |
4090 | socket_id, aid_id); | |
4091 | ||
4092 | if (AMDGPU_RAS_GPU_ERR_USR_DP_LINK_TRAINING(boot_error)) | |
4093 | dev_info(adev->dev, "socket: %d, aid: %d, usr dp link training failed\n", | |
4094 | socket_id, aid_id); | |
4095 | ||
4096 | if (AMDGPU_RAS_GPU_ERR_HBM_MEM_TEST(boot_error)) | |
4097 | dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm memory test failed\n", | |
4098 | socket_id, aid_id, hbm_id); | |
4099 | ||
4100 | if (AMDGPU_RAS_GPU_ERR_HBM_BIST_TEST(boot_error)) | |
4101 | dev_info(adev->dev, "socket: %d, aid: %d, hbm: %d, hbm bist test failed\n", | |
4102 | socket_id, aid_id, hbm_id); | |
4103 | } | |
4104 | ||
4105 | static int amdgpu_ras_wait_for_boot_complete(struct amdgpu_device *adev, | |
4106 | u32 instance, u32 *boot_error) | |
4107 | { | |
4108 | u32 reg_addr; | |
4109 | u32 reg_data; | |
4110 | int retry_loop; | |
4111 | ||
4112 | /* The pattern for smn addressing in other SOC could be different from | |
4113 | * the one for aqua_vanjaram. We should revisit the code if the pattern | |
4114 | * is changed. In such case, replace the aqua_vanjaram implementation | |
4115 | * with more common helper */ | |
4116 | reg_addr = (mmMP0_SMN_C2PMSG_126 << 2) + | |
4117 | aqua_vanjaram_encode_ext_smn_addressing(instance); | |
4118 | ||
4119 | for (retry_loop = 0; retry_loop < 1000; retry_loop++) { | |
4120 | reg_data = amdgpu_device_indirect_rreg_ext(adev, reg_addr); | |
4121 | if (AMDGPU_RAS_GPU_ERR_BOOT_STATUS(reg_data)) { | |
4122 | *boot_error = reg_data; | |
4123 | return 0; | |
4124 | } | |
4125 | msleep(1); | |
4126 | } | |
4127 | ||
4128 | *boot_error = reg_data; | |
4129 | return -ETIME; | |
4130 | } | |
4131 | ||
4132 | void amdgpu_ras_query_boot_status(struct amdgpu_device *adev, u32 num_instances) | |
4133 | { | |
4134 | u32 boot_error = 0; | |
4135 | u32 i; | |
4136 | ||
4137 | for (i = 0; i < num_instances; i++) { | |
4138 | if (amdgpu_ras_wait_for_boot_complete(adev, i, &boot_error)) | |
4139 | amdgpu_ras_boot_time_error_reporting(adev, i, boot_error); | |
4140 | } | |
4141 | } |