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drm/amdgpu: pass xcc mask to ras ta
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c
CommitLineData
c030f2e4 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
f867723b 27#include <linux/uaccess.h>
7c6e68c7
AG		 28#include <linux/reboot.h>
29#include <linux/syscalls.h>
05adfd80 30#include <linux/pm_runtime.h>
f867723b 31
c030f2e4 32#include "amdgpu.h"
33#include "amdgpu_ras.h"
b404ae82 34#include "amdgpu_atomfirmware.h"
19744f5f 35#include "amdgpu_xgmi.h"
4e644fff 36#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
9af357bc 37#include "nbio_v4_3.h"
f50160cf 38#include "atom.h"
25a2b22e
AG		 39#include "amdgpu_reset.h"
40
12b2cab7
MJ		 41#ifdef CONFIG_X86_MCE_AMD
42#include <asm/mce.h>
c030f2e4 43
12b2cab7
MJ		 44static bool notifier_registered;
45#endif
eb0c3cd4
GC		 46static const char *RAS_FS_NAME = "ras";
47
c030f2e4 48const char *ras_error_string[] = {
49 "none",
50 "parity",
51 "single_correctable",
52 "multi_uncorrectable",
53 "poison",
54};
55
56const char *ras_block_string[] = {
57 "umc",
58 "sdma",
59 "gfx",
60 "mmhub",
61 "athub",
62 "pcie_bif",
63 "hdp",
64 "xgmi_wafl",
65 "df",
66 "smn",
67 "sem",
68 "mp0",
69 "mp1",
70 "fuse",
640ae42e 71 "mca",
a3d63c62
MZZ		 72 "vcn",
73 "jpeg",
c030f2e4 74};
75
640ae42e
JC		 76const char *ras_mca_block_string[] = {
77 "mca_mp0",
78 "mca_mp1",
79 "mca_mpio",
80 "mca_iohc",
81};
82
d5e8ff5f 83struct amdgpu_ras_block_list {
84 /* ras block link */
85 struct list_head node;
86
87 struct amdgpu_ras_block_object *ras_obj;
88};
89
640ae42e
JC		 90const char *get_ras_block_str(struct ras_common_if *ras_block)
91{
92 if (!ras_block)
93 return "NULL";
94
95 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
96 return "OUT OF RANGE";
97
98 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
99 return ras_mca_block_string[ras_block->sub_block_index];
100
101 return ras_block_string[ras_block->block];
102}
103
954ea6aa 104#define ras_block_str(_BLOCK_) \
105 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
8b0fb0e9 106
c030f2e4 107#define ras_err_str(i) (ras_error_string[ffs(i)])
c030f2e4 108
108c6a63 109#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
110
7cdc2ee3
TZ		 111/* inject address is 52 bits */
112#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
113
e4e6a589
LT		 114/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
115#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
c84d4670 116
52dd95f2
GC		 117enum amdgpu_ras_retire_page_reservation {
118 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
119 AMDGPU_RAS_RETIRE_PAGE_PENDING,
120 AMDGPU_RAS_RETIRE_PAGE_FAULT,
121};
7c6e68c7
AG		 122
123atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
124
676deb38
DL		 125static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
126 uint64_t addr);
6e4be987
TZ		 127static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
128 uint64_t addr);
12b2cab7 129#ifdef CONFIG_X86_MCE_AMD
91a1a52d
MJ		 130static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
131struct mce_notifier_adev_list {
132 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
133 int num_gpu;
134};
135static struct mce_notifier_adev_list mce_adev_list;
12b2cab7 136#endif
6e4be987 137
61380faa
JC		 138void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
139{
a9d82d2f 140 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 141 amdgpu_ras_get_context(adev)->error_query_ready = ready;
142}
143
f3167919 144static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
61380faa 145{
a9d82d2f 146 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 147 return amdgpu_ras_get_context(adev)->error_query_ready;
148
149 return false;
150}
151
cbb8f989
JC		 152static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
153{
154 struct ras_err_data err_data = {0, 0, 0, NULL};
155 struct eeprom_table_record err_rec;
156
157 if ((address >= adev->gmc.mc_vram_size) ||
158 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
159 dev_warn(adev->dev,
160 "RAS WARN: input address 0x%llx is invalid.\n",
161 address);
162 return -EINVAL;
163 }
164
165 if (amdgpu_ras_check_bad_page(adev, address)) {
166 dev_warn(adev->dev,
80b0cd0f 167 "RAS WARN: 0x%llx has already been marked as bad page!\n",
cbb8f989
JC		 168 address);
169 return 0;
170 }
171
172 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
cbb8f989 173 err_data.err_addr = &err_rec;
400013b2
TZ		 174 amdgpu_umc_fill_error_record(&err_data, address,
175 (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
cbb8f989
JC		 176
177 if (amdgpu_bad_page_threshold != 0) {
178 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
179 err_data.err_addr_cnt);
4d33e0f1 180 amdgpu_ras_save_bad_pages(adev, NULL);
cbb8f989
JC		 181 }
182
183 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
184 dev_warn(adev->dev, "Clear EEPROM:\n");
185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
186
187 return 0;
188}
189
c030f2e4 190static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
191 size_t size, loff_t *pos)
192{
193 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
194 struct ras_query_if info = {
195 .head = obj->head,
196 };
197 ssize_t s;
198 char val[128];
199
761d86d3 200 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 201 return -EINVAL;
202
2a460963
CL		 203 /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
204 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
205 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
206 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
207 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
208 }
209
c030f2e4 210 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
211 "ue", info.ue_count,
212 "ce", info.ce_count);
213 if (*pos >= s)
214 return 0;
215
216 s -= *pos;
217 s = min_t(u64, s, size);
218
219
220 if (copy_to_user(buf, &val[*pos], s))
221 return -EINVAL;
222
223 *pos += s;
224
225 return s;
226}
227
c030f2e4 228static const struct file_operations amdgpu_ras_debugfs_ops = {
229 .owner = THIS_MODULE,
230 .read = amdgpu_ras_debugfs_read,
190211ab 231 .write = NULL,
c030f2e4 232 .llseek = default_llseek
233};
234
96ebb307 235static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
236{
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
240 *block_id = i;
640ae42e 241 if (strcmp(name, ras_block_string[i]) == 0)
96ebb307 242 return 0;
243 }
244 return -EINVAL;
245}
246
247static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
248 const char __user *buf, size_t size,
249 loff_t *pos, struct ras_debug_if *data)
250{
251 ssize_t s = min_t(u64, 64, size);
252 char str[65];
253 char block_name[33];
254 char err[9] = "ue";
255 int op = -1;
256 int block_id;
44494f96 257 uint32_t sub_block;
96ebb307 258 u64 address, value;
2c22ed0b
TZ		 259 /* default value is 0 if the mask is not set by user */
260 u32 instance_mask = 0;
96ebb307 261
262 if (*pos)
263 return -EINVAL;
264 *pos = size;
265
266 memset(str, 0, sizeof(str));
267 memset(data, 0, sizeof(*data));
268
269 if (copy_from_user(str, buf, s))
270 return -EINVAL;
271
272 if (sscanf(str, "disable %32s", block_name) == 1)
273 op = 0;
274 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
275 op = 1;
276 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
277 op = 2;
6df23f4c 278 else if (strstr(str, "retire_page") != NULL)
cbb8f989 279 op = 3;
b076296b 280 else if (str[0] && str[1] && str[2] && str[3])
96ebb307 281 /* ascii string, but commands are not matched. */
282 return -EINVAL;
283
284 if (op != -1) {
cbb8f989 285 if (op == 3) {
546aa546
LT		 286 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
287 sscanf(str, "%*s %llu", &address) != 1)
6cb7a1d4 288 return -EINVAL;
cbb8f989
JC		 289
290 data->op = op;
291 data->inject.address = address;
292
293 return 0;
294 }
295
96ebb307 296 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
297 return -EINVAL;
298
299 data->head.block = block_id;
e1063493
TZ		 300 /* only ue and ce errors are supported */
301 if (!memcmp("ue", err, 2))
302 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
303 else if (!memcmp("ce", err, 2))
304 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
305 else
306 return -EINVAL;
307
96ebb307 308 data->op = op;
309
310 if (op == 2) {
2c22ed0b
TZ		 311 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x",
312 &sub_block, &address, &value, &instance_mask) != 4 &&
313 sscanf(str, "%*s %*s %*s %u %llu %llu %u",
314 &sub_block, &address, &value, &instance_mask) != 4 &&
315 sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
546aa546
LT		 316 &sub_block, &address, &value) != 3 &&
317 sscanf(str, "%*s %*s %*s %u %llu %llu",
6cb7a1d4
LT		 318 &sub_block, &address, &value) != 3)
319 return -EINVAL;
44494f96 320 data->head.sub_block_index = sub_block;
96ebb307 321 data->inject.address = address;
322 data->inject.value = value;
2c22ed0b 323 data->inject.instance_mask = instance_mask;
96ebb307 324 }
325 } else {
73aa8e1a 326 if (size < sizeof(*data))
96ebb307 327 return -EINVAL;
328
329 if (copy_from_user(data, buf, sizeof(*data)))
330 return -EINVAL;
331 }
332
333 return 0;
334}
7c6e68c7 335
f464c5dd
TZ		 336static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev,
337 struct ras_debug_if *data)
338{
339 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
340 uint32_t mask, inst_mask = data->inject.instance_mask;
341
342 /* no need to set instance mask if there is only one instance */
343 if (num_xcc <= 1 && inst_mask) {
344 data->inject.instance_mask = 0;
345 dev_dbg(adev->dev,
346 "RAS inject mask(0x%x) isn't supported and force it to 0.\n",
347 inst_mask);
348
349 return;
350 }
351
352 switch (data->head.block) {
353 case AMDGPU_RAS_BLOCK__GFX:
354 mask = GENMASK(num_xcc - 1, 0);
355 break;
356 case AMDGPU_RAS_BLOCK__SDMA:
357 mask = GENMASK(adev->sdma.num_instances - 1, 0);
358 break;
359 default:
360 mask = 0;
361 break;
362 }
363
364 /* remove invalid bits in instance mask */
365 data->inject.instance_mask &= mask;
366 if (inst_mask != data->inject.instance_mask)
367 dev_dbg(adev->dev,
368 "Adjust RAS inject mask 0x%x to 0x%x\n",
369 inst_mask, data->inject.instance_mask);
370}
371
74abc221
TSD		 372/**
373 * DOC: AMDGPU RAS debugfs control interface
36ea1bd2 374 *
737c375b 375 * The control interface accepts struct ras_debug_if which has two members.
36ea1bd2 376 *
377 * First member: ras_debug_if::head or ras_debug_if::inject.
96ebb307 378 *
379 * head is used to indicate which IP block will be under control.
36ea1bd2 380 *
381 * head has four members, they are block, type, sub_block_index, name.
382 * block: which IP will be under control.
383 * type: what kind of error will be enabled/disabled/injected.
384 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
385 * name: the name of IP.
386 *
2c22ed0b 387 * inject has three more members than head, they are address, value and mask.
36ea1bd2 388 * As their names indicate, inject operation will write the
389 * value to the address.
390 *
ef177d11 391 * The second member: struct ras_debug_if::op.
c688a06b 392 * It has three kinds of operations.
879e723d
AZ		 393 *
394 * - 0: disable RAS on the block. Take ::head as its data.
395 * - 1: enable RAS on the block. Take ::head as its data.
396 * - 2: inject errors on the block. Take ::inject as its data.
36ea1bd2 397 *
96ebb307 398 * How to use the interface?
ef177d11 399 *
737c375b 400 * In a program
ef177d11 401 *
737c375b
LT		 402 * Copy the struct ras_debug_if in your code and initialize it.
403 * Write the struct to the control interface.
ef177d11 404 *
737c375b 405 * From shell
96ebb307 406 *
879e723d
AZ		 407 * .. code-block:: bash
408 *
737c375b
LT		 409 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
410 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
2c22ed0b 411 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
879e723d 412 *
737c375b 413 * Where N, is the card which you want to affect.
ef177d11 414 *
737c375b
LT		 415 * "disable" requires only the block.
416 * "enable" requires the block and error type.
417 * "inject" requires the block, error type, address, and value.
c666bbf0 418 *
737c375b 419 * The block is one of: umc, sdma, gfx, etc.
879e723d 420 * see ras_block_string[] for details
c666bbf0 421 *
737c375b
LT		 422 * The error type is one of: ue, ce, where,
423 * ue is multi-uncorrectable
424 * ce is single-correctable
c666bbf0 425 *
737c375b
LT		 426 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
427 * The address and value are hexadecimal numbers, leading 0x is optional.
2c22ed0b 428 * The mask means instance mask, is optional, default value is 0x1.
879e723d 429 *
737c375b 430 * For instance,
879e723d
AZ		 431 *
432 * .. code-block:: bash
96ebb307 433 *
44494f96 434 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
2c22ed0b 435 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
96ebb307 436 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
437 *
737c375b 438 * How to check the result of the operation?
36ea1bd2 439 *
737c375b 440 * To check disable/enable, see "ras" features at,
36ea1bd2 441 * /sys/class/drm/card[0/1/2...]/device/ras/features
442 *
737c375b
LT		 443 * To check inject, see the corresponding error count at,
444 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
36ea1bd2 445 *
879e723d 446 * .. note::
ef177d11 447 * Operations are only allowed on blocks which are supported.
737c375b 448 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
ef177d11
AD		 449 * to see which blocks support RAS on a particular asic.
450 *
36ea1bd2 451 */
cf696091
LT		 452static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
453 const char __user *buf,
454 size_t size, loff_t *pos)
36ea1bd2 455{
456 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
457 struct ras_debug_if data;
458 int ret = 0;
459
61380faa 460 if (!amdgpu_ras_get_error_query_ready(adev)) {
6952e99c
GC		 461 dev_warn(adev->dev, "RAS WARN: error injection "
462 "currently inaccessible\n");
43c4d576
JC		 463 return size;
464 }
465
96ebb307 466 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
467 if (ret)
cf696091 468 return ret;
36ea1bd2 469
80b0cd0f 470 if (data.op == 3) {
cbb8f989 471 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
80b0cd0f 472 if (!ret)
cbb8f989
JC		 473 return size;
474 else
475 return ret;
476 }
477
36ea1bd2 478 if (!amdgpu_ras_is_supported(adev, data.head.block))
479 return -EINVAL;
480
481 switch (data.op) {
482 case 0:
483 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
484 break;
485 case 1:
486 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
487 break;
488 case 2:
7cdc2ee3
TZ		 489 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
490 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
b0d4783a
GC		 491 dev_warn(adev->dev, "RAS WARN: input address "
492 "0x%llx is invalid.",
493 data.inject.address);
7cdc2ee3
TZ		 494 ret = -EINVAL;
495 break;
496 }
497
6e4be987
TZ		 498 /* umc ce/ue error injection for a bad page is not allowed */
499 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
500 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
c65b0805
LT		 501 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
502 "already been marked as bad!\n",
503 data.inject.address);
6e4be987
TZ		 504 break;
505 }
506
f464c5dd
TZ		 507 amdgpu_ras_instance_mask_check(adev, &data);
508
7cdc2ee3 509 /* data.inject.address is offset instead of absolute gpu address */
36ea1bd2 510 ret = amdgpu_ras_error_inject(adev, &data.inject);
511 break;
96ebb307 512 default:
513 ret = -EINVAL;
514 break;
374bf7bd 515 }
36ea1bd2 516
517 if (ret)
79c04621 518 return ret;
36ea1bd2 519
520 return size;
521}
522
084fe13b
AG		 523/**
524 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
525 *
f77c7109 526 * Some boards contain an EEPROM which is used to persistently store a list of
ef177d11 527 * bad pages which experiences ECC errors in vram. This interface provides
f77c7109
AD		 528 * a way to reset the EEPROM, e.g., after testing error injection.
529 *
530 * Usage:
531 *
532 * .. code-block:: bash
533 *
534 * echo 1 > ../ras/ras_eeprom_reset
535 *
536 * will reset EEPROM table to 0 entries.
537 *
084fe13b 538 */
cf696091
LT		 539static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
540 const char __user *buf,
541 size_t size, loff_t *pos)
084fe13b 542{
bf0b91b7
GC		 543 struct amdgpu_device *adev =
544 (struct amdgpu_device *)file_inode(f)->i_private;
084fe13b
AG		 545 int ret;
546
bf0b91b7 547 ret = amdgpu_ras_eeprom_reset_table(
cf696091 548 &(amdgpu_ras_get_context(adev)->eeprom_control));
084fe13b 549
63d4c081 550 if (!ret) {
cf696091
LT		 551 /* Something was written to EEPROM.
552 */
bf0b91b7
GC		 553 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
554 return size;
555 } else {
cf696091 556 return ret;
bf0b91b7 557 }
084fe13b
AG		 558}
559
36ea1bd2 560static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
561 .owner = THIS_MODULE,
562 .read = NULL,
563 .write = amdgpu_ras_debugfs_ctrl_write,
564 .llseek = default_llseek
565};
566
084fe13b
AG		 567static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
568 .owner = THIS_MODULE,
569 .read = NULL,
570 .write = amdgpu_ras_debugfs_eeprom_write,
571 .llseek = default_llseek
572};
573
f77c7109
AD		 574/**
575 * DOC: AMDGPU RAS sysfs Error Count Interface
576 *
ef177d11 577 * It allows the user to read the error count for each IP block on the gpu through
f77c7109
AD		 578 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
579 *
580 * It outputs the multiple lines which report the uncorrected (ue) and corrected
581 * (ce) error counts.
582 *
583 * The format of one line is below,
584 *
585 * [ce|ue]: count
586 *
587 * Example:
588 *
589 * .. code-block:: bash
590 *
591 * ue: 0
592 * ce: 1
593 *
594 */
c030f2e4 595static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
596 struct device_attribute *attr, char *buf)
597{
598 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
599 struct ras_query_if info = {
600 .head = obj->head,
601 };
602
61380faa 603 if (!amdgpu_ras_get_error_query_ready(obj->adev))
36000c7a 604 return sysfs_emit(buf, "Query currently inaccessible\n");
43c4d576 605
761d86d3 606 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 607 return -EINVAL;
608
2a460963
CL		 609 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
610 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1f0d8e37 611 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
2a460963 612 dev_warn(obj->adev->dev, "Failed to reset error counter and error status");
1f0d8e37
MJ		 613 }
614
36000c7a
TT		 615 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
616 "ce", info.ce_count);
c030f2e4 617}
618
619/* obj begin */
620
621#define get_obj(obj) do { (obj)->use++; } while (0)
622#define alive_obj(obj) ((obj)->use)
623
624static inline void put_obj(struct ras_manager *obj)
625{
f0872686 626 if (obj && (--obj->use == 0))
c030f2e4 627 list_del(&obj->node);
f0872686 628 if (obj && (obj->use < 0))
640ae42e 629 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
c030f2e4 630}
631
632/* make one obj and return it. */
633static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
634 struct ras_common_if *head)
635{
636 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
637 struct ras_manager *obj;
638
8ab0d6f0 639 if (!adev->ras_enabled || !con)
c030f2e4 640 return NULL;
641
642 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
643 return NULL;
644
640ae42e
JC		 645 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
646 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
647 return NULL;
648
649 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
650 } else
651 obj = &con->objs[head->block];
652
c030f2e4 653 /* already exist. return obj? */
654 if (alive_obj(obj))
655 return NULL;
656
657 obj->head = *head;
658 obj->adev = adev;
659 list_add(&obj->node, &con->head);
660 get_obj(obj);
661
662 return obj;
663}
664
665/* return an obj equal to head, or the first when head is NULL */
f2a79be1 666struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
c030f2e4 667 struct ras_common_if *head)
668{
669 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
670 struct ras_manager *obj;
671 int i;
672
8ab0d6f0 673 if (!adev->ras_enabled || !con)
c030f2e4 674 return NULL;
675
676 if (head) {
677 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
678 return NULL;
679
640ae42e
JC		 680 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
681 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
682 return NULL;
683
684 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
685 } else
686 obj = &con->objs[head->block];
c030f2e4 687
640ae42e 688 if (alive_obj(obj))
c030f2e4 689 return obj;
c030f2e4 690 } else {
640ae42e 691 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
c030f2e4 692 obj = &con->objs[i];
640ae42e 693 if (alive_obj(obj))
c030f2e4 694 return obj;
c030f2e4 695 }
696 }
697
698 return NULL;
699}
700/* obj end */
701
702/* feature ctl begin */
703static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
e509965e 704 struct ras_common_if *head)
c030f2e4 705{
8ab0d6f0 706 return adev->ras_hw_enabled & BIT(head->block);
c030f2e4 707}
708
709static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
710 struct ras_common_if *head)
711{
712 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
713
714 return con->features & BIT(head->block);
715}
716
717/*
718 * if obj is not created, then create one.
719 * set feature enable flag.
720 */
721static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
722 struct ras_common_if *head, int enable)
723{
724 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
725 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
726
5caf466a 727 /* If hardware does not support ras, then do not create obj.
728 * But if hardware support ras, we can create the obj.
729 * Ras framework checks con->hw_supported to see if it need do
730 * corresponding initialization.
731 * IP checks con->support to see if it need disable ras.
732 */
c030f2e4 733 if (!amdgpu_ras_is_feature_allowed(adev, head))
734 return 0;
c030f2e4 735
736 if (enable) {
737 if (!obj) {
738 obj = amdgpu_ras_create_obj(adev, head);
739 if (!obj)
740 return -EINVAL;
741 } else {
742 /* In case we create obj somewhere else */
743 get_obj(obj);
744 }
745 con->features |= BIT(head->block);
746 } else {
747 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
19d0dfda 748 con->features &= ~BIT(head->block);
c030f2e4 749 put_obj(obj);
750 }
751 }
752
753 return 0;
754}
755
c26cd999
SY		 756static int amdgpu_ras_check_feature_allowed(struct amdgpu_device *adev,
757 struct ras_common_if *head)
758{
759 if (amdgpu_ras_is_feature_allowed(adev, head) ||
760 amdgpu_ras_is_poison_mode_supported(adev))
761 return 1;
762 else
763 return 0;
764}
765
c030f2e4 766/* wrapper of psp_ras_enable_features */
767int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
768 struct ras_common_if *head, bool enable)
769{
770 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
7fcffecf 771 union ta_ras_cmd_input *info;
c26cd999 772 int ret = 0;
c030f2e4 773
774 if (!con)
775 return -EINVAL;
776
26093ce1
SY		 777 if (head->block == AMDGPU_RAS_BLOCK__GFX) {
778 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
779 if (!info)
780 return -ENOMEM;
781
782 if (!enable) {
783 info->disable_features = (struct ta_ras_disable_features_input) {
784 .block_id = amdgpu_ras_block_to_ta(head->block),
785 .error_type = amdgpu_ras_error_to_ta(head->type),
786 };
787 } else {
788 info->enable_features = (struct ta_ras_enable_features_input) {
789 .block_id = amdgpu_ras_block_to_ta(head->block),
790 .error_type = amdgpu_ras_error_to_ta(head->type),
791 };
792 }
c030f2e4 793 }
794
795 /* Do not enable if it is not allowed. */
c26cd999
SY		 796 if (enable && !amdgpu_ras_check_feature_allowed(adev, head))
797 goto out;
c030f2e4 798
950d6425 799 /* Only enable ras feature operation handle on host side */
26093ce1
SY		 800 if (head->block == AMDGPU_RAS_BLOCK__GFX &&
801 !amdgpu_sriov_vf(adev) &&
950d6425 802 !amdgpu_ras_intr_triggered()) {
7fcffecf 803 ret = psp_ras_enable_features(&adev->psp, info, enable);
bff77e86 804 if (ret) {
e4348849 805 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
011907fd 806 enable ? "enable":"disable",
640ae42e 807 get_ras_block_str(head),
e4348849 808 amdgpu_ras_is_poison_mode_supported(adev), ret);
7fcffecf 809 goto out;
bff77e86 810 }
c030f2e4 811 }
812
813 /* setup the obj */
814 __amdgpu_ras_feature_enable(adev, head, enable);
7fcffecf 815out:
26093ce1
SY		 816 if (head->block == AMDGPU_RAS_BLOCK__GFX)
817 kfree(info);
7fcffecf 818 return ret;
c030f2e4 819}
820
77de502b 821/* Only used in device probe stage and called only once. */
822int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
823 struct ras_common_if *head, bool enable)
824{
825 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
826 int ret;
827
828 if (!con)
829 return -EINVAL;
830
831 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
7af23ebe 832 if (enable) {
833 /* There is no harm to issue a ras TA cmd regardless of
834 * the currecnt ras state.
835 * If current state == target state, it will do nothing
836 * But sometimes it requests driver to reset and repost
837 * with error code -EAGAIN.
838 */
839 ret = amdgpu_ras_feature_enable(adev, head, 1);
840 /* With old ras TA, we might fail to enable ras.
841 * Log it and just setup the object.
842 * TODO need remove this WA in the future.
843 */
844 if (ret == -EINVAL) {
845 ret = __amdgpu_ras_feature_enable(adev, head, 1);
846 if (!ret)
6952e99c
GC		 847 dev_info(adev->dev,
848 "RAS INFO: %s setup object\n",
640ae42e 849 get_ras_block_str(head));
7af23ebe 850 }
851 } else {
852 /* setup the object then issue a ras TA disable cmd.*/
853 ret = __amdgpu_ras_feature_enable(adev, head, 1);
854 if (ret)
855 return ret;
77de502b 856
970fd197
SY		 857 /* gfx block ras dsiable cmd must send to ras-ta */
858 if (head->block == AMDGPU_RAS_BLOCK__GFX)
859 con->features |= BIT(head->block);
860
77de502b 861 ret = amdgpu_ras_feature_enable(adev, head, 0);
19d0dfda
SY		 862
863 /* clean gfx block ras features flag */
8ab0d6f0 864 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
19d0dfda 865 con->features &= ~BIT(head->block);
7af23ebe 866 }
77de502b 867 } else
868 ret = amdgpu_ras_feature_enable(adev, head, enable);
869
870 return ret;
871}
872
c030f2e4 873static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
874 bool bypass)
875{
876 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
877 struct ras_manager *obj, *tmp;
878
879 list_for_each_entry_safe(obj, tmp, &con->head, node) {
880 /* bypass psp.
881 * aka just release the obj and corresponding flags
882 */
883 if (bypass) {
884 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
885 break;
886 } else {
887 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
888 break;
889 }
289d513b 890 }
c030f2e4 891
892 return con->features;
893}
894
895static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
896 bool bypass)
897{
898 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c030f2e4 899 int i;
640ae42e 900 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
c030f2e4 901
640ae42e 902 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
c030f2e4 903 struct ras_common_if head = {
904 .block = i,
191051a1 905 .type = default_ras_type,
c030f2e4 906 .sub_block_index = 0,
907 };
640ae42e
JC		 908
909 if (i == AMDGPU_RAS_BLOCK__MCA)
910 continue;
911
912 if (bypass) {
913 /*
914 * bypass psp. vbios enable ras for us.
915 * so just create the obj
916 */
917 if (__amdgpu_ras_feature_enable(adev, &head, 1))
918 break;
919 } else {
920 if (amdgpu_ras_feature_enable(adev, &head, 1))
921 break;
922 }
923 }
924
925 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
926 struct ras_common_if head = {
927 .block = AMDGPU_RAS_BLOCK__MCA,
928 .type = default_ras_type,
929 .sub_block_index = i,
930 };
931
c030f2e4 932 if (bypass) {
933 /*
934 * bypass psp. vbios enable ras for us.
935 * so just create the obj
936 */
937 if (__amdgpu_ras_feature_enable(adev, &head, 1))
938 break;
939 } else {
940 if (amdgpu_ras_feature_enable(adev, &head, 1))
941 break;
942 }
289d513b 943 }
c030f2e4 944
945 return con->features;
946}
947/* feature ctl end */
948
e3d833f4 949static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
950 enum amdgpu_ras_block block)
6492e1b0 951{
b6efdb02 952 if (!block_obj)
6492e1b0 953 return -EINVAL;
954
bdb3489c 955 if (block_obj->ras_comm.block == block)
6492e1b0 956 return 0;
640ae42e 957
6492e1b0 958 return -EINVAL;
959}
960
b6efdb02 961static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
6492e1b0 962 enum amdgpu_ras_block block, uint32_t sub_block_index)
640ae42e 963{
d5e8ff5f 964 struct amdgpu_ras_block_list *node, *tmp;
965 struct amdgpu_ras_block_object *obj;
6492e1b0 966
967 if (block >= AMDGPU_RAS_BLOCK__LAST)
968 return NULL;
969
d5e8ff5f 970 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
971 if (!node->ras_obj) {
972 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
973 continue;
974 }
975
976 obj = node->ras_obj;
6492e1b0 977 if (obj->ras_block_match) {
978 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
979 return obj;
980 } else {
981 if (amdgpu_ras_block_match_default(obj, block) == 0)
982 return obj;
983 }
640ae42e 984 }
6492e1b0 985
986 return NULL;
640ae42e
JC		 987}
988
fdcb279d
SY		 989static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
990{
991 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
992 int ret = 0;
993
994 /*
995 * choosing right query method according to
996 * whether smu support query error information
997 */
bc143d8b 998 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
fdcb279d 999 if (ret == -EOPNOTSUPP) {
efe17d5a 1000 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1001 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
1002 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
fdcb279d
SY		 1003
1004 /* umc query_ras_error_address is also responsible for clearing
1005 * error status
1006 */
efe17d5a 1007 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
1008 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
1009 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
fdcb279d 1010 } else if (!ret) {
efe17d5a 1011 if (adev->umc.ras &&
1012 adev->umc.ras->ecc_info_query_ras_error_count)
1013 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
fdcb279d 1014
efe17d5a 1015 if (adev->umc.ras &&
1016 adev->umc.ras->ecc_info_query_ras_error_address)
1017 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
fdcb279d
SY		 1018 }
1019}
1020
c030f2e4 1021/* query/inject/cure begin */
761d86d3 1022int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
4d9f771e 1023 struct ras_query_if *info)
c030f2e4 1024{
b6efdb02 1025 struct amdgpu_ras_block_object *block_obj = NULL;
c030f2e4 1026 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
6f102dba 1027 struct ras_err_data err_data = {0, 0, 0, NULL};
c030f2e4 1028
1029 if (!obj)
1030 return -EINVAL;
c030f2e4 1031
7389a5b8 1032 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
fdcb279d 1033 amdgpu_ras_get_ecc_info(adev, &err_data);
7389a5b8 1034 } else {
1035 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
8b0fb0e9 1036 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1037 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1038 get_ras_block_str(&info->head));
8b0fb0e9 1039 return -EINVAL;
3e81ee9a 1040 }
761d86d3 1041
6c245386 1042 if (block_obj->hw_ops->query_ras_error_count)
1043 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
7389a5b8 1044
1045 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
1046 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
1047 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
1048 if (block_obj->hw_ops->query_ras_error_status)
1049 block_obj->hw_ops->query_ras_error_status(adev);
1050 }
939e2258 1051 }
05a58345
TZ		 1052
1053 obj->err_data.ue_count += err_data.ue_count;
1054 obj->err_data.ce_count += err_data.ce_count;
1055
c030f2e4 1056 info->ue_count = obj->err_data.ue_count;
1057 info->ce_count = obj->err_data.ce_count;
1058
7c6e68c7 1059 if (err_data.ce_count) {
a30f1286
HZ		 1060 if (adev->smuio.funcs &&
1061 adev->smuio.funcs->get_socket_id &&
1062 adev->smuio.funcs->get_die_id) {
1063 dev_info(adev->dev, "socket: %d, die: %d "
1064 "%ld correctable hardware errors "
6952e99c
GC		 1065 "detected in %s block, no user "
1066 "action is needed.\n",
a30f1286
HZ		 1067 adev->smuio.funcs->get_socket_id(adev),
1068 adev->smuio.funcs->get_die_id(adev),
6952e99c 1069 obj->err_data.ce_count,
640ae42e 1070 get_ras_block_str(&info->head));
a30f1286
HZ		 1071 } else {
1072 dev_info(adev->dev, "%ld correctable hardware errors "
6952e99c
GC		 1073 "detected in %s block, no user "
1074 "action is needed.\n",
1075 obj->err_data.ce_count,
640ae42e 1076 get_ras_block_str(&info->head));
a30f1286 1077 }
7c6e68c7
AG		 1078 }
1079 if (err_data.ue_count) {
a30f1286
HZ		 1080 if (adev->smuio.funcs &&
1081 adev->smuio.funcs->get_socket_id &&
1082 adev->smuio.funcs->get_die_id) {
1083 dev_info(adev->dev, "socket: %d, die: %d "
1084 "%ld uncorrectable hardware errors "
6952e99c 1085 "detected in %s block\n",
a30f1286
HZ		 1086 adev->smuio.funcs->get_socket_id(adev),
1087 adev->smuio.funcs->get_die_id(adev),
6952e99c 1088 obj->err_data.ue_count,
640ae42e 1089 get_ras_block_str(&info->head));
a30f1286
HZ		 1090 } else {
1091 dev_info(adev->dev, "%ld uncorrectable hardware errors "
6952e99c
GC		 1092 "detected in %s block\n",
1093 obj->err_data.ue_count,
640ae42e 1094 get_ras_block_str(&info->head));
a30f1286 1095 }
7c6e68c7 1096 }
05a58345 1097
c030f2e4 1098 return 0;
1099}
1100
761d86d3
DL		 1101int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1102 enum amdgpu_ras_block block)
1103{
b6efdb02 1104 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
8b0fb0e9 1105
761d86d3
DL		 1106 if (!amdgpu_ras_is_supported(adev, block))
1107 return -EINVAL;
1108
7389a5b8 1109 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1110 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1111 ras_block_str(block));
7389a5b8 1112 return -EINVAL;
761d86d3
DL		 1113 }
1114
7389a5b8 1115 if (block_obj->hw_ops->reset_ras_error_count)
1116 block_obj->hw_ops->reset_ras_error_count(adev);
5c23e9e0 1117
7389a5b8 1118 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1119 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
8b0fb0e9 1120 if (block_obj->hw_ops->reset_ras_error_status)
1121 block_obj->hw_ops->reset_ras_error_status(adev);
761d86d3 1122 }
5c23e9e0 1123
761d86d3 1124 return 0;
5c23e9e0
JC		 1125}
1126
c030f2e4 1127/* wrapper of psp_ras_trigger_error */
1128int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1129 struct ras_inject_if *info)
1130{
1131 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1132 struct ta_ras_trigger_error_input block_info = {
828cfa29 1133 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1134 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
c030f2e4 1135 .sub_block_index = info->head.sub_block_index,
1136 .address = info->address,
1137 .value = info->value,
1138 };
ab3b9de6
YL		 1139 int ret = -EINVAL;
1140 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1141 info->head.block,
1142 info->head.sub_block_index);
c030f2e4 1143
248c9635
TZ		 1144 /* inject on guest isn't allowed, return success directly */
1145 if (amdgpu_sriov_vf(adev))
1146 return 0;
1147
c030f2e4 1148 if (!obj)
1149 return -EINVAL;
1150
22d4ba53 1151 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1152 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1153 get_ras_block_str(&info->head));
22d4ba53 1154 return -EINVAL;
1155 }
1156
a6c44d25
JC		 1157 /* Calculate XGMI relative offset */
1158 if (adev->gmc.xgmi.num_physical_nodes > 1) {
19744f5f
HZ		 1159 block_info.address =
1160 amdgpu_xgmi_get_relative_phy_addr(adev,
1161 block_info.address);
a6c44d25
JC		 1162 }
1163
27c5f295
TZ		 1164 if (block_obj->hw_ops->ras_error_inject) {
1165 if (info->head.block == AMDGPU_RAS_BLOCK__GFX)
2c22ed0b 1166 ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask);
27c5f295 1167 else /* Special ras_error_inject is defined (e.g: xgmi) */
2c22ed0b
TZ		 1168 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info,
1169 info->instance_mask);
27c5f295
TZ		 1170 } else {
1171 /* default path */
1172 ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask);
a5dd40ca
HZ		 1173 }
1174
011907fd
DL		 1175 if (ret)
1176 dev_err(adev->dev, "ras inject %s failed %d\n",
640ae42e 1177 get_ras_block_str(&info->head), ret);
c030f2e4 1178
1179 return ret;
1180}
1181
4d9f771e 1182/**
4a1c9a44
HZ		 1183 * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP
1184 * @adev: pointer to AMD GPU device
1185 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1186 * @ue_count: pointer to an integer to be set to the count of uncorrectible errors.
1187 * @query_info: pointer to ras_query_if
1188 *
1189 * Return 0 for query success or do nothing, otherwise return an error
1190 * on failures
1191 */
1192static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev,
1193 unsigned long *ce_count,
1194 unsigned long *ue_count,
1195 struct ras_query_if *query_info)
1196{
1197 int ret;
1198
1199 if (!query_info)
1200 /* do nothing if query_info is not specified */
1201 return 0;
1202
1203 ret = amdgpu_ras_query_error_status(adev, query_info);
1204 if (ret)
1205 return ret;
1206
1207 *ce_count += query_info->ce_count;
1208 *ue_count += query_info->ue_count;
1209
1210 /* some hardware/IP supports read to clear
1211 * no need to explictly reset the err status after the query call */
1212 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
1213 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
1214 if (amdgpu_ras_reset_error_status(adev, query_info->head.block))
1215 dev_warn(adev->dev,
1216 "Failed to reset error counter and error status\n");
1217 }
1218
1219 return 0;
1220}
1221
1222/**
1223 * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP
bbe04dec
IB		 1224 * @adev: pointer to AMD GPU device
1225 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1226 * @ue_count: pointer to an integer to be set to the count of uncorrectible
4d9f771e 1227 * errors.
4a1c9a44
HZ		 1228 * @query_info: pointer to ras_query_if if the query request is only for
1229 * specific ip block; if info is NULL, then the qurey request is for
1230 * all the ip blocks that support query ras error counters/status
4d9f771e
LT		 1231 *
1232 * If set, @ce_count or @ue_count, count and return the corresponding
1233 * error counts in those integer pointers. Return 0 if the device
1234 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1235 */
1236int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1237 unsigned long *ce_count,
4a1c9a44
HZ		 1238 unsigned long *ue_count,
1239 struct ras_query_if *query_info)
c030f2e4 1240{
1241 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1242 struct ras_manager *obj;
a46751fb 1243 unsigned long ce, ue;
4a1c9a44 1244 int ret;
c030f2e4 1245
8ab0d6f0 1246 if (!adev->ras_enabled || !con)
4d9f771e
LT		 1247 return -EOPNOTSUPP;
1248
1249 /* Don't count since no reporting.
1250 */
1251 if (!ce_count && !ue_count)
1252 return 0;
c030f2e4 1253
a46751fb
LT		 1254 ce = 0;
1255 ue = 0;
4a1c9a44
HZ		 1256 if (!query_info) {
1257 /* query all the ip blocks that support ras query interface */
1258 list_for_each_entry(obj, &con->head, node) {
1259 struct ras_query_if info = {
1260 .head = obj->head,
1261 };
c030f2e4 1262
4a1c9a44 1263 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info);
2a460963 1264 }
4a1c9a44
HZ		 1265 } else {
1266 /* query specific ip block */
1267 ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info);
c030f2e4 1268 }
1269
4a1c9a44
HZ		 1270 if (ret)
1271 return ret;
1272
a46751fb
LT		 1273 if (ce_count)
1274 *ce_count = ce;
1275
1276 if (ue_count)
1277 *ue_count = ue;
4d9f771e
LT		 1278
1279 return 0;
c030f2e4 1280}
1281/* query/inject/cure end */
1282
1283
1284/* sysfs begin */
1285
466b1793 1286static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1287 struct ras_badpage **bps, unsigned int *count);
1288
1289static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1290{
1291 switch (flags) {
52dd95f2 1292 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
466b1793 1293 return "R";
52dd95f2 1294 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
466b1793 1295 return "P";
52dd95f2 1296 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
466b1793 1297 default:
1298 return "F";
aec576f9 1299 }
466b1793 1300}
1301
f77c7109
AD		 1302/**
1303 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
466b1793 1304 *
1305 * It allows user to read the bad pages of vram on the gpu through
1306 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1307 *
1308 * It outputs multiple lines, and each line stands for one gpu page.
1309 *
1310 * The format of one line is below,
1311 * gpu pfn : gpu page size : flags
1312 *
1313 * gpu pfn and gpu page size are printed in hex format.
1314 * flags can be one of below character,
f77c7109 1315 *
466b1793 1316 * R: reserved, this gpu page is reserved and not able to use.
f77c7109 1317 *
466b1793 1318 * P: pending for reserve, this gpu page is marked as bad, will be reserved
f77c7109
AD		 1319 * in next window of page_reserve.
1320 *
466b1793 1321 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1322 *
f77c7109
AD		 1323 * Examples:
1324 *
1325 * .. code-block:: bash
1326 *
1327 * 0x00000001 : 0x00001000 : R
1328 * 0x00000002 : 0x00001000 : P
1329 *
466b1793 1330 */
1331
1332static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1333 struct kobject *kobj, struct bin_attribute *attr,
1334 char *buf, loff_t ppos, size_t count)
1335{
1336 struct amdgpu_ras *con =
1337 container_of(attr, struct amdgpu_ras, badpages_attr);
1338 struct amdgpu_device *adev = con->adev;
1339 const unsigned int element_size =
1340 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
d6ee400e
SA		 1341 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1342 unsigned int end = div64_ul(ppos + count - 1, element_size);
466b1793 1343 ssize_t s = 0;
1344 struct ras_badpage *bps = NULL;
1345 unsigned int bps_count = 0;
1346
1347 memset(buf, 0, count);
1348
1349 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1350 return 0;
1351
1352 for (; start < end && start < bps_count; start++)
1353 s += scnprintf(&buf[s], element_size + 1,
1354 "0x%08x : 0x%08x : %1s\n",
1355 bps[start].bp,
1356 bps[start].size,
1357 amdgpu_ras_badpage_flags_str(bps[start].flags));
1358
1359 kfree(bps);
1360
1361 return s;
1362}
1363
c030f2e4 1364static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1365 struct device_attribute *attr, char *buf)
1366{
1367 struct amdgpu_ras *con =
1368 container_of(attr, struct amdgpu_ras, features_attr);
c030f2e4 1369
2cffcb66 1370 return sysfs_emit(buf, "feature mask: 0x%x\n", con->features);
c030f2e4 1371}
1372
f848159b
GC		 1373static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1374{
1375 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1376
1377 sysfs_remove_file_from_group(&adev->dev->kobj,
1378 &con->badpages_attr.attr,
1379 RAS_FS_NAME);
1380}
1381
c030f2e4 1382static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1383{
1384 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1385 struct attribute *attrs[] = {
1386 &con->features_attr.attr,
1387 NULL
1388 };
1389 struct attribute_group group = {
eb0c3cd4 1390 .name = RAS_FS_NAME,
c030f2e4 1391 .attrs = attrs,
1392 };
1393
1394 sysfs_remove_group(&adev->dev->kobj, &group);
1395
1396 return 0;
1397}
1398
1399int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
9252d33d 1400 struct ras_common_if *head)
c030f2e4 1401{
9252d33d 1402 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1403
1404 if (!obj || obj->attr_inuse)
1405 return -EINVAL;
1406
1407 get_obj(obj);
1408
9252d33d 1409 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1410 "%s_err_count", head->name);
c030f2e4 1411
1412 obj->sysfs_attr = (struct device_attribute){
1413 .attr = {
1414 .name = obj->fs_data.sysfs_name,
1415 .mode = S_IRUGO,
1416 },
1417 .show = amdgpu_ras_sysfs_read,
1418 };
163def43 1419 sysfs_attr_init(&obj->sysfs_attr.attr);
c030f2e4 1420
1421 if (sysfs_add_file_to_group(&adev->dev->kobj,
1422 &obj->sysfs_attr.attr,
eb0c3cd4 1423 RAS_FS_NAME)) {
c030f2e4 1424 put_obj(obj);
1425 return -EINVAL;
1426 }
1427
1428 obj->attr_inuse = 1;
1429
1430 return 0;
1431}
1432
1433int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1434 struct ras_common_if *head)
1435{
1436 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1437
1438 if (!obj || !obj->attr_inuse)
1439 return -EINVAL;
1440
1441 sysfs_remove_file_from_group(&adev->dev->kobj,
1442 &obj->sysfs_attr.attr,
eb0c3cd4 1443 RAS_FS_NAME);
c030f2e4 1444 obj->attr_inuse = 0;
1445 put_obj(obj);
1446
1447 return 0;
1448}
1449
1450static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1451{
1452 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1453 struct ras_manager *obj, *tmp;
1454
1455 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1456 amdgpu_ras_sysfs_remove(adev, &obj->head);
1457 }
1458
f848159b
GC		 1459 if (amdgpu_bad_page_threshold != 0)
1460 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1461
c030f2e4 1462 amdgpu_ras_sysfs_remove_feature_node(adev);
1463
1464 return 0;
1465}
1466/* sysfs end */
1467
ef177d11
AD		 1468/**
1469 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1470 *
1471 * Normally when there is an uncorrectable error, the driver will reset
1472 * the GPU to recover. However, in the event of an unrecoverable error,
1473 * the driver provides an interface to reboot the system automatically
1474 * in that event.
1475 *
1476 * The following file in debugfs provides that interface:
1477 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1478 *
1479 * Usage:
1480 *
1481 * .. code-block:: bash
1482 *
1483 * echo true > .../ras/auto_reboot
1484 *
1485 */
c030f2e4 1486/* debugfs begin */
ea1b8c9b 1487static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
36ea1bd2 1488{
1489 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
ef0d7d20
LT		 1490 struct drm_minor *minor = adev_to_drm(adev)->primary;
1491 struct dentry *dir;
36ea1bd2 1492
88293c03
ND		 1493 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1494 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1495 &amdgpu_ras_debugfs_ctrl_ops);
1496 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1497 &amdgpu_ras_debugfs_eeprom_ops);
7fb64071
LT		 1498 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1499 &con->bad_page_cnt_threshold);
ef0d7d20
LT		 1500 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1501 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
c65b0805
LT		 1502 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1503 &amdgpu_ras_debugfs_eeprom_size_ops);
1504 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1505 S_IRUGO, dir, adev,
1506 &amdgpu_ras_debugfs_eeprom_table_ops);
1507 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
c688a06b
GC		 1508
1509 /*
1510 * After one uncorrectable error happens, usually GPU recovery will
1511 * be scheduled. But due to the known problem in GPU recovery failing
1512 * to bring GPU back, below interface provides one direct way to
1513 * user to reboot system automatically in such case within
1514 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1515 * will never be called.
1516 */
88293c03 1517 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
66459e1d
GC		 1518
1519 /*
1520 * User could set this not to clean up hardware's error count register
1521 * of RAS IPs during ras recovery.
1522 */
88293c03
ND		 1523 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1524 &con->disable_ras_err_cnt_harvest);
1525 return dir;
36ea1bd2 1526}
1527
cedf7884 1528static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
88293c03
ND		 1529 struct ras_fs_if *head,
1530 struct dentry *dir)
c030f2e4 1531{
c030f2e4 1532 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
c030f2e4 1533
88293c03 1534 if (!obj || !dir)
450f30ea 1535 return;
c030f2e4 1536
1537 get_obj(obj);
1538
1539 memcpy(obj->fs_data.debugfs_name,
1540 head->debugfs_name,
1541 sizeof(obj->fs_data.debugfs_name));
1542
88293c03
ND		 1543 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1544 obj, &amdgpu_ras_debugfs_ops);
c030f2e4 1545}
1546
f9317014
TZ		 1547void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1548{
1549 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
88293c03 1550 struct dentry *dir;
c1509f3f 1551 struct ras_manager *obj;
f9317014
TZ		 1552 struct ras_fs_if fs_info;
1553
1554 /*
1555 * it won't be called in resume path, no need to check
1556 * suspend and gpu reset status
1557 */
cedf7884 1558 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
f9317014
TZ		 1559 return;
1560
88293c03 1561 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
f9317014 1562
c1509f3f 1563 list_for_each_entry(obj, &con->head, node) {
f9317014
TZ		 1564 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1565 (obj->attr_inuse == 1)) {
1566 sprintf(fs_info.debugfs_name, "%s_err_inject",
640ae42e 1567 get_ras_block_str(&obj->head));
f9317014 1568 fs_info.head = obj->head;
88293c03 1569 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
f9317014
TZ		 1570 }
1571 }
1572}
1573
c030f2e4 1574/* debugfs end */
1575
1576/* ras fs */
c3d4d45d
GC		 1577static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1578 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1579static DEVICE_ATTR(features, S_IRUGO,
1580 amdgpu_ras_sysfs_features_read, NULL);
c030f2e4 1581static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1582{
c3d4d45d
GC		 1583 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1584 struct attribute_group group = {
1585 .name = RAS_FS_NAME,
1586 };
1587 struct attribute *attrs[] = {
1588 &con->features_attr.attr,
1589 NULL
1590 };
1591 struct bin_attribute *bin_attrs[] = {
1592 NULL,
1593 NULL,
1594 };
a069a9eb 1595 int r;
c030f2e4 1596
c3d4d45d
GC		 1597 /* add features entry */
1598 con->features_attr = dev_attr_features;
1599 group.attrs = attrs;
1600 sysfs_attr_init(attrs[0]);
1601
1602 if (amdgpu_bad_page_threshold != 0) {
1603 /* add bad_page_features entry */
1604 bin_attr_gpu_vram_bad_pages.private = NULL;
1605 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1606 bin_attrs[0] = &con->badpages_attr;
1607 group.bin_attrs = bin_attrs;
1608 sysfs_bin_attr_init(bin_attrs[0]);
1609 }
1610
a069a9eb
AD		 1611 r = sysfs_create_group(&adev->dev->kobj, &group);
1612 if (r)
1613 dev_err(adev->dev, "Failed to create RAS sysfs group!");
f848159b 1614
c030f2e4 1615 return 0;
1616}
1617
1618static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1619{
88293c03
ND		 1620 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1621 struct ras_manager *con_obj, *ip_obj, *tmp;
1622
1623 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1624 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1625 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1626 if (ip_obj)
1627 put_obj(ip_obj);
1628 }
1629 }
1630
c030f2e4 1631 amdgpu_ras_sysfs_remove_all(adev);
1632 return 0;
1633}
1634/* ras fs end */
1635
1636/* ih begin */
b3c76814
TZ		 1637
1638/* For the hardware that cannot enable bif ring for both ras_controller_irq
1639 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1640 * register to check whether the interrupt is triggered or not, and properly
1641 * ack the interrupt if it is there
1642 */
1643void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1644{
950d6425 1645 /* Fatal error events are handled on host side */
8eba7205 1646 if (amdgpu_sriov_vf(adev))
b3c76814
TZ		 1647 return;
1648
1649 if (adev->nbio.ras &&
1650 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1651 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1652
1653 if (adev->nbio.ras &&
1654 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1655 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1656}
1657
66f87949
TZ		 1658static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1659 struct amdgpu_iv_entry *entry)
1660{
b63ac5d3 1661 bool poison_stat = false;
66f87949 1662 struct amdgpu_device *adev = obj->adev;
66f87949
TZ		 1663 struct amdgpu_ras_block_object *block_obj =
1664 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1665
ac7b25d9 1666 if (!block_obj)
b63ac5d3 1667 return;
66f87949 1668
b63ac5d3
TZ		 1669 /* both query_poison_status and handle_poison_consumption are optional,
1670 * but at least one of them should be implemented if we need poison
1671 * consumption handler
1672 */
ac7b25d9 1673 if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) {
b63ac5d3
TZ		 1674 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1675 if (!poison_stat) {
1676 /* Not poison consumption interrupt, no need to handle it */
1677 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1678 block_obj->ras_comm.name);
1679
1680 return;
66f87949
TZ		 1681 }
1682 }
1683
b63ac5d3 1684 if (!adev->gmc.xgmi.connected_to_cpu)
1ed0e176 1685 amdgpu_umc_poison_handler(adev, false);
b63ac5d3 1686
ac7b25d9 1687 if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption)
b63ac5d3
TZ		 1688 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1689
1690 /* gpu reset is fallback for failed and default cases */
1691 if (poison_stat) {
1692 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1693 block_obj->ras_comm.name);
66f87949 1694 amdgpu_ras_reset_gpu(adev);
ac7b25d9
YC		 1695 } else {
1696 amdgpu_gfx_poison_consumption_handler(adev, entry);
b63ac5d3 1697 }
66f87949
TZ		 1698}
1699
50a7d025
TZ		 1700static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1701 struct amdgpu_iv_entry *entry)
1702{
1703 dev_info(obj->adev->dev,
1704 "Poison is created, no user action is needed.\n");
1705}
1706
1707static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1708 struct amdgpu_iv_entry *entry)
1709{
1710 struct ras_ih_data *data = &obj->ih_data;
1711 struct ras_err_data err_data = {0, 0, 0, NULL};
1712 int ret;
1713
1714 if (!data->cb)
1715 return;
1716
1717 /* Let IP handle its data, maybe we need get the output
1718 * from the callback to update the error type/count, etc
1719 */
1720 ret = data->cb(obj->adev, &err_data, entry);
1721 /* ue will trigger an interrupt, and in that case
1722 * we need do a reset to recovery the whole system.
1723 * But leave IP do that recovery, here we just dispatch
1724 * the error.
1725 */
1726 if (ret == AMDGPU_RAS_SUCCESS) {
1727 /* these counts could be left as 0 if
1728 * some blocks do not count error number
1729 */
1730 obj->err_data.ue_count += err_data.ue_count;
1731 obj->err_data.ce_count += err_data.ce_count;
1732 }
1733}
1734
c030f2e4 1735static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1736{
1737 struct ras_ih_data *data = &obj->ih_data;
1738 struct amdgpu_iv_entry entry;
c030f2e4 1739
1740 while (data->rptr != data->wptr) {
1741 rmb();
1742 memcpy(&entry, &data->ring[data->rptr],
1743 data->element_size);
1744
1745 wmb();
1746 data->rptr = (data->aligned_element_size +
1747 data->rptr) % data->ring_size;
1748
50a7d025
TZ		 1749 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1750 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1751 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
66f87949
TZ		 1752 else
1753 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
50a7d025
TZ		 1754 } else {
1755 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1756 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1757 else
1758 dev_warn(obj->adev->dev,
1759 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
c030f2e4 1760 }
1761 }
1762}
1763
1764static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1765{
1766 struct ras_ih_data *data =
1767 container_of(work, struct ras_ih_data, ih_work);
1768 struct ras_manager *obj =
1769 container_of(data, struct ras_manager, ih_data);
1770
1771 amdgpu_ras_interrupt_handler(obj);
1772}
1773
1774int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1775 struct ras_dispatch_if *info)
1776{
1777 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1778 struct ras_ih_data *data = &obj->ih_data;
1779
1780 if (!obj)
1781 return -EINVAL;
1782
1783 if (data->inuse == 0)
1784 return 0;
1785
1786 /* Might be overflow... */
1787 memcpy(&data->ring[data->wptr], info->entry,
1788 data->element_size);
1789
1790 wmb();
1791 data->wptr = (data->aligned_element_size +
1792 data->wptr) % data->ring_size;
1793
1794 schedule_work(&data->ih_work);
1795
1796 return 0;
1797}
1798
1799int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
9252d33d 1800 struct ras_common_if *head)
c030f2e4 1801{
9252d33d 1802 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1803 struct ras_ih_data *data;
1804
1805 if (!obj)
1806 return -EINVAL;
1807
1808 data = &obj->ih_data;
1809 if (data->inuse == 0)
1810 return 0;
1811
1812 cancel_work_sync(&data->ih_work);
1813
1814 kfree(data->ring);
1815 memset(data, 0, sizeof(*data));
1816 put_obj(obj);
1817
1818 return 0;
1819}
1820
1821int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
9252d33d 1822 struct ras_common_if *head)
c030f2e4 1823{
9252d33d 1824 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1825 struct ras_ih_data *data;
9252d33d 1826 struct amdgpu_ras_block_object *ras_obj;
c030f2e4 1827
1828 if (!obj) {
1829 /* in case we registe the IH before enable ras feature */
9252d33d 1830 obj = amdgpu_ras_create_obj(adev, head);
c030f2e4 1831 if (!obj)
1832 return -EINVAL;
1833 } else
1834 get_obj(obj);
1835
9252d33d 1836 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1837
c030f2e4 1838 data = &obj->ih_data;
1839 /* add the callback.etc */
1840 *data = (struct ras_ih_data) {
1841 .inuse = 0,
9252d33d 1842 .cb = ras_obj->ras_cb,
c030f2e4 1843 .element_size = sizeof(struct amdgpu_iv_entry),
1844 .rptr = 0,
1845 .wptr = 0,
1846 };
1847
1848 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1849
1850 data->aligned_element_size = ALIGN(data->element_size, 8);
1851 /* the ring can store 64 iv entries. */
1852 data->ring_size = 64 * data->aligned_element_size;
1853 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1854 if (!data->ring) {
1855 put_obj(obj);
1856 return -ENOMEM;
1857 }
1858
1859 /* IH is ready */
1860 data->inuse = 1;
1861
1862 return 0;
1863}
1864
1865static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1866{
1867 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1868 struct ras_manager *obj, *tmp;
1869
1870 list_for_each_entry_safe(obj, tmp, &con->head, node) {
9252d33d 1871 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
c030f2e4 1872 }
1873
1874 return 0;
1875}
1876/* ih end */
1877
313c8fd3
GC		 1878/* traversal all IPs except NBIO to query error counter */
1879static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1880{
1881 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1882 struct ras_manager *obj;
1883
8ab0d6f0 1884 if (!adev->ras_enabled || !con)
313c8fd3
GC		 1885 return;
1886
1887 list_for_each_entry(obj, &con->head, node) {
1888 struct ras_query_if info = {
1889 .head = obj->head,
1890 };
1891
1892 /*
1893 * PCIE_BIF IP has one different isr by ras controller
1894 * interrupt, the specific ras counter query will be
1895 * done in that isr. So skip such block from common
1896 * sync flood interrupt isr calling.
1897 */
1898 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1899 continue;
1900
cf63b702
SY		 1901 /*
1902 * this is a workaround for aldebaran, skip send msg to
1903 * smu to get ecc_info table due to smu handle get ecc
1904 * info table failed temporarily.
1905 * should be removed until smu fix handle ecc_info table.
1906 */
1907 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1908 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1909 continue;
1910
761d86d3 1911 amdgpu_ras_query_error_status(adev, &info);
2a460963
CL		 1912
1913 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
6da15a23
CL		 1914 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
1915 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
2a460963
CL		 1916 if (amdgpu_ras_reset_error_status(adev, info.head.block))
1917 dev_warn(adev->dev, "Failed to reset error counter and error status");
1918 }
313c8fd3
GC		 1919 }
1920}
1921
3f975d0f 1922/* Parse RdRspStatus and WrRspStatus */
cd92df93
LJ		 1923static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1924 struct ras_query_if *info)
3f975d0f 1925{
8eb53bb2 1926 struct amdgpu_ras_block_object *block_obj;
3f975d0f
SY		 1927 /*
1928 * Only two block need to query read/write
1929 * RspStatus at current state
1930 */
5e67bba3 1931 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1932 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
b6efdb02 1933 return;
1934
1935 block_obj = amdgpu_ras_get_ras_block(adev,
1936 info->head.block,
1937 info->head.sub_block_index);
5e67bba3 1938
5e67bba3 1939 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1940 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1941 get_ras_block_str(&info->head));
b6efdb02 1942 return;
3f975d0f 1943 }
5e67bba3 1944
1945 if (block_obj->hw_ops->query_ras_error_status)
ab3b9de6 1946 block_obj->hw_ops->query_ras_error_status(adev);
5e67bba3 1947
3f975d0f
SY		 1948}
1949
1950static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1951{
1952 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1953 struct ras_manager *obj;
1954
8ab0d6f0 1955 if (!adev->ras_enabled || !con)
3f975d0f
SY		 1956 return;
1957
1958 list_for_each_entry(obj, &con->head, node) {
1959 struct ras_query_if info = {
1960 .head = obj->head,
1961 };
1962
1963 amdgpu_ras_error_status_query(adev, &info);
1964 }
1965}
1966
c030f2e4 1967/* recovery begin */
466b1793 1968
1969/* return 0 on success.
1970 * caller need free bps.
1971 */
1972static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1973 struct ras_badpage **bps, unsigned int *count)
1974{
1975 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1976 struct ras_err_handler_data *data;
1977 int i = 0;
732f2a30 1978 int ret = 0, status;
466b1793 1979
1980 if (!con || !con->eh_data || !bps || !count)
1981 return -EINVAL;
1982
1983 mutex_lock(&con->recovery_lock);
1984 data = con->eh_data;
1985 if (!data || data->count == 0) {
1986 *bps = NULL;
46cf2fec 1987 ret = -EINVAL;
466b1793 1988 goto out;
1989 }
1990
1991 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1992 if (!*bps) {
1993 ret = -ENOMEM;
1994 goto out;
1995 }
1996
1997 for (; i < data->count; i++) {
1998 (*bps)[i] = (struct ras_badpage){
9dc23a63 1999 .bp = data->bps[i].retired_page,
466b1793 2000 .size = AMDGPU_GPU_PAGE_SIZE,
52dd95f2 2001 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
466b1793 2002 };
ec6aae97 2003 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
676deb38 2004 data->bps[i].retired_page);
732f2a30 2005 if (status == -EBUSY)
52dd95f2 2006 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
732f2a30 2007 else if (status == -ENOENT)
52dd95f2 2008 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
466b1793 2009 }
2010
2011 *count = data->count;
2012out:
2013 mutex_unlock(&con->recovery_lock);
2014 return ret;
2015}
2016
c030f2e4 2017static void amdgpu_ras_do_recovery(struct work_struct *work)
2018{
2019 struct amdgpu_ras *ras =
2020 container_of(work, struct amdgpu_ras, recovery_work);
b3dbd6d3
JC		 2021 struct amdgpu_device *remote_adev = NULL;
2022 struct amdgpu_device *adev = ras->adev;
2023 struct list_head device_list, *device_list_handle = NULL;
b3dbd6d3 2024
f75e94d8 2025 if (!ras->disable_ras_err_cnt_harvest) {
d95e8e97
DL		 2026 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
2027
f75e94d8
GC		 2028 /* Build list of devices to query RAS related errors */
2029 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
2030 device_list_handle = &hive->device_list;
2031 } else {
2032 INIT_LIST_HEAD(&device_list);
2033 list_add_tail(&adev->gmc.xgmi.head, &device_list);
2034 device_list_handle = &device_list;
2035 }
c030f2e4 2036
f75e94d8 2037 list_for_each_entry(remote_adev,
3f975d0f
SY		 2038 device_list_handle, gmc.xgmi.head) {
2039 amdgpu_ras_query_err_status(remote_adev);
f75e94d8 2040 amdgpu_ras_log_on_err_counter(remote_adev);
3f975d0f 2041 }
d95e8e97
DL		 2042
2043 amdgpu_put_xgmi_hive(hive);
b3dbd6d3 2044 }
313c8fd3 2045
f1549c09
LG		 2046 if (amdgpu_device_should_recover_gpu(ras->adev)) {
2047 struct amdgpu_reset_context reset_context;
2048 memset(&reset_context, 0, sizeof(reset_context));
2049
2050 reset_context.method = AMD_RESET_METHOD_NONE;
2051 reset_context.reset_req_dev = adev;
1a11a65d
YC		 2052
2053 /* Perform full reset in fatal error mode */
2054 if (!amdgpu_ras_is_poison_mode_supported(ras->adev))
2055 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
6c47a79b 2056 else {
1a11a65d 2057 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
f1549c09 2058
6c47a79b
YC		 2059 if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) {
2060 ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET;
2061 reset_context.method = AMD_RESET_METHOD_MODE2;
2062 }
2063 }
2064
f1549c09
LG		 2065 amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
2066 }
c030f2e4 2067 atomic_set(&ras->in_recovery, 0);
2068}
2069
c030f2e4 2070/* alloc/realloc bps array */
2071static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
2072 struct ras_err_handler_data *data, int pages)
2073{
2074 unsigned int old_space = data->count + data->space_left;
2075 unsigned int new_space = old_space + pages;
9dc23a63
TZ		 2076 unsigned int align_space = ALIGN(new_space, 512);
2077 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
9dc23a63 2078
676deb38 2079 if (!bps) {
c030f2e4 2080 return -ENOMEM;
9dc23a63 2081 }
c030f2e4 2082
2083 if (data->bps) {
9dc23a63 2084 memcpy(bps, data->bps,
c030f2e4 2085 data->count * sizeof(*data->bps));
2086 kfree(data->bps);
2087 }
2088
9dc23a63 2089 data->bps = bps;
c030f2e4 2090 data->space_left += align_space - old_space;
2091 return 0;
2092}
2093
2094/* it deal with vram only. */
2095int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
9dc23a63 2096 struct eeprom_table_record *bps, int pages)
c030f2e4 2097{
2098 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
73aa8e1a 2099 struct ras_err_handler_data *data;
c030f2e4 2100 int ret = 0;
676deb38 2101 uint32_t i;
c030f2e4 2102
73aa8e1a 2103 if (!con || !con->eh_data || !bps || pages <= 0)
c030f2e4 2104 return 0;
2105
2106 mutex_lock(&con->recovery_lock);
73aa8e1a 2107 data = con->eh_data;
c030f2e4 2108 if (!data)
2109 goto out;
2110
676deb38
DL		 2111 for (i = 0; i < pages; i++) {
2112 if (amdgpu_ras_check_bad_page_unlock(con,
2113 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
2114 continue;
2115
2116 if (!data->space_left &&
2117 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
c030f2e4 2118 ret = -ENOMEM;
2119 goto out;
2120 }
2121
ec6aae97 2122 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
676deb38
DL		 2123 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
2124 AMDGPU_GPU_PAGE_SIZE);
9dc23a63 2125
676deb38
DL		 2126 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
2127 data->count++;
2128 data->space_left--;
2129 }
c030f2e4 2130out:
2131 mutex_unlock(&con->recovery_lock);
2132
2133 return ret;
2134}
2135
78ad00c9
TZ		 2136/*
2137 * write error record array to eeprom, the function should be
2138 * protected by recovery_lock
4d33e0f1 2139 * new_cnt: new added UE count, excluding reserved bad pages, can be NULL
78ad00c9 2140 */
4d33e0f1
TZ		 2141int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev,
2142 unsigned long *new_cnt)
78ad00c9
TZ		 2143{
2144 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2145 struct ras_err_handler_data *data;
8a3e801f 2146 struct amdgpu_ras_eeprom_control *control;
78ad00c9
TZ		 2147 int save_count;
2148
4d33e0f1
TZ		 2149 if (!con || !con->eh_data) {
2150 if (new_cnt)
2151 *new_cnt = 0;
2152
78ad00c9 2153 return 0;
4d33e0f1 2154 }
78ad00c9 2155
d9a69fe5 2156 mutex_lock(&con->recovery_lock);
8a3e801f 2157 control = &con->eeprom_control;
78ad00c9 2158 data = con->eh_data;
0686627b 2159 save_count = data->count - control->ras_num_recs;
d9a69fe5 2160 mutex_unlock(&con->recovery_lock);
4d33e0f1
TZ		 2161
2162 if (new_cnt)
2163 *new_cnt = save_count / adev->umc.retire_unit;
2164
78ad00c9 2165 /* only new entries are saved */
b1628425 2166 if (save_count > 0) {
63d4c081
LT		 2167 if (amdgpu_ras_eeprom_append(control,
2168 &data->bps[control->ras_num_recs],
2169 save_count)) {
6952e99c 2170 dev_err(adev->dev, "Failed to save EEPROM table data!");
78ad00c9
TZ		 2171 return -EIO;
2172 }
2173
b1628425
GC		 2174 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2175 }
2176
78ad00c9
TZ		 2177 return 0;
2178}
2179
2180/*
2181 * read error record array in eeprom and reserve enough space for
2182 * storing new bad pages
2183 */
2184static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2185{
2186 struct amdgpu_ras_eeprom_control *control =
6457205c 2187 &adev->psp.ras_context.ras->eeprom_control;
e4e6a589
LT		 2188 struct eeprom_table_record *bps;
2189 int ret;
78ad00c9
TZ		 2190
2191 /* no bad page record, skip eeprom access */
0686627b 2192 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
e4e6a589 2193 return 0;
78ad00c9 2194
0686627b 2195 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
78ad00c9
TZ		 2196 if (!bps)
2197 return -ENOMEM;
2198
0686627b 2199 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
e4e6a589 2200 if (ret)
6952e99c 2201 dev_err(adev->dev, "Failed to load EEPROM table records!");
e4e6a589 2202 else
0686627b 2203 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
78ad00c9 2204
78ad00c9
TZ		 2205 kfree(bps);
2206 return ret;
2207}
2208
676deb38
DL		 2209static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2210 uint64_t addr)
2211{
2212 struct ras_err_handler_data *data = con->eh_data;
2213 int i;
2214
2215 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2216 for (i = 0; i < data->count; i++)
2217 if (addr == data->bps[i].retired_page)
2218 return true;
2219
2220 return false;
2221}
2222
6e4be987
TZ		 2223/*
2224 * check if an address belongs to bad page
2225 *
2226 * Note: this check is only for umc block
2227 */
2228static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2229 uint64_t addr)
2230{
2231 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
6e4be987
TZ		 2232 bool ret = false;
2233
2234 if (!con || !con->eh_data)
2235 return ret;
2236
2237 mutex_lock(&con->recovery_lock);
676deb38 2238 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
6e4be987
TZ		 2239 mutex_unlock(&con->recovery_lock);
2240 return ret;
2241}
2242
e5c04edf 2243static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
e4e6a589 2244 uint32_t max_count)
c84d4670 2245{
e5c04edf 2246 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c84d4670
GC		 2247
2248 /*
2249 * Justification of value bad_page_cnt_threshold in ras structure
2250 *
f3cbe70e
TZ		 2251 * Generally, 0 <= amdgpu_bad_page_threshold <= max record length
2252 * in eeprom or amdgpu_bad_page_threshold == -2, introduce two
2253 * scenarios accordingly.
c84d4670
GC		 2254 *
2255 * Bad page retirement enablement:
f3cbe70e 2256 * - If amdgpu_bad_page_threshold = -2,
c84d4670
GC		 2257 * bad_page_cnt_threshold = typical value by formula.
2258 *
2259 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2260 * max record length in eeprom, use it directly.
2261 *
2262 * Bad page retirement disablement:
2263 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2264 * functionality is disabled, and bad_page_cnt_threshold will
2265 * take no effect.
2266 */
2267
e4e6a589
LT		 2268 if (amdgpu_bad_page_threshold < 0) {
2269 u64 val = adev->gmc.mc_vram_size;
c84d4670 2270
e4e6a589 2271 do_div(val, RAS_BAD_PAGE_COVER);
e5c04edf 2272 con->bad_page_cnt_threshold = min(lower_32_bits(val),
e4e6a589 2273 max_count);
e5c04edf 2274 } else {
e4e6a589
LT		 2275 con->bad_page_cnt_threshold = min_t(int, max_count,
2276 amdgpu_bad_page_threshold);
c84d4670
GC		 2277 }
2278}
2279
1a6fc071 2280int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
c030f2e4 2281{
2282 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4d1337d2 2283 struct ras_err_handler_data **data;
e4e6a589 2284 u32 max_eeprom_records_count = 0;
b82e65a9 2285 bool exc_err_limit = false;
78ad00c9 2286 int ret;
c030f2e4 2287
e0e146d5 2288 if (!con || amdgpu_sriov_vf(adev))
1d9d2ca8
LT		 2289 return 0;
2290
2291 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2292 * supports RAS and debugfs is enabled, but when
2293 * adev->ras_enabled is unset, i.e. when "ras_enable"
2294 * module parameter is set to 0.
2295 */
2296 con->adev = adev;
2297
2298 if (!adev->ras_enabled)
4d1337d2
AG		 2299 return 0;
2300
1d9d2ca8 2301 data = &con->eh_data;
1a6fc071
TZ		 2302 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2303 if (!*data) {
2304 ret = -ENOMEM;
2305 goto out;
2306 }
c030f2e4 2307
2308 mutex_init(&con->recovery_lock);
2309 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2310 atomic_set(&con->in_recovery, 0);
69691c82 2311 con->eeprom_control.bad_channel_bitmap = 0;
c030f2e4 2312
e4e6a589
LT		 2313 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2314 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
c84d4670 2315
e5086659 2316 /* Todo: During test the SMU might fail to read the eeprom through I2C
2317 * when the GPU is pending on XGMI reset during probe time
2318 * (Mostly after second bus reset), skip it now
2319 */
2320 if (adev->gmc.xgmi.pending_reset)
2321 return 0;
b82e65a9
GC		 2322 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2323 /*
2324 * This calling fails when exc_err_limit is true or
2325 * ret != 0.
2326 */
2327 if (exc_err_limit || ret)
1a6fc071 2328 goto free;
78ad00c9 2329
0686627b 2330 if (con->eeprom_control.ras_num_recs) {
78ad00c9
TZ		 2331 ret = amdgpu_ras_load_bad_pages(adev);
2332 if (ret)
1a6fc071 2333 goto free;
513befa6 2334
bc143d8b 2335 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
69691c82
SY		 2336
2337 if (con->update_channel_flag == true) {
2338 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2339 con->update_channel_flag = false;
2340 }
78ad00c9 2341 }
c030f2e4 2342
12b2cab7
MJ		 2343#ifdef CONFIG_X86_MCE_AMD
2344 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2345 (adev->gmc.xgmi.connected_to_cpu))
91a1a52d 2346 amdgpu_register_bad_pages_mca_notifier(adev);
12b2cab7 2347#endif
c030f2e4 2348 return 0;
1a6fc071 2349
1a6fc071 2350free:
1a6fc071 2351 kfree((*data)->bps);
1a6fc071 2352 kfree(*data);
1995b3a3 2353 con->eh_data = NULL;
1a6fc071 2354out:
cf696091 2355 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
1a6fc071 2356
b82e65a9
GC		 2357 /*
2358 * Except error threshold exceeding case, other failure cases in this
2359 * function would not fail amdgpu driver init.
2360 */
2361 if (!exc_err_limit)
2362 ret = 0;
2363 else
2364 ret = -EINVAL;
2365
1a6fc071 2366 return ret;
c030f2e4 2367}
2368
2369static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2370{
2371 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2372 struct ras_err_handler_data *data = con->eh_data;
2373
1a6fc071
TZ		 2374 /* recovery_init failed to init it, fini is useless */
2375 if (!data)
2376 return 0;
2377
c030f2e4 2378 cancel_work_sync(&con->recovery_work);
c030f2e4 2379
2380 mutex_lock(&con->recovery_lock);
2381 con->eh_data = NULL;
2382 kfree(data->bps);
2383 kfree(data);
2384 mutex_unlock(&con->recovery_lock);
2385
2386 return 0;
2387}
2388/* recovery end */
2389
084e2640 2390static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
5436ab94 2391{
82835055
YC		 2392 if (amdgpu_sriov_vf(adev)) {
2393 switch (adev->ip_versions[MP0_HWIP][0]) {
2394 case IP_VERSION(13, 0, 2):
2395 return true;
2396 default:
2397 return false;
2398 }
2399 }
2400
073285ef
YC		 2401 if (adev->asic_type == CHIP_IP_DISCOVERY) {
2402 switch (adev->ip_versions[MP0_HWIP][0]) {
2403 case IP_VERSION(13, 0, 0):
2404 case IP_VERSION(13, 0, 10):
2405 return true;
2406 default:
2407 return false;
2408 }
2409 }
2410
084e2640
LT		 2411 return adev->asic_type == CHIP_VEGA10 ||
2412 adev->asic_type == CHIP_VEGA20 ||
2413 adev->asic_type == CHIP_ARCTURUS ||
75f06251 2414 adev->asic_type == CHIP_ALDEBARAN ||
084e2640 2415 adev->asic_type == CHIP_SIENNA_CICHLID;
5436ab94
SY		 2416}
2417
f50160cf
SY		 2418/*
2419 * this is workaround for vega20 workstation sku,
2420 * force enable gfx ras, ignore vbios gfx ras flag
2421 * due to GC EDC can not write
2422 */
e509965e 2423static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
f50160cf
SY		 2424{
2425 struct atom_context *ctx = adev->mode_info.atom_context;
2426
2427 if (!ctx)
2428 return;
2429
2430 if (strnstr(ctx->vbios_version, "D16406",
e11d5e0d
SY		 2431 sizeof(ctx->vbios_version)) ||
2432 strnstr(ctx->vbios_version, "D36002",
2433 sizeof(ctx->vbios_version)))
8ab0d6f0 2434 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
f50160cf
SY		 2435}
2436
5caf466a 2437/*
2438 * check hardware's ras ability which will be saved in hw_supported.
2439 * if hardware does not support ras, we can skip some ras initializtion and
2440 * forbid some ras operations from IP.
2441 * if software itself, say boot parameter, limit the ras ability. We still
2442 * need allow IP do some limited operations, like disable. In such case,
2443 * we have to initialize ras as normal. but need check if operation is
2444 * allowed or not in each function.
2445 */
e509965e 2446static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
c030f2e4 2447{
8ab0d6f0 2448 adev->ras_hw_enabled = adev->ras_enabled = 0;
c030f2e4 2449
950d6425 2450 if (!adev->is_atom_fw ||
084e2640 2451 !amdgpu_ras_asic_supported(adev))
5caf466a 2452 return;
b404ae82 2453
75f06251
HZ		 2454 if (!adev->gmc.xgmi.connected_to_cpu) {
2455 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2456 dev_info(adev->dev, "MEM ECC is active.\n");
8ab0d6f0 2457 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
e509965e 2458 1 << AMDGPU_RAS_BLOCK__DF);
75f06251
HZ		 2459 } else {
2460 dev_info(adev->dev, "MEM ECC is not presented.\n");
2461 }
88474cca 2462
75f06251
HZ		 2463 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2464 dev_info(adev->dev, "SRAM ECC is active.\n");
3189501e 2465 if (!amdgpu_sriov_vf(adev))
950d6425
SY		 2466 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2467 1 << AMDGPU_RAS_BLOCK__DF);
3189501e 2468 else
950d6425
SY		 2469 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2470 1 << AMDGPU_RAS_BLOCK__SDMA |
2471 1 << AMDGPU_RAS_BLOCK__GFX);
3189501e
TZ		 2472
2473 /* VCN/JPEG RAS can be supported on both bare metal and
2474 * SRIOV environment
2475 */
2476 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0) ||
2477 adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 0))
2478 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2479 1 << AMDGPU_RAS_BLOCK__JPEG);
2480 else
2481 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2482 1 << AMDGPU_RAS_BLOCK__JPEG);
58bc2a9c
SY		 2483
2484 /*
2485 * XGMI RAS is not supported if xgmi num physical nodes
2486 * is zero
2487 */
2488 if (!adev->gmc.xgmi.num_physical_nodes)
2489 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL);
75f06251
HZ		 2490 } else {
2491 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2492 }
2493 } else {
2494 /* driver only manages a few IP blocks RAS feature
2495 * when GPU is connected cpu through XGMI */
8ab0d6f0 2496 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
e509965e
LT		 2497 1 << AMDGPU_RAS_BLOCK__SDMA |
2498 1 << AMDGPU_RAS_BLOCK__MMHUB);
75f06251 2499 }
88474cca 2500
e509965e 2501 amdgpu_ras_get_quirks(adev);
f50160cf 2502
88474cca 2503 /* hw_supported needs to be aligned with RAS block mask. */
8ab0d6f0 2504 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
b404ae82 2505
8ab0d6f0
LT		 2506 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2507 adev->ras_hw_enabled & amdgpu_ras_mask;
c030f2e4 2508}
2509
05adfd80
LT		 2510static void amdgpu_ras_counte_dw(struct work_struct *work)
2511{
2512 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2513 ras_counte_delay_work.work);
2514 struct amdgpu_device *adev = con->adev;
a3fbb0d8 2515 struct drm_device *dev = adev_to_drm(adev);
05adfd80
LT		 2516 unsigned long ce_count, ue_count;
2517 int res;
2518
2519 res = pm_runtime_get_sync(dev->dev);
2520 if (res < 0)
2521 goto Out;
2522
2523 /* Cache new values.
2524 */
4a1c9a44 2525 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) {
4d9f771e
LT		 2526 atomic_set(&con->ras_ce_count, ce_count);
2527 atomic_set(&con->ras_ue_count, ue_count);
2528 }
05adfd80
LT		 2529
2530 pm_runtime_mark_last_busy(dev->dev);
2531Out:
2532 pm_runtime_put_autosuspend(dev->dev);
2533}
2534
2dd9032b
TZ		 2535static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev)
2536{
2537 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2538 bool df_poison, umc_poison;
2539
2540 /* poison setting is useless on SRIOV guest */
2541 if (amdgpu_sriov_vf(adev) || !con)
2542 return;
2543
2544 /* Init poison supported flag, the default value is false */
2545 if (adev->gmc.xgmi.connected_to_cpu) {
2546 /* enabled by default when GPU is connected to CPU */
2547 con->poison_supported = true;
2548 } else if (adev->df.funcs &&
2549 adev->df.funcs->query_ras_poison_mode &&
2550 adev->umc.ras &&
2551 adev->umc.ras->query_ras_poison_mode) {
2552 df_poison =
2553 adev->df.funcs->query_ras_poison_mode(adev);
2554 umc_poison =
2555 adev->umc.ras->query_ras_poison_mode(adev);
2556
2557 /* Only poison is set in both DF and UMC, we can support it */
2558 if (df_poison && umc_poison)
2559 con->poison_supported = true;
2560 else if (df_poison != umc_poison)
2561 dev_warn(adev->dev,
2562 "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2563 df_poison, umc_poison);
2564 }
2565}
2566
c030f2e4 2567int amdgpu_ras_init(struct amdgpu_device *adev)
2568{
2569 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4e644fff 2570 int r;
c030f2e4 2571
b404ae82 2572 if (con)
c030f2e4 2573 return 0;
2574
2575 con = kmalloc(sizeof(struct amdgpu_ras) +
640ae42e
JC		 2576 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2577 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
c030f2e4 2578 GFP_KERNEL|__GFP_ZERO);
2579 if (!con)
2580 return -ENOMEM;
2581
05adfd80
LT		 2582 con->adev = adev;
2583 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2584 atomic_set(&con->ras_ce_count, 0);
2585 atomic_set(&con->ras_ue_count, 0);
2586
c030f2e4 2587 con->objs = (struct ras_manager *)(con + 1);
2588
2589 amdgpu_ras_set_context(adev, con);
2590
e509965e
LT		 2591 amdgpu_ras_check_supported(adev);
2592
7ddd9770 2593 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
970fd197
SY		 2594 /* set gfx block ras context feature for VEGA20 Gaming
2595 * send ras disable cmd to ras ta during ras late init.
2596 */
8ab0d6f0 2597 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
970fd197
SY		 2598 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2599
2600 return 0;
2601 }
2602
5e91160a 2603 r = 0;
5436ab94 2604 goto release_con;
fb2a3607
HZ		 2605 }
2606
69691c82 2607 con->update_channel_flag = false;
c030f2e4 2608 con->features = 0;
2609 INIT_LIST_HEAD(&con->head);
108c6a63 2610 /* Might need get this flag from vbios. */
2611 con->flags = RAS_DEFAULT_FLAGS;
c030f2e4 2612
6e36f231
HZ		 2613 /* initialize nbio ras function ahead of any other
2614 * ras functions so hardware fatal error interrupt
2615 * can be enabled as early as possible */
fdc94d3a
HZ		 2616 switch (adev->ip_versions[NBIO_HWIP][0]) {
2617 case IP_VERSION(7, 4, 0):
2618 case IP_VERSION(7, 4, 1):
2619 case IP_VERSION(7, 4, 4):
2620 if (!adev->gmc.xgmi.connected_to_cpu)
2e54fe5d 2621 adev->nbio.ras = &nbio_v7_4_ras;
6e36f231 2622 break;
9af357bc
HZ		 2623 case IP_VERSION(4, 3, 0):
2624 if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF))
2625 /* unlike other generation of nbio ras,
2626 * nbio v4_3 only support fatal error interrupt
2627 * to inform software that DF is freezed due to
2628 * system fatal error event. driver should not
2629 * enable nbio ras in such case. Instead,
2630 * check DF RAS */
2631 adev->nbio.ras = &nbio_v4_3_ras;
2632 break;
6e36f231
HZ		 2633 default:
2634 /* nbio ras is not available */
2635 break;
2636 }
2637
fdc94d3a
HZ		 2638 /* nbio ras block needs to be enabled ahead of other ras blocks
2639 * to handle fatal error */
2640 r = amdgpu_nbio_ras_sw_init(adev);
2641 if (r)
2642 return r;
2643
2e54fe5d 2644 if (adev->nbio.ras &&
2645 adev->nbio.ras->init_ras_controller_interrupt) {
2646 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
4e644fff 2647 if (r)
5436ab94 2648 goto release_con;
4e644fff
HZ		 2649 }
2650
2e54fe5d 2651 if (adev->nbio.ras &&
2652 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2653 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
4e644fff 2654 if (r)
5436ab94 2655 goto release_con;
4e644fff
HZ		 2656 }
2657
2dd9032b 2658 amdgpu_ras_query_poison_mode(adev);
e4348849 2659
5e91160a
GC		 2660 if (amdgpu_ras_fs_init(adev)) {
2661 r = -EINVAL;
5436ab94 2662 goto release_con;
5e91160a 2663 }
c030f2e4 2664
6952e99c 2665 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
e509965e 2666 "hardware ability[%x] ras_mask[%x]\n",
8ab0d6f0 2667 adev->ras_hw_enabled, adev->ras_enabled);
e509965e 2668
c030f2e4 2669 return 0;
5436ab94 2670release_con:
c030f2e4 2671 amdgpu_ras_set_context(adev, NULL);
2672 kfree(con);
2673
5e91160a 2674 return r;
c030f2e4 2675}
2676
8f6368a9 2677int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
134d16d5 2678{
8107e499
HZ		 2679 if (adev->gmc.xgmi.connected_to_cpu ||
2680 adev->gmc.is_app_apu)
134d16d5
JC		 2681 return 1;
2682 return 0;
2683}
2684
2685static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2686 struct ras_common_if *ras_block)
2687{
2688 struct ras_query_if info = {
2689 .head = *ras_block,
2690 };
2691
2692 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2693 return 0;
2694
2695 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2696 DRM_WARN("RAS init harvest failure");
2697
2698 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2699 DRM_WARN("RAS init harvest reset failure");
2700
2701 return 0;
2702}
2703
e4348849
TZ		 2704bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2705{
2706 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2707
2708 if (!con)
2709 return false;
2710
2711 return con->poison_supported;
2712}
2713
b293e891 2714/* helper function to handle common stuff in ip late init phase */
563285c8 2715int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2716 struct ras_common_if *ras_block)
b293e891 2717{
29c9b6cd 2718 struct amdgpu_ras_block_object *ras_obj = NULL;
05adfd80 2719 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4a1c9a44 2720 struct ras_query_if *query_info;
05adfd80 2721 unsigned long ue_count, ce_count;
b293e891
HZ		 2722 int r;
2723
2724 /* disable RAS feature per IP block if it is not supported */
2725 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2726 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2727 return 0;
2728 }
2729
2730 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2731 if (r) {
9080a18f 2732 if (adev->in_suspend || amdgpu_in_reset(adev)) {
b293e891
HZ		 2733 /* in resume phase, if fail to enable ras,
2734 * clean up all ras fs nodes, and disable ras */
2735 goto cleanup;
2736 } else
2737 return r;
2738 }
2739
134d16d5
JC		 2740 /* check for errors on warm reset edc persisant supported ASIC */
2741 amdgpu_persistent_edc_harvesting(adev, ras_block);
2742
b293e891 2743 /* in resume phase, no need to create ras fs node */
53b3f8f4 2744 if (adev->in_suspend || amdgpu_in_reset(adev))
b293e891
HZ		 2745 return 0;
2746
563285c8 2747 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
36780606
TZ		 2748 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2749 (ras_obj->hw_ops->query_poison_status ||
2750 ras_obj->hw_ops->handle_poison_consumption))) {
9252d33d 2751 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
b293e891 2752 if (r)
779596ce 2753 goto cleanup;
b293e891
HZ		 2754 }
2755
9252d33d 2756 r = amdgpu_ras_sysfs_create(adev, ras_block);
b293e891 2757 if (r)
779596ce 2758 goto interrupt;
b293e891 2759
05adfd80
LT		 2760 /* Those are the cached values at init.
2761 */
4a1c9a44
HZ		 2762 query_info = kzalloc(sizeof(struct ras_query_if), GFP_KERNEL);
2763 if (!query_info)
2764 return -ENOMEM;
2765 memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if));
2766
2767 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) {
4d9f771e
LT		 2768 atomic_set(&con->ras_ce_count, ce_count);
2769 atomic_set(&con->ras_ue_count, ue_count);
2770 }
05adfd80 2771
4a1c9a44 2772 kfree(query_info);
b293e891 2773 return 0;
779596ce
TR		 2774
2775interrupt:
563285c8 2776 if (ras_obj->ras_cb)
9252d33d 2777 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
779596ce 2778cleanup:
b293e891
HZ		 2779 amdgpu_ras_feature_enable(adev, ras_block, 0);
2780 return r;
2781}
2782
d41ff22a 2783static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
418abce2 2784 struct ras_common_if *ras_block)
2785{
2786 return amdgpu_ras_block_late_init(adev, ras_block);
2787}
2788
b293e891 2789/* helper function to remove ras fs node and interrupt handler */
bdb3489c 2790void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2791 struct ras_common_if *ras_block)
2792{
563285c8 2793 struct amdgpu_ras_block_object *ras_obj;
bdb3489c 2794 if (!ras_block)
2795 return;
2796
563285c8 2797 amdgpu_ras_sysfs_remove(adev, ras_block);
bdb3489c 2798
563285c8 2799 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2800 if (ras_obj->ras_cb)
2801 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
bdb3489c 2802}
2803
80e0c2cb 2804static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2805 struct ras_common_if *ras_block)
2806{
2807 return amdgpu_ras_block_late_fini(adev, ras_block);
2808}
2809
a564808e 2810/* do some init work after IP late init as dependence.
511fdbc3 2811 * and it runs in resume/gpu reset/booting up cases.
a564808e 2812 */
511fdbc3 2813void amdgpu_ras_resume(struct amdgpu_device *adev)
108c6a63 2814{
2815 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2816 struct ras_manager *obj, *tmp;
2817
8ab0d6f0 2818 if (!adev->ras_enabled || !con) {
970fd197
SY		 2819 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2820 amdgpu_release_ras_context(adev);
2821
108c6a63 2822 return;
970fd197 2823 }
108c6a63 2824
108c6a63 2825 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
191051a1 2826 /* Set up all other IPs which are not implemented. There is a
2827 * tricky thing that IP's actual ras error type should be
2828 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2829 * ERROR_NONE make sense anyway.
2830 */
2831 amdgpu_ras_enable_all_features(adev, 1);
2832
2833 /* We enable ras on all hw_supported block, but as boot
2834 * parameter might disable some of them and one or more IP has
2835 * not implemented yet. So we disable them on behalf.
2836 */
108c6a63 2837 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2838 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2839 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2840 /* there should be no any reference. */
2841 WARN_ON(alive_obj(obj));
2842 }
191051a1 2843 }
108c6a63 2844 }
2845}
2846
511fdbc3 2847void amdgpu_ras_suspend(struct amdgpu_device *adev)
2848{
2849 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2850
8ab0d6f0 2851 if (!adev->ras_enabled || !con)
511fdbc3 2852 return;
2853
2854 amdgpu_ras_disable_all_features(adev, 0);
2855 /* Make sure all ras objects are disabled. */
2856 if (con->features)
2857 amdgpu_ras_disable_all_features(adev, 1);
2858}
2859
867e24ca 2860int amdgpu_ras_late_init(struct amdgpu_device *adev)
2861{
2862 struct amdgpu_ras_block_list *node, *tmp;
2863 struct amdgpu_ras_block_object *obj;
2864 int r;
2865
950d6425
SY		 2866 /* Guest side doesn't need init ras feature */
2867 if (amdgpu_sriov_vf(adev))
2868 return 0;
2869
867e24ca 2870 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2871 if (!node->ras_obj) {
2872 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2873 continue;
2874 }
418abce2 2875
867e24ca 2876 obj = node->ras_obj;
2877 if (obj->ras_late_init) {
2878 r = obj->ras_late_init(adev, &obj->ras_comm);
2879 if (r) {
2880 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2881 obj->ras_comm.name, r);
2882 return r;
2883 }
418abce2 2884 } else
2885 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
867e24ca 2886 }
2887
2888 return 0;
2889}
2890
c030f2e4 2891/* do some fini work before IP fini as dependence */
2892int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2893{
2894 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2895
8ab0d6f0 2896 if (!adev->ras_enabled || !con)
c030f2e4 2897 return 0;
2898
72c8c97b 2899
c030f2e4 2900 /* Need disable ras on all IPs here before ip [hw/sw]fini */
642c0401
YC		 2901 if (con->features)
2902 amdgpu_ras_disable_all_features(adev, 0);
c030f2e4 2903 amdgpu_ras_recovery_fini(adev);
2904 return 0;
2905}
2906
2907int amdgpu_ras_fini(struct amdgpu_device *adev)
2908{
d5e8ff5f 2909 struct amdgpu_ras_block_list *ras_node, *tmp;
1f211a82 2910 struct amdgpu_ras_block_object *obj = NULL;
c030f2e4 2911 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2912
8ab0d6f0 2913 if (!adev->ras_enabled || !con)
c030f2e4 2914 return 0;
2915
1f211a82 2916 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2917 if (ras_node->ras_obj) {
2918 obj = ras_node->ras_obj;
2919 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2920 obj->ras_fini)
2921 obj->ras_fini(adev, &obj->ras_comm);
80e0c2cb 2922 else
2923 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
1f211a82 2924 }
2925
2926 /* Clear ras blocks from ras_list and free ras block list node */
2927 list_del(&ras_node->node);
2928 kfree(ras_node);
2929 }
2930
c030f2e4 2931 amdgpu_ras_fs_fini(adev);
2932 amdgpu_ras_interrupt_remove_all(adev);
2933
2934 WARN(con->features, "Feature mask is not cleared");
2935
2936 if (con->features)
2937 amdgpu_ras_disable_all_features(adev, 1);
2938
05adfd80
LT		 2939 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2940
c030f2e4 2941 amdgpu_ras_set_context(adev, NULL);
2942 kfree(con);
2943
2944 return 0;
2945}
7c6e68c7
AG		 2946
2947void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2948{
e509965e 2949 amdgpu_ras_check_supported(adev);
8ab0d6f0 2950 if (!adev->ras_hw_enabled)
ed606f8a
AG		 2951 return;
2952
7c6e68c7 2953 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
6952e99c
GC		 2954 dev_info(adev->dev, "uncorrectable hardware error"
2955 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
d5ea093e 2956
61934624 2957 amdgpu_ras_reset_gpu(adev);
7c6e68c7
AG		 2958 }
2959}
bb5c7235
WS		 2960
2961bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2962{
2963 if (adev->asic_type == CHIP_VEGA20 &&
2964 adev->pm.fw_version <= 0x283400) {
2965 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2966 amdgpu_ras_intr_triggered();
2967 }
2968
2969 return false;
2970}
970fd197
SY		 2971
2972void amdgpu_release_ras_context(struct amdgpu_device *adev)
2973{
2974 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2975
2976 if (!con)
2977 return;
2978
8ab0d6f0 2979 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
970fd197
SY		 2980 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2981 amdgpu_ras_set_context(adev, NULL);
2982 kfree(con);
2983 }
2984}
12b2cab7
MJ		 2985
2986#ifdef CONFIG_X86_MCE_AMD
2987static struct amdgpu_device *find_adev(uint32_t node_id)
2988{
12b2cab7
MJ		 2989 int i;
2990 struct amdgpu_device *adev = NULL;
2991
91a1a52d
MJ		 2992 for (i = 0; i < mce_adev_list.num_gpu; i++) {
2993 adev = mce_adev_list.devs[i];
12b2cab7 2994
91a1a52d 2995 if (adev && adev->gmc.xgmi.connected_to_cpu &&
12b2cab7
MJ		 2996 adev->gmc.xgmi.physical_node_id == node_id)
2997 break;
2998 adev = NULL;
2999 }
3000
12b2cab7
MJ		 3001 return adev;
3002}
3003
3004#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
3005#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
3006#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
3007#define GPU_ID_OFFSET 8
3008
3009static int amdgpu_bad_page_notifier(struct notifier_block *nb,
3010 unsigned long val, void *data)
3011{
3012 struct mce *m = (struct mce *)data;
3013 struct amdgpu_device *adev = NULL;
3014 uint32_t gpu_id = 0;
cd4c99f1 3015 uint32_t umc_inst = 0, ch_inst = 0;
12b2cab7
MJ		 3016
3017 /*
3018 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
3019 * and error occurred in DramECC (Extended error code = 0) then only
3020 * process the error, else bail out.
3021 */
91f75eb4 3022 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
12b2cab7
MJ		 3023 (XEC(m->status, 0x3f) == 0x0)))
3024 return NOTIFY_DONE;
3025
3026 /*
3027 * If it is correctable error, return.
3028 */
3029 if (mce_is_correctable(m))
3030 return NOTIFY_OK;
3031
3032 /*
3033 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
3034 */
3035 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
3036
3037 adev = find_adev(gpu_id);
3038 if (!adev) {
3039 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
3040 gpu_id);
3041 return NOTIFY_DONE;
3042 }
3043
3044 /*
3045 * If it is uncorrectable error, then find out UMC instance and
3046 * channel index.
3047 */
3048 umc_inst = GET_UMC_INST(m->ipid);
3049 ch_inst = GET_CHAN_INDEX(m->ipid);
3050
3051 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
3052 umc_inst, ch_inst);
3053
24b82292
TZ		 3054 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3055 return NOTIFY_OK;
3056 else
6c0ca748 3057 return NOTIFY_DONE;
12b2cab7
MJ		 3058}
3059
3060static struct notifier_block amdgpu_bad_page_nb = {
3061 .notifier_call = amdgpu_bad_page_notifier,
3062 .priority = MCE_PRIO_UC,
3063};
3064
91a1a52d 3065static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
12b2cab7 3066{
91a1a52d
MJ		 3067 /*
3068 * Add the adev to the mce_adev_list.
3069 * During mode2 reset, amdgpu device is temporarily
3070 * removed from the mgpu_info list which can cause
3071 * page retirement to fail.
3072 * Use this list instead of mgpu_info to find the amdgpu
3073 * device on which the UMC error was reported.
3074 */
3075 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
3076
12b2cab7
MJ		 3077 /*
3078 * Register the x86 notifier only once
3079 * with MCE subsystem.
3080 */
3081 if (notifier_registered == false) {
3082 mce_register_decode_chain(&amdgpu_bad_page_nb);
3083 notifier_registered = true;
3084 }
3085}
3086#endif
7cab2124 3087
b6efdb02 3088struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
7cab2124 3089{
3090 if (!adev)
3091 return NULL;
3092
3093 return adev->psp.ras_context.ras;
3094}
3095
b6efdb02 3096int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
7cab2124 3097{
3098 if (!adev)
69f91d32 3099 return -EINVAL;
7cab2124 3100
3101 adev->psp.ras_context.ras = ras_con;
3102 return 0;
3103}
3104
3105/* check if ras is supported on block, say, sdma, gfx */
3106int amdgpu_ras_is_supported(struct amdgpu_device *adev,
3107 unsigned int block)
3108{
8f453c51 3109 int ret = 0;
7cab2124 3110 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3111
3112 if (block >= AMDGPU_RAS_BLOCK_COUNT)
3113 return 0;
8f453c51
YC		 3114
3115 ret = ras && (adev->ras_enabled & (1 << block));
3116
3117 /* For the special asic with mem ecc enabled but sram ecc
3118 * not enabled, even if the ras block is not supported on
3119 * .ras_enabled, if the asic supports poison mode and the
3120 * ras block has ras configuration, it can be considered
3121 * that the ras block supports ras function.
3122 */
3123 if (!ret &&
3124 amdgpu_ras_is_poison_mode_supported(adev) &&
3125 amdgpu_ras_get_ras_block(adev, block, 0))
3126 ret = 1;
3127
3128 return ret;
7cab2124 3129}
3130
3131int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
3132{
3133 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
3134
3135 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
25a2b22e 3136 amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
7cab2124 3137 return 0;
3138}
3139
3140
6492e1b0 3141/* Register each ip ras block into amdgpu ras */
3142int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
b6efdb02 3143 struct amdgpu_ras_block_object *ras_block_obj)
6492e1b0 3144{
d5e8ff5f 3145 struct amdgpu_ras_block_list *ras_node;
6492e1b0 3146 if (!adev || !ras_block_obj)
3147 return -EINVAL;
3148
d5e8ff5f 3149 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
3150 if (!ras_node)
3151 return -ENOMEM;
3152
3153 INIT_LIST_HEAD(&ras_node->node);
3154 ras_node->ras_obj = ras_block_obj;
3155 list_add_tail(&ras_node->node, &adev->ras_list);
6492e1b0 3156
3157 return 0;
3158}
322a7e00
HZ		 3159
3160void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name)
3161{
3162 if (!err_type_name)
3163 return;
3164
3165 switch (err_type) {
3166 case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
3167 sprintf(err_type_name, "correctable");
3168 break;
3169 case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
3170 sprintf(err_type_name, "uncorrectable");
3171 break;
3172 default:
3173 sprintf(err_type_name, "unknown");
3174 break;
3175 }
3176}
3177
3178bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev,
3179 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3180 uint32_t instance,
3181 uint32_t *memory_id)
3182{
3183 uint32_t err_status_lo_data, err_status_lo_offset;
3184
3185 if (!reg_entry)
3186 return false;
3187
3188 err_status_lo_offset =
3189 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3190 reg_entry->seg_lo, reg_entry->reg_lo);
3191 err_status_lo_data = RREG32(err_status_lo_offset);
3192
3193 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) &&
3194 !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG))
3195 return false;
3196
3197 *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID);
3198
3199 return true;
3200}
3201
3202bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev,
3203 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
3204 uint32_t instance,
3205 unsigned long *err_cnt)
3206{
3207 uint32_t err_status_hi_data, err_status_hi_offset;
3208
3209 if (!reg_entry)
3210 return false;
3211
3212 err_status_hi_offset =
3213 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance,
3214 reg_entry->seg_hi, reg_entry->reg_hi);
3215 err_status_hi_data = RREG32(err_status_hi_offset);
3216
3217 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) &&
3218 !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG))
9b337b7d
HZ		 3219 /* keep the check here in case we need to refer to the result later */
3220 dev_dbg(adev->dev, "Invalid err_info field\n");
322a7e00
HZ		 3221
3222 /* read err count */
3223 *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT);
3224
3225 return true;
3226}
3227
3228void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev,
3229 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3230 uint32_t reg_list_size,
3231 const struct amdgpu_ras_memory_id_entry *mem_list,
3232 uint32_t mem_list_size,
3233 uint32_t instance,
3234 uint32_t err_type,
3235 unsigned long *err_count)
3236{
3237 uint32_t memory_id;
3238 unsigned long err_cnt;
3239 char err_type_name[16];
3240 uint32_t i, j;
3241
3242 for (i = 0; i < reg_list_size; i++) {
9b337b7d
HZ		 3243 /* query memory_id from err_status_lo */
3244 if (!amdgpu_ras_inst_get_memory_id_field(adev, &reg_list[i],
3245 instance, &memory_id))
3246 continue;
3247
322a7e00
HZ		 3248 /* query err_cnt from err_status_hi */
3249 if (!amdgpu_ras_inst_get_err_cnt_field(adev, &reg_list[i],
3250 instance, &err_cnt) ||
3251 !err_cnt)
3252 continue;
3253
322a7e00
HZ		 3254 *err_count += err_cnt;
3255
3256 /* log the errors */
3257 amdgpu_ras_get_error_type_name(err_type, err_type_name);
3258 if (!mem_list) {
3259 /* memory_list is not supported */
3260 dev_info(adev->dev,
3261 "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n",
3262 err_cnt, err_type_name,
3263 reg_list[i].block_name,
3264 instance, memory_id);
3265 } else {
3266 for (j = 0; j < mem_list_size; j++) {
3267 if (memory_id == mem_list[j].memory_id) {
3268 dev_info(adev->dev,
3269 "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n",
3270 err_cnt, err_type_name,
3271 reg_list[i].block_name,
3272 instance, mem_list[j].name);
3273 break;
3274 }
3275 }
3276 }
3277 }
3278}
e53a3250
HZ		 3279
3280void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev,
3281 const struct amdgpu_ras_err_status_reg_entry *reg_list,
3282 uint32_t reg_list_size,
3283 uint32_t instance)
3284{
3285 uint32_t err_status_lo_offset, err_status_hi_offset;
3286 uint32_t i;
3287
3288 for (i = 0; i < reg_list_size; i++) {
3289 err_status_lo_offset =
3290 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3291 reg_list[i].seg_lo, reg_list[i].reg_lo);
3292 err_status_hi_offset =
3293 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance,
3294 reg_list[i].seg_hi, reg_list[i].reg_hi);
3295 WREG32(err_status_lo_offset, 0);
3296 WREG32(err_status_hi_offset, 0);
3297 }
3298}
Linux 6.x block layer and io_uring tree(s)