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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
c030f2e4 | 37 | const char *ras_error_string[] = { |
38 | "none", | |
39 | "parity", | |
40 | "single_correctable", | |
41 | "multi_uncorrectable", | |
42 | "poison", | |
43 | }; | |
44 | ||
45 | const char *ras_block_string[] = { | |
46 | "umc", | |
47 | "sdma", | |
48 | "gfx", | |
49 | "mmhub", | |
50 | "athub", | |
51 | "pcie_bif", | |
52 | "hdp", | |
53 | "xgmi_wafl", | |
54 | "df", | |
55 | "smn", | |
56 | "sem", | |
57 | "mp0", | |
58 | "mp1", | |
59 | "fuse", | |
60 | }; | |
61 | ||
62 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
63 | #define ras_block_str(i) (ras_block_string[i]) | |
64 | ||
a564808e | 65 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 |
66 | #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 | |
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
52dd95f2 GC |
72 | enum amdgpu_ras_retire_page_reservation { |
73 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
74 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
75 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
76 | }; | |
7c6e68c7 AG |
77 | |
78 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
79 | ||
6e4be987 TZ |
80 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
81 | uint64_t addr); | |
82 | ||
61380faa JC |
83 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
84 | { | |
a9d82d2f | 85 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
86 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
87 | } | |
88 | ||
89 | bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) | |
90 | { | |
a9d82d2f | 91 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
92 | return amdgpu_ras_get_context(adev)->error_query_ready; |
93 | ||
94 | return false; | |
95 | } | |
96 | ||
c030f2e4 | 97 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
98 | size_t size, loff_t *pos) | |
99 | { | |
100 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
101 | struct ras_query_if info = { | |
102 | .head = obj->head, | |
103 | }; | |
104 | ssize_t s; | |
105 | char val[128]; | |
106 | ||
107 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
108 | return -EINVAL; | |
109 | ||
110 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
111 | "ue", info.ue_count, | |
112 | "ce", info.ce_count); | |
113 | if (*pos >= s) | |
114 | return 0; | |
115 | ||
116 | s -= *pos; | |
117 | s = min_t(u64, s, size); | |
118 | ||
119 | ||
120 | if (copy_to_user(buf, &val[*pos], s)) | |
121 | return -EINVAL; | |
122 | ||
123 | *pos += s; | |
124 | ||
125 | return s; | |
126 | } | |
127 | ||
c030f2e4 | 128 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
129 | .owner = THIS_MODULE, | |
130 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 131 | .write = NULL, |
c030f2e4 | 132 | .llseek = default_llseek |
133 | }; | |
134 | ||
96ebb307 | 135 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
136 | { | |
137 | int i; | |
138 | ||
139 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
140 | *block_id = i; | |
141 | if (strcmp(name, ras_block_str(i)) == 0) | |
142 | return 0; | |
143 | } | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
147 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
148 | const char __user *buf, size_t size, | |
149 | loff_t *pos, struct ras_debug_if *data) | |
150 | { | |
151 | ssize_t s = min_t(u64, 64, size); | |
152 | char str[65]; | |
153 | char block_name[33]; | |
154 | char err[9] = "ue"; | |
155 | int op = -1; | |
156 | int block_id; | |
44494f96 | 157 | uint32_t sub_block; |
96ebb307 | 158 | u64 address, value; |
159 | ||
160 | if (*pos) | |
161 | return -EINVAL; | |
162 | *pos = size; | |
163 | ||
164 | memset(str, 0, sizeof(str)); | |
165 | memset(data, 0, sizeof(*data)); | |
166 | ||
167 | if (copy_from_user(str, buf, s)) | |
168 | return -EINVAL; | |
169 | ||
170 | if (sscanf(str, "disable %32s", block_name) == 1) | |
171 | op = 0; | |
172 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
173 | op = 1; | |
174 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
175 | op = 2; | |
b076296b | 176 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 177 | /* ascii string, but commands are not matched. */ |
178 | return -EINVAL; | |
179 | ||
180 | if (op != -1) { | |
181 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
182 | return -EINVAL; | |
183 | ||
184 | data->head.block = block_id; | |
e1063493 TZ |
185 | /* only ue and ce errors are supported */ |
186 | if (!memcmp("ue", err, 2)) | |
187 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
188 | else if (!memcmp("ce", err, 2)) | |
189 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
190 | else | |
191 | return -EINVAL; | |
192 | ||
96ebb307 | 193 | data->op = op; |
194 | ||
195 | if (op == 2) { | |
44494f96 TZ |
196 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
197 | &sub_block, &address, &value) != 3) | |
198 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
199 | &sub_block, &address, &value) != 3) | |
96ebb307 | 200 | return -EINVAL; |
44494f96 | 201 | data->head.sub_block_index = sub_block; |
96ebb307 | 202 | data->inject.address = address; |
203 | data->inject.value = value; | |
204 | } | |
205 | } else { | |
73aa8e1a | 206 | if (size < sizeof(*data)) |
96ebb307 | 207 | return -EINVAL; |
208 | ||
209 | if (copy_from_user(data, buf, sizeof(*data))) | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | } | |
7c6e68c7 | 215 | |
74abc221 TSD |
216 | /** |
217 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 218 | * |
219 | * It accepts struct ras_debug_if who has two members. | |
220 | * | |
221 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 222 | * |
223 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 224 | * |
225 | * head has four members, they are block, type, sub_block_index, name. | |
226 | * block: which IP will be under control. | |
227 | * type: what kind of error will be enabled/disabled/injected. | |
228 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
229 | * name: the name of IP. | |
230 | * | |
231 | * inject has two more members than head, they are address, value. | |
232 | * As their names indicate, inject operation will write the | |
233 | * value to the address. | |
234 | * | |
ef177d11 | 235 | * The second member: struct ras_debug_if::op. |
c688a06b | 236 | * It has three kinds of operations. |
879e723d AZ |
237 | * |
238 | * - 0: disable RAS on the block. Take ::head as its data. | |
239 | * - 1: enable RAS on the block. Take ::head as its data. | |
240 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 241 | * |
96ebb307 | 242 | * How to use the interface? |
ef177d11 AD |
243 | * |
244 | * Programs | |
245 | * | |
246 | * Copy the struct ras_debug_if in your codes and initialize it. | |
247 | * Write the struct to the control node. | |
248 | * | |
249 | * Shells | |
96ebb307 | 250 | * |
879e723d AZ |
251 | * .. code-block:: bash |
252 | * | |
a20bfd0f | 253 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 254 | * |
ef177d11 AD |
255 | * Parameters: |
256 | * | |
879e723d AZ |
257 | * op: disable, enable, inject |
258 | * disable: only block is needed | |
259 | * enable: block and error are needed | |
260 | * inject: error, address, value are needed | |
a20bfd0f | 261 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
262 | * see ras_block_string[] for details |
263 | * error: ue, ce | |
264 | * ue: multi_uncorrectable | |
265 | * ce: single_correctable | |
266 | * sub_block: | |
267 | * sub block index, pass 0 if there is no sub block | |
268 | * | |
269 | * here are some examples for bash commands: | |
270 | * | |
271 | * .. code-block:: bash | |
96ebb307 | 272 | * |
44494f96 TZ |
273 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
274 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 275 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
276 | * | |
36ea1bd2 | 277 | * How to check the result? |
278 | * | |
279 | * For disable/enable, please check ras features at | |
280 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
281 | * | |
282 | * For inject, please check corresponding err count at | |
283 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
284 | * | |
879e723d | 285 | * .. note:: |
ef177d11 | 286 | * Operations are only allowed on blocks which are supported. |
879e723d | 287 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
288 | * to see which blocks support RAS on a particular asic. |
289 | * | |
36ea1bd2 | 290 | */ |
291 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
292 | size_t size, loff_t *pos) | |
293 | { | |
294 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
295 | struct ras_debug_if data; | |
296 | int ret = 0; | |
297 | ||
61380faa | 298 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
299 | dev_warn(adev->dev, "RAS WARN: error injection " |
300 | "currently inaccessible\n"); | |
43c4d576 JC |
301 | return size; |
302 | } | |
303 | ||
96ebb307 | 304 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
305 | if (ret) | |
36ea1bd2 | 306 | return -EINVAL; |
307 | ||
36ea1bd2 | 308 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
309 | return -EINVAL; | |
310 | ||
311 | switch (data.op) { | |
312 | case 0: | |
313 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
314 | break; | |
315 | case 1: | |
316 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
317 | break; | |
318 | case 2: | |
7cdc2ee3 TZ |
319 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
320 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
321 | ret = -EINVAL; | |
322 | break; | |
323 | } | |
324 | ||
6e4be987 TZ |
325 | /* umc ce/ue error injection for a bad page is not allowed */ |
326 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
327 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
328 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
329 | "as bad before error injection!\n", | |
6e4be987 TZ |
330 | data.inject.address); |
331 | break; | |
332 | } | |
333 | ||
7cdc2ee3 | 334 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 335 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
336 | break; | |
96ebb307 | 337 | default: |
338 | ret = -EINVAL; | |
339 | break; | |
374bf7bd | 340 | } |
36ea1bd2 | 341 | |
342 | if (ret) | |
343 | return -EINVAL; | |
344 | ||
345 | return size; | |
346 | } | |
347 | ||
084fe13b AG |
348 | /** |
349 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
350 | * | |
f77c7109 | 351 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 352 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
353 | * a way to reset the EEPROM, e.g., after testing error injection. |
354 | * | |
355 | * Usage: | |
356 | * | |
357 | * .. code-block:: bash | |
358 | * | |
359 | * echo 1 > ../ras/ras_eeprom_reset | |
360 | * | |
361 | * will reset EEPROM table to 0 entries. | |
362 | * | |
084fe13b AG |
363 | */ |
364 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
365 | size_t size, loff_t *pos) | |
366 | { | |
367 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
368 | int ret; | |
369 | ||
370 | ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); | |
371 | ||
372 | return ret == 1 ? size : -EIO; | |
373 | } | |
374 | ||
36ea1bd2 | 375 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
376 | .owner = THIS_MODULE, | |
377 | .read = NULL, | |
378 | .write = amdgpu_ras_debugfs_ctrl_write, | |
379 | .llseek = default_llseek | |
380 | }; | |
381 | ||
084fe13b AG |
382 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
383 | .owner = THIS_MODULE, | |
384 | .read = NULL, | |
385 | .write = amdgpu_ras_debugfs_eeprom_write, | |
386 | .llseek = default_llseek | |
387 | }; | |
388 | ||
f77c7109 AD |
389 | /** |
390 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
391 | * | |
ef177d11 | 392 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
393 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
394 | * | |
395 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
396 | * (ce) error counts. | |
397 | * | |
398 | * The format of one line is below, | |
399 | * | |
400 | * [ce|ue]: count | |
401 | * | |
402 | * Example: | |
403 | * | |
404 | * .. code-block:: bash | |
405 | * | |
406 | * ue: 0 | |
407 | * ce: 1 | |
408 | * | |
409 | */ | |
c030f2e4 | 410 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
411 | struct device_attribute *attr, char *buf) | |
412 | { | |
413 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
414 | struct ras_query_if info = { | |
415 | .head = obj->head, | |
416 | }; | |
417 | ||
61380faa | 418 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
43c4d576 JC |
419 | return snprintf(buf, PAGE_SIZE, |
420 | "Query currently inaccessible\n"); | |
421 | ||
c030f2e4 | 422 | if (amdgpu_ras_error_query(obj->adev, &info)) |
423 | return -EINVAL; | |
424 | ||
425 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
426 | "ue", info.ue_count, | |
427 | "ce", info.ce_count); | |
428 | } | |
429 | ||
430 | /* obj begin */ | |
431 | ||
432 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
433 | #define alive_obj(obj) ((obj)->use) | |
434 | ||
435 | static inline void put_obj(struct ras_manager *obj) | |
436 | { | |
437 | if (obj && --obj->use == 0) | |
438 | list_del(&obj->node); | |
439 | if (obj && obj->use < 0) { | |
440 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
441 | } | |
442 | } | |
443 | ||
444 | /* make one obj and return it. */ | |
445 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
446 | struct ras_common_if *head) | |
447 | { | |
448 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
449 | struct ras_manager *obj; | |
450 | ||
451 | if (!con) | |
452 | return NULL; | |
453 | ||
454 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
455 | return NULL; | |
456 | ||
457 | obj = &con->objs[head->block]; | |
458 | /* already exist. return obj? */ | |
459 | if (alive_obj(obj)) | |
460 | return NULL; | |
461 | ||
462 | obj->head = *head; | |
463 | obj->adev = adev; | |
464 | list_add(&obj->node, &con->head); | |
465 | get_obj(obj); | |
466 | ||
467 | return obj; | |
468 | } | |
469 | ||
470 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 471 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 472 | struct ras_common_if *head) |
473 | { | |
474 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
475 | struct ras_manager *obj; | |
476 | int i; | |
477 | ||
478 | if (!con) | |
479 | return NULL; | |
480 | ||
481 | if (head) { | |
482 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
483 | return NULL; | |
484 | ||
485 | obj = &con->objs[head->block]; | |
486 | ||
487 | if (alive_obj(obj)) { | |
488 | WARN_ON(head->block != obj->head.block); | |
489 | return obj; | |
490 | } | |
491 | } else { | |
492 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
493 | obj = &con->objs[i]; | |
494 | if (alive_obj(obj)) { | |
495 | WARN_ON(i != obj->head.block); | |
496 | return obj; | |
497 | } | |
498 | } | |
499 | } | |
500 | ||
501 | return NULL; | |
502 | } | |
503 | /* obj end */ | |
504 | ||
a200034b JC |
505 | void amdgpu_ras_parse_status_code(struct amdgpu_device* adev, |
506 | const char* invoke_type, | |
507 | const char* block_name, | |
508 | enum ta_ras_status ret) | |
509 | { | |
510 | switch (ret) { | |
511 | case TA_RAS_STATUS__SUCCESS: | |
512 | return; | |
513 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
514 | dev_warn(adev->dev, | |
515 | "RAS WARN: %s %s currently unavailable\n", | |
516 | invoke_type, | |
517 | block_name); | |
518 | break; | |
519 | default: | |
520 | dev_err(adev->dev, | |
521 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
522 | invoke_type, | |
523 | block_name, | |
524 | ret); | |
525 | } | |
526 | } | |
527 | ||
c030f2e4 | 528 | /* feature ctl begin */ |
529 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
530 | struct ras_common_if *head) | |
531 | { | |
5caf466a | 532 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
533 | ||
534 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 535 | } |
536 | ||
537 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
538 | struct ras_common_if *head) | |
539 | { | |
540 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
541 | ||
542 | return con->features & BIT(head->block); | |
543 | } | |
544 | ||
545 | /* | |
546 | * if obj is not created, then create one. | |
547 | * set feature enable flag. | |
548 | */ | |
549 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
550 | struct ras_common_if *head, int enable) | |
551 | { | |
552 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
553 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
554 | ||
5caf466a | 555 | /* If hardware does not support ras, then do not create obj. |
556 | * But if hardware support ras, we can create the obj. | |
557 | * Ras framework checks con->hw_supported to see if it need do | |
558 | * corresponding initialization. | |
559 | * IP checks con->support to see if it need disable ras. | |
560 | */ | |
c030f2e4 | 561 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
562 | return 0; | |
563 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
564 | return 0; | |
565 | ||
566 | if (enable) { | |
567 | if (!obj) { | |
568 | obj = amdgpu_ras_create_obj(adev, head); | |
569 | if (!obj) | |
570 | return -EINVAL; | |
571 | } else { | |
572 | /* In case we create obj somewhere else */ | |
573 | get_obj(obj); | |
574 | } | |
575 | con->features |= BIT(head->block); | |
576 | } else { | |
577 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
578 | con->features &= ~BIT(head->block); | |
579 | put_obj(obj); | |
580 | } | |
581 | } | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | /* wrapper of psp_ras_enable_features */ | |
587 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
588 | struct ras_common_if *head, bool enable) | |
589 | { | |
590 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 591 | union ta_ras_cmd_input *info; |
c030f2e4 | 592 | int ret; |
593 | ||
594 | if (!con) | |
595 | return -EINVAL; | |
596 | ||
7fcffecf AB |
597 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
598 | if (!info) | |
599 | return -ENOMEM; | |
600 | ||
c030f2e4 | 601 | if (!enable) { |
7fcffecf | 602 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 603 | .block_id = amdgpu_ras_block_to_ta(head->block), |
604 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 605 | }; |
606 | } else { | |
7fcffecf | 607 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 608 | .block_id = amdgpu_ras_block_to_ta(head->block), |
609 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 610 | }; |
611 | } | |
612 | ||
613 | /* Do not enable if it is not allowed. */ | |
614 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
615 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
616 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
617 | ret = 0; | |
618 | goto out; | |
619 | } | |
c030f2e4 | 620 | |
bff77e86 | 621 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 622 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 623 | if (ret) { |
a200034b JC |
624 | amdgpu_ras_parse_status_code(adev, |
625 | enable ? "enable":"disable", | |
626 | ras_block_str(head->block), | |
627 | (enum ta_ras_status)ret); | |
bff77e86 | 628 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
629 | ret = -EAGAIN; |
630 | else | |
631 | ret = -EINVAL; | |
632 | ||
633 | goto out; | |
bff77e86 | 634 | } |
c030f2e4 | 635 | } |
636 | ||
637 | /* setup the obj */ | |
638 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
639 | ret = 0; |
640 | out: | |
641 | kfree(info); | |
642 | return ret; | |
c030f2e4 | 643 | } |
644 | ||
77de502b | 645 | /* Only used in device probe stage and called only once. */ |
646 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
647 | struct ras_common_if *head, bool enable) | |
648 | { | |
649 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
650 | int ret; | |
651 | ||
652 | if (!con) | |
653 | return -EINVAL; | |
654 | ||
655 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 656 | if (enable) { |
657 | /* There is no harm to issue a ras TA cmd regardless of | |
658 | * the currecnt ras state. | |
659 | * If current state == target state, it will do nothing | |
660 | * But sometimes it requests driver to reset and repost | |
661 | * with error code -EAGAIN. | |
662 | */ | |
663 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
664 | /* With old ras TA, we might fail to enable ras. | |
665 | * Log it and just setup the object. | |
666 | * TODO need remove this WA in the future. | |
667 | */ | |
668 | if (ret == -EINVAL) { | |
669 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
670 | if (!ret) | |
6952e99c GC |
671 | dev_info(adev->dev, |
672 | "RAS INFO: %s setup object\n", | |
7af23ebe | 673 | ras_block_str(head->block)); |
674 | } | |
675 | } else { | |
676 | /* setup the object then issue a ras TA disable cmd.*/ | |
677 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
678 | if (ret) | |
679 | return ret; | |
77de502b | 680 | |
77de502b | 681 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 682 | } |
77de502b | 683 | } else |
684 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
685 | ||
686 | return ret; | |
687 | } | |
688 | ||
c030f2e4 | 689 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
690 | bool bypass) | |
691 | { | |
692 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
693 | struct ras_manager *obj, *tmp; | |
694 | ||
695 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
696 | /* bypass psp. | |
697 | * aka just release the obj and corresponding flags | |
698 | */ | |
699 | if (bypass) { | |
700 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
701 | break; | |
702 | } else { | |
703 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
704 | break; | |
705 | } | |
289d513b | 706 | } |
c030f2e4 | 707 | |
708 | return con->features; | |
709 | } | |
710 | ||
711 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
712 | bool bypass) | |
713 | { | |
714 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
715 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
716 | int i; | |
191051a1 | 717 | const enum amdgpu_ras_error_type default_ras_type = |
718 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 719 | |
720 | for (i = 0; i < ras_block_count; i++) { | |
721 | struct ras_common_if head = { | |
722 | .block = i, | |
191051a1 | 723 | .type = default_ras_type, |
c030f2e4 | 724 | .sub_block_index = 0, |
725 | }; | |
726 | strcpy(head.name, ras_block_str(i)); | |
727 | if (bypass) { | |
728 | /* | |
729 | * bypass psp. vbios enable ras for us. | |
730 | * so just create the obj | |
731 | */ | |
732 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
733 | break; | |
734 | } else { | |
735 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
736 | break; | |
737 | } | |
289d513b | 738 | } |
c030f2e4 | 739 | |
740 | return con->features; | |
741 | } | |
742 | /* feature ctl end */ | |
743 | ||
744 | /* query/inject/cure begin */ | |
745 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
746 | struct ras_query_if *info) | |
747 | { | |
748 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 749 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 750 | int i; |
c030f2e4 | 751 | |
752 | if (!obj) | |
753 | return -EINVAL; | |
c030f2e4 | 754 | |
939e2258 HZ |
755 | switch (info->head.block) { |
756 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
757 | if (adev->umc.funcs->query_ras_error_count) |
758 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
759 | /* umc query_ras_error_address is also responsible for clearing |
760 | * error status | |
761 | */ | |
762 | if (adev->umc.funcs->query_ras_error_address) | |
763 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 764 | break; |
3e81ee9a HZ |
765 | case AMDGPU_RAS_BLOCK__SDMA: |
766 | if (adev->sdma.funcs->query_ras_error_count) { | |
767 | for (i = 0; i < adev->sdma.num_instances; i++) | |
768 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
769 | &err_data); | |
770 | } | |
771 | break; | |
83b0582c DL |
772 | case AMDGPU_RAS_BLOCK__GFX: |
773 | if (adev->gfx.funcs->query_ras_error_count) | |
774 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
775 | break; | |
9fb2d8de | 776 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
777 | if (adev->mmhub.funcs->query_ras_error_count) |
778 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 779 | break; |
d7bd680d GC |
780 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
781 | if (adev->nbio.funcs->query_ras_error_count) | |
782 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
783 | break; | |
ec01fe2d HZ |
784 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
785 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
786 | break; | |
939e2258 HZ |
787 | default: |
788 | break; | |
789 | } | |
05a58345 TZ |
790 | |
791 | obj->err_data.ue_count += err_data.ue_count; | |
792 | obj->err_data.ce_count += err_data.ce_count; | |
793 | ||
c030f2e4 | 794 | info->ue_count = obj->err_data.ue_count; |
795 | info->ce_count = obj->err_data.ce_count; | |
796 | ||
7c6e68c7 | 797 | if (err_data.ce_count) { |
6952e99c GC |
798 | dev_info(adev->dev, "%ld correctable hardware errors " |
799 | "detected in %s block, no user " | |
800 | "action is needed.\n", | |
801 | obj->err_data.ce_count, | |
802 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
803 | } |
804 | if (err_data.ue_count) { | |
6952e99c GC |
805 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
806 | "detected in %s block\n", | |
807 | obj->err_data.ue_count, | |
808 | ras_block_str(info->head.block)); | |
7c6e68c7 | 809 | } |
05a58345 | 810 | |
c030f2e4 | 811 | return 0; |
812 | } | |
813 | ||
814 | /* wrapper of psp_ras_trigger_error */ | |
815 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
816 | struct ras_inject_if *info) | |
817 | { | |
818 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
819 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 820 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
821 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 822 | .sub_block_index = info->head.sub_block_index, |
823 | .address = info->address, | |
824 | .value = info->value, | |
825 | }; | |
826 | int ret = 0; | |
827 | ||
828 | if (!obj) | |
829 | return -EINVAL; | |
830 | ||
a6c44d25 JC |
831 | /* Calculate XGMI relative offset */ |
832 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
833 | block_info.address = |
834 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
835 | block_info.address); | |
a6c44d25 JC |
836 | } |
837 | ||
83b0582c DL |
838 | switch (info->head.block) { |
839 | case AMDGPU_RAS_BLOCK__GFX: | |
840 | if (adev->gfx.funcs->ras_error_inject) | |
841 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
842 | else | |
843 | ret = -EINVAL; | |
844 | break; | |
845 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 846 | case AMDGPU_RAS_BLOCK__MMHUB: |
f3170352 | 847 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
d7bd680d | 848 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
849 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
850 | break; | |
851 | default: | |
6952e99c | 852 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 853 | ras_block_str(info->head.block)); |
83b0582c | 854 | ret = -EINVAL; |
a5dd40ca HZ |
855 | } |
856 | ||
a200034b JC |
857 | amdgpu_ras_parse_status_code(adev, |
858 | "inject", | |
859 | ras_block_str(info->head.block), | |
860 | (enum ta_ras_status)ret); | |
c030f2e4 | 861 | |
862 | return ret; | |
863 | } | |
864 | ||
865 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
866 | struct ras_cure_if *info) | |
867 | { | |
868 | /* psp fw has no cure interface for now. */ | |
869 | return 0; | |
870 | } | |
871 | ||
872 | /* get the total error counts on all IPs */ | |
64cc5414 | 873 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 874 | bool is_ce) |
875 | { | |
876 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
877 | struct ras_manager *obj; | |
878 | struct ras_err_data data = {0, 0}; | |
879 | ||
880 | if (!con) | |
64cc5414 | 881 | return 0; |
c030f2e4 | 882 | |
883 | list_for_each_entry(obj, &con->head, node) { | |
884 | struct ras_query_if info = { | |
885 | .head = obj->head, | |
886 | }; | |
887 | ||
888 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 889 | return 0; |
c030f2e4 | 890 | |
891 | data.ce_count += info.ce_count; | |
892 | data.ue_count += info.ue_count; | |
893 | } | |
894 | ||
895 | return is_ce ? data.ce_count : data.ue_count; | |
896 | } | |
897 | /* query/inject/cure end */ | |
898 | ||
899 | ||
900 | /* sysfs begin */ | |
901 | ||
466b1793 | 902 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
903 | struct ras_badpage **bps, unsigned int *count); | |
904 | ||
905 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
906 | { | |
907 | switch (flags) { | |
52dd95f2 | 908 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 909 | return "R"; |
52dd95f2 | 910 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 911 | return "P"; |
52dd95f2 | 912 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 913 | default: |
914 | return "F"; | |
915 | }; | |
916 | } | |
917 | ||
f77c7109 AD |
918 | /** |
919 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 920 | * |
921 | * It allows user to read the bad pages of vram on the gpu through | |
922 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
923 | * | |
924 | * It outputs multiple lines, and each line stands for one gpu page. | |
925 | * | |
926 | * The format of one line is below, | |
927 | * gpu pfn : gpu page size : flags | |
928 | * | |
929 | * gpu pfn and gpu page size are printed in hex format. | |
930 | * flags can be one of below character, | |
f77c7109 | 931 | * |
466b1793 | 932 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 933 | * |
466b1793 | 934 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
935 | * in next window of page_reserve. |
936 | * | |
466b1793 | 937 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
938 | * | |
f77c7109 AD |
939 | * Examples: |
940 | * | |
941 | * .. code-block:: bash | |
942 | * | |
943 | * 0x00000001 : 0x00001000 : R | |
944 | * 0x00000002 : 0x00001000 : P | |
945 | * | |
466b1793 | 946 | */ |
947 | ||
948 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
949 | struct kobject *kobj, struct bin_attribute *attr, | |
950 | char *buf, loff_t ppos, size_t count) | |
951 | { | |
952 | struct amdgpu_ras *con = | |
953 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
954 | struct amdgpu_device *adev = con->adev; | |
955 | const unsigned int element_size = | |
956 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
957 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
958 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 959 | ssize_t s = 0; |
960 | struct ras_badpage *bps = NULL; | |
961 | unsigned int bps_count = 0; | |
962 | ||
963 | memset(buf, 0, count); | |
964 | ||
965 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
966 | return 0; | |
967 | ||
968 | for (; start < end && start < bps_count; start++) | |
969 | s += scnprintf(&buf[s], element_size + 1, | |
970 | "0x%08x : 0x%08x : %1s\n", | |
971 | bps[start].bp, | |
972 | bps[start].size, | |
973 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
974 | ||
975 | kfree(bps); | |
976 | ||
977 | return s; | |
978 | } | |
979 | ||
c030f2e4 | 980 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
981 | struct device_attribute *attr, char *buf) | |
982 | { | |
983 | struct amdgpu_ras *con = | |
984 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 985 | |
5212a3bd | 986 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 987 | } |
988 | ||
989 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
990 | { | |
991 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
992 | struct attribute *attrs[] = { | |
993 | &con->features_attr.attr, | |
994 | NULL | |
995 | }; | |
466b1793 | 996 | struct bin_attribute *bin_attrs[] = { |
997 | &con->badpages_attr, | |
998 | NULL | |
999 | }; | |
c030f2e4 | 1000 | struct attribute_group group = { |
1001 | .name = "ras", | |
1002 | .attrs = attrs, | |
466b1793 | 1003 | .bin_attrs = bin_attrs, |
c030f2e4 | 1004 | }; |
1005 | ||
1006 | con->features_attr = (struct device_attribute) { | |
1007 | .attr = { | |
1008 | .name = "features", | |
1009 | .mode = S_IRUGO, | |
1010 | }, | |
1011 | .show = amdgpu_ras_sysfs_features_read, | |
1012 | }; | |
466b1793 | 1013 | |
1014 | con->badpages_attr = (struct bin_attribute) { | |
1015 | .attr = { | |
1016 | .name = "gpu_vram_bad_pages", | |
1017 | .mode = S_IRUGO, | |
1018 | }, | |
1019 | .size = 0, | |
1020 | .private = NULL, | |
1021 | .read = amdgpu_ras_sysfs_badpages_read, | |
1022 | }; | |
1023 | ||
163def43 | 1024 | sysfs_attr_init(attrs[0]); |
466b1793 | 1025 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 1026 | |
1027 | return sysfs_create_group(&adev->dev->kobj, &group); | |
1028 | } | |
1029 | ||
1030 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
1031 | { | |
1032 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1033 | struct attribute *attrs[] = { | |
1034 | &con->features_attr.attr, | |
1035 | NULL | |
1036 | }; | |
466b1793 | 1037 | struct bin_attribute *bin_attrs[] = { |
1038 | &con->badpages_attr, | |
1039 | NULL | |
1040 | }; | |
c030f2e4 | 1041 | struct attribute_group group = { |
1042 | .name = "ras", | |
1043 | .attrs = attrs, | |
466b1793 | 1044 | .bin_attrs = bin_attrs, |
c030f2e4 | 1045 | }; |
1046 | ||
1047 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1053 | struct ras_fs_if *head) | |
1054 | { | |
1055 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1056 | ||
1057 | if (!obj || obj->attr_inuse) | |
1058 | return -EINVAL; | |
1059 | ||
1060 | get_obj(obj); | |
1061 | ||
1062 | memcpy(obj->fs_data.sysfs_name, | |
1063 | head->sysfs_name, | |
1064 | sizeof(obj->fs_data.sysfs_name)); | |
1065 | ||
1066 | obj->sysfs_attr = (struct device_attribute){ | |
1067 | .attr = { | |
1068 | .name = obj->fs_data.sysfs_name, | |
1069 | .mode = S_IRUGO, | |
1070 | }, | |
1071 | .show = amdgpu_ras_sysfs_read, | |
1072 | }; | |
163def43 | 1073 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1074 | |
1075 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1076 | &obj->sysfs_attr.attr, | |
1077 | "ras")) { | |
1078 | put_obj(obj); | |
1079 | return -EINVAL; | |
1080 | } | |
1081 | ||
1082 | obj->attr_inuse = 1; | |
1083 | ||
1084 | return 0; | |
1085 | } | |
1086 | ||
1087 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1088 | struct ras_common_if *head) | |
1089 | { | |
1090 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1091 | ||
1092 | if (!obj || !obj->attr_inuse) | |
1093 | return -EINVAL; | |
1094 | ||
1095 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1096 | &obj->sysfs_attr.attr, | |
1097 | "ras"); | |
1098 | obj->attr_inuse = 0; | |
1099 | put_obj(obj); | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1105 | { | |
1106 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1107 | struct ras_manager *obj, *tmp; | |
1108 | ||
1109 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1110 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1111 | } | |
1112 | ||
1113 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | /* sysfs end */ | |
1118 | ||
ef177d11 AD |
1119 | /** |
1120 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1121 | * | |
1122 | * Normally when there is an uncorrectable error, the driver will reset | |
1123 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1124 | * the driver provides an interface to reboot the system automatically | |
1125 | * in that event. | |
1126 | * | |
1127 | * The following file in debugfs provides that interface: | |
1128 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1129 | * | |
1130 | * Usage: | |
1131 | * | |
1132 | * .. code-block:: bash | |
1133 | * | |
1134 | * echo true > .../ras/auto_reboot | |
1135 | * | |
1136 | */ | |
c030f2e4 | 1137 | /* debugfs begin */ |
450f30ea | 1138 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1139 | { |
1140 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1141 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 1142 | |
450f30ea | 1143 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
012dd14d GC |
1144 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1145 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1146 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1147 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1148 | |
1149 | /* | |
1150 | * After one uncorrectable error happens, usually GPU recovery will | |
1151 | * be scheduled. But due to the known problem in GPU recovery failing | |
1152 | * to bring GPU back, below interface provides one direct way to | |
1153 | * user to reboot system automatically in such case within | |
1154 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1155 | * will never be called. | |
1156 | */ | |
1157 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1158 | &con->reboot); | |
36ea1bd2 | 1159 | } |
1160 | ||
450f30ea | 1161 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1162 | struct ras_fs_if *head) |
1163 | { | |
1164 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1165 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1166 | |
1167 | if (!obj || obj->ent) | |
450f30ea | 1168 | return; |
c030f2e4 | 1169 | |
1170 | get_obj(obj); | |
1171 | ||
1172 | memcpy(obj->fs_data.debugfs_name, | |
1173 | head->debugfs_name, | |
1174 | sizeof(obj->fs_data.debugfs_name)); | |
1175 | ||
450f30ea GKH |
1176 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1177 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1178 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1179 | } |
1180 | ||
f9317014 TZ |
1181 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1182 | { | |
1183 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c1509f3f | 1184 | struct ras_manager *obj; |
f9317014 TZ |
1185 | struct ras_fs_if fs_info; |
1186 | ||
1187 | /* | |
1188 | * it won't be called in resume path, no need to check | |
1189 | * suspend and gpu reset status | |
1190 | */ | |
1191 | if (!con) | |
1192 | return; | |
1193 | ||
1194 | amdgpu_ras_debugfs_create_ctrl_node(adev); | |
1195 | ||
c1509f3f | 1196 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1197 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1198 | (obj->attr_inuse == 1)) { | |
1199 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1200 | ras_block_str(obj->head.block)); | |
1201 | fs_info.head = obj->head; | |
1202 | amdgpu_ras_debugfs_create(adev, &fs_info); | |
1203 | } | |
1204 | } | |
1205 | } | |
1206 | ||
450f30ea | 1207 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1208 | struct ras_common_if *head) |
1209 | { | |
1210 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1211 | ||
1212 | if (!obj || !obj->ent) | |
450f30ea | 1213 | return; |
c030f2e4 | 1214 | |
1215 | debugfs_remove(obj->ent); | |
1216 | obj->ent = NULL; | |
1217 | put_obj(obj); | |
c030f2e4 | 1218 | } |
1219 | ||
450f30ea | 1220 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1221 | { |
1222 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1223 | struct ras_manager *obj, *tmp; | |
1224 | ||
1225 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1226 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1227 | } | |
1228 | ||
012dd14d | 1229 | debugfs_remove_recursive(con->dir); |
c030f2e4 | 1230 | con->dir = NULL; |
c030f2e4 | 1231 | } |
1232 | /* debugfs end */ | |
1233 | ||
1234 | /* ras fs */ | |
1235 | ||
1236 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1237 | { | |
c030f2e4 | 1238 | amdgpu_ras_sysfs_create_feature_node(adev); |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
1243 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1244 | { | |
1245 | amdgpu_ras_debugfs_remove_all(adev); | |
1246 | amdgpu_ras_sysfs_remove_all(adev); | |
1247 | return 0; | |
1248 | } | |
1249 | /* ras fs end */ | |
1250 | ||
1251 | /* ih begin */ | |
1252 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1253 | { | |
1254 | struct ras_ih_data *data = &obj->ih_data; | |
1255 | struct amdgpu_iv_entry entry; | |
1256 | int ret; | |
cf04dfd0 | 1257 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1258 | |
1259 | while (data->rptr != data->wptr) { | |
1260 | rmb(); | |
1261 | memcpy(&entry, &data->ring[data->rptr], | |
1262 | data->element_size); | |
1263 | ||
1264 | wmb(); | |
1265 | data->rptr = (data->aligned_element_size + | |
1266 | data->rptr) % data->ring_size; | |
1267 | ||
1268 | /* Let IP handle its data, maybe we need get the output | |
1269 | * from the callback to udpate the error type/count, etc | |
1270 | */ | |
1271 | if (data->cb) { | |
cf04dfd0 | 1272 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1273 | /* ue will trigger an interrupt, and in that case |
1274 | * we need do a reset to recovery the whole system. | |
1275 | * But leave IP do that recovery, here we just dispatch | |
1276 | * the error. | |
1277 | */ | |
bd2280da | 1278 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1279 | /* these counts could be left as 0 if |
1280 | * some blocks do not count error number | |
1281 | */ | |
cf04dfd0 | 1282 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1283 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1284 | } |
c030f2e4 | 1285 | } |
1286 | } | |
1287 | } | |
1288 | ||
1289 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1290 | { | |
1291 | struct ras_ih_data *data = | |
1292 | container_of(work, struct ras_ih_data, ih_work); | |
1293 | struct ras_manager *obj = | |
1294 | container_of(data, struct ras_manager, ih_data); | |
1295 | ||
1296 | amdgpu_ras_interrupt_handler(obj); | |
1297 | } | |
1298 | ||
1299 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1300 | struct ras_dispatch_if *info) | |
1301 | { | |
1302 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1303 | struct ras_ih_data *data = &obj->ih_data; | |
1304 | ||
1305 | if (!obj) | |
1306 | return -EINVAL; | |
1307 | ||
1308 | if (data->inuse == 0) | |
1309 | return 0; | |
1310 | ||
1311 | /* Might be overflow... */ | |
1312 | memcpy(&data->ring[data->wptr], info->entry, | |
1313 | data->element_size); | |
1314 | ||
1315 | wmb(); | |
1316 | data->wptr = (data->aligned_element_size + | |
1317 | data->wptr) % data->ring_size; | |
1318 | ||
1319 | schedule_work(&data->ih_work); | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1325 | struct ras_ih_if *info) | |
1326 | { | |
1327 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1328 | struct ras_ih_data *data; | |
1329 | ||
1330 | if (!obj) | |
1331 | return -EINVAL; | |
1332 | ||
1333 | data = &obj->ih_data; | |
1334 | if (data->inuse == 0) | |
1335 | return 0; | |
1336 | ||
1337 | cancel_work_sync(&data->ih_work); | |
1338 | ||
1339 | kfree(data->ring); | |
1340 | memset(data, 0, sizeof(*data)); | |
1341 | put_obj(obj); | |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | ||
1346 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1347 | struct ras_ih_if *info) | |
1348 | { | |
1349 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1350 | struct ras_ih_data *data; | |
1351 | ||
1352 | if (!obj) { | |
1353 | /* in case we registe the IH before enable ras feature */ | |
1354 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1355 | if (!obj) | |
1356 | return -EINVAL; | |
1357 | } else | |
1358 | get_obj(obj); | |
1359 | ||
1360 | data = &obj->ih_data; | |
1361 | /* add the callback.etc */ | |
1362 | *data = (struct ras_ih_data) { | |
1363 | .inuse = 0, | |
1364 | .cb = info->cb, | |
1365 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1366 | .rptr = 0, | |
1367 | .wptr = 0, | |
1368 | }; | |
1369 | ||
1370 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1371 | ||
1372 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1373 | /* the ring can store 64 iv entries. */ | |
1374 | data->ring_size = 64 * data->aligned_element_size; | |
1375 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1376 | if (!data->ring) { | |
1377 | put_obj(obj); | |
1378 | return -ENOMEM; | |
1379 | } | |
1380 | ||
1381 | /* IH is ready */ | |
1382 | data->inuse = 1; | |
1383 | ||
1384 | return 0; | |
1385 | } | |
1386 | ||
1387 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1388 | { | |
1389 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1390 | struct ras_manager *obj, *tmp; | |
1391 | ||
1392 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1393 | struct ras_ih_if info = { | |
1394 | .head = obj->head, | |
1395 | }; | |
1396 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1397 | } | |
1398 | ||
1399 | return 0; | |
1400 | } | |
1401 | /* ih end */ | |
1402 | ||
313c8fd3 GC |
1403 | /* traversal all IPs except NBIO to query error counter */ |
1404 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1405 | { | |
1406 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1407 | struct ras_manager *obj; | |
1408 | ||
1409 | if (!con) | |
1410 | return; | |
1411 | ||
1412 | list_for_each_entry(obj, &con->head, node) { | |
1413 | struct ras_query_if info = { | |
1414 | .head = obj->head, | |
1415 | }; | |
1416 | ||
1417 | /* | |
1418 | * PCIE_BIF IP has one different isr by ras controller | |
1419 | * interrupt, the specific ras counter query will be | |
1420 | * done in that isr. So skip such block from common | |
1421 | * sync flood interrupt isr calling. | |
1422 | */ | |
1423 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1424 | continue; | |
1425 | ||
1426 | amdgpu_ras_error_query(adev, &info); | |
1427 | } | |
1428 | } | |
1429 | ||
c030f2e4 | 1430 | /* recovery begin */ |
466b1793 | 1431 | |
1432 | /* return 0 on success. | |
1433 | * caller need free bps. | |
1434 | */ | |
1435 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1436 | struct ras_badpage **bps, unsigned int *count) | |
1437 | { | |
1438 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1439 | struct ras_err_handler_data *data; | |
1440 | int i = 0; | |
1441 | int ret = 0; | |
1442 | ||
1443 | if (!con || !con->eh_data || !bps || !count) | |
1444 | return -EINVAL; | |
1445 | ||
1446 | mutex_lock(&con->recovery_lock); | |
1447 | data = con->eh_data; | |
1448 | if (!data || data->count == 0) { | |
1449 | *bps = NULL; | |
46cf2fec | 1450 | ret = -EINVAL; |
466b1793 | 1451 | goto out; |
1452 | } | |
1453 | ||
1454 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1455 | if (!*bps) { | |
1456 | ret = -ENOMEM; | |
1457 | goto out; | |
1458 | } | |
1459 | ||
1460 | for (; i < data->count; i++) { | |
1461 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1462 | .bp = data->bps[i].retired_page, |
466b1793 | 1463 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1464 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1465 | }; |
1466 | ||
1467 | if (data->last_reserved <= i) | |
52dd95f2 | 1468 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
9dc23a63 | 1469 | else if (data->bps_bo[i] == NULL) |
52dd95f2 | 1470 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1471 | } |
1472 | ||
1473 | *count = data->count; | |
1474 | out: | |
1475 | mutex_unlock(&con->recovery_lock); | |
1476 | return ret; | |
1477 | } | |
1478 | ||
c030f2e4 | 1479 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1480 | { | |
1481 | struct amdgpu_ras *ras = | |
1482 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1483 | struct amdgpu_device *remote_adev = NULL; |
1484 | struct amdgpu_device *adev = ras->adev; | |
1485 | struct list_head device_list, *device_list_handle = NULL; | |
1486 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false); | |
1487 | ||
1488 | /* Build list of devices to query RAS related errors */ | |
12c17b9d | 1489 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) |
b3dbd6d3 | 1490 | device_list_handle = &hive->device_list; |
12c17b9d GC |
1491 | else { |
1492 | INIT_LIST_HEAD(&device_list); | |
b3dbd6d3 JC |
1493 | list_add_tail(&adev->gmc.xgmi.head, &device_list); |
1494 | device_list_handle = &device_list; | |
1495 | } | |
c030f2e4 | 1496 | |
b3dbd6d3 JC |
1497 | list_for_each_entry(remote_adev, device_list_handle, gmc.xgmi.head) { |
1498 | amdgpu_ras_log_on_err_counter(remote_adev); | |
1499 | } | |
313c8fd3 | 1500 | |
93af20f7 HZ |
1501 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
1502 | amdgpu_device_gpu_recover(ras->adev, 0); | |
c030f2e4 | 1503 | atomic_set(&ras->in_recovery, 0); |
1504 | } | |
1505 | ||
c030f2e4 | 1506 | /* alloc/realloc bps array */ |
1507 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1508 | struct ras_err_handler_data *data, int pages) | |
1509 | { | |
1510 | unsigned int old_space = data->count + data->space_left; | |
1511 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1512 | unsigned int align_space = ALIGN(new_space, 512); |
1513 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1514 | struct amdgpu_bo **bps_bo = | |
1515 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1516 | ||
1517 | if (!bps || !bps_bo) { | |
1518 | kfree(bps); | |
1519 | kfree(bps_bo); | |
c030f2e4 | 1520 | return -ENOMEM; |
9dc23a63 | 1521 | } |
c030f2e4 | 1522 | |
1523 | if (data->bps) { | |
9dc23a63 | 1524 | memcpy(bps, data->bps, |
c030f2e4 | 1525 | data->count * sizeof(*data->bps)); |
1526 | kfree(data->bps); | |
1527 | } | |
9dc23a63 TZ |
1528 | if (data->bps_bo) { |
1529 | memcpy(bps_bo, data->bps_bo, | |
1530 | data->count * sizeof(*data->bps_bo)); | |
1531 | kfree(data->bps_bo); | |
1532 | } | |
c030f2e4 | 1533 | |
9dc23a63 TZ |
1534 | data->bps = bps; |
1535 | data->bps_bo = bps_bo; | |
c030f2e4 | 1536 | data->space_left += align_space - old_space; |
1537 | return 0; | |
1538 | } | |
1539 | ||
1540 | /* it deal with vram only. */ | |
1541 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1542 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1543 | { |
1544 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1545 | struct ras_err_handler_data *data; |
c030f2e4 | 1546 | int ret = 0; |
1547 | ||
73aa8e1a | 1548 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1549 | return 0; |
1550 | ||
1551 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1552 | data = con->eh_data; |
c030f2e4 | 1553 | if (!data) |
1554 | goto out; | |
1555 | ||
1556 | if (data->space_left <= pages) | |
1557 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1558 | ret = -ENOMEM; | |
1559 | goto out; | |
1560 | } | |
1561 | ||
9dc23a63 TZ |
1562 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1563 | data->count += pages; | |
c030f2e4 | 1564 | data->space_left -= pages; |
9dc23a63 | 1565 | |
c030f2e4 | 1566 | out: |
1567 | mutex_unlock(&con->recovery_lock); | |
1568 | ||
1569 | return ret; | |
1570 | } | |
1571 | ||
78ad00c9 TZ |
1572 | /* |
1573 | * write error record array to eeprom, the function should be | |
1574 | * protected by recovery_lock | |
1575 | */ | |
1576 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1577 | { | |
1578 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1579 | struct ras_err_handler_data *data; | |
8a3e801f | 1580 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1581 | int save_count; |
1582 | ||
1583 | if (!con || !con->eh_data) | |
1584 | return 0; | |
1585 | ||
8a3e801f | 1586 | control = &con->eeprom_control; |
78ad00c9 TZ |
1587 | data = con->eh_data; |
1588 | save_count = data->count - control->num_recs; | |
1589 | /* only new entries are saved */ | |
1590 | if (save_count > 0) | |
0771b0bf | 1591 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1592 | &data->bps[control->num_recs], |
1593 | true, | |
1594 | save_count)) { | |
6952e99c | 1595 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1596 | return -EIO; |
1597 | } | |
1598 | ||
1599 | return 0; | |
1600 | } | |
1601 | ||
1602 | /* | |
1603 | * read error record array in eeprom and reserve enough space for | |
1604 | * storing new bad pages | |
1605 | */ | |
1606 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1607 | { | |
1608 | struct amdgpu_ras_eeprom_control *control = | |
1609 | &adev->psp.ras.ras->eeprom_control; | |
1610 | struct eeprom_table_record *bps = NULL; | |
1611 | int ret = 0; | |
1612 | ||
1613 | /* no bad page record, skip eeprom access */ | |
1614 | if (!control->num_recs) | |
1615 | return ret; | |
1616 | ||
1617 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1618 | if (!bps) | |
1619 | return -ENOMEM; | |
1620 | ||
1621 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1622 | control->num_recs)) { | |
6952e99c | 1623 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1624 | ret = -EIO; |
1625 | goto out; | |
1626 | } | |
1627 | ||
1628 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1629 | ||
1630 | out: | |
1631 | kfree(bps); | |
1632 | return ret; | |
1633 | } | |
1634 | ||
6e4be987 TZ |
1635 | /* |
1636 | * check if an address belongs to bad page | |
1637 | * | |
1638 | * Note: this check is only for umc block | |
1639 | */ | |
1640 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1641 | uint64_t addr) | |
1642 | { | |
1643 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1644 | struct ras_err_handler_data *data; | |
1645 | int i; | |
1646 | bool ret = false; | |
1647 | ||
1648 | if (!con || !con->eh_data) | |
1649 | return ret; | |
1650 | ||
1651 | mutex_lock(&con->recovery_lock); | |
1652 | data = con->eh_data; | |
1653 | if (!data) | |
1654 | goto out; | |
1655 | ||
1656 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1657 | for (i = 0; i < data->count; i++) | |
1658 | if (addr == data->bps[i].retired_page) { | |
1659 | ret = true; | |
1660 | goto out; | |
1661 | } | |
1662 | ||
1663 | out: | |
1664 | mutex_unlock(&con->recovery_lock); | |
1665 | return ret; | |
1666 | } | |
1667 | ||
c030f2e4 | 1668 | /* called in gpu recovery/init */ |
1669 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1670 | { | |
1671 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1672 | struct ras_err_handler_data *data; |
c030f2e4 | 1673 | uint64_t bp; |
de7b45ba | 1674 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1675 | int i, ret = 0; |
c030f2e4 | 1676 | |
73aa8e1a | 1677 | if (!con || !con->eh_data) |
c030f2e4 | 1678 | return 0; |
1679 | ||
1680 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1681 | data = con->eh_data; |
1682 | if (!data) | |
1683 | goto out; | |
c030f2e4 | 1684 | /* reserve vram at driver post stage. */ |
1685 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1686 | bp = data->bps[i].retired_page; |
c030f2e4 | 1687 | |
ae115c81 TZ |
1688 | /* There are two cases of reserve error should be ignored: |
1689 | * 1) a ras bad page has been allocated (used by someone); | |
1690 | * 2) a ras bad page has been reserved (duplicate error injection | |
1691 | * for one page); | |
1692 | */ | |
a142ba88 AD |
1693 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, |
1694 | AMDGPU_GPU_PAGE_SIZE, | |
de7b45ba CK |
1695 | AMDGPU_GEM_DOMAIN_VRAM, |
1696 | &bo, NULL)) | |
6952e99c GC |
1697 | dev_warn(adev->dev, "RAS WARN: reserve vram for " |
1698 | "retired page %llx fail\n", bp); | |
c030f2e4 | 1699 | |
9dc23a63 | 1700 | data->bps_bo[i] = bo; |
c030f2e4 | 1701 | data->last_reserved = i + 1; |
de7b45ba | 1702 | bo = NULL; |
c030f2e4 | 1703 | } |
78ad00c9 TZ |
1704 | |
1705 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1706 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1707 | out: |
c030f2e4 | 1708 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1709 | return ret; |
c030f2e4 | 1710 | } |
1711 | ||
1712 | /* called when driver unload */ | |
1713 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1714 | { | |
1715 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1716 | struct ras_err_handler_data *data; |
c030f2e4 | 1717 | struct amdgpu_bo *bo; |
1718 | int i; | |
1719 | ||
73aa8e1a | 1720 | if (!con || !con->eh_data) |
c030f2e4 | 1721 | return 0; |
1722 | ||
1723 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1724 | data = con->eh_data; |
1725 | if (!data) | |
1726 | goto out; | |
1727 | ||
c030f2e4 | 1728 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1729 | bo = data->bps_bo[i]; |
c030f2e4 | 1730 | |
de7b45ba | 1731 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1732 | |
9dc23a63 | 1733 | data->bps_bo[i] = bo; |
c030f2e4 | 1734 | data->last_reserved = i; |
1735 | } | |
73aa8e1a | 1736 | out: |
c030f2e4 | 1737 | mutex_unlock(&con->recovery_lock); |
1738 | return 0; | |
1739 | } | |
1740 | ||
1a6fc071 | 1741 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1742 | { |
1743 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1744 | struct ras_err_handler_data **data; |
78ad00c9 | 1745 | int ret; |
c030f2e4 | 1746 | |
4d1337d2 AG |
1747 | if (con) |
1748 | data = &con->eh_data; | |
1749 | else | |
1750 | return 0; | |
1751 | ||
1a6fc071 TZ |
1752 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1753 | if (!*data) { | |
1754 | ret = -ENOMEM; | |
1755 | goto out; | |
1756 | } | |
c030f2e4 | 1757 | |
1758 | mutex_init(&con->recovery_lock); | |
1759 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1760 | atomic_set(&con->in_recovery, 0); | |
1761 | con->adev = adev; | |
1762 | ||
0771b0bf | 1763 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control); |
78ad00c9 | 1764 | if (ret) |
1a6fc071 | 1765 | goto free; |
78ad00c9 | 1766 | |
0771b0bf | 1767 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1768 | ret = amdgpu_ras_load_bad_pages(adev); |
1769 | if (ret) | |
1a6fc071 | 1770 | goto free; |
78ad00c9 TZ |
1771 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1772 | if (ret) | |
1a6fc071 | 1773 | goto release; |
78ad00c9 | 1774 | } |
c030f2e4 | 1775 | |
1776 | return 0; | |
1a6fc071 TZ |
1777 | |
1778 | release: | |
1779 | amdgpu_ras_release_bad_pages(adev); | |
1780 | free: | |
1a6fc071 TZ |
1781 | kfree((*data)->bps); |
1782 | kfree((*data)->bps_bo); | |
1783 | kfree(*data); | |
1995b3a3 | 1784 | con->eh_data = NULL; |
1a6fc071 | 1785 | out: |
6952e99c | 1786 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 TZ |
1787 | |
1788 | return ret; | |
c030f2e4 | 1789 | } |
1790 | ||
1791 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1792 | { | |
1793 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1794 | struct ras_err_handler_data *data = con->eh_data; | |
1795 | ||
1a6fc071 TZ |
1796 | /* recovery_init failed to init it, fini is useless */ |
1797 | if (!data) | |
1798 | return 0; | |
1799 | ||
c030f2e4 | 1800 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1801 | amdgpu_ras_release_bad_pages(adev); |
1802 | ||
1803 | mutex_lock(&con->recovery_lock); | |
1804 | con->eh_data = NULL; | |
1805 | kfree(data->bps); | |
1a6fc071 | 1806 | kfree(data->bps_bo); |
c030f2e4 | 1807 | kfree(data); |
1808 | mutex_unlock(&con->recovery_lock); | |
1809 | ||
1810 | return 0; | |
1811 | } | |
1812 | /* recovery end */ | |
1813 | ||
a564808e | 1814 | /* return 0 if ras will reset gpu and repost.*/ |
1815 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1816 | unsigned int block) | |
1817 | { | |
1818 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1819 | ||
1820 | if (!ras) | |
1821 | return -EINVAL; | |
1822 | ||
1823 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1824 | return 0; | |
1825 | } | |
1826 | ||
5caf466a | 1827 | /* |
1828 | * check hardware's ras ability which will be saved in hw_supported. | |
1829 | * if hardware does not support ras, we can skip some ras initializtion and | |
1830 | * forbid some ras operations from IP. | |
1831 | * if software itself, say boot parameter, limit the ras ability. We still | |
1832 | * need allow IP do some limited operations, like disable. In such case, | |
1833 | * we have to initialize ras as normal. but need check if operation is | |
1834 | * allowed or not in each function. | |
1835 | */ | |
1836 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1837 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1838 | { |
5caf466a | 1839 | *hw_supported = 0; |
1840 | *supported = 0; | |
c030f2e4 | 1841 | |
88474cca | 1842 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
baaeb610 HZ |
1843 | (adev->asic_type != CHIP_VEGA20 && |
1844 | adev->asic_type != CHIP_ARCTURUS)) | |
5caf466a | 1845 | return; |
b404ae82 | 1846 | |
88474cca | 1847 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
6952e99c | 1848 | dev_info(adev->dev, "HBM ECC is active.\n"); |
88474cca GC |
1849 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | |
1850 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1851 | } else | |
6952e99c | 1852 | dev_info(adev->dev, "HBM ECC is not presented.\n"); |
88474cca GC |
1853 | |
1854 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
6952e99c | 1855 | dev_info(adev->dev, "SRAM ECC is active.\n"); |
88474cca GC |
1856 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
1857 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1858 | } else | |
6952e99c | 1859 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); |
88474cca GC |
1860 | |
1861 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1862 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1863 | |
5caf466a | 1864 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1865 | 0 : *hw_supported & amdgpu_ras_mask; |
c030f2e4 | 1866 | } |
1867 | ||
1868 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1869 | { | |
1870 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1871 | int r; |
c030f2e4 | 1872 | |
b404ae82 | 1873 | if (con) |
c030f2e4 | 1874 | return 0; |
1875 | ||
1876 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1877 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1878 | GFP_KERNEL|__GFP_ZERO); | |
1879 | if (!con) | |
1880 | return -ENOMEM; | |
1881 | ||
1882 | con->objs = (struct ras_manager *)(con + 1); | |
1883 | ||
1884 | amdgpu_ras_set_context(adev, con); | |
1885 | ||
5caf466a | 1886 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1887 | &con->supported); | |
fb2a3607 HZ |
1888 | if (!con->hw_supported) { |
1889 | amdgpu_ras_set_context(adev, NULL); | |
1890 | kfree(con); | |
1891 | return 0; | |
1892 | } | |
1893 | ||
c030f2e4 | 1894 | con->features = 0; |
1895 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1896 | /* Might need get this flag from vbios. */ |
1897 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1898 | |
4e644fff HZ |
1899 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1900 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1901 | if (r) | |
1902 | return r; | |
1903 | } | |
1904 | ||
1905 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1906 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
1907 | if (r) | |
1908 | return r; | |
1909 | } | |
1910 | ||
c030f2e4 | 1911 | amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK; |
1912 | ||
c030f2e4 | 1913 | if (amdgpu_ras_fs_init(adev)) |
1914 | goto fs_out; | |
1915 | ||
6952e99c | 1916 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 1917 | "hardware ability[%x] ras_mask[%x]\n", |
1918 | con->hw_supported, con->supported); | |
c030f2e4 | 1919 | return 0; |
1920 | fs_out: | |
c030f2e4 | 1921 | amdgpu_ras_set_context(adev, NULL); |
1922 | kfree(con); | |
1923 | ||
1924 | return -EINVAL; | |
1925 | } | |
1926 | ||
b293e891 HZ |
1927 | /* helper function to handle common stuff in ip late init phase */ |
1928 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
1929 | struct ras_common_if *ras_block, | |
1930 | struct ras_fs_if *fs_info, | |
1931 | struct ras_ih_if *ih_info) | |
1932 | { | |
1933 | int r; | |
1934 | ||
1935 | /* disable RAS feature per IP block if it is not supported */ | |
1936 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
1937 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
1942 | if (r) { | |
1943 | if (r == -EAGAIN) { | |
1944 | /* request gpu reset. will run again */ | |
1945 | amdgpu_ras_request_reset_on_boot(adev, | |
1946 | ras_block->block); | |
1947 | return 0; | |
1948 | } else if (adev->in_suspend || adev->in_gpu_reset) { | |
1949 | /* in resume phase, if fail to enable ras, | |
1950 | * clean up all ras fs nodes, and disable ras */ | |
1951 | goto cleanup; | |
1952 | } else | |
1953 | return r; | |
1954 | } | |
1955 | ||
1956 | /* in resume phase, no need to create ras fs node */ | |
a891d239 | 1957 | if (adev->in_suspend || adev->in_gpu_reset) |
b293e891 HZ |
1958 | return 0; |
1959 | ||
1960 | if (ih_info->cb) { | |
1961 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
1962 | if (r) | |
1963 | goto interrupt; | |
1964 | } | |
1965 | ||
b293e891 HZ |
1966 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
1967 | if (r) | |
1968 | goto sysfs; | |
1969 | ||
1970 | return 0; | |
1971 | cleanup: | |
1972 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
1973 | sysfs: | |
b293e891 HZ |
1974 | if (ih_info->cb) |
1975 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1976 | interrupt: | |
1977 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1978 | return r; | |
1979 | } | |
1980 | ||
1981 | /* helper function to remove ras fs node and interrupt handler */ | |
1982 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
1983 | struct ras_common_if *ras_block, | |
1984 | struct ras_ih_if *ih_info) | |
1985 | { | |
1986 | if (!ras_block || !ih_info) | |
1987 | return; | |
1988 | ||
1989 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 HZ |
1990 | if (ih_info->cb) |
1991 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1992 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1993 | } | |
1994 | ||
a564808e | 1995 | /* do some init work after IP late init as dependence. |
511fdbc3 | 1996 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 1997 | */ |
511fdbc3 | 1998 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 1999 | { |
2000 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2001 | struct ras_manager *obj, *tmp; | |
2002 | ||
2003 | if (!con) | |
2004 | return; | |
2005 | ||
108c6a63 | 2006 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2007 | /* Set up all other IPs which are not implemented. There is a |
2008 | * tricky thing that IP's actual ras error type should be | |
2009 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2010 | * ERROR_NONE make sense anyway. | |
2011 | */ | |
2012 | amdgpu_ras_enable_all_features(adev, 1); | |
2013 | ||
2014 | /* We enable ras on all hw_supported block, but as boot | |
2015 | * parameter might disable some of them and one or more IP has | |
2016 | * not implemented yet. So we disable them on behalf. | |
2017 | */ | |
108c6a63 | 2018 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2019 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2020 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2021 | /* there should be no any reference. */ | |
2022 | WARN_ON(alive_obj(obj)); | |
2023 | } | |
191051a1 | 2024 | } |
108c6a63 | 2025 | } |
a564808e | 2026 | |
2027 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2028 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2029 | /* setup ras obj state as disabled. | |
2030 | * for init_by_vbios case. | |
2031 | * if we want to enable ras, just enable it in a normal way. | |
2032 | * If we want do disable it, need setup ras obj as enabled, | |
2033 | * then issue another TA disable cmd. | |
2034 | * See feature_enable_on_boot | |
2035 | */ | |
2036 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2037 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2038 | } |
108c6a63 | 2039 | } |
2040 | ||
511fdbc3 | 2041 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2042 | { | |
2043 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2044 | ||
2045 | if (!con) | |
2046 | return; | |
2047 | ||
2048 | amdgpu_ras_disable_all_features(adev, 0); | |
2049 | /* Make sure all ras objects are disabled. */ | |
2050 | if (con->features) | |
2051 | amdgpu_ras_disable_all_features(adev, 1); | |
2052 | } | |
2053 | ||
c030f2e4 | 2054 | /* do some fini work before IP fini as dependence */ |
2055 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2056 | { | |
2057 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2058 | ||
2059 | if (!con) | |
2060 | return 0; | |
2061 | ||
2062 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2063 | amdgpu_ras_disable_all_features(adev, 0); | |
2064 | amdgpu_ras_recovery_fini(adev); | |
2065 | return 0; | |
2066 | } | |
2067 | ||
2068 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2069 | { | |
2070 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2071 | ||
2072 | if (!con) | |
2073 | return 0; | |
2074 | ||
2075 | amdgpu_ras_fs_fini(adev); | |
2076 | amdgpu_ras_interrupt_remove_all(adev); | |
2077 | ||
2078 | WARN(con->features, "Feature mask is not cleared"); | |
2079 | ||
2080 | if (con->features) | |
2081 | amdgpu_ras_disable_all_features(adev, 1); | |
2082 | ||
2083 | amdgpu_ras_set_context(adev, NULL); | |
2084 | kfree(con); | |
2085 | ||
2086 | return 0; | |
2087 | } | |
7c6e68c7 AG |
2088 | |
2089 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2090 | { | |
ed606f8a AG |
2091 | uint32_t hw_supported, supported; |
2092 | ||
2093 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2094 | if (!hw_supported) | |
2095 | return; | |
2096 | ||
7c6e68c7 | 2097 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2098 | dev_info(adev->dev, "uncorrectable hardware error" |
2099 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2100 | |
61934624 | 2101 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2102 | } |
2103 | } |