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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
f50160cf | 37 | #include "atom.h" |
c030f2e4 | 38 | |
eb0c3cd4 GC |
39 | static const char *RAS_FS_NAME = "ras"; |
40 | ||
c030f2e4 | 41 | const char *ras_error_string[] = { |
42 | "none", | |
43 | "parity", | |
44 | "single_correctable", | |
45 | "multi_uncorrectable", | |
46 | "poison", | |
47 | }; | |
48 | ||
49 | const char *ras_block_string[] = { | |
50 | "umc", | |
51 | "sdma", | |
52 | "gfx", | |
53 | "mmhub", | |
54 | "athub", | |
55 | "pcie_bif", | |
56 | "hdp", | |
57 | "xgmi_wafl", | |
58 | "df", | |
59 | "smn", | |
60 | "sem", | |
61 | "mp0", | |
62 | "mp1", | |
63 | "fuse", | |
64 | }; | |
65 | ||
66 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
67 | #define ras_block_str(i) (ras_block_string[i]) | |
68 | ||
108c6a63 | 69 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
70 | ||
7cdc2ee3 TZ |
71 | /* inject address is 52 bits */ |
72 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
73 | ||
c84d4670 GC |
74 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
75 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
76 | ||
52dd95f2 GC |
77 | enum amdgpu_ras_retire_page_reservation { |
78 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
79 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
80 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
81 | }; | |
7c6e68c7 AG |
82 | |
83 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
84 | ||
676deb38 DL |
85 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
86 | uint64_t addr); | |
6e4be987 TZ |
87 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
88 | uint64_t addr); | |
89 | ||
61380faa JC |
90 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
91 | { | |
a9d82d2f | 92 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
93 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
94 | } | |
95 | ||
f3167919 | 96 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 97 | { |
a9d82d2f | 98 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
99 | return amdgpu_ras_get_context(adev)->error_query_ready; |
100 | ||
101 | return false; | |
102 | } | |
103 | ||
cbb8f989 JC |
104 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
105 | { | |
106 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
107 | struct eeprom_table_record err_rec; | |
108 | ||
109 | if ((address >= adev->gmc.mc_vram_size) || | |
110 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
111 | dev_warn(adev->dev, | |
112 | "RAS WARN: input address 0x%llx is invalid.\n", | |
113 | address); | |
114 | return -EINVAL; | |
115 | } | |
116 | ||
117 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
118 | dev_warn(adev->dev, | |
80b0cd0f | 119 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
120 | address); |
121 | return 0; | |
122 | } | |
123 | ||
124 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
125 | ||
126 | err_rec.address = address; | |
127 | err_rec.retired_page = address >> AMDGPU_GPU_PAGE_SHIFT; | |
128 | err_rec.ts = (uint64_t)ktime_get_real_seconds(); | |
129 | err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE; | |
130 | ||
131 | err_data.err_addr = &err_rec; | |
132 | err_data.err_addr_cnt = 1; | |
133 | ||
134 | if (amdgpu_bad_page_threshold != 0) { | |
135 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
136 | err_data.err_addr_cnt); | |
137 | amdgpu_ras_save_bad_pages(adev); | |
138 | } | |
139 | ||
140 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
141 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
142 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
c030f2e4 | 147 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
148 | size_t size, loff_t *pos) | |
149 | { | |
150 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
151 | struct ras_query_if info = { | |
152 | .head = obj->head, | |
153 | }; | |
154 | ssize_t s; | |
155 | char val[128]; | |
156 | ||
761d86d3 | 157 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 158 | return -EINVAL; |
159 | ||
160 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
161 | "ue", info.ue_count, | |
162 | "ce", info.ce_count); | |
163 | if (*pos >= s) | |
164 | return 0; | |
165 | ||
166 | s -= *pos; | |
167 | s = min_t(u64, s, size); | |
168 | ||
169 | ||
170 | if (copy_to_user(buf, &val[*pos], s)) | |
171 | return -EINVAL; | |
172 | ||
173 | *pos += s; | |
174 | ||
175 | return s; | |
176 | } | |
177 | ||
c030f2e4 | 178 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
179 | .owner = THIS_MODULE, | |
180 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 181 | .write = NULL, |
c030f2e4 | 182 | .llseek = default_llseek |
183 | }; | |
184 | ||
96ebb307 | 185 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
186 | { | |
187 | int i; | |
188 | ||
189 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
190 | *block_id = i; | |
191 | if (strcmp(name, ras_block_str(i)) == 0) | |
192 | return 0; | |
193 | } | |
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
198 | const char __user *buf, size_t size, | |
199 | loff_t *pos, struct ras_debug_if *data) | |
200 | { | |
201 | ssize_t s = min_t(u64, 64, size); | |
202 | char str[65]; | |
203 | char block_name[33]; | |
204 | char err[9] = "ue"; | |
205 | int op = -1; | |
206 | int block_id; | |
44494f96 | 207 | uint32_t sub_block; |
96ebb307 | 208 | u64 address, value; |
209 | ||
210 | if (*pos) | |
211 | return -EINVAL; | |
212 | *pos = size; | |
213 | ||
214 | memset(str, 0, sizeof(str)); | |
215 | memset(data, 0, sizeof(*data)); | |
216 | ||
217 | if (copy_from_user(str, buf, s)) | |
218 | return -EINVAL; | |
219 | ||
220 | if (sscanf(str, "disable %32s", block_name) == 1) | |
221 | op = 0; | |
222 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
223 | op = 1; | |
224 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
225 | op = 2; | |
6df23f4c | 226 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 227 | op = 3; |
b076296b | 228 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 229 | /* ascii string, but commands are not matched. */ |
230 | return -EINVAL; | |
231 | ||
232 | if (op != -1) { | |
cbb8f989 | 233 | if (op == 3) { |
546aa546 LT |
234 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
235 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 236 | return -EINVAL; |
cbb8f989 JC |
237 | |
238 | data->op = op; | |
239 | data->inject.address = address; | |
240 | ||
241 | return 0; | |
242 | } | |
243 | ||
96ebb307 | 244 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
245 | return -EINVAL; | |
246 | ||
247 | data->head.block = block_id; | |
e1063493 TZ |
248 | /* only ue and ce errors are supported */ |
249 | if (!memcmp("ue", err, 2)) | |
250 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
251 | else if (!memcmp("ce", err, 2)) | |
252 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
253 | else | |
254 | return -EINVAL; | |
255 | ||
96ebb307 | 256 | data->op = op; |
257 | ||
258 | if (op == 2) { | |
546aa546 LT |
259 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", |
260 | &sub_block, &address, &value) != 3 && | |
261 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
262 | &sub_block, &address, &value) != 3) |
263 | return -EINVAL; | |
44494f96 | 264 | data->head.sub_block_index = sub_block; |
96ebb307 | 265 | data->inject.address = address; |
266 | data->inject.value = value; | |
267 | } | |
268 | } else { | |
73aa8e1a | 269 | if (size < sizeof(*data)) |
96ebb307 | 270 | return -EINVAL; |
271 | ||
272 | if (copy_from_user(data, buf, sizeof(*data))) | |
273 | return -EINVAL; | |
274 | } | |
275 | ||
276 | return 0; | |
277 | } | |
7c6e68c7 | 278 | |
74abc221 TSD |
279 | /** |
280 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 281 | * |
737c375b | 282 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 283 | * |
284 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 285 | * |
286 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 287 | * |
288 | * head has four members, they are block, type, sub_block_index, name. | |
289 | * block: which IP will be under control. | |
290 | * type: what kind of error will be enabled/disabled/injected. | |
291 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
292 | * name: the name of IP. | |
293 | * | |
294 | * inject has two more members than head, they are address, value. | |
295 | * As their names indicate, inject operation will write the | |
296 | * value to the address. | |
297 | * | |
ef177d11 | 298 | * The second member: struct ras_debug_if::op. |
c688a06b | 299 | * It has three kinds of operations. |
879e723d AZ |
300 | * |
301 | * - 0: disable RAS on the block. Take ::head as its data. | |
302 | * - 1: enable RAS on the block. Take ::head as its data. | |
303 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 304 | * |
96ebb307 | 305 | * How to use the interface? |
ef177d11 | 306 | * |
737c375b | 307 | * In a program |
ef177d11 | 308 | * |
737c375b LT |
309 | * Copy the struct ras_debug_if in your code and initialize it. |
310 | * Write the struct to the control interface. | |
ef177d11 | 311 | * |
737c375b | 312 | * From shell |
96ebb307 | 313 | * |
879e723d AZ |
314 | * .. code-block:: bash |
315 | * | |
737c375b LT |
316 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
317 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
318 | * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
879e723d | 319 | * |
737c375b | 320 | * Where N, is the card which you want to affect. |
ef177d11 | 321 | * |
737c375b LT |
322 | * "disable" requires only the block. |
323 | * "enable" requires the block and error type. | |
324 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 325 | * |
737c375b | 326 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 327 | * see ras_block_string[] for details |
c666bbf0 | 328 | * |
737c375b LT |
329 | * The error type is one of: ue, ce, where, |
330 | * ue is multi-uncorrectable | |
331 | * ce is single-correctable | |
c666bbf0 | 332 | * |
737c375b LT |
333 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
334 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
879e723d | 335 | * |
737c375b | 336 | * For instance, |
879e723d AZ |
337 | * |
338 | * .. code-block:: bash | |
96ebb307 | 339 | * |
44494f96 TZ |
340 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
341 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 342 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
343 | * | |
737c375b | 344 | * How to check the result of the operation? |
36ea1bd2 | 345 | * |
737c375b | 346 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 347 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
348 | * | |
737c375b LT |
349 | * To check inject, see the corresponding error count at, |
350 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 351 | * |
879e723d | 352 | * .. note:: |
ef177d11 | 353 | * Operations are only allowed on blocks which are supported. |
737c375b | 354 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
355 | * to see which blocks support RAS on a particular asic. |
356 | * | |
36ea1bd2 | 357 | */ |
358 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
359 | size_t size, loff_t *pos) | |
360 | { | |
361 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
362 | struct ras_debug_if data; | |
363 | int ret = 0; | |
364 | ||
61380faa | 365 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
366 | dev_warn(adev->dev, "RAS WARN: error injection " |
367 | "currently inaccessible\n"); | |
43c4d576 JC |
368 | return size; |
369 | } | |
370 | ||
96ebb307 | 371 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
372 | if (ret) | |
36ea1bd2 | 373 | return -EINVAL; |
374 | ||
80b0cd0f | 375 | if (data.op == 3) { |
cbb8f989 | 376 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 377 | if (!ret) |
cbb8f989 JC |
378 | return size; |
379 | else | |
380 | return ret; | |
381 | } | |
382 | ||
36ea1bd2 | 383 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
384 | return -EINVAL; | |
385 | ||
386 | switch (data.op) { | |
387 | case 0: | |
388 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
389 | break; | |
390 | case 1: | |
391 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
392 | break; | |
393 | case 2: | |
7cdc2ee3 TZ |
394 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
395 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
396 | dev_warn(adev->dev, "RAS WARN: input address " |
397 | "0x%llx is invalid.", | |
398 | data.inject.address); | |
7cdc2ee3 TZ |
399 | ret = -EINVAL; |
400 | break; | |
401 | } | |
402 | ||
6e4be987 TZ |
403 | /* umc ce/ue error injection for a bad page is not allowed */ |
404 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
405 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
406 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
407 | "as bad before error injection!\n", | |
6e4be987 TZ |
408 | data.inject.address); |
409 | break; | |
410 | } | |
411 | ||
7cdc2ee3 | 412 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 413 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
414 | break; | |
96ebb307 | 415 | default: |
416 | ret = -EINVAL; | |
417 | break; | |
374bf7bd | 418 | } |
36ea1bd2 | 419 | |
420 | if (ret) | |
421 | return -EINVAL; | |
422 | ||
423 | return size; | |
424 | } | |
425 | ||
084fe13b AG |
426 | /** |
427 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
428 | * | |
f77c7109 | 429 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 430 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
431 | * a way to reset the EEPROM, e.g., after testing error injection. |
432 | * | |
433 | * Usage: | |
434 | * | |
435 | * .. code-block:: bash | |
436 | * | |
437 | * echo 1 > ../ras/ras_eeprom_reset | |
438 | * | |
439 | * will reset EEPROM table to 0 entries. | |
440 | * | |
084fe13b AG |
441 | */ |
442 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
443 | size_t size, loff_t *pos) | |
444 | { | |
bf0b91b7 GC |
445 | struct amdgpu_device *adev = |
446 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
447 | int ret; |
448 | ||
bf0b91b7 GC |
449 | ret = amdgpu_ras_eeprom_reset_table( |
450 | &(amdgpu_ras_get_context(adev)->eeprom_control)); | |
084fe13b | 451 | |
bf0b91b7 GC |
452 | if (ret == 1) { |
453 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; | |
454 | return size; | |
455 | } else { | |
456 | return -EIO; | |
457 | } | |
084fe13b AG |
458 | } |
459 | ||
36ea1bd2 | 460 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
461 | .owner = THIS_MODULE, | |
462 | .read = NULL, | |
463 | .write = amdgpu_ras_debugfs_ctrl_write, | |
464 | .llseek = default_llseek | |
465 | }; | |
466 | ||
084fe13b AG |
467 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
468 | .owner = THIS_MODULE, | |
469 | .read = NULL, | |
470 | .write = amdgpu_ras_debugfs_eeprom_write, | |
471 | .llseek = default_llseek | |
472 | }; | |
473 | ||
f77c7109 AD |
474 | /** |
475 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
476 | * | |
ef177d11 | 477 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
478 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
479 | * | |
480 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
481 | * (ce) error counts. | |
482 | * | |
483 | * The format of one line is below, | |
484 | * | |
485 | * [ce|ue]: count | |
486 | * | |
487 | * Example: | |
488 | * | |
489 | * .. code-block:: bash | |
490 | * | |
491 | * ue: 0 | |
492 | * ce: 1 | |
493 | * | |
494 | */ | |
c030f2e4 | 495 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
496 | struct device_attribute *attr, char *buf) | |
497 | { | |
498 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
499 | struct ras_query_if info = { | |
500 | .head = obj->head, | |
501 | }; | |
502 | ||
61380faa | 503 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 504 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 505 | |
761d86d3 | 506 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 507 | return -EINVAL; |
508 | ||
1f0d8e37 MJ |
509 | |
510 | if (obj->adev->asic_type == CHIP_ALDEBARAN) { | |
511 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) | |
512 | DRM_WARN("Failed to reset error counter and error status"); | |
513 | } | |
514 | ||
36000c7a TT |
515 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
516 | "ce", info.ce_count); | |
c030f2e4 | 517 | } |
518 | ||
519 | /* obj begin */ | |
520 | ||
521 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
522 | #define alive_obj(obj) ((obj)->use) | |
523 | ||
524 | static inline void put_obj(struct ras_manager *obj) | |
525 | { | |
f0872686 | 526 | if (obj && (--obj->use == 0)) |
c030f2e4 | 527 | list_del(&obj->node); |
f0872686 BZ |
528 | if (obj && (obj->use < 0)) |
529 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
c030f2e4 | 530 | } |
531 | ||
532 | /* make one obj and return it. */ | |
533 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
534 | struct ras_common_if *head) | |
535 | { | |
536 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
537 | struct ras_manager *obj; | |
538 | ||
8ab0d6f0 | 539 | if (!adev->ras_enabled || !con) |
c030f2e4 | 540 | return NULL; |
541 | ||
542 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
543 | return NULL; | |
544 | ||
545 | obj = &con->objs[head->block]; | |
546 | /* already exist. return obj? */ | |
547 | if (alive_obj(obj)) | |
548 | return NULL; | |
549 | ||
550 | obj->head = *head; | |
551 | obj->adev = adev; | |
552 | list_add(&obj->node, &con->head); | |
553 | get_obj(obj); | |
554 | ||
555 | return obj; | |
556 | } | |
557 | ||
558 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 559 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 560 | struct ras_common_if *head) |
561 | { | |
562 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
563 | struct ras_manager *obj; | |
564 | int i; | |
565 | ||
8ab0d6f0 | 566 | if (!adev->ras_enabled || !con) |
c030f2e4 | 567 | return NULL; |
568 | ||
569 | if (head) { | |
570 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
571 | return NULL; | |
572 | ||
573 | obj = &con->objs[head->block]; | |
574 | ||
575 | if (alive_obj(obj)) { | |
576 | WARN_ON(head->block != obj->head.block); | |
577 | return obj; | |
578 | } | |
579 | } else { | |
580 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
581 | obj = &con->objs[i]; | |
582 | if (alive_obj(obj)) { | |
583 | WARN_ON(i != obj->head.block); | |
584 | return obj; | |
585 | } | |
586 | } | |
587 | } | |
588 | ||
589 | return NULL; | |
590 | } | |
591 | /* obj end */ | |
592 | ||
593 | /* feature ctl begin */ | |
594 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 595 | struct ras_common_if *head) |
c030f2e4 | 596 | { |
8ab0d6f0 | 597 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 598 | } |
599 | ||
600 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
601 | struct ras_common_if *head) | |
602 | { | |
603 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
604 | ||
605 | return con->features & BIT(head->block); | |
606 | } | |
607 | ||
608 | /* | |
609 | * if obj is not created, then create one. | |
610 | * set feature enable flag. | |
611 | */ | |
612 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
613 | struct ras_common_if *head, int enable) | |
614 | { | |
615 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
616 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
617 | ||
5caf466a | 618 | /* If hardware does not support ras, then do not create obj. |
619 | * But if hardware support ras, we can create the obj. | |
620 | * Ras framework checks con->hw_supported to see if it need do | |
621 | * corresponding initialization. | |
622 | * IP checks con->support to see if it need disable ras. | |
623 | */ | |
c030f2e4 | 624 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
625 | return 0; | |
626 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
627 | return 0; | |
628 | ||
629 | if (enable) { | |
630 | if (!obj) { | |
631 | obj = amdgpu_ras_create_obj(adev, head); | |
632 | if (!obj) | |
633 | return -EINVAL; | |
634 | } else { | |
635 | /* In case we create obj somewhere else */ | |
636 | get_obj(obj); | |
637 | } | |
638 | con->features |= BIT(head->block); | |
639 | } else { | |
640 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 641 | con->features &= ~BIT(head->block); |
c030f2e4 | 642 | put_obj(obj); |
643 | } | |
644 | } | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | /* wrapper of psp_ras_enable_features */ | |
650 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
651 | struct ras_common_if *head, bool enable) | |
652 | { | |
653 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 654 | union ta_ras_cmd_input *info; |
c030f2e4 | 655 | int ret; |
656 | ||
657 | if (!con) | |
658 | return -EINVAL; | |
659 | ||
f3729f7b | 660 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
661 | if (!info) |
662 | return -ENOMEM; | |
663 | ||
c030f2e4 | 664 | if (!enable) { |
7fcffecf | 665 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 666 | .block_id = amdgpu_ras_block_to_ta(head->block), |
667 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 668 | }; |
669 | } else { | |
7fcffecf | 670 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 671 | .block_id = amdgpu_ras_block_to_ta(head->block), |
672 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 673 | }; |
674 | } | |
675 | ||
676 | /* Do not enable if it is not allowed. */ | |
677 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
678 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
679 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
680 | ret = 0; | |
681 | goto out; | |
682 | } | |
c030f2e4 | 683 | |
bff77e86 | 684 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 685 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 686 | if (ret) { |
011907fd DL |
687 | dev_err(adev->dev, "ras %s %s failed %d\n", |
688 | enable ? "enable":"disable", | |
689 | ras_block_str(head->block), | |
690 | ret); | |
7fcffecf | 691 | goto out; |
bff77e86 | 692 | } |
c030f2e4 | 693 | } |
694 | ||
695 | /* setup the obj */ | |
696 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
697 | ret = 0; |
698 | out: | |
699 | kfree(info); | |
700 | return ret; | |
c030f2e4 | 701 | } |
702 | ||
77de502b | 703 | /* Only used in device probe stage and called only once. */ |
704 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
705 | struct ras_common_if *head, bool enable) | |
706 | { | |
707 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
708 | int ret; | |
709 | ||
710 | if (!con) | |
711 | return -EINVAL; | |
712 | ||
713 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 714 | if (enable) { |
715 | /* There is no harm to issue a ras TA cmd regardless of | |
716 | * the currecnt ras state. | |
717 | * If current state == target state, it will do nothing | |
718 | * But sometimes it requests driver to reset and repost | |
719 | * with error code -EAGAIN. | |
720 | */ | |
721 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
722 | /* With old ras TA, we might fail to enable ras. | |
723 | * Log it and just setup the object. | |
724 | * TODO need remove this WA in the future. | |
725 | */ | |
726 | if (ret == -EINVAL) { | |
727 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
728 | if (!ret) | |
6952e99c GC |
729 | dev_info(adev->dev, |
730 | "RAS INFO: %s setup object\n", | |
7af23ebe | 731 | ras_block_str(head->block)); |
732 | } | |
733 | } else { | |
734 | /* setup the object then issue a ras TA disable cmd.*/ | |
735 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
736 | if (ret) | |
737 | return ret; | |
77de502b | 738 | |
970fd197 SY |
739 | /* gfx block ras dsiable cmd must send to ras-ta */ |
740 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
741 | con->features |= BIT(head->block); | |
742 | ||
77de502b | 743 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
744 | |
745 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 746 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 747 | con->features &= ~BIT(head->block); |
7af23ebe | 748 | } |
77de502b | 749 | } else |
750 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
751 | ||
752 | return ret; | |
753 | } | |
754 | ||
c030f2e4 | 755 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
756 | bool bypass) | |
757 | { | |
758 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
759 | struct ras_manager *obj, *tmp; | |
760 | ||
761 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
762 | /* bypass psp. | |
763 | * aka just release the obj and corresponding flags | |
764 | */ | |
765 | if (bypass) { | |
766 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
767 | break; | |
768 | } else { | |
769 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
770 | break; | |
771 | } | |
289d513b | 772 | } |
c030f2e4 | 773 | |
774 | return con->features; | |
775 | } | |
776 | ||
777 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
778 | bool bypass) | |
779 | { | |
780 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
781 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
782 | int i; | |
191051a1 | 783 | const enum amdgpu_ras_error_type default_ras_type = |
784 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 785 | |
786 | for (i = 0; i < ras_block_count; i++) { | |
787 | struct ras_common_if head = { | |
788 | .block = i, | |
191051a1 | 789 | .type = default_ras_type, |
c030f2e4 | 790 | .sub_block_index = 0, |
791 | }; | |
792 | strcpy(head.name, ras_block_str(i)); | |
793 | if (bypass) { | |
794 | /* | |
795 | * bypass psp. vbios enable ras for us. | |
796 | * so just create the obj | |
797 | */ | |
798 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
799 | break; | |
800 | } else { | |
801 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
802 | break; | |
803 | } | |
289d513b | 804 | } |
c030f2e4 | 805 | |
806 | return con->features; | |
807 | } | |
808 | /* feature ctl end */ | |
809 | ||
810 | /* query/inject/cure begin */ | |
761d86d3 DL |
811 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
812 | struct ras_query_if *info) | |
c030f2e4 | 813 | { |
814 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 815 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 816 | int i; |
c030f2e4 | 817 | |
818 | if (!obj) | |
819 | return -EINVAL; | |
c030f2e4 | 820 | |
939e2258 HZ |
821 | switch (info->head.block) { |
822 | case AMDGPU_RAS_BLOCK__UMC: | |
49070c4e HZ |
823 | if (adev->umc.ras_funcs && |
824 | adev->umc.ras_funcs->query_ras_error_count) | |
825 | adev->umc.ras_funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
826 | /* umc query_ras_error_address is also responsible for clearing |
827 | * error status | |
828 | */ | |
49070c4e HZ |
829 | if (adev->umc.ras_funcs && |
830 | adev->umc.ras_funcs->query_ras_error_address) | |
831 | adev->umc.ras_funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 832 | break; |
3e81ee9a HZ |
833 | case AMDGPU_RAS_BLOCK__SDMA: |
834 | if (adev->sdma.funcs->query_ras_error_count) { | |
835 | for (i = 0; i < adev->sdma.num_instances; i++) | |
836 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
837 | &err_data); | |
838 | } | |
839 | break; | |
83b0582c | 840 | case AMDGPU_RAS_BLOCK__GFX: |
719a9b33 HZ |
841 | if (adev->gfx.ras_funcs && |
842 | adev->gfx.ras_funcs->query_ras_error_count) | |
843 | adev->gfx.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 844 | |
719a9b33 HZ |
845 | if (adev->gfx.ras_funcs && |
846 | adev->gfx.ras_funcs->query_ras_error_status) | |
847 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
83b0582c | 848 | break; |
9fb2d8de | 849 | case AMDGPU_RAS_BLOCK__MMHUB: |
8bc7b360 HZ |
850 | if (adev->mmhub.ras_funcs && |
851 | adev->mmhub.ras_funcs->query_ras_error_count) | |
852 | adev->mmhub.ras_funcs->query_ras_error_count(adev, &err_data); | |
761d86d3 | 853 | |
8bc7b360 HZ |
854 | if (adev->mmhub.ras_funcs && |
855 | adev->mmhub.ras_funcs->query_ras_error_status) | |
856 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
9fb2d8de | 857 | break; |
d7bd680d | 858 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
6e36f231 HZ |
859 | if (adev->nbio.ras_funcs && |
860 | adev->nbio.ras_funcs->query_ras_error_count) | |
861 | adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data); | |
d7bd680d | 862 | break; |
ec01fe2d | 863 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
52137ca8 HZ |
864 | if (adev->gmc.xgmi.ras_funcs && |
865 | adev->gmc.xgmi.ras_funcs->query_ras_error_count) | |
866 | adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data); | |
ec01fe2d | 867 | break; |
78871b6c HZ |
868 | case AMDGPU_RAS_BLOCK__HDP: |
869 | if (adev->hdp.ras_funcs && | |
870 | adev->hdp.ras_funcs->query_ras_error_count) | |
871 | adev->hdp.ras_funcs->query_ras_error_count(adev, &err_data); | |
872 | break; | |
939e2258 HZ |
873 | default: |
874 | break; | |
875 | } | |
05a58345 TZ |
876 | |
877 | obj->err_data.ue_count += err_data.ue_count; | |
878 | obj->err_data.ce_count += err_data.ce_count; | |
879 | ||
c030f2e4 | 880 | info->ue_count = obj->err_data.ue_count; |
881 | info->ce_count = obj->err_data.ce_count; | |
882 | ||
7c6e68c7 | 883 | if (err_data.ce_count) { |
a30f1286 HZ |
884 | if (adev->smuio.funcs && |
885 | adev->smuio.funcs->get_socket_id && | |
886 | adev->smuio.funcs->get_die_id) { | |
887 | dev_info(adev->dev, "socket: %d, die: %d " | |
888 | "%ld correctable hardware errors " | |
6952e99c GC |
889 | "detected in %s block, no user " |
890 | "action is needed.\n", | |
a30f1286 HZ |
891 | adev->smuio.funcs->get_socket_id(adev), |
892 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c GC |
893 | obj->err_data.ce_count, |
894 | ras_block_str(info->head.block)); | |
a30f1286 HZ |
895 | } else { |
896 | dev_info(adev->dev, "%ld correctable hardware errors " | |
6952e99c GC |
897 | "detected in %s block, no user " |
898 | "action is needed.\n", | |
899 | obj->err_data.ce_count, | |
900 | ras_block_str(info->head.block)); | |
a30f1286 | 901 | } |
7c6e68c7 AG |
902 | } |
903 | if (err_data.ue_count) { | |
a30f1286 HZ |
904 | if (adev->smuio.funcs && |
905 | adev->smuio.funcs->get_socket_id && | |
906 | adev->smuio.funcs->get_die_id) { | |
907 | dev_info(adev->dev, "socket: %d, die: %d " | |
908 | "%ld uncorrectable hardware errors " | |
6952e99c | 909 | "detected in %s block\n", |
a30f1286 HZ |
910 | adev->smuio.funcs->get_socket_id(adev), |
911 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c GC |
912 | obj->err_data.ue_count, |
913 | ras_block_str(info->head.block)); | |
a30f1286 HZ |
914 | } else { |
915 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
6952e99c GC |
916 | "detected in %s block\n", |
917 | obj->err_data.ue_count, | |
918 | ras_block_str(info->head.block)); | |
a30f1286 | 919 | } |
7c6e68c7 | 920 | } |
05a58345 | 921 | |
c030f2e4 | 922 | return 0; |
923 | } | |
924 | ||
761d86d3 DL |
925 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
926 | enum amdgpu_ras_block block) | |
927 | { | |
928 | if (!amdgpu_ras_is_supported(adev, block)) | |
929 | return -EINVAL; | |
930 | ||
931 | switch (block) { | |
932 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
933 | if (adev->gfx.ras_funcs && |
934 | adev->gfx.ras_funcs->reset_ras_error_count) | |
935 | adev->gfx.ras_funcs->reset_ras_error_count(adev); | |
761d86d3 | 936 | |
719a9b33 HZ |
937 | if (adev->gfx.ras_funcs && |
938 | adev->gfx.ras_funcs->reset_ras_error_status) | |
939 | adev->gfx.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
940 | break; |
941 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
942 | if (adev->mmhub.ras_funcs && |
943 | adev->mmhub.ras_funcs->reset_ras_error_count) | |
944 | adev->mmhub.ras_funcs->reset_ras_error_count(adev); | |
7780f503 DL |
945 | |
946 | if (adev->mmhub.ras_funcs && | |
947 | adev->mmhub.ras_funcs->reset_ras_error_status) | |
948 | adev->mmhub.ras_funcs->reset_ras_error_status(adev); | |
761d86d3 DL |
949 | break; |
950 | case AMDGPU_RAS_BLOCK__SDMA: | |
951 | if (adev->sdma.funcs->reset_ras_error_count) | |
952 | adev->sdma.funcs->reset_ras_error_count(adev); | |
953 | break; | |
78871b6c HZ |
954 | case AMDGPU_RAS_BLOCK__HDP: |
955 | if (adev->hdp.ras_funcs && | |
956 | adev->hdp.ras_funcs->reset_ras_error_count) | |
957 | adev->hdp.ras_funcs->reset_ras_error_count(adev); | |
958 | break; | |
761d86d3 DL |
959 | default: |
960 | break; | |
961 | } | |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
5c23e9e0 | 966 | /* Trigger XGMI/WAFL error */ |
f3167919 | 967 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
968 | struct ta_ras_trigger_error_input *block_info) |
969 | { | |
970 | int ret; | |
971 | ||
972 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
973 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
974 | ||
975 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
976 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
977 | ||
978 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
979 | ||
980 | if (amdgpu_ras_intr_triggered()) | |
981 | return ret; | |
982 | ||
983 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
984 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
985 | ||
fe2d9f5a | 986 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) |
5c23e9e0 JC |
987 | dev_warn(adev->dev, "Failed to allow df cstate"); |
988 | ||
989 | return ret; | |
990 | } | |
991 | ||
c030f2e4 | 992 | /* wrapper of psp_ras_trigger_error */ |
993 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
994 | struct ras_inject_if *info) | |
995 | { | |
996 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
997 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 998 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
999 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1000 | .sub_block_index = info->head.sub_block_index, |
1001 | .address = info->address, | |
1002 | .value = info->value, | |
1003 | }; | |
1004 | int ret = 0; | |
1005 | ||
1006 | if (!obj) | |
1007 | return -EINVAL; | |
1008 | ||
a6c44d25 JC |
1009 | /* Calculate XGMI relative offset */ |
1010 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
1011 | block_info.address = |
1012 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1013 | block_info.address); | |
a6c44d25 JC |
1014 | } |
1015 | ||
83b0582c DL |
1016 | switch (info->head.block) { |
1017 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1018 | if (adev->gfx.ras_funcs && |
1019 | adev->gfx.ras_funcs->ras_error_inject) | |
1020 | ret = adev->gfx.ras_funcs->ras_error_inject(adev, info); | |
83b0582c DL |
1021 | else |
1022 | ret = -EINVAL; | |
1023 | break; | |
1024 | case AMDGPU_RAS_BLOCK__UMC: | |
5a434527 | 1025 | case AMDGPU_RAS_BLOCK__SDMA: |
9fb2d8de | 1026 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 1027 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
1028 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
1029 | break; | |
5c23e9e0 JC |
1030 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
1031 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
1032 | break; | |
83b0582c | 1033 | default: |
6952e99c | 1034 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 1035 | ras_block_str(info->head.block)); |
83b0582c | 1036 | ret = -EINVAL; |
a5dd40ca HZ |
1037 | } |
1038 | ||
011907fd DL |
1039 | if (ret) |
1040 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
1041 | ras_block_str(info->head.block), ret); | |
c030f2e4 | 1042 | |
1043 | return ret; | |
1044 | } | |
1045 | ||
c030f2e4 | 1046 | /* get the total error counts on all IPs */ |
a46751fb LT |
1047 | void amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
1048 | unsigned long *ce_count, | |
1049 | unsigned long *ue_count) | |
c030f2e4 | 1050 | { |
1051 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1052 | struct ras_manager *obj; | |
a46751fb | 1053 | unsigned long ce, ue; |
c030f2e4 | 1054 | |
8ab0d6f0 | 1055 | if (!adev->ras_enabled || !con) |
a46751fb | 1056 | return; |
c030f2e4 | 1057 | |
a46751fb LT |
1058 | ce = 0; |
1059 | ue = 0; | |
c030f2e4 | 1060 | list_for_each_entry(obj, &con->head, node) { |
1061 | struct ras_query_if info = { | |
1062 | .head = obj->head, | |
1063 | }; | |
1064 | ||
761d86d3 | 1065 | if (amdgpu_ras_query_error_status(adev, &info)) |
a46751fb | 1066 | return; |
c030f2e4 | 1067 | |
a46751fb LT |
1068 | ce += info.ce_count; |
1069 | ue += info.ue_count; | |
c030f2e4 | 1070 | } |
1071 | ||
a46751fb LT |
1072 | if (ce_count) |
1073 | *ce_count = ce; | |
1074 | ||
1075 | if (ue_count) | |
1076 | *ue_count = ue; | |
c030f2e4 | 1077 | } |
1078 | /* query/inject/cure end */ | |
1079 | ||
1080 | ||
1081 | /* sysfs begin */ | |
1082 | ||
466b1793 | 1083 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1084 | struct ras_badpage **bps, unsigned int *count); | |
1085 | ||
1086 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1087 | { | |
1088 | switch (flags) { | |
52dd95f2 | 1089 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1090 | return "R"; |
52dd95f2 | 1091 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1092 | return "P"; |
52dd95f2 | 1093 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1094 | default: |
1095 | return "F"; | |
aec576f9 | 1096 | } |
466b1793 | 1097 | } |
1098 | ||
f77c7109 AD |
1099 | /** |
1100 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1101 | * |
1102 | * It allows user to read the bad pages of vram on the gpu through | |
1103 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1104 | * | |
1105 | * It outputs multiple lines, and each line stands for one gpu page. | |
1106 | * | |
1107 | * The format of one line is below, | |
1108 | * gpu pfn : gpu page size : flags | |
1109 | * | |
1110 | * gpu pfn and gpu page size are printed in hex format. | |
1111 | * flags can be one of below character, | |
f77c7109 | 1112 | * |
466b1793 | 1113 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1114 | * |
466b1793 | 1115 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1116 | * in next window of page_reserve. |
1117 | * | |
466b1793 | 1118 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1119 | * | |
f77c7109 AD |
1120 | * Examples: |
1121 | * | |
1122 | * .. code-block:: bash | |
1123 | * | |
1124 | * 0x00000001 : 0x00001000 : R | |
1125 | * 0x00000002 : 0x00001000 : P | |
1126 | * | |
466b1793 | 1127 | */ |
1128 | ||
1129 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1130 | struct kobject *kobj, struct bin_attribute *attr, | |
1131 | char *buf, loff_t ppos, size_t count) | |
1132 | { | |
1133 | struct amdgpu_ras *con = | |
1134 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1135 | struct amdgpu_device *adev = con->adev; | |
1136 | const unsigned int element_size = | |
1137 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1138 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1139 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1140 | ssize_t s = 0; |
1141 | struct ras_badpage *bps = NULL; | |
1142 | unsigned int bps_count = 0; | |
1143 | ||
1144 | memset(buf, 0, count); | |
1145 | ||
1146 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1147 | return 0; | |
1148 | ||
1149 | for (; start < end && start < bps_count; start++) | |
1150 | s += scnprintf(&buf[s], element_size + 1, | |
1151 | "0x%08x : 0x%08x : %1s\n", | |
1152 | bps[start].bp, | |
1153 | bps[start].size, | |
1154 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1155 | ||
1156 | kfree(bps); | |
1157 | ||
1158 | return s; | |
1159 | } | |
1160 | ||
c030f2e4 | 1161 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1162 | struct device_attribute *attr, char *buf) | |
1163 | { | |
1164 | struct amdgpu_ras *con = | |
1165 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1166 | |
5212a3bd | 1167 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1168 | } |
1169 | ||
f848159b GC |
1170 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1171 | { | |
1172 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1173 | ||
1174 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1175 | &con->badpages_attr.attr, | |
1176 | RAS_FS_NAME); | |
1177 | } | |
1178 | ||
c030f2e4 | 1179 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1180 | { | |
1181 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1182 | struct attribute *attrs[] = { | |
1183 | &con->features_attr.attr, | |
1184 | NULL | |
1185 | }; | |
1186 | struct attribute_group group = { | |
eb0c3cd4 | 1187 | .name = RAS_FS_NAME, |
c030f2e4 | 1188 | .attrs = attrs, |
1189 | }; | |
1190 | ||
1191 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1197 | struct ras_fs_if *head) | |
1198 | { | |
1199 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1200 | ||
1201 | if (!obj || obj->attr_inuse) | |
1202 | return -EINVAL; | |
1203 | ||
1204 | get_obj(obj); | |
1205 | ||
1206 | memcpy(obj->fs_data.sysfs_name, | |
1207 | head->sysfs_name, | |
1208 | sizeof(obj->fs_data.sysfs_name)); | |
1209 | ||
1210 | obj->sysfs_attr = (struct device_attribute){ | |
1211 | .attr = { | |
1212 | .name = obj->fs_data.sysfs_name, | |
1213 | .mode = S_IRUGO, | |
1214 | }, | |
1215 | .show = amdgpu_ras_sysfs_read, | |
1216 | }; | |
163def43 | 1217 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1218 | |
1219 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1220 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1221 | RAS_FS_NAME)) { |
c030f2e4 | 1222 | put_obj(obj); |
1223 | return -EINVAL; | |
1224 | } | |
1225 | ||
1226 | obj->attr_inuse = 1; | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1232 | struct ras_common_if *head) | |
1233 | { | |
1234 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1235 | ||
1236 | if (!obj || !obj->attr_inuse) | |
1237 | return -EINVAL; | |
1238 | ||
1239 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1240 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1241 | RAS_FS_NAME); |
c030f2e4 | 1242 | obj->attr_inuse = 0; |
1243 | put_obj(obj); | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
1248 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1249 | { | |
1250 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1251 | struct ras_manager *obj, *tmp; | |
1252 | ||
1253 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1254 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1255 | } | |
1256 | ||
f848159b GC |
1257 | if (amdgpu_bad_page_threshold != 0) |
1258 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1259 | ||
c030f2e4 | 1260 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | /* sysfs end */ | |
1265 | ||
ef177d11 AD |
1266 | /** |
1267 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1268 | * | |
1269 | * Normally when there is an uncorrectable error, the driver will reset | |
1270 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1271 | * the driver provides an interface to reboot the system automatically | |
1272 | * in that event. | |
1273 | * | |
1274 | * The following file in debugfs provides that interface: | |
1275 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1276 | * | |
1277 | * Usage: | |
1278 | * | |
1279 | * .. code-block:: bash | |
1280 | * | |
1281 | * echo true > .../ras/auto_reboot | |
1282 | * | |
1283 | */ | |
c030f2e4 | 1284 | /* debugfs begin */ |
ea1b8c9b | 1285 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1286 | { |
1287 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
ef0d7d20 LT |
1288 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1289 | struct dentry *dir; | |
36ea1bd2 | 1290 | |
88293c03 ND |
1291 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1292 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1293 | &amdgpu_ras_debugfs_ctrl_ops); | |
1294 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1295 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1296 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1297 | &con->bad_page_cnt_threshold); | |
ef0d7d20 LT |
1298 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1299 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c688a06b GC |
1300 | |
1301 | /* | |
1302 | * After one uncorrectable error happens, usually GPU recovery will | |
1303 | * be scheduled. But due to the known problem in GPU recovery failing | |
1304 | * to bring GPU back, below interface provides one direct way to | |
1305 | * user to reboot system automatically in such case within | |
1306 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1307 | * will never be called. | |
1308 | */ | |
88293c03 | 1309 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1310 | |
1311 | /* | |
1312 | * User could set this not to clean up hardware's error count register | |
1313 | * of RAS IPs during ras recovery. | |
1314 | */ | |
88293c03 ND |
1315 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1316 | &con->disable_ras_err_cnt_harvest); | |
1317 | return dir; | |
36ea1bd2 | 1318 | } |
1319 | ||
cedf7884 | 1320 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1321 | struct ras_fs_if *head, |
1322 | struct dentry *dir) | |
c030f2e4 | 1323 | { |
c030f2e4 | 1324 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1325 | |
88293c03 | 1326 | if (!obj || !dir) |
450f30ea | 1327 | return; |
c030f2e4 | 1328 | |
1329 | get_obj(obj); | |
1330 | ||
1331 | memcpy(obj->fs_data.debugfs_name, | |
1332 | head->debugfs_name, | |
1333 | sizeof(obj->fs_data.debugfs_name)); | |
1334 | ||
88293c03 ND |
1335 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1336 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1337 | } |
1338 | ||
f9317014 TZ |
1339 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1340 | { | |
1341 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1342 | struct dentry *dir; |
c1509f3f | 1343 | struct ras_manager *obj; |
f9317014 TZ |
1344 | struct ras_fs_if fs_info; |
1345 | ||
1346 | /* | |
1347 | * it won't be called in resume path, no need to check | |
1348 | * suspend and gpu reset status | |
1349 | */ | |
cedf7884 | 1350 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1351 | return; |
1352 | ||
88293c03 | 1353 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1354 | |
c1509f3f | 1355 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1356 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1357 | (obj->attr_inuse == 1)) { | |
1358 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1359 | ras_block_str(obj->head.block)); | |
1360 | fs_info.head = obj->head; | |
88293c03 | 1361 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1362 | } |
1363 | } | |
1364 | } | |
1365 | ||
c030f2e4 | 1366 | /* debugfs end */ |
1367 | ||
1368 | /* ras fs */ | |
c3d4d45d GC |
1369 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1370 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1371 | static DEVICE_ATTR(features, S_IRUGO, | |
1372 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1373 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1374 | { | |
c3d4d45d GC |
1375 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1376 | struct attribute_group group = { | |
1377 | .name = RAS_FS_NAME, | |
1378 | }; | |
1379 | struct attribute *attrs[] = { | |
1380 | &con->features_attr.attr, | |
1381 | NULL | |
1382 | }; | |
1383 | struct bin_attribute *bin_attrs[] = { | |
1384 | NULL, | |
1385 | NULL, | |
1386 | }; | |
a069a9eb | 1387 | int r; |
c030f2e4 | 1388 | |
c3d4d45d GC |
1389 | /* add features entry */ |
1390 | con->features_attr = dev_attr_features; | |
1391 | group.attrs = attrs; | |
1392 | sysfs_attr_init(attrs[0]); | |
1393 | ||
1394 | if (amdgpu_bad_page_threshold != 0) { | |
1395 | /* add bad_page_features entry */ | |
1396 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1397 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1398 | bin_attrs[0] = &con->badpages_attr; | |
1399 | group.bin_attrs = bin_attrs; | |
1400 | sysfs_bin_attr_init(bin_attrs[0]); | |
1401 | } | |
1402 | ||
a069a9eb AD |
1403 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1404 | if (r) | |
1405 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1406 | |
c030f2e4 | 1407 | return 0; |
1408 | } | |
1409 | ||
1410 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1411 | { | |
88293c03 ND |
1412 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1413 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1414 | ||
1415 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1416 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1417 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1418 | if (ip_obj) | |
1419 | put_obj(ip_obj); | |
1420 | } | |
1421 | } | |
1422 | ||
c030f2e4 | 1423 | amdgpu_ras_sysfs_remove_all(adev); |
1424 | return 0; | |
1425 | } | |
1426 | /* ras fs end */ | |
1427 | ||
1428 | /* ih begin */ | |
1429 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1430 | { | |
1431 | struct ras_ih_data *data = &obj->ih_data; | |
1432 | struct amdgpu_iv_entry entry; | |
1433 | int ret; | |
cf04dfd0 | 1434 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1435 | |
1436 | while (data->rptr != data->wptr) { | |
1437 | rmb(); | |
1438 | memcpy(&entry, &data->ring[data->rptr], | |
1439 | data->element_size); | |
1440 | ||
1441 | wmb(); | |
1442 | data->rptr = (data->aligned_element_size + | |
1443 | data->rptr) % data->ring_size; | |
1444 | ||
1445 | /* Let IP handle its data, maybe we need get the output | |
1446 | * from the callback to udpate the error type/count, etc | |
1447 | */ | |
1448 | if (data->cb) { | |
cf04dfd0 | 1449 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1450 | /* ue will trigger an interrupt, and in that case |
1451 | * we need do a reset to recovery the whole system. | |
1452 | * But leave IP do that recovery, here we just dispatch | |
1453 | * the error. | |
1454 | */ | |
bd2280da | 1455 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1456 | /* these counts could be left as 0 if |
1457 | * some blocks do not count error number | |
1458 | */ | |
cf04dfd0 | 1459 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1460 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1461 | } |
c030f2e4 | 1462 | } |
1463 | } | |
1464 | } | |
1465 | ||
1466 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1467 | { | |
1468 | struct ras_ih_data *data = | |
1469 | container_of(work, struct ras_ih_data, ih_work); | |
1470 | struct ras_manager *obj = | |
1471 | container_of(data, struct ras_manager, ih_data); | |
1472 | ||
1473 | amdgpu_ras_interrupt_handler(obj); | |
1474 | } | |
1475 | ||
1476 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1477 | struct ras_dispatch_if *info) | |
1478 | { | |
1479 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1480 | struct ras_ih_data *data = &obj->ih_data; | |
1481 | ||
1482 | if (!obj) | |
1483 | return -EINVAL; | |
1484 | ||
1485 | if (data->inuse == 0) | |
1486 | return 0; | |
1487 | ||
1488 | /* Might be overflow... */ | |
1489 | memcpy(&data->ring[data->wptr], info->entry, | |
1490 | data->element_size); | |
1491 | ||
1492 | wmb(); | |
1493 | data->wptr = (data->aligned_element_size + | |
1494 | data->wptr) % data->ring_size; | |
1495 | ||
1496 | schedule_work(&data->ih_work); | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
1501 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1502 | struct ras_ih_if *info) | |
1503 | { | |
1504 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1505 | struct ras_ih_data *data; | |
1506 | ||
1507 | if (!obj) | |
1508 | return -EINVAL; | |
1509 | ||
1510 | data = &obj->ih_data; | |
1511 | if (data->inuse == 0) | |
1512 | return 0; | |
1513 | ||
1514 | cancel_work_sync(&data->ih_work); | |
1515 | ||
1516 | kfree(data->ring); | |
1517 | memset(data, 0, sizeof(*data)); | |
1518 | put_obj(obj); | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1524 | struct ras_ih_if *info) | |
1525 | { | |
1526 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1527 | struct ras_ih_data *data; | |
1528 | ||
1529 | if (!obj) { | |
1530 | /* in case we registe the IH before enable ras feature */ | |
1531 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1532 | if (!obj) | |
1533 | return -EINVAL; | |
1534 | } else | |
1535 | get_obj(obj); | |
1536 | ||
1537 | data = &obj->ih_data; | |
1538 | /* add the callback.etc */ | |
1539 | *data = (struct ras_ih_data) { | |
1540 | .inuse = 0, | |
1541 | .cb = info->cb, | |
1542 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1543 | .rptr = 0, | |
1544 | .wptr = 0, | |
1545 | }; | |
1546 | ||
1547 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1548 | ||
1549 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1550 | /* the ring can store 64 iv entries. */ | |
1551 | data->ring_size = 64 * data->aligned_element_size; | |
1552 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1553 | if (!data->ring) { | |
1554 | put_obj(obj); | |
1555 | return -ENOMEM; | |
1556 | } | |
1557 | ||
1558 | /* IH is ready */ | |
1559 | data->inuse = 1; | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1565 | { | |
1566 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1567 | struct ras_manager *obj, *tmp; | |
1568 | ||
1569 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1570 | struct ras_ih_if info = { | |
1571 | .head = obj->head, | |
1572 | }; | |
1573 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1574 | } | |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | /* ih end */ | |
1579 | ||
313c8fd3 GC |
1580 | /* traversal all IPs except NBIO to query error counter */ |
1581 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1582 | { | |
1583 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1584 | struct ras_manager *obj; | |
1585 | ||
8ab0d6f0 | 1586 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
1587 | return; |
1588 | ||
1589 | list_for_each_entry(obj, &con->head, node) { | |
1590 | struct ras_query_if info = { | |
1591 | .head = obj->head, | |
1592 | }; | |
1593 | ||
1594 | /* | |
1595 | * PCIE_BIF IP has one different isr by ras controller | |
1596 | * interrupt, the specific ras counter query will be | |
1597 | * done in that isr. So skip such block from common | |
1598 | * sync flood interrupt isr calling. | |
1599 | */ | |
1600 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1601 | continue; | |
1602 | ||
761d86d3 | 1603 | amdgpu_ras_query_error_status(adev, &info); |
313c8fd3 GC |
1604 | } |
1605 | } | |
1606 | ||
3f975d0f | 1607 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1608 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1609 | struct ras_query_if *info) | |
3f975d0f SY |
1610 | { |
1611 | /* | |
1612 | * Only two block need to query read/write | |
1613 | * RspStatus at current state | |
1614 | */ | |
1615 | switch (info->head.block) { | |
1616 | case AMDGPU_RAS_BLOCK__GFX: | |
719a9b33 HZ |
1617 | if (adev->gfx.ras_funcs && |
1618 | adev->gfx.ras_funcs->query_ras_error_status) | |
1619 | adev->gfx.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1620 | break; |
1621 | case AMDGPU_RAS_BLOCK__MMHUB: | |
8bc7b360 HZ |
1622 | if (adev->mmhub.ras_funcs && |
1623 | adev->mmhub.ras_funcs->query_ras_error_status) | |
1624 | adev->mmhub.ras_funcs->query_ras_error_status(adev); | |
3f975d0f SY |
1625 | break; |
1626 | default: | |
1627 | break; | |
1628 | } | |
1629 | } | |
1630 | ||
1631 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1632 | { | |
1633 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1634 | struct ras_manager *obj; | |
1635 | ||
8ab0d6f0 | 1636 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
1637 | return; |
1638 | ||
1639 | list_for_each_entry(obj, &con->head, node) { | |
1640 | struct ras_query_if info = { | |
1641 | .head = obj->head, | |
1642 | }; | |
1643 | ||
1644 | amdgpu_ras_error_status_query(adev, &info); | |
1645 | } | |
1646 | } | |
1647 | ||
c030f2e4 | 1648 | /* recovery begin */ |
466b1793 | 1649 | |
1650 | /* return 0 on success. | |
1651 | * caller need free bps. | |
1652 | */ | |
1653 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1654 | struct ras_badpage **bps, unsigned int *count) | |
1655 | { | |
1656 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1657 | struct ras_err_handler_data *data; | |
1658 | int i = 0; | |
732f2a30 | 1659 | int ret = 0, status; |
466b1793 | 1660 | |
1661 | if (!con || !con->eh_data || !bps || !count) | |
1662 | return -EINVAL; | |
1663 | ||
1664 | mutex_lock(&con->recovery_lock); | |
1665 | data = con->eh_data; | |
1666 | if (!data || data->count == 0) { | |
1667 | *bps = NULL; | |
46cf2fec | 1668 | ret = -EINVAL; |
466b1793 | 1669 | goto out; |
1670 | } | |
1671 | ||
1672 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1673 | if (!*bps) { | |
1674 | ret = -ENOMEM; | |
1675 | goto out; | |
1676 | } | |
1677 | ||
1678 | for (; i < data->count; i++) { | |
1679 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1680 | .bp = data->bps[i].retired_page, |
466b1793 | 1681 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1682 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1683 | }; |
732f2a30 | 1684 | status = amdgpu_vram_mgr_query_page_status( |
676deb38 DL |
1685 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), |
1686 | data->bps[i].retired_page); | |
732f2a30 | 1687 | if (status == -EBUSY) |
52dd95f2 | 1688 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 1689 | else if (status == -ENOENT) |
52dd95f2 | 1690 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1691 | } |
1692 | ||
1693 | *count = data->count; | |
1694 | out: | |
1695 | mutex_unlock(&con->recovery_lock); | |
1696 | return ret; | |
1697 | } | |
1698 | ||
c030f2e4 | 1699 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1700 | { | |
1701 | struct amdgpu_ras *ras = | |
1702 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1703 | struct amdgpu_device *remote_adev = NULL; |
1704 | struct amdgpu_device *adev = ras->adev; | |
1705 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1706 | |
f75e94d8 | 1707 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1708 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1709 | ||
f75e94d8 GC |
1710 | /* Build list of devices to query RAS related errors */ |
1711 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1712 | device_list_handle = &hive->device_list; | |
1713 | } else { | |
1714 | INIT_LIST_HEAD(&device_list); | |
1715 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1716 | device_list_handle = &device_list; | |
1717 | } | |
c030f2e4 | 1718 | |
f75e94d8 | 1719 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1720 | device_list_handle, gmc.xgmi.head) { |
1721 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1722 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1723 | } |
d95e8e97 DL |
1724 | |
1725 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1726 | } |
313c8fd3 | 1727 | |
93af20f7 | 1728 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1729 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1730 | atomic_set(&ras->in_recovery, 0); |
1731 | } | |
1732 | ||
c030f2e4 | 1733 | /* alloc/realloc bps array */ |
1734 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1735 | struct ras_err_handler_data *data, int pages) | |
1736 | { | |
1737 | unsigned int old_space = data->count + data->space_left; | |
1738 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1739 | unsigned int align_space = ALIGN(new_space, 512); |
1740 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1741 | |
676deb38 | 1742 | if (!bps) { |
9dc23a63 | 1743 | kfree(bps); |
c030f2e4 | 1744 | return -ENOMEM; |
9dc23a63 | 1745 | } |
c030f2e4 | 1746 | |
1747 | if (data->bps) { | |
9dc23a63 | 1748 | memcpy(bps, data->bps, |
c030f2e4 | 1749 | data->count * sizeof(*data->bps)); |
1750 | kfree(data->bps); | |
1751 | } | |
1752 | ||
9dc23a63 | 1753 | data->bps = bps; |
c030f2e4 | 1754 | data->space_left += align_space - old_space; |
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | /* it deal with vram only. */ | |
1759 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1760 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1761 | { |
1762 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1763 | struct ras_err_handler_data *data; |
c030f2e4 | 1764 | int ret = 0; |
676deb38 | 1765 | uint32_t i; |
c030f2e4 | 1766 | |
73aa8e1a | 1767 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1768 | return 0; |
1769 | ||
1770 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1771 | data = con->eh_data; |
c030f2e4 | 1772 | if (!data) |
1773 | goto out; | |
1774 | ||
676deb38 DL |
1775 | for (i = 0; i < pages; i++) { |
1776 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1777 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1778 | continue; | |
1779 | ||
1780 | if (!data->space_left && | |
1781 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1782 | ret = -ENOMEM; |
1783 | goto out; | |
1784 | } | |
1785 | ||
676deb38 DL |
1786 | amdgpu_vram_mgr_reserve_range( |
1787 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1788 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1789 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1790 | |
676deb38 DL |
1791 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1792 | data->count++; | |
1793 | data->space_left--; | |
1794 | } | |
c030f2e4 | 1795 | out: |
1796 | mutex_unlock(&con->recovery_lock); | |
1797 | ||
1798 | return ret; | |
1799 | } | |
1800 | ||
78ad00c9 TZ |
1801 | /* |
1802 | * write error record array to eeprom, the function should be | |
1803 | * protected by recovery_lock | |
1804 | */ | |
22503d80 | 1805 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1806 | { |
1807 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1808 | struct ras_err_handler_data *data; | |
8a3e801f | 1809 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1810 | int save_count; |
1811 | ||
1812 | if (!con || !con->eh_data) | |
1813 | return 0; | |
1814 | ||
8a3e801f | 1815 | control = &con->eeprom_control; |
78ad00c9 TZ |
1816 | data = con->eh_data; |
1817 | save_count = data->count - control->num_recs; | |
1818 | /* only new entries are saved */ | |
b1628425 | 1819 | if (save_count > 0) { |
1fab841f LT |
1820 | if (amdgpu_ras_eeprom_write(control, |
1821 | &data->bps[control->num_recs], | |
1822 | save_count)) { | |
6952e99c | 1823 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1824 | return -EIO; |
1825 | } | |
1826 | ||
b1628425 GC |
1827 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1828 | } | |
1829 | ||
78ad00c9 TZ |
1830 | return 0; |
1831 | } | |
1832 | ||
1833 | /* | |
1834 | * read error record array in eeprom and reserve enough space for | |
1835 | * storing new bad pages | |
1836 | */ | |
1837 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1838 | { | |
1839 | struct amdgpu_ras_eeprom_control *control = | |
1840 | &adev->psp.ras.ras->eeprom_control; | |
1841 | struct eeprom_table_record *bps = NULL; | |
1842 | int ret = 0; | |
1843 | ||
1844 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1845 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1846 | return ret; |
1847 | ||
1848 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1849 | if (!bps) | |
1850 | return -ENOMEM; | |
1851 | ||
1fab841f | 1852 | if (amdgpu_ras_eeprom_read(control, bps, control->num_recs)) { |
6952e99c | 1853 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1854 | ret = -EIO; |
1855 | goto out; | |
1856 | } | |
1857 | ||
1858 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1859 | ||
1860 | out: | |
1861 | kfree(bps); | |
1862 | return ret; | |
1863 | } | |
1864 | ||
676deb38 DL |
1865 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1866 | uint64_t addr) | |
1867 | { | |
1868 | struct ras_err_handler_data *data = con->eh_data; | |
1869 | int i; | |
1870 | ||
1871 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1872 | for (i = 0; i < data->count; i++) | |
1873 | if (addr == data->bps[i].retired_page) | |
1874 | return true; | |
1875 | ||
1876 | return false; | |
1877 | } | |
1878 | ||
6e4be987 TZ |
1879 | /* |
1880 | * check if an address belongs to bad page | |
1881 | * | |
1882 | * Note: this check is only for umc block | |
1883 | */ | |
1884 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1885 | uint64_t addr) | |
1886 | { | |
1887 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1888 | bool ret = false; |
1889 | ||
1890 | if (!con || !con->eh_data) | |
1891 | return ret; | |
1892 | ||
1893 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1894 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1895 | mutex_unlock(&con->recovery_lock); |
1896 | return ret; | |
1897 | } | |
1898 | ||
e5c04edf CK |
1899 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1900 | uint32_t max_length) | |
c84d4670 | 1901 | { |
e5c04edf | 1902 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
1903 | int tmp_threshold = amdgpu_bad_page_threshold; |
1904 | u64 val; | |
1905 | ||
1906 | /* | |
1907 | * Justification of value bad_page_cnt_threshold in ras structure | |
1908 | * | |
1909 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1910 | * in eeprom, and introduce two scenarios accordingly. | |
1911 | * | |
1912 | * Bad page retirement enablement: | |
1913 | * - If amdgpu_bad_page_threshold = -1, | |
1914 | * bad_page_cnt_threshold = typical value by formula. | |
1915 | * | |
1916 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1917 | * max record length in eeprom, use it directly. | |
1918 | * | |
1919 | * Bad page retirement disablement: | |
1920 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1921 | * functionality is disabled, and bad_page_cnt_threshold will | |
1922 | * take no effect. | |
1923 | */ | |
1924 | ||
1925 | if (tmp_threshold < -1) | |
1926 | tmp_threshold = -1; | |
1927 | else if (tmp_threshold > max_length) | |
1928 | tmp_threshold = max_length; | |
1929 | ||
1930 | if (tmp_threshold == -1) { | |
e5c04edf | 1931 | val = adev->gmc.mc_vram_size; |
c84d4670 | 1932 | do_div(val, RAS_BAD_PAGE_RATE); |
e5c04edf CK |
1933 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
1934 | max_length); | |
1935 | } else { | |
1936 | con->bad_page_cnt_threshold = tmp_threshold; | |
c84d4670 GC |
1937 | } |
1938 | } | |
1939 | ||
1a6fc071 | 1940 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1941 | { |
1942 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1943 | struct ras_err_handler_data **data; |
e5c04edf | 1944 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1945 | bool exc_err_limit = false; |
78ad00c9 | 1946 | int ret; |
c030f2e4 | 1947 | |
8ab0d6f0 | 1948 | if (adev->ras_enabled && con) |
4d1337d2 AG |
1949 | data = &con->eh_data; |
1950 | else | |
1951 | return 0; | |
1952 | ||
1a6fc071 TZ |
1953 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1954 | if (!*data) { | |
1955 | ret = -ENOMEM; | |
1956 | goto out; | |
1957 | } | |
c030f2e4 | 1958 | |
1959 | mutex_init(&con->recovery_lock); | |
1960 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1961 | atomic_set(&con->in_recovery, 0); | |
1962 | con->adev = adev; | |
1963 | ||
e5c04edf CK |
1964 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1965 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
c84d4670 | 1966 | |
e5086659 | 1967 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
1968 | * when the GPU is pending on XGMI reset during probe time | |
1969 | * (Mostly after second bus reset), skip it now | |
1970 | */ | |
1971 | if (adev->gmc.xgmi.pending_reset) | |
1972 | return 0; | |
b82e65a9 GC |
1973 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1974 | /* | |
1975 | * This calling fails when exc_err_limit is true or | |
1976 | * ret != 0. | |
1977 | */ | |
1978 | if (exc_err_limit || ret) | |
1a6fc071 | 1979 | goto free; |
78ad00c9 | 1980 | |
0771b0bf | 1981 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1982 | ret = amdgpu_ras_load_bad_pages(adev); |
1983 | if (ret) | |
1a6fc071 | 1984 | goto free; |
513befa6 SY |
1985 | |
1986 | if (adev->smu.ppt_funcs && adev->smu.ppt_funcs->send_hbm_bad_pages_num) | |
1987 | adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.num_recs); | |
78ad00c9 | 1988 | } |
c030f2e4 | 1989 | |
1990 | return 0; | |
1a6fc071 | 1991 | |
1a6fc071 | 1992 | free: |
1a6fc071 | 1993 | kfree((*data)->bps); |
1a6fc071 | 1994 | kfree(*data); |
1995b3a3 | 1995 | con->eh_data = NULL; |
1a6fc071 | 1996 | out: |
6952e99c | 1997 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1998 | |
b82e65a9 GC |
1999 | /* |
2000 | * Except error threshold exceeding case, other failure cases in this | |
2001 | * function would not fail amdgpu driver init. | |
2002 | */ | |
2003 | if (!exc_err_limit) | |
2004 | ret = 0; | |
2005 | else | |
2006 | ret = -EINVAL; | |
2007 | ||
1a6fc071 | 2008 | return ret; |
c030f2e4 | 2009 | } |
2010 | ||
2011 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2012 | { | |
2013 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2014 | struct ras_err_handler_data *data = con->eh_data; | |
2015 | ||
1a6fc071 TZ |
2016 | /* recovery_init failed to init it, fini is useless */ |
2017 | if (!data) | |
2018 | return 0; | |
2019 | ||
c030f2e4 | 2020 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2021 | |
2022 | mutex_lock(&con->recovery_lock); | |
2023 | con->eh_data = NULL; | |
2024 | kfree(data->bps); | |
2025 | kfree(data); | |
2026 | mutex_unlock(&con->recovery_lock); | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | /* recovery end */ | |
2031 | ||
a564808e | 2032 | /* return 0 if ras will reset gpu and repost.*/ |
2033 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
2034 | unsigned int block) | |
2035 | { | |
2036 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
2037 | ||
2038 | if (!ras) | |
2039 | return -EINVAL; | |
2040 | ||
2041 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2042 | return 0; | |
2043 | } | |
2044 | ||
084e2640 | 2045 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2046 | { |
084e2640 LT |
2047 | return adev->asic_type == CHIP_VEGA10 || |
2048 | adev->asic_type == CHIP_VEGA20 || | |
2049 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2050 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2051 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2052 | } |
2053 | ||
f50160cf SY |
2054 | /* |
2055 | * this is workaround for vega20 workstation sku, | |
2056 | * force enable gfx ras, ignore vbios gfx ras flag | |
2057 | * due to GC EDC can not write | |
2058 | */ | |
e509965e | 2059 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2060 | { |
2061 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2062 | ||
2063 | if (!ctx) | |
2064 | return; | |
2065 | ||
2066 | if (strnstr(ctx->vbios_version, "D16406", | |
e11d5e0d SY |
2067 | sizeof(ctx->vbios_version)) || |
2068 | strnstr(ctx->vbios_version, "D36002", | |
2069 | sizeof(ctx->vbios_version))) | |
8ab0d6f0 | 2070 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2071 | } |
2072 | ||
5caf466a | 2073 | /* |
2074 | * check hardware's ras ability which will be saved in hw_supported. | |
2075 | * if hardware does not support ras, we can skip some ras initializtion and | |
2076 | * forbid some ras operations from IP. | |
2077 | * if software itself, say boot parameter, limit the ras ability. We still | |
2078 | * need allow IP do some limited operations, like disable. In such case, | |
2079 | * we have to initialize ras as normal. but need check if operation is | |
2080 | * allowed or not in each function. | |
2081 | */ | |
e509965e | 2082 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2083 | { |
8ab0d6f0 | 2084 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2085 | |
88474cca | 2086 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
084e2640 | 2087 | !amdgpu_ras_asic_supported(adev)) |
5caf466a | 2088 | return; |
b404ae82 | 2089 | |
75f06251 HZ |
2090 | if (!adev->gmc.xgmi.connected_to_cpu) { |
2091 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { | |
2092 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2093 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2094 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2095 | } else { |
2096 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2097 | } | |
88474cca | 2098 | |
75f06251 HZ |
2099 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2100 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
8ab0d6f0 | 2101 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2102 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2103 | } else { |
2104 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2105 | } | |
2106 | } else { | |
2107 | /* driver only manages a few IP blocks RAS feature | |
2108 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2109 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2110 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2111 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2112 | } |
88474cca | 2113 | |
e509965e | 2114 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2115 | |
88474cca | 2116 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2117 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2118 | |
8ab0d6f0 LT |
2119 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : |
2120 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2121 | } |
2122 | ||
05adfd80 LT |
2123 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2124 | { | |
2125 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2126 | ras_counte_delay_work.work); | |
2127 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2128 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2129 | unsigned long ce_count, ue_count; |
2130 | int res; | |
2131 | ||
2132 | res = pm_runtime_get_sync(dev->dev); | |
2133 | if (res < 0) | |
2134 | goto Out; | |
2135 | ||
2136 | /* Cache new values. | |
2137 | */ | |
2138 | amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
2139 | atomic_set(&con->ras_ce_count, ce_count); | |
2140 | atomic_set(&con->ras_ue_count, ue_count); | |
2141 | ||
2142 | pm_runtime_mark_last_busy(dev->dev); | |
2143 | Out: | |
2144 | pm_runtime_put_autosuspend(dev->dev); | |
2145 | } | |
2146 | ||
c030f2e4 | 2147 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2148 | { | |
2149 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2150 | int r; |
c030f2e4 | 2151 | |
b404ae82 | 2152 | if (con) |
c030f2e4 | 2153 | return 0; |
2154 | ||
2155 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
2156 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
2157 | GFP_KERNEL|__GFP_ZERO); | |
2158 | if (!con) | |
2159 | return -ENOMEM; | |
2160 | ||
05adfd80 LT |
2161 | con->adev = adev; |
2162 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2163 | atomic_set(&con->ras_ce_count, 0); | |
2164 | atomic_set(&con->ras_ue_count, 0); | |
2165 | ||
c030f2e4 | 2166 | con->objs = (struct ras_manager *)(con + 1); |
2167 | ||
2168 | amdgpu_ras_set_context(adev, con); | |
2169 | ||
e509965e LT |
2170 | amdgpu_ras_check_supported(adev); |
2171 | ||
7ddd9770 | 2172 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2173 | /* set gfx block ras context feature for VEGA20 Gaming |
2174 | * send ras disable cmd to ras ta during ras late init. | |
2175 | */ | |
8ab0d6f0 | 2176 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2177 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2178 | ||
2179 | return 0; | |
2180 | } | |
2181 | ||
5e91160a | 2182 | r = 0; |
5436ab94 | 2183 | goto release_con; |
fb2a3607 HZ |
2184 | } |
2185 | ||
c030f2e4 | 2186 | con->features = 0; |
2187 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2188 | /* Might need get this flag from vbios. */ |
2189 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2190 | |
6e36f231 HZ |
2191 | /* initialize nbio ras function ahead of any other |
2192 | * ras functions so hardware fatal error interrupt | |
2193 | * can be enabled as early as possible */ | |
2194 | switch (adev->asic_type) { | |
2195 | case CHIP_VEGA20: | |
2196 | case CHIP_ARCTURUS: | |
2197 | case CHIP_ALDEBARAN: | |
2198 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2199 | adev->nbio.ras_funcs = &nbio_v7_4_ras_funcs; | |
2200 | break; | |
2201 | default: | |
2202 | /* nbio ras is not available */ | |
2203 | break; | |
2204 | } | |
2205 | ||
2206 | if (adev->nbio.ras_funcs && | |
2207 | adev->nbio.ras_funcs->init_ras_controller_interrupt) { | |
2208 | r = adev->nbio.ras_funcs->init_ras_controller_interrupt(adev); | |
4e644fff | 2209 | if (r) |
5436ab94 | 2210 | goto release_con; |
4e644fff HZ |
2211 | } |
2212 | ||
6e36f231 HZ |
2213 | if (adev->nbio.ras_funcs && |
2214 | adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt) { | |
2215 | r = adev->nbio.ras_funcs->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2216 | if (r) |
5436ab94 | 2217 | goto release_con; |
4e644fff HZ |
2218 | } |
2219 | ||
5e91160a GC |
2220 | if (amdgpu_ras_fs_init(adev)) { |
2221 | r = -EINVAL; | |
5436ab94 | 2222 | goto release_con; |
5e91160a | 2223 | } |
c030f2e4 | 2224 | |
6952e99c | 2225 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2226 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2227 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2228 | |
c030f2e4 | 2229 | return 0; |
5436ab94 | 2230 | release_con: |
c030f2e4 | 2231 | amdgpu_ras_set_context(adev, NULL); |
2232 | kfree(con); | |
2233 | ||
5e91160a | 2234 | return r; |
c030f2e4 | 2235 | } |
2236 | ||
8f6368a9 | 2237 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 JC |
2238 | { |
2239 | if (adev->gmc.xgmi.connected_to_cpu) | |
2240 | return 1; | |
2241 | return 0; | |
2242 | } | |
2243 | ||
2244 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2245 | struct ras_common_if *ras_block) | |
2246 | { | |
2247 | struct ras_query_if info = { | |
2248 | .head = *ras_block, | |
2249 | }; | |
2250 | ||
2251 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2252 | return 0; | |
2253 | ||
2254 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2255 | DRM_WARN("RAS init harvest failure"); | |
2256 | ||
2257 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2258 | DRM_WARN("RAS init harvest reset failure"); | |
2259 | ||
2260 | return 0; | |
2261 | } | |
2262 | ||
b293e891 HZ |
2263 | /* helper function to handle common stuff in ip late init phase */ |
2264 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2265 | struct ras_common_if *ras_block, | |
2266 | struct ras_fs_if *fs_info, | |
2267 | struct ras_ih_if *ih_info) | |
2268 | { | |
05adfd80 LT |
2269 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2270 | unsigned long ue_count, ce_count; | |
b293e891 HZ |
2271 | int r; |
2272 | ||
2273 | /* disable RAS feature per IP block if it is not supported */ | |
2274 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2275 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2276 | return 0; | |
2277 | } | |
2278 | ||
2279 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2280 | if (r) { | |
2281 | if (r == -EAGAIN) { | |
2282 | /* request gpu reset. will run again */ | |
2283 | amdgpu_ras_request_reset_on_boot(adev, | |
2284 | ras_block->block); | |
2285 | return 0; | |
53b3f8f4 | 2286 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2287 | /* in resume phase, if fail to enable ras, |
2288 | * clean up all ras fs nodes, and disable ras */ | |
2289 | goto cleanup; | |
2290 | } else | |
2291 | return r; | |
2292 | } | |
2293 | ||
134d16d5 JC |
2294 | /* check for errors on warm reset edc persisant supported ASIC */ |
2295 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2296 | ||
b293e891 | 2297 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2298 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2299 | return 0; |
2300 | ||
2301 | if (ih_info->cb) { | |
2302 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2303 | if (r) | |
2304 | goto interrupt; | |
2305 | } | |
2306 | ||
b293e891 HZ |
2307 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2308 | if (r) | |
2309 | goto sysfs; | |
2310 | ||
05adfd80 LT |
2311 | /* Those are the cached values at init. |
2312 | */ | |
2313 | amdgpu_ras_query_error_count(adev, &ce_count, &ue_count); | |
2314 | atomic_set(&con->ras_ce_count, ce_count); | |
2315 | atomic_set(&con->ras_ue_count, ue_count); | |
2316 | ||
b293e891 HZ |
2317 | return 0; |
2318 | cleanup: | |
2319 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2320 | sysfs: | |
b293e891 HZ |
2321 | if (ih_info->cb) |
2322 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2323 | interrupt: | |
2324 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2325 | return r; | |
2326 | } | |
2327 | ||
2328 | /* helper function to remove ras fs node and interrupt handler */ | |
2329 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2330 | struct ras_common_if *ras_block, | |
2331 | struct ras_ih_if *ih_info) | |
2332 | { | |
2333 | if (!ras_block || !ih_info) | |
2334 | return; | |
2335 | ||
2336 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2337 | if (ih_info->cb) |
f3729f7b | 2338 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2339 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2340 | } | |
2341 | ||
a564808e | 2342 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2343 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2344 | */ |
511fdbc3 | 2345 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2346 | { |
2347 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2348 | struct ras_manager *obj, *tmp; | |
2349 | ||
8ab0d6f0 | 2350 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2351 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2352 | amdgpu_release_ras_context(adev); | |
2353 | ||
108c6a63 | 2354 | return; |
970fd197 | 2355 | } |
108c6a63 | 2356 | |
108c6a63 | 2357 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2358 | /* Set up all other IPs which are not implemented. There is a |
2359 | * tricky thing that IP's actual ras error type should be | |
2360 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2361 | * ERROR_NONE make sense anyway. | |
2362 | */ | |
2363 | amdgpu_ras_enable_all_features(adev, 1); | |
2364 | ||
2365 | /* We enable ras on all hw_supported block, but as boot | |
2366 | * parameter might disable some of them and one or more IP has | |
2367 | * not implemented yet. So we disable them on behalf. | |
2368 | */ | |
108c6a63 | 2369 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2370 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2371 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2372 | /* there should be no any reference. */ | |
2373 | WARN_ON(alive_obj(obj)); | |
2374 | } | |
191051a1 | 2375 | } |
108c6a63 | 2376 | } |
a564808e | 2377 | |
2378 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2379 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2380 | /* setup ras obj state as disabled. | |
2381 | * for init_by_vbios case. | |
2382 | * if we want to enable ras, just enable it in a normal way. | |
2383 | * If we want do disable it, need setup ras obj as enabled, | |
2384 | * then issue another TA disable cmd. | |
2385 | * See feature_enable_on_boot | |
2386 | */ | |
2387 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2388 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2389 | } |
108c6a63 | 2390 | } |
2391 | ||
511fdbc3 | 2392 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2393 | { | |
2394 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2395 | ||
8ab0d6f0 | 2396 | if (!adev->ras_enabled || !con) |
511fdbc3 | 2397 | return; |
2398 | ||
2399 | amdgpu_ras_disable_all_features(adev, 0); | |
2400 | /* Make sure all ras objects are disabled. */ | |
2401 | if (con->features) | |
2402 | amdgpu_ras_disable_all_features(adev, 1); | |
2403 | } | |
2404 | ||
c030f2e4 | 2405 | /* do some fini work before IP fini as dependence */ |
2406 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2407 | { | |
2408 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2409 | ||
8ab0d6f0 | 2410 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2411 | return 0; |
2412 | ||
72c8c97b | 2413 | |
c030f2e4 | 2414 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
2415 | amdgpu_ras_disable_all_features(adev, 0); | |
2416 | amdgpu_ras_recovery_fini(adev); | |
2417 | return 0; | |
2418 | } | |
2419 | ||
2420 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2421 | { | |
2422 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2423 | ||
8ab0d6f0 | 2424 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2425 | return 0; |
2426 | ||
2427 | amdgpu_ras_fs_fini(adev); | |
2428 | amdgpu_ras_interrupt_remove_all(adev); | |
2429 | ||
2430 | WARN(con->features, "Feature mask is not cleared"); | |
2431 | ||
2432 | if (con->features) | |
2433 | amdgpu_ras_disable_all_features(adev, 1); | |
2434 | ||
05adfd80 LT |
2435 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
2436 | ||
c030f2e4 | 2437 | amdgpu_ras_set_context(adev, NULL); |
2438 | kfree(con); | |
2439 | ||
2440 | return 0; | |
2441 | } | |
7c6e68c7 AG |
2442 | |
2443 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2444 | { | |
e509965e | 2445 | amdgpu_ras_check_supported(adev); |
8ab0d6f0 | 2446 | if (!adev->ras_hw_enabled) |
ed606f8a AG |
2447 | return; |
2448 | ||
7c6e68c7 | 2449 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2450 | dev_info(adev->dev, "uncorrectable hardware error" |
2451 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2452 | |
61934624 | 2453 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2454 | } |
2455 | } | |
bb5c7235 WS |
2456 | |
2457 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2458 | { | |
2459 | if (adev->asic_type == CHIP_VEGA20 && | |
2460 | adev->pm.fw_version <= 0x283400) { | |
2461 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2462 | amdgpu_ras_intr_triggered(); | |
2463 | } | |
2464 | ||
2465 | return false; | |
2466 | } | |
970fd197 SY |
2467 | |
2468 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
2469 | { | |
2470 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2471 | ||
2472 | if (!con) | |
2473 | return; | |
2474 | ||
8ab0d6f0 | 2475 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
2476 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
2477 | amdgpu_ras_set_context(adev, NULL); | |
2478 | kfree(con); | |
2479 | } | |
2480 | } |