Commit | Line | Data |
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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
eb0c3cd4 GC |
37 | static const char *RAS_FS_NAME = "ras"; |
38 | ||
c030f2e4 | 39 | const char *ras_error_string[] = { |
40 | "none", | |
41 | "parity", | |
42 | "single_correctable", | |
43 | "multi_uncorrectable", | |
44 | "poison", | |
45 | }; | |
46 | ||
47 | const char *ras_block_string[] = { | |
48 | "umc", | |
49 | "sdma", | |
50 | "gfx", | |
51 | "mmhub", | |
52 | "athub", | |
53 | "pcie_bif", | |
54 | "hdp", | |
55 | "xgmi_wafl", | |
56 | "df", | |
57 | "smn", | |
58 | "sem", | |
59 | "mp0", | |
60 | "mp1", | |
61 | "fuse", | |
62 | }; | |
63 | ||
64 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
65 | #define ras_block_str(i) (ras_block_string[i]) | |
66 | ||
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
c84d4670 GC |
72 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
73 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
74 | ||
52dd95f2 GC |
75 | enum amdgpu_ras_retire_page_reservation { |
76 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
77 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
78 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
79 | }; | |
7c6e68c7 AG |
80 | |
81 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
82 | ||
676deb38 DL |
83 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
84 | uint64_t addr); | |
6e4be987 TZ |
85 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
86 | uint64_t addr); | |
87 | ||
61380faa JC |
88 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
89 | { | |
a9d82d2f | 90 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
91 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
92 | } | |
93 | ||
f3167919 | 94 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 95 | { |
a9d82d2f | 96 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
97 | return amdgpu_ras_get_context(adev)->error_query_ready; |
98 | ||
99 | return false; | |
100 | } | |
101 | ||
c030f2e4 | 102 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
103 | size_t size, loff_t *pos) | |
104 | { | |
105 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
106 | struct ras_query_if info = { | |
107 | .head = obj->head, | |
108 | }; | |
109 | ssize_t s; | |
110 | char val[128]; | |
111 | ||
112 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
113 | return -EINVAL; | |
114 | ||
115 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
116 | "ue", info.ue_count, | |
117 | "ce", info.ce_count); | |
118 | if (*pos >= s) | |
119 | return 0; | |
120 | ||
121 | s -= *pos; | |
122 | s = min_t(u64, s, size); | |
123 | ||
124 | ||
125 | if (copy_to_user(buf, &val[*pos], s)) | |
126 | return -EINVAL; | |
127 | ||
128 | *pos += s; | |
129 | ||
130 | return s; | |
131 | } | |
132 | ||
c030f2e4 | 133 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
134 | .owner = THIS_MODULE, | |
135 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 136 | .write = NULL, |
c030f2e4 | 137 | .llseek = default_llseek |
138 | }; | |
139 | ||
96ebb307 | 140 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
141 | { | |
142 | int i; | |
143 | ||
144 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
145 | *block_id = i; | |
146 | if (strcmp(name, ras_block_str(i)) == 0) | |
147 | return 0; | |
148 | } | |
149 | return -EINVAL; | |
150 | } | |
151 | ||
152 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
153 | const char __user *buf, size_t size, | |
154 | loff_t *pos, struct ras_debug_if *data) | |
155 | { | |
156 | ssize_t s = min_t(u64, 64, size); | |
157 | char str[65]; | |
158 | char block_name[33]; | |
159 | char err[9] = "ue"; | |
160 | int op = -1; | |
161 | int block_id; | |
44494f96 | 162 | uint32_t sub_block; |
96ebb307 | 163 | u64 address, value; |
164 | ||
165 | if (*pos) | |
166 | return -EINVAL; | |
167 | *pos = size; | |
168 | ||
169 | memset(str, 0, sizeof(str)); | |
170 | memset(data, 0, sizeof(*data)); | |
171 | ||
172 | if (copy_from_user(str, buf, s)) | |
173 | return -EINVAL; | |
174 | ||
175 | if (sscanf(str, "disable %32s", block_name) == 1) | |
176 | op = 0; | |
177 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
178 | op = 1; | |
179 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
180 | op = 2; | |
b076296b | 181 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 182 | /* ascii string, but commands are not matched. */ |
183 | return -EINVAL; | |
184 | ||
185 | if (op != -1) { | |
186 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
187 | return -EINVAL; | |
188 | ||
189 | data->head.block = block_id; | |
e1063493 TZ |
190 | /* only ue and ce errors are supported */ |
191 | if (!memcmp("ue", err, 2)) | |
192 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
193 | else if (!memcmp("ce", err, 2)) | |
194 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
195 | else | |
196 | return -EINVAL; | |
197 | ||
96ebb307 | 198 | data->op = op; |
199 | ||
200 | if (op == 2) { | |
44494f96 TZ |
201 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
202 | &sub_block, &address, &value) != 3) | |
203 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
204 | &sub_block, &address, &value) != 3) | |
96ebb307 | 205 | return -EINVAL; |
44494f96 | 206 | data->head.sub_block_index = sub_block; |
96ebb307 | 207 | data->inject.address = address; |
208 | data->inject.value = value; | |
209 | } | |
210 | } else { | |
73aa8e1a | 211 | if (size < sizeof(*data)) |
96ebb307 | 212 | return -EINVAL; |
213 | ||
214 | if (copy_from_user(data, buf, sizeof(*data))) | |
215 | return -EINVAL; | |
216 | } | |
217 | ||
218 | return 0; | |
219 | } | |
7c6e68c7 | 220 | |
74abc221 TSD |
221 | /** |
222 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 223 | * |
224 | * It accepts struct ras_debug_if who has two members. | |
225 | * | |
226 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 227 | * |
228 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 229 | * |
230 | * head has four members, they are block, type, sub_block_index, name. | |
231 | * block: which IP will be under control. | |
232 | * type: what kind of error will be enabled/disabled/injected. | |
233 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
234 | * name: the name of IP. | |
235 | * | |
236 | * inject has two more members than head, they are address, value. | |
237 | * As their names indicate, inject operation will write the | |
238 | * value to the address. | |
239 | * | |
ef177d11 | 240 | * The second member: struct ras_debug_if::op. |
c688a06b | 241 | * It has three kinds of operations. |
879e723d AZ |
242 | * |
243 | * - 0: disable RAS on the block. Take ::head as its data. | |
244 | * - 1: enable RAS on the block. Take ::head as its data. | |
245 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 246 | * |
96ebb307 | 247 | * How to use the interface? |
ef177d11 AD |
248 | * |
249 | * Programs | |
250 | * | |
251 | * Copy the struct ras_debug_if in your codes and initialize it. | |
252 | * Write the struct to the control node. | |
253 | * | |
254 | * Shells | |
96ebb307 | 255 | * |
879e723d AZ |
256 | * .. code-block:: bash |
257 | * | |
a20bfd0f | 258 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 259 | * |
ef177d11 AD |
260 | * Parameters: |
261 | * | |
879e723d AZ |
262 | * op: disable, enable, inject |
263 | * disable: only block is needed | |
264 | * enable: block and error are needed | |
265 | * inject: error, address, value are needed | |
a20bfd0f | 266 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
267 | * see ras_block_string[] for details |
268 | * error: ue, ce | |
269 | * ue: multi_uncorrectable | |
270 | * ce: single_correctable | |
271 | * sub_block: | |
272 | * sub block index, pass 0 if there is no sub block | |
273 | * | |
274 | * here are some examples for bash commands: | |
275 | * | |
276 | * .. code-block:: bash | |
96ebb307 | 277 | * |
44494f96 TZ |
278 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
279 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 280 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
281 | * | |
36ea1bd2 | 282 | * How to check the result? |
283 | * | |
284 | * For disable/enable, please check ras features at | |
285 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
286 | * | |
287 | * For inject, please check corresponding err count at | |
288 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
289 | * | |
879e723d | 290 | * .. note:: |
ef177d11 | 291 | * Operations are only allowed on blocks which are supported. |
879e723d | 292 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
293 | * to see which blocks support RAS on a particular asic. |
294 | * | |
36ea1bd2 | 295 | */ |
296 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
297 | size_t size, loff_t *pos) | |
298 | { | |
299 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
300 | struct ras_debug_if data; | |
301 | int ret = 0; | |
302 | ||
61380faa | 303 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
304 | dev_warn(adev->dev, "RAS WARN: error injection " |
305 | "currently inaccessible\n"); | |
43c4d576 JC |
306 | return size; |
307 | } | |
308 | ||
96ebb307 | 309 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
310 | if (ret) | |
36ea1bd2 | 311 | return -EINVAL; |
312 | ||
36ea1bd2 | 313 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
314 | return -EINVAL; | |
315 | ||
316 | switch (data.op) { | |
317 | case 0: | |
318 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
319 | break; | |
320 | case 1: | |
321 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
322 | break; | |
323 | case 2: | |
7cdc2ee3 TZ |
324 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
325 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
326 | dev_warn(adev->dev, "RAS WARN: input address " |
327 | "0x%llx is invalid.", | |
328 | data.inject.address); | |
7cdc2ee3 TZ |
329 | ret = -EINVAL; |
330 | break; | |
331 | } | |
332 | ||
6e4be987 TZ |
333 | /* umc ce/ue error injection for a bad page is not allowed */ |
334 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
335 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
336 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
337 | "as bad before error injection!\n", | |
6e4be987 TZ |
338 | data.inject.address); |
339 | break; | |
340 | } | |
341 | ||
7cdc2ee3 | 342 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 343 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
344 | break; | |
96ebb307 | 345 | default: |
346 | ret = -EINVAL; | |
347 | break; | |
374bf7bd | 348 | } |
36ea1bd2 | 349 | |
350 | if (ret) | |
351 | return -EINVAL; | |
352 | ||
353 | return size; | |
354 | } | |
355 | ||
084fe13b AG |
356 | /** |
357 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
358 | * | |
f77c7109 | 359 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 360 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
361 | * a way to reset the EEPROM, e.g., after testing error injection. |
362 | * | |
363 | * Usage: | |
364 | * | |
365 | * .. code-block:: bash | |
366 | * | |
367 | * echo 1 > ../ras/ras_eeprom_reset | |
368 | * | |
369 | * will reset EEPROM table to 0 entries. | |
370 | * | |
084fe13b AG |
371 | */ |
372 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
373 | size_t size, loff_t *pos) | |
374 | { | |
bf0b91b7 GC |
375 | struct amdgpu_device *adev = |
376 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
377 | int ret; |
378 | ||
bf0b91b7 GC |
379 | ret = amdgpu_ras_eeprom_reset_table( |
380 | &(amdgpu_ras_get_context(adev)->eeprom_control)); | |
084fe13b | 381 | |
bf0b91b7 GC |
382 | if (ret == 1) { |
383 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; | |
384 | return size; | |
385 | } else { | |
386 | return -EIO; | |
387 | } | |
084fe13b AG |
388 | } |
389 | ||
36ea1bd2 | 390 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
391 | .owner = THIS_MODULE, | |
392 | .read = NULL, | |
393 | .write = amdgpu_ras_debugfs_ctrl_write, | |
394 | .llseek = default_llseek | |
395 | }; | |
396 | ||
084fe13b AG |
397 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
398 | .owner = THIS_MODULE, | |
399 | .read = NULL, | |
400 | .write = amdgpu_ras_debugfs_eeprom_write, | |
401 | .llseek = default_llseek | |
402 | }; | |
403 | ||
f77c7109 AD |
404 | /** |
405 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
406 | * | |
ef177d11 | 407 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
408 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
409 | * | |
410 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
411 | * (ce) error counts. | |
412 | * | |
413 | * The format of one line is below, | |
414 | * | |
415 | * [ce|ue]: count | |
416 | * | |
417 | * Example: | |
418 | * | |
419 | * .. code-block:: bash | |
420 | * | |
421 | * ue: 0 | |
422 | * ce: 1 | |
423 | * | |
424 | */ | |
c030f2e4 | 425 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
426 | struct device_attribute *attr, char *buf) | |
427 | { | |
428 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
429 | struct ras_query_if info = { | |
430 | .head = obj->head, | |
431 | }; | |
432 | ||
61380faa | 433 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
43c4d576 JC |
434 | return snprintf(buf, PAGE_SIZE, |
435 | "Query currently inaccessible\n"); | |
436 | ||
c030f2e4 | 437 | if (amdgpu_ras_error_query(obj->adev, &info)) |
438 | return -EINVAL; | |
439 | ||
440 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
441 | "ue", info.ue_count, | |
442 | "ce", info.ce_count); | |
443 | } | |
444 | ||
445 | /* obj begin */ | |
446 | ||
447 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
448 | #define alive_obj(obj) ((obj)->use) | |
449 | ||
450 | static inline void put_obj(struct ras_manager *obj) | |
451 | { | |
452 | if (obj && --obj->use == 0) | |
453 | list_del(&obj->node); | |
454 | if (obj && obj->use < 0) { | |
455 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
456 | } | |
457 | } | |
458 | ||
459 | /* make one obj and return it. */ | |
460 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
461 | struct ras_common_if *head) | |
462 | { | |
463 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
464 | struct ras_manager *obj; | |
465 | ||
466 | if (!con) | |
467 | return NULL; | |
468 | ||
469 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
470 | return NULL; | |
471 | ||
472 | obj = &con->objs[head->block]; | |
473 | /* already exist. return obj? */ | |
474 | if (alive_obj(obj)) | |
475 | return NULL; | |
476 | ||
477 | obj->head = *head; | |
478 | obj->adev = adev; | |
479 | list_add(&obj->node, &con->head); | |
480 | get_obj(obj); | |
481 | ||
482 | return obj; | |
483 | } | |
484 | ||
485 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 486 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 487 | struct ras_common_if *head) |
488 | { | |
489 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
490 | struct ras_manager *obj; | |
491 | int i; | |
492 | ||
493 | if (!con) | |
494 | return NULL; | |
495 | ||
496 | if (head) { | |
497 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
498 | return NULL; | |
499 | ||
500 | obj = &con->objs[head->block]; | |
501 | ||
502 | if (alive_obj(obj)) { | |
503 | WARN_ON(head->block != obj->head.block); | |
504 | return obj; | |
505 | } | |
506 | } else { | |
507 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
508 | obj = &con->objs[i]; | |
509 | if (alive_obj(obj)) { | |
510 | WARN_ON(i != obj->head.block); | |
511 | return obj; | |
512 | } | |
513 | } | |
514 | } | |
515 | ||
516 | return NULL; | |
517 | } | |
518 | /* obj end */ | |
519 | ||
f3167919 | 520 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
f3729f7b DV |
521 | const char* invoke_type, |
522 | const char* block_name, | |
523 | enum ta_ras_status ret) | |
a200034b JC |
524 | { |
525 | switch (ret) { | |
526 | case TA_RAS_STATUS__SUCCESS: | |
527 | return; | |
528 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
529 | dev_warn(adev->dev, | |
530 | "RAS WARN: %s %s currently unavailable\n", | |
531 | invoke_type, | |
532 | block_name); | |
533 | break; | |
534 | default: | |
535 | dev_err(adev->dev, | |
536 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
537 | invoke_type, | |
538 | block_name, | |
539 | ret); | |
540 | } | |
541 | } | |
542 | ||
c030f2e4 | 543 | /* feature ctl begin */ |
544 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
545 | struct ras_common_if *head) | |
546 | { | |
5caf466a | 547 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
548 | ||
549 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 550 | } |
551 | ||
552 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
553 | struct ras_common_if *head) | |
554 | { | |
555 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
556 | ||
557 | return con->features & BIT(head->block); | |
558 | } | |
559 | ||
560 | /* | |
561 | * if obj is not created, then create one. | |
562 | * set feature enable flag. | |
563 | */ | |
564 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
565 | struct ras_common_if *head, int enable) | |
566 | { | |
567 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
568 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
569 | ||
5caf466a | 570 | /* If hardware does not support ras, then do not create obj. |
571 | * But if hardware support ras, we can create the obj. | |
572 | * Ras framework checks con->hw_supported to see if it need do | |
573 | * corresponding initialization. | |
574 | * IP checks con->support to see if it need disable ras. | |
575 | */ | |
c030f2e4 | 576 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
577 | return 0; | |
578 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
579 | return 0; | |
580 | ||
581 | if (enable) { | |
582 | if (!obj) { | |
583 | obj = amdgpu_ras_create_obj(adev, head); | |
584 | if (!obj) | |
585 | return -EINVAL; | |
586 | } else { | |
587 | /* In case we create obj somewhere else */ | |
588 | get_obj(obj); | |
589 | } | |
590 | con->features |= BIT(head->block); | |
591 | } else { | |
592 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
593 | con->features &= ~BIT(head->block); | |
594 | put_obj(obj); | |
595 | } | |
596 | } | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
601 | /* wrapper of psp_ras_enable_features */ | |
602 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
603 | struct ras_common_if *head, bool enable) | |
604 | { | |
605 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 606 | union ta_ras_cmd_input *info; |
c030f2e4 | 607 | int ret; |
608 | ||
609 | if (!con) | |
610 | return -EINVAL; | |
611 | ||
f3729f7b | 612 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
7fcffecf AB |
613 | if (!info) |
614 | return -ENOMEM; | |
615 | ||
c030f2e4 | 616 | if (!enable) { |
7fcffecf | 617 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 618 | .block_id = amdgpu_ras_block_to_ta(head->block), |
619 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 620 | }; |
621 | } else { | |
7fcffecf | 622 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 623 | .block_id = amdgpu_ras_block_to_ta(head->block), |
624 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 625 | }; |
626 | } | |
627 | ||
628 | /* Do not enable if it is not allowed. */ | |
629 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
630 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
631 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
632 | ret = 0; | |
633 | goto out; | |
634 | } | |
c030f2e4 | 635 | |
bff77e86 | 636 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 637 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 638 | if (ret) { |
a200034b JC |
639 | amdgpu_ras_parse_status_code(adev, |
640 | enable ? "enable":"disable", | |
641 | ras_block_str(head->block), | |
642 | (enum ta_ras_status)ret); | |
bff77e86 | 643 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
644 | ret = -EAGAIN; |
645 | else | |
646 | ret = -EINVAL; | |
647 | ||
648 | goto out; | |
bff77e86 | 649 | } |
c030f2e4 | 650 | } |
651 | ||
652 | /* setup the obj */ | |
653 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
654 | ret = 0; |
655 | out: | |
656 | kfree(info); | |
657 | return ret; | |
c030f2e4 | 658 | } |
659 | ||
77de502b | 660 | /* Only used in device probe stage and called only once. */ |
661 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
662 | struct ras_common_if *head, bool enable) | |
663 | { | |
664 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
665 | int ret; | |
666 | ||
667 | if (!con) | |
668 | return -EINVAL; | |
669 | ||
670 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 671 | if (enable) { |
672 | /* There is no harm to issue a ras TA cmd regardless of | |
673 | * the currecnt ras state. | |
674 | * If current state == target state, it will do nothing | |
675 | * But sometimes it requests driver to reset and repost | |
676 | * with error code -EAGAIN. | |
677 | */ | |
678 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
679 | /* With old ras TA, we might fail to enable ras. | |
680 | * Log it and just setup the object. | |
681 | * TODO need remove this WA in the future. | |
682 | */ | |
683 | if (ret == -EINVAL) { | |
684 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
685 | if (!ret) | |
6952e99c GC |
686 | dev_info(adev->dev, |
687 | "RAS INFO: %s setup object\n", | |
7af23ebe | 688 | ras_block_str(head->block)); |
689 | } | |
690 | } else { | |
691 | /* setup the object then issue a ras TA disable cmd.*/ | |
692 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
693 | if (ret) | |
694 | return ret; | |
77de502b | 695 | |
77de502b | 696 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 697 | } |
77de502b | 698 | } else |
699 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
700 | ||
701 | return ret; | |
702 | } | |
703 | ||
c030f2e4 | 704 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
705 | bool bypass) | |
706 | { | |
707 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
708 | struct ras_manager *obj, *tmp; | |
709 | ||
710 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
711 | /* bypass psp. | |
712 | * aka just release the obj and corresponding flags | |
713 | */ | |
714 | if (bypass) { | |
715 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
716 | break; | |
717 | } else { | |
718 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
719 | break; | |
720 | } | |
289d513b | 721 | } |
c030f2e4 | 722 | |
723 | return con->features; | |
724 | } | |
725 | ||
726 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
727 | bool bypass) | |
728 | { | |
729 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
730 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
731 | int i; | |
191051a1 | 732 | const enum amdgpu_ras_error_type default_ras_type = |
733 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 734 | |
735 | for (i = 0; i < ras_block_count; i++) { | |
736 | struct ras_common_if head = { | |
737 | .block = i, | |
191051a1 | 738 | .type = default_ras_type, |
c030f2e4 | 739 | .sub_block_index = 0, |
740 | }; | |
741 | strcpy(head.name, ras_block_str(i)); | |
742 | if (bypass) { | |
743 | /* | |
744 | * bypass psp. vbios enable ras for us. | |
745 | * so just create the obj | |
746 | */ | |
747 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
748 | break; | |
749 | } else { | |
750 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
751 | break; | |
752 | } | |
289d513b | 753 | } |
c030f2e4 | 754 | |
755 | return con->features; | |
756 | } | |
757 | /* feature ctl end */ | |
758 | ||
759 | /* query/inject/cure begin */ | |
760 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
761 | struct ras_query_if *info) | |
762 | { | |
763 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 764 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 765 | int i; |
c030f2e4 | 766 | |
767 | if (!obj) | |
768 | return -EINVAL; | |
c030f2e4 | 769 | |
939e2258 HZ |
770 | switch (info->head.block) { |
771 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
772 | if (adev->umc.funcs->query_ras_error_count) |
773 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
774 | /* umc query_ras_error_address is also responsible for clearing |
775 | * error status | |
776 | */ | |
777 | if (adev->umc.funcs->query_ras_error_address) | |
778 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 779 | break; |
3e81ee9a HZ |
780 | case AMDGPU_RAS_BLOCK__SDMA: |
781 | if (adev->sdma.funcs->query_ras_error_count) { | |
782 | for (i = 0; i < adev->sdma.num_instances; i++) | |
783 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
784 | &err_data); | |
785 | } | |
786 | break; | |
83b0582c DL |
787 | case AMDGPU_RAS_BLOCK__GFX: |
788 | if (adev->gfx.funcs->query_ras_error_count) | |
789 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
790 | break; | |
9fb2d8de | 791 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
792 | if (adev->mmhub.funcs->query_ras_error_count) |
793 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 794 | break; |
d7bd680d GC |
795 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
796 | if (adev->nbio.funcs->query_ras_error_count) | |
797 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
798 | break; | |
ec01fe2d HZ |
799 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
800 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
801 | break; | |
939e2258 HZ |
802 | default: |
803 | break; | |
804 | } | |
05a58345 TZ |
805 | |
806 | obj->err_data.ue_count += err_data.ue_count; | |
807 | obj->err_data.ce_count += err_data.ce_count; | |
808 | ||
c030f2e4 | 809 | info->ue_count = obj->err_data.ue_count; |
810 | info->ce_count = obj->err_data.ce_count; | |
811 | ||
7c6e68c7 | 812 | if (err_data.ce_count) { |
6952e99c GC |
813 | dev_info(adev->dev, "%ld correctable hardware errors " |
814 | "detected in %s block, no user " | |
815 | "action is needed.\n", | |
816 | obj->err_data.ce_count, | |
817 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
818 | } |
819 | if (err_data.ue_count) { | |
6952e99c GC |
820 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
821 | "detected in %s block\n", | |
822 | obj->err_data.ue_count, | |
823 | ras_block_str(info->head.block)); | |
7c6e68c7 | 824 | } |
05a58345 | 825 | |
c030f2e4 | 826 | return 0; |
827 | } | |
828 | ||
5c23e9e0 | 829 | /* Trigger XGMI/WAFL error */ |
f3167919 | 830 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
831 | struct ta_ras_trigger_error_input *block_info) |
832 | { | |
833 | int ret; | |
834 | ||
835 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
836 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
837 | ||
838 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
839 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
840 | ||
841 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
842 | ||
843 | if (amdgpu_ras_intr_triggered()) | |
844 | return ret; | |
845 | ||
846 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
847 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
848 | ||
849 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
850 | dev_warn(adev->dev, "Failed to allow df cstate"); | |
851 | ||
852 | return ret; | |
853 | } | |
854 | ||
c030f2e4 | 855 | /* wrapper of psp_ras_trigger_error */ |
856 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
857 | struct ras_inject_if *info) | |
858 | { | |
859 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
860 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 861 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
862 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 863 | .sub_block_index = info->head.sub_block_index, |
864 | .address = info->address, | |
865 | .value = info->value, | |
866 | }; | |
867 | int ret = 0; | |
868 | ||
869 | if (!obj) | |
870 | return -EINVAL; | |
871 | ||
a6c44d25 JC |
872 | /* Calculate XGMI relative offset */ |
873 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
874 | block_info.address = |
875 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
876 | block_info.address); | |
a6c44d25 JC |
877 | } |
878 | ||
83b0582c DL |
879 | switch (info->head.block) { |
880 | case AMDGPU_RAS_BLOCK__GFX: | |
881 | if (adev->gfx.funcs->ras_error_inject) | |
882 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
883 | else | |
884 | ret = -EINVAL; | |
885 | break; | |
886 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 887 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 888 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
889 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
890 | break; | |
5c23e9e0 JC |
891 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
892 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
893 | break; | |
83b0582c | 894 | default: |
6952e99c | 895 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 896 | ras_block_str(info->head.block)); |
83b0582c | 897 | ret = -EINVAL; |
a5dd40ca HZ |
898 | } |
899 | ||
a200034b JC |
900 | amdgpu_ras_parse_status_code(adev, |
901 | "inject", | |
902 | ras_block_str(info->head.block), | |
903 | (enum ta_ras_status)ret); | |
c030f2e4 | 904 | |
905 | return ret; | |
906 | } | |
907 | ||
c030f2e4 | 908 | /* get the total error counts on all IPs */ |
64cc5414 | 909 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 910 | bool is_ce) |
911 | { | |
912 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
913 | struct ras_manager *obj; | |
914 | struct ras_err_data data = {0, 0}; | |
915 | ||
916 | if (!con) | |
64cc5414 | 917 | return 0; |
c030f2e4 | 918 | |
919 | list_for_each_entry(obj, &con->head, node) { | |
920 | struct ras_query_if info = { | |
921 | .head = obj->head, | |
922 | }; | |
923 | ||
924 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 925 | return 0; |
c030f2e4 | 926 | |
927 | data.ce_count += info.ce_count; | |
928 | data.ue_count += info.ue_count; | |
929 | } | |
930 | ||
931 | return is_ce ? data.ce_count : data.ue_count; | |
932 | } | |
933 | /* query/inject/cure end */ | |
934 | ||
935 | ||
936 | /* sysfs begin */ | |
937 | ||
466b1793 | 938 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
939 | struct ras_badpage **bps, unsigned int *count); | |
940 | ||
941 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
942 | { | |
943 | switch (flags) { | |
52dd95f2 | 944 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 945 | return "R"; |
52dd95f2 | 946 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 947 | return "P"; |
52dd95f2 | 948 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 949 | default: |
950 | return "F"; | |
aec576f9 | 951 | } |
466b1793 | 952 | } |
953 | ||
f77c7109 AD |
954 | /** |
955 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 956 | * |
957 | * It allows user to read the bad pages of vram on the gpu through | |
958 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
959 | * | |
960 | * It outputs multiple lines, and each line stands for one gpu page. | |
961 | * | |
962 | * The format of one line is below, | |
963 | * gpu pfn : gpu page size : flags | |
964 | * | |
965 | * gpu pfn and gpu page size are printed in hex format. | |
966 | * flags can be one of below character, | |
f77c7109 | 967 | * |
466b1793 | 968 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 969 | * |
466b1793 | 970 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
971 | * in next window of page_reserve. |
972 | * | |
466b1793 | 973 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
974 | * | |
f77c7109 AD |
975 | * Examples: |
976 | * | |
977 | * .. code-block:: bash | |
978 | * | |
979 | * 0x00000001 : 0x00001000 : R | |
980 | * 0x00000002 : 0x00001000 : P | |
981 | * | |
466b1793 | 982 | */ |
983 | ||
984 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
985 | struct kobject *kobj, struct bin_attribute *attr, | |
986 | char *buf, loff_t ppos, size_t count) | |
987 | { | |
988 | struct amdgpu_ras *con = | |
989 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
990 | struct amdgpu_device *adev = con->adev; | |
991 | const unsigned int element_size = | |
992 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
993 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
994 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 995 | ssize_t s = 0; |
996 | struct ras_badpage *bps = NULL; | |
997 | unsigned int bps_count = 0; | |
998 | ||
999 | memset(buf, 0, count); | |
1000 | ||
1001 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1002 | return 0; | |
1003 | ||
1004 | for (; start < end && start < bps_count; start++) | |
1005 | s += scnprintf(&buf[s], element_size + 1, | |
1006 | "0x%08x : 0x%08x : %1s\n", | |
1007 | bps[start].bp, | |
1008 | bps[start].size, | |
1009 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1010 | ||
1011 | kfree(bps); | |
1012 | ||
1013 | return s; | |
1014 | } | |
1015 | ||
c030f2e4 | 1016 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1017 | struct device_attribute *attr, char *buf) | |
1018 | { | |
1019 | struct amdgpu_ras *con = | |
1020 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1021 | |
5212a3bd | 1022 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1023 | } |
1024 | ||
f848159b GC |
1025 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1026 | { | |
1027 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1028 | ||
1029 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1030 | &con->badpages_attr.attr, | |
1031 | RAS_FS_NAME); | |
1032 | } | |
1033 | ||
c030f2e4 | 1034 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1035 | { | |
1036 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1037 | struct attribute *attrs[] = { | |
1038 | &con->features_attr.attr, | |
1039 | NULL | |
1040 | }; | |
1041 | struct attribute_group group = { | |
eb0c3cd4 | 1042 | .name = RAS_FS_NAME, |
c030f2e4 | 1043 | .attrs = attrs, |
1044 | }; | |
1045 | ||
1046 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1047 | ||
1048 | return 0; | |
1049 | } | |
1050 | ||
1051 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1052 | struct ras_fs_if *head) | |
1053 | { | |
1054 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1055 | ||
1056 | if (!obj || obj->attr_inuse) | |
1057 | return -EINVAL; | |
1058 | ||
1059 | get_obj(obj); | |
1060 | ||
1061 | memcpy(obj->fs_data.sysfs_name, | |
1062 | head->sysfs_name, | |
1063 | sizeof(obj->fs_data.sysfs_name)); | |
1064 | ||
1065 | obj->sysfs_attr = (struct device_attribute){ | |
1066 | .attr = { | |
1067 | .name = obj->fs_data.sysfs_name, | |
1068 | .mode = S_IRUGO, | |
1069 | }, | |
1070 | .show = amdgpu_ras_sysfs_read, | |
1071 | }; | |
163def43 | 1072 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1073 | |
1074 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1075 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1076 | RAS_FS_NAME)) { |
c030f2e4 | 1077 | put_obj(obj); |
1078 | return -EINVAL; | |
1079 | } | |
1080 | ||
1081 | obj->attr_inuse = 1; | |
1082 | ||
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1087 | struct ras_common_if *head) | |
1088 | { | |
1089 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1090 | ||
1091 | if (!obj || !obj->attr_inuse) | |
1092 | return -EINVAL; | |
1093 | ||
1094 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1095 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1096 | RAS_FS_NAME); |
c030f2e4 | 1097 | obj->attr_inuse = 0; |
1098 | put_obj(obj); | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1104 | { | |
1105 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1106 | struct ras_manager *obj, *tmp; | |
1107 | ||
1108 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1109 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1110 | } | |
1111 | ||
f848159b GC |
1112 | if (amdgpu_bad_page_threshold != 0) |
1113 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1114 | ||
c030f2e4 | 1115 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | /* sysfs end */ | |
1120 | ||
ef177d11 AD |
1121 | /** |
1122 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1123 | * | |
1124 | * Normally when there is an uncorrectable error, the driver will reset | |
1125 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1126 | * the driver provides an interface to reboot the system automatically | |
1127 | * in that event. | |
1128 | * | |
1129 | * The following file in debugfs provides that interface: | |
1130 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1131 | * | |
1132 | * Usage: | |
1133 | * | |
1134 | * .. code-block:: bash | |
1135 | * | |
1136 | * echo true > .../ras/auto_reboot | |
1137 | * | |
1138 | */ | |
c030f2e4 | 1139 | /* debugfs begin */ |
450f30ea | 1140 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1141 | { |
1142 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4a580877 | 1143 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
36ea1bd2 | 1144 | |
eb0c3cd4 | 1145 | con->dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
012dd14d GC |
1146 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1147 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1148 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1149 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1150 | |
1151 | /* | |
1152 | * After one uncorrectable error happens, usually GPU recovery will | |
1153 | * be scheduled. But due to the known problem in GPU recovery failing | |
1154 | * to bring GPU back, below interface provides one direct way to | |
1155 | * user to reboot system automatically in such case within | |
1156 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1157 | * will never be called. | |
1158 | */ | |
1159 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1160 | &con->reboot); | |
66459e1d GC |
1161 | |
1162 | /* | |
1163 | * User could set this not to clean up hardware's error count register | |
1164 | * of RAS IPs during ras recovery. | |
1165 | */ | |
1166 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, | |
1167 | con->dir, &con->disable_ras_err_cnt_harvest); | |
36ea1bd2 | 1168 | } |
1169 | ||
450f30ea | 1170 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1171 | struct ras_fs_if *head) |
1172 | { | |
1173 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1174 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1175 | |
1176 | if (!obj || obj->ent) | |
450f30ea | 1177 | return; |
c030f2e4 | 1178 | |
1179 | get_obj(obj); | |
1180 | ||
1181 | memcpy(obj->fs_data.debugfs_name, | |
1182 | head->debugfs_name, | |
1183 | sizeof(obj->fs_data.debugfs_name)); | |
1184 | ||
450f30ea GKH |
1185 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1186 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1187 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1188 | } |
1189 | ||
f9317014 TZ |
1190 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1191 | { | |
ae2bf61f | 1192 | #if defined(CONFIG_DEBUG_FS) |
f9317014 | 1193 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c1509f3f | 1194 | struct ras_manager *obj; |
f9317014 TZ |
1195 | struct ras_fs_if fs_info; |
1196 | ||
1197 | /* | |
1198 | * it won't be called in resume path, no need to check | |
1199 | * suspend and gpu reset status | |
1200 | */ | |
1201 | if (!con) | |
1202 | return; | |
1203 | ||
1204 | amdgpu_ras_debugfs_create_ctrl_node(adev); | |
1205 | ||
c1509f3f | 1206 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1207 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1208 | (obj->attr_inuse == 1)) { | |
1209 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1210 | ras_block_str(obj->head.block)); | |
1211 | fs_info.head = obj->head; | |
1212 | amdgpu_ras_debugfs_create(adev, &fs_info); | |
1213 | } | |
1214 | } | |
ae2bf61f | 1215 | #endif |
f9317014 TZ |
1216 | } |
1217 | ||
450f30ea | 1218 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1219 | struct ras_common_if *head) |
1220 | { | |
1221 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1222 | ||
1223 | if (!obj || !obj->ent) | |
450f30ea | 1224 | return; |
c030f2e4 | 1225 | |
c030f2e4 | 1226 | obj->ent = NULL; |
1227 | put_obj(obj); | |
c030f2e4 | 1228 | } |
1229 | ||
450f30ea | 1230 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1231 | { |
ae2bf61f | 1232 | #if defined(CONFIG_DEBUG_FS) |
c030f2e4 | 1233 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1234 | struct ras_manager *obj, *tmp; | |
1235 | ||
1236 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1237 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1238 | } | |
1239 | ||
c030f2e4 | 1240 | con->dir = NULL; |
ae2bf61f | 1241 | #endif |
c030f2e4 | 1242 | } |
1243 | /* debugfs end */ | |
1244 | ||
1245 | /* ras fs */ | |
c3d4d45d GC |
1246 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1247 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1248 | static DEVICE_ATTR(features, S_IRUGO, | |
1249 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1250 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1251 | { | |
c3d4d45d GC |
1252 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1253 | struct attribute_group group = { | |
1254 | .name = RAS_FS_NAME, | |
1255 | }; | |
1256 | struct attribute *attrs[] = { | |
1257 | &con->features_attr.attr, | |
1258 | NULL | |
1259 | }; | |
1260 | struct bin_attribute *bin_attrs[] = { | |
1261 | NULL, | |
1262 | NULL, | |
1263 | }; | |
a069a9eb | 1264 | int r; |
c030f2e4 | 1265 | |
c3d4d45d GC |
1266 | /* add features entry */ |
1267 | con->features_attr = dev_attr_features; | |
1268 | group.attrs = attrs; | |
1269 | sysfs_attr_init(attrs[0]); | |
1270 | ||
1271 | if (amdgpu_bad_page_threshold != 0) { | |
1272 | /* add bad_page_features entry */ | |
1273 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1274 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1275 | bin_attrs[0] = &con->badpages_attr; | |
1276 | group.bin_attrs = bin_attrs; | |
1277 | sysfs_bin_attr_init(bin_attrs[0]); | |
1278 | } | |
1279 | ||
a069a9eb AD |
1280 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1281 | if (r) | |
1282 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1283 | |
c030f2e4 | 1284 | return 0; |
1285 | } | |
1286 | ||
1287 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1288 | { | |
1289 | amdgpu_ras_debugfs_remove_all(adev); | |
1290 | amdgpu_ras_sysfs_remove_all(adev); | |
1291 | return 0; | |
1292 | } | |
1293 | /* ras fs end */ | |
1294 | ||
1295 | /* ih begin */ | |
1296 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1297 | { | |
1298 | struct ras_ih_data *data = &obj->ih_data; | |
1299 | struct amdgpu_iv_entry entry; | |
1300 | int ret; | |
cf04dfd0 | 1301 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1302 | |
1303 | while (data->rptr != data->wptr) { | |
1304 | rmb(); | |
1305 | memcpy(&entry, &data->ring[data->rptr], | |
1306 | data->element_size); | |
1307 | ||
1308 | wmb(); | |
1309 | data->rptr = (data->aligned_element_size + | |
1310 | data->rptr) % data->ring_size; | |
1311 | ||
1312 | /* Let IP handle its data, maybe we need get the output | |
1313 | * from the callback to udpate the error type/count, etc | |
1314 | */ | |
1315 | if (data->cb) { | |
cf04dfd0 | 1316 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1317 | /* ue will trigger an interrupt, and in that case |
1318 | * we need do a reset to recovery the whole system. | |
1319 | * But leave IP do that recovery, here we just dispatch | |
1320 | * the error. | |
1321 | */ | |
bd2280da | 1322 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1323 | /* these counts could be left as 0 if |
1324 | * some blocks do not count error number | |
1325 | */ | |
cf04dfd0 | 1326 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1327 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1328 | } |
c030f2e4 | 1329 | } |
1330 | } | |
1331 | } | |
1332 | ||
1333 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1334 | { | |
1335 | struct ras_ih_data *data = | |
1336 | container_of(work, struct ras_ih_data, ih_work); | |
1337 | struct ras_manager *obj = | |
1338 | container_of(data, struct ras_manager, ih_data); | |
1339 | ||
1340 | amdgpu_ras_interrupt_handler(obj); | |
1341 | } | |
1342 | ||
1343 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1344 | struct ras_dispatch_if *info) | |
1345 | { | |
1346 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1347 | struct ras_ih_data *data = &obj->ih_data; | |
1348 | ||
1349 | if (!obj) | |
1350 | return -EINVAL; | |
1351 | ||
1352 | if (data->inuse == 0) | |
1353 | return 0; | |
1354 | ||
1355 | /* Might be overflow... */ | |
1356 | memcpy(&data->ring[data->wptr], info->entry, | |
1357 | data->element_size); | |
1358 | ||
1359 | wmb(); | |
1360 | data->wptr = (data->aligned_element_size + | |
1361 | data->wptr) % data->ring_size; | |
1362 | ||
1363 | schedule_work(&data->ih_work); | |
1364 | ||
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1369 | struct ras_ih_if *info) | |
1370 | { | |
1371 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1372 | struct ras_ih_data *data; | |
1373 | ||
1374 | if (!obj) | |
1375 | return -EINVAL; | |
1376 | ||
1377 | data = &obj->ih_data; | |
1378 | if (data->inuse == 0) | |
1379 | return 0; | |
1380 | ||
1381 | cancel_work_sync(&data->ih_work); | |
1382 | ||
1383 | kfree(data->ring); | |
1384 | memset(data, 0, sizeof(*data)); | |
1385 | put_obj(obj); | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1391 | struct ras_ih_if *info) | |
1392 | { | |
1393 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1394 | struct ras_ih_data *data; | |
1395 | ||
1396 | if (!obj) { | |
1397 | /* in case we registe the IH before enable ras feature */ | |
1398 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1399 | if (!obj) | |
1400 | return -EINVAL; | |
1401 | } else | |
1402 | get_obj(obj); | |
1403 | ||
1404 | data = &obj->ih_data; | |
1405 | /* add the callback.etc */ | |
1406 | *data = (struct ras_ih_data) { | |
1407 | .inuse = 0, | |
1408 | .cb = info->cb, | |
1409 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1410 | .rptr = 0, | |
1411 | .wptr = 0, | |
1412 | }; | |
1413 | ||
1414 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1415 | ||
1416 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1417 | /* the ring can store 64 iv entries. */ | |
1418 | data->ring_size = 64 * data->aligned_element_size; | |
1419 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1420 | if (!data->ring) { | |
1421 | put_obj(obj); | |
1422 | return -ENOMEM; | |
1423 | } | |
1424 | ||
1425 | /* IH is ready */ | |
1426 | data->inuse = 1; | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1432 | { | |
1433 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1434 | struct ras_manager *obj, *tmp; | |
1435 | ||
1436 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1437 | struct ras_ih_if info = { | |
1438 | .head = obj->head, | |
1439 | }; | |
1440 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1441 | } | |
1442 | ||
1443 | return 0; | |
1444 | } | |
1445 | /* ih end */ | |
1446 | ||
313c8fd3 GC |
1447 | /* traversal all IPs except NBIO to query error counter */ |
1448 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1449 | { | |
1450 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1451 | struct ras_manager *obj; | |
1452 | ||
1453 | if (!con) | |
1454 | return; | |
1455 | ||
1456 | list_for_each_entry(obj, &con->head, node) { | |
1457 | struct ras_query_if info = { | |
1458 | .head = obj->head, | |
1459 | }; | |
1460 | ||
1461 | /* | |
1462 | * PCIE_BIF IP has one different isr by ras controller | |
1463 | * interrupt, the specific ras counter query will be | |
1464 | * done in that isr. So skip such block from common | |
1465 | * sync flood interrupt isr calling. | |
1466 | */ | |
1467 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1468 | continue; | |
1469 | ||
1470 | amdgpu_ras_error_query(adev, &info); | |
1471 | } | |
1472 | } | |
1473 | ||
3f975d0f SY |
1474 | /* Parse RdRspStatus and WrRspStatus */ |
1475 | void amdgpu_ras_error_status_query(struct amdgpu_device *adev, | |
1476 | struct ras_query_if *info) | |
1477 | { | |
1478 | /* | |
1479 | * Only two block need to query read/write | |
1480 | * RspStatus at current state | |
1481 | */ | |
1482 | switch (info->head.block) { | |
1483 | case AMDGPU_RAS_BLOCK__GFX: | |
1484 | if (adev->gfx.funcs->query_ras_error_status) | |
1485 | adev->gfx.funcs->query_ras_error_status(adev); | |
1486 | break; | |
1487 | case AMDGPU_RAS_BLOCK__MMHUB: | |
1488 | if (adev->mmhub.funcs->query_ras_error_status) | |
1489 | adev->mmhub.funcs->query_ras_error_status(adev); | |
1490 | break; | |
1491 | default: | |
1492 | break; | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1497 | { | |
1498 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1499 | struct ras_manager *obj; | |
1500 | ||
1501 | if (!con) | |
1502 | return; | |
1503 | ||
1504 | list_for_each_entry(obj, &con->head, node) { | |
1505 | struct ras_query_if info = { | |
1506 | .head = obj->head, | |
1507 | }; | |
1508 | ||
1509 | amdgpu_ras_error_status_query(adev, &info); | |
1510 | } | |
1511 | } | |
1512 | ||
c030f2e4 | 1513 | /* recovery begin */ |
466b1793 | 1514 | |
1515 | /* return 0 on success. | |
1516 | * caller need free bps. | |
1517 | */ | |
1518 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1519 | struct ras_badpage **bps, unsigned int *count) | |
1520 | { | |
1521 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1522 | struct ras_err_handler_data *data; | |
1523 | int i = 0; | |
1524 | int ret = 0; | |
1525 | ||
1526 | if (!con || !con->eh_data || !bps || !count) | |
1527 | return -EINVAL; | |
1528 | ||
1529 | mutex_lock(&con->recovery_lock); | |
1530 | data = con->eh_data; | |
1531 | if (!data || data->count == 0) { | |
1532 | *bps = NULL; | |
46cf2fec | 1533 | ret = -EINVAL; |
466b1793 | 1534 | goto out; |
1535 | } | |
1536 | ||
1537 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1538 | if (!*bps) { | |
1539 | ret = -ENOMEM; | |
1540 | goto out; | |
1541 | } | |
1542 | ||
1543 | for (; i < data->count; i++) { | |
1544 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1545 | .bp = data->bps[i].retired_page, |
466b1793 | 1546 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1547 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1548 | }; |
676deb38 DL |
1549 | ret = amdgpu_vram_mgr_query_page_status( |
1550 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1551 | data->bps[i].retired_page); | |
1552 | if (ret == -EBUSY) | |
52dd95f2 | 1553 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
676deb38 | 1554 | else if (ret == -ENOENT) |
52dd95f2 | 1555 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1556 | } |
1557 | ||
1558 | *count = data->count; | |
1559 | out: | |
1560 | mutex_unlock(&con->recovery_lock); | |
1561 | return ret; | |
1562 | } | |
1563 | ||
c030f2e4 | 1564 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1565 | { | |
1566 | struct amdgpu_ras *ras = | |
1567 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1568 | struct amdgpu_device *remote_adev = NULL; |
1569 | struct amdgpu_device *adev = ras->adev; | |
1570 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 1571 | |
f75e94d8 | 1572 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
1573 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
1574 | ||
f75e94d8 GC |
1575 | /* Build list of devices to query RAS related errors */ |
1576 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1577 | device_list_handle = &hive->device_list; | |
1578 | } else { | |
1579 | INIT_LIST_HEAD(&device_list); | |
1580 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1581 | device_list_handle = &device_list; | |
1582 | } | |
c030f2e4 | 1583 | |
f75e94d8 | 1584 | list_for_each_entry(remote_adev, |
3f975d0f SY |
1585 | device_list_handle, gmc.xgmi.head) { |
1586 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 1587 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 1588 | } |
d95e8e97 DL |
1589 | |
1590 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 1591 | } |
313c8fd3 | 1592 | |
93af20f7 | 1593 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1594 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1595 | atomic_set(&ras->in_recovery, 0); |
1596 | } | |
1597 | ||
c030f2e4 | 1598 | /* alloc/realloc bps array */ |
1599 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1600 | struct ras_err_handler_data *data, int pages) | |
1601 | { | |
1602 | unsigned int old_space = data->count + data->space_left; | |
1603 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1604 | unsigned int align_space = ALIGN(new_space, 512); |
1605 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 1606 | |
676deb38 | 1607 | if (!bps) { |
9dc23a63 | 1608 | kfree(bps); |
c030f2e4 | 1609 | return -ENOMEM; |
9dc23a63 | 1610 | } |
c030f2e4 | 1611 | |
1612 | if (data->bps) { | |
9dc23a63 | 1613 | memcpy(bps, data->bps, |
c030f2e4 | 1614 | data->count * sizeof(*data->bps)); |
1615 | kfree(data->bps); | |
1616 | } | |
1617 | ||
9dc23a63 | 1618 | data->bps = bps; |
c030f2e4 | 1619 | data->space_left += align_space - old_space; |
1620 | return 0; | |
1621 | } | |
1622 | ||
1623 | /* it deal with vram only. */ | |
1624 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1625 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1626 | { |
1627 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1628 | struct ras_err_handler_data *data; |
c030f2e4 | 1629 | int ret = 0; |
676deb38 | 1630 | uint32_t i; |
c030f2e4 | 1631 | |
73aa8e1a | 1632 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1633 | return 0; |
1634 | ||
1635 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1636 | data = con->eh_data; |
c030f2e4 | 1637 | if (!data) |
1638 | goto out; | |
1639 | ||
676deb38 DL |
1640 | for (i = 0; i < pages; i++) { |
1641 | if (amdgpu_ras_check_bad_page_unlock(con, | |
1642 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
1643 | continue; | |
1644 | ||
1645 | if (!data->space_left && | |
1646 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 1647 | ret = -ENOMEM; |
1648 | goto out; | |
1649 | } | |
1650 | ||
676deb38 DL |
1651 | amdgpu_vram_mgr_reserve_range( |
1652 | ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), | |
1653 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, | |
1654 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 1655 | |
676deb38 DL |
1656 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
1657 | data->count++; | |
1658 | data->space_left--; | |
1659 | } | |
c030f2e4 | 1660 | out: |
1661 | mutex_unlock(&con->recovery_lock); | |
1662 | ||
1663 | return ret; | |
1664 | } | |
1665 | ||
78ad00c9 TZ |
1666 | /* |
1667 | * write error record array to eeprom, the function should be | |
1668 | * protected by recovery_lock | |
1669 | */ | |
22503d80 | 1670 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) |
78ad00c9 TZ |
1671 | { |
1672 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1673 | struct ras_err_handler_data *data; | |
8a3e801f | 1674 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1675 | int save_count; |
1676 | ||
1677 | if (!con || !con->eh_data) | |
1678 | return 0; | |
1679 | ||
8a3e801f | 1680 | control = &con->eeprom_control; |
78ad00c9 TZ |
1681 | data = con->eh_data; |
1682 | save_count = data->count - control->num_recs; | |
1683 | /* only new entries are saved */ | |
b1628425 | 1684 | if (save_count > 0) { |
0771b0bf | 1685 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1686 | &data->bps[control->num_recs], |
1687 | true, | |
1688 | save_count)) { | |
6952e99c | 1689 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1690 | return -EIO; |
1691 | } | |
1692 | ||
b1628425 GC |
1693 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1694 | } | |
1695 | ||
78ad00c9 TZ |
1696 | return 0; |
1697 | } | |
1698 | ||
1699 | /* | |
1700 | * read error record array in eeprom and reserve enough space for | |
1701 | * storing new bad pages | |
1702 | */ | |
1703 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1704 | { | |
1705 | struct amdgpu_ras_eeprom_control *control = | |
1706 | &adev->psp.ras.ras->eeprom_control; | |
1707 | struct eeprom_table_record *bps = NULL; | |
1708 | int ret = 0; | |
1709 | ||
1710 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1711 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1712 | return ret; |
1713 | ||
1714 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1715 | if (!bps) | |
1716 | return -ENOMEM; | |
1717 | ||
1718 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1719 | control->num_recs)) { | |
6952e99c | 1720 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1721 | ret = -EIO; |
1722 | goto out; | |
1723 | } | |
1724 | ||
1725 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1726 | ||
1727 | out: | |
1728 | kfree(bps); | |
1729 | return ret; | |
1730 | } | |
1731 | ||
676deb38 DL |
1732 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
1733 | uint64_t addr) | |
1734 | { | |
1735 | struct ras_err_handler_data *data = con->eh_data; | |
1736 | int i; | |
1737 | ||
1738 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1739 | for (i = 0; i < data->count; i++) | |
1740 | if (addr == data->bps[i].retired_page) | |
1741 | return true; | |
1742 | ||
1743 | return false; | |
1744 | } | |
1745 | ||
6e4be987 TZ |
1746 | /* |
1747 | * check if an address belongs to bad page | |
1748 | * | |
1749 | * Note: this check is only for umc block | |
1750 | */ | |
1751 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1752 | uint64_t addr) | |
1753 | { | |
1754 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
1755 | bool ret = false; |
1756 | ||
1757 | if (!con || !con->eh_data) | |
1758 | return ret; | |
1759 | ||
1760 | mutex_lock(&con->recovery_lock); | |
676deb38 | 1761 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
1762 | mutex_unlock(&con->recovery_lock); |
1763 | return ret; | |
1764 | } | |
1765 | ||
c84d4670 GC |
1766 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1767 | uint32_t max_length) | |
1768 | { | |
1769 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1770 | int tmp_threshold = amdgpu_bad_page_threshold; | |
1771 | u64 val; | |
1772 | ||
1773 | /* | |
1774 | * Justification of value bad_page_cnt_threshold in ras structure | |
1775 | * | |
1776 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1777 | * in eeprom, and introduce two scenarios accordingly. | |
1778 | * | |
1779 | * Bad page retirement enablement: | |
1780 | * - If amdgpu_bad_page_threshold = -1, | |
1781 | * bad_page_cnt_threshold = typical value by formula. | |
1782 | * | |
1783 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1784 | * max record length in eeprom, use it directly. | |
1785 | * | |
1786 | * Bad page retirement disablement: | |
1787 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1788 | * functionality is disabled, and bad_page_cnt_threshold will | |
1789 | * take no effect. | |
1790 | */ | |
1791 | ||
1792 | if (tmp_threshold < -1) | |
1793 | tmp_threshold = -1; | |
1794 | else if (tmp_threshold > max_length) | |
1795 | tmp_threshold = max_length; | |
1796 | ||
1797 | if (tmp_threshold == -1) { | |
1798 | val = adev->gmc.mc_vram_size; | |
1799 | do_div(val, RAS_BAD_PAGE_RATE); | |
1800 | con->bad_page_cnt_threshold = min(lower_32_bits(val), | |
1801 | max_length); | |
1802 | } else { | |
1803 | con->bad_page_cnt_threshold = tmp_threshold; | |
1804 | } | |
1805 | } | |
1806 | ||
1a6fc071 | 1807 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1808 | { |
1809 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1810 | struct ras_err_handler_data **data; |
c84d4670 | 1811 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1812 | bool exc_err_limit = false; |
78ad00c9 | 1813 | int ret; |
c030f2e4 | 1814 | |
4d1337d2 AG |
1815 | if (con) |
1816 | data = &con->eh_data; | |
1817 | else | |
1818 | return 0; | |
1819 | ||
1a6fc071 TZ |
1820 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1821 | if (!*data) { | |
1822 | ret = -ENOMEM; | |
1823 | goto out; | |
1824 | } | |
c030f2e4 | 1825 | |
1826 | mutex_init(&con->recovery_lock); | |
1827 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1828 | atomic_set(&con->in_recovery, 0); | |
1829 | con->adev = adev; | |
1830 | ||
c84d4670 GC |
1831 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1832 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
1833 | ||
b82e65a9 GC |
1834 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1835 | /* | |
1836 | * This calling fails when exc_err_limit is true or | |
1837 | * ret != 0. | |
1838 | */ | |
1839 | if (exc_err_limit || ret) | |
1a6fc071 | 1840 | goto free; |
78ad00c9 | 1841 | |
0771b0bf | 1842 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1843 | ret = amdgpu_ras_load_bad_pages(adev); |
1844 | if (ret) | |
1a6fc071 | 1845 | goto free; |
78ad00c9 | 1846 | } |
c030f2e4 | 1847 | |
1848 | return 0; | |
1a6fc071 | 1849 | |
1a6fc071 | 1850 | free: |
1a6fc071 | 1851 | kfree((*data)->bps); |
1a6fc071 | 1852 | kfree(*data); |
1995b3a3 | 1853 | con->eh_data = NULL; |
1a6fc071 | 1854 | out: |
6952e99c | 1855 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1856 | |
b82e65a9 GC |
1857 | /* |
1858 | * Except error threshold exceeding case, other failure cases in this | |
1859 | * function would not fail amdgpu driver init. | |
1860 | */ | |
1861 | if (!exc_err_limit) | |
1862 | ret = 0; | |
1863 | else | |
1864 | ret = -EINVAL; | |
1865 | ||
1a6fc071 | 1866 | return ret; |
c030f2e4 | 1867 | } |
1868 | ||
1869 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1870 | { | |
1871 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1872 | struct ras_err_handler_data *data = con->eh_data; | |
1873 | ||
1a6fc071 TZ |
1874 | /* recovery_init failed to init it, fini is useless */ |
1875 | if (!data) | |
1876 | return 0; | |
1877 | ||
c030f2e4 | 1878 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1879 | |
1880 | mutex_lock(&con->recovery_lock); | |
1881 | con->eh_data = NULL; | |
1882 | kfree(data->bps); | |
1883 | kfree(data); | |
1884 | mutex_unlock(&con->recovery_lock); | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | /* recovery end */ | |
1889 | ||
a564808e | 1890 | /* return 0 if ras will reset gpu and repost.*/ |
1891 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1892 | unsigned int block) | |
1893 | { | |
1894 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1895 | ||
1896 | if (!ras) | |
1897 | return -EINVAL; | |
1898 | ||
1899 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1900 | return 0; | |
1901 | } | |
1902 | ||
5436ab94 SY |
1903 | static int amdgpu_ras_check_asic_type(struct amdgpu_device *adev) |
1904 | { | |
1905 | if (adev->asic_type != CHIP_VEGA10 && | |
1906 | adev->asic_type != CHIP_VEGA20 && | |
4d2aae33 JC |
1907 | adev->asic_type != CHIP_ARCTURUS && |
1908 | adev->asic_type != CHIP_SIENNA_CICHLID) | |
5436ab94 SY |
1909 | return 1; |
1910 | else | |
1911 | return 0; | |
1912 | } | |
1913 | ||
5caf466a | 1914 | /* |
1915 | * check hardware's ras ability which will be saved in hw_supported. | |
1916 | * if hardware does not support ras, we can skip some ras initializtion and | |
1917 | * forbid some ras operations from IP. | |
1918 | * if software itself, say boot parameter, limit the ras ability. We still | |
1919 | * need allow IP do some limited operations, like disable. In such case, | |
1920 | * we have to initialize ras as normal. but need check if operation is | |
1921 | * allowed or not in each function. | |
1922 | */ | |
1923 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1924 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1925 | { |
5caf466a | 1926 | *hw_supported = 0; |
1927 | *supported = 0; | |
c030f2e4 | 1928 | |
88474cca | 1929 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
5436ab94 | 1930 | amdgpu_ras_check_asic_type(adev)) |
5caf466a | 1931 | return; |
b404ae82 | 1932 | |
88474cca | 1933 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
6952e99c | 1934 | dev_info(adev->dev, "HBM ECC is active.\n"); |
88474cca GC |
1935 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | |
1936 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1937 | } else | |
6952e99c | 1938 | dev_info(adev->dev, "HBM ECC is not presented.\n"); |
88474cca GC |
1939 | |
1940 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
6952e99c | 1941 | dev_info(adev->dev, "SRAM ECC is active.\n"); |
88474cca GC |
1942 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
1943 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1944 | } else | |
6952e99c | 1945 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); |
88474cca GC |
1946 | |
1947 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1948 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1949 | |
5caf466a | 1950 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1951 | 0 : *hw_supported & amdgpu_ras_mask; |
5436ab94 | 1952 | adev->ras_features = *supported; |
c030f2e4 | 1953 | } |
1954 | ||
1955 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1956 | { | |
1957 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1958 | int r; |
c030f2e4 | 1959 | |
b404ae82 | 1960 | if (con) |
c030f2e4 | 1961 | return 0; |
1962 | ||
1963 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1964 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1965 | GFP_KERNEL|__GFP_ZERO); | |
1966 | if (!con) | |
1967 | return -ENOMEM; | |
1968 | ||
1969 | con->objs = (struct ras_manager *)(con + 1); | |
1970 | ||
1971 | amdgpu_ras_set_context(adev, con); | |
1972 | ||
5caf466a | 1973 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1974 | &con->supported); | |
5436ab94 | 1975 | if (!con->hw_supported || (adev->asic_type == CHIP_VEGA10)) { |
5e91160a | 1976 | r = 0; |
5436ab94 | 1977 | goto release_con; |
fb2a3607 HZ |
1978 | } |
1979 | ||
c030f2e4 | 1980 | con->features = 0; |
1981 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1982 | /* Might need get this flag from vbios. */ |
1983 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1984 | |
4e644fff HZ |
1985 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1986 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1987 | if (r) | |
5436ab94 | 1988 | goto release_con; |
4e644fff HZ |
1989 | } |
1990 | ||
1991 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1992 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
1993 | if (r) | |
5436ab94 | 1994 | goto release_con; |
4e644fff HZ |
1995 | } |
1996 | ||
5e91160a GC |
1997 | if (amdgpu_ras_fs_init(adev)) { |
1998 | r = -EINVAL; | |
5436ab94 | 1999 | goto release_con; |
5e91160a | 2000 | } |
c030f2e4 | 2001 | |
6952e99c | 2002 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 2003 | "hardware ability[%x] ras_mask[%x]\n", |
2004 | con->hw_supported, con->supported); | |
c030f2e4 | 2005 | return 0; |
5436ab94 | 2006 | release_con: |
c030f2e4 | 2007 | amdgpu_ras_set_context(adev, NULL); |
2008 | kfree(con); | |
2009 | ||
5e91160a | 2010 | return r; |
c030f2e4 | 2011 | } |
2012 | ||
b293e891 HZ |
2013 | /* helper function to handle common stuff in ip late init phase */ |
2014 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2015 | struct ras_common_if *ras_block, | |
2016 | struct ras_fs_if *fs_info, | |
2017 | struct ras_ih_if *ih_info) | |
2018 | { | |
2019 | int r; | |
2020 | ||
2021 | /* disable RAS feature per IP block if it is not supported */ | |
2022 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2023 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2024 | return 0; | |
2025 | } | |
2026 | ||
2027 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2028 | if (r) { | |
2029 | if (r == -EAGAIN) { | |
2030 | /* request gpu reset. will run again */ | |
2031 | amdgpu_ras_request_reset_on_boot(adev, | |
2032 | ras_block->block); | |
2033 | return 0; | |
53b3f8f4 | 2034 | } else if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2035 | /* in resume phase, if fail to enable ras, |
2036 | * clean up all ras fs nodes, and disable ras */ | |
2037 | goto cleanup; | |
2038 | } else | |
2039 | return r; | |
2040 | } | |
2041 | ||
2042 | /* in resume phase, no need to create ras fs node */ | |
53b3f8f4 | 2043 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2044 | return 0; |
2045 | ||
2046 | if (ih_info->cb) { | |
2047 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2048 | if (r) | |
2049 | goto interrupt; | |
2050 | } | |
2051 | ||
b293e891 HZ |
2052 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2053 | if (r) | |
2054 | goto sysfs; | |
2055 | ||
2056 | return 0; | |
2057 | cleanup: | |
2058 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2059 | sysfs: | |
b293e891 HZ |
2060 | if (ih_info->cb) |
2061 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2062 | interrupt: | |
2063 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2064 | return r; | |
2065 | } | |
2066 | ||
2067 | /* helper function to remove ras fs node and interrupt handler */ | |
2068 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2069 | struct ras_common_if *ras_block, | |
2070 | struct ras_ih_if *ih_info) | |
2071 | { | |
2072 | if (!ras_block || !ih_info) | |
2073 | return; | |
2074 | ||
2075 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 | 2076 | if (ih_info->cb) |
f3729f7b | 2077 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); |
b293e891 HZ |
2078 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2079 | } | |
2080 | ||
a564808e | 2081 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2082 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2083 | */ |
511fdbc3 | 2084 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2085 | { |
2086 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2087 | struct ras_manager *obj, *tmp; | |
2088 | ||
2089 | if (!con) | |
2090 | return; | |
2091 | ||
108c6a63 | 2092 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2093 | /* Set up all other IPs which are not implemented. There is a |
2094 | * tricky thing that IP's actual ras error type should be | |
2095 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2096 | * ERROR_NONE make sense anyway. | |
2097 | */ | |
2098 | amdgpu_ras_enable_all_features(adev, 1); | |
2099 | ||
2100 | /* We enable ras on all hw_supported block, but as boot | |
2101 | * parameter might disable some of them and one or more IP has | |
2102 | * not implemented yet. So we disable them on behalf. | |
2103 | */ | |
108c6a63 | 2104 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2105 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2106 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2107 | /* there should be no any reference. */ | |
2108 | WARN_ON(alive_obj(obj)); | |
2109 | } | |
191051a1 | 2110 | } |
108c6a63 | 2111 | } |
a564808e | 2112 | |
2113 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2114 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2115 | /* setup ras obj state as disabled. | |
2116 | * for init_by_vbios case. | |
2117 | * if we want to enable ras, just enable it in a normal way. | |
2118 | * If we want do disable it, need setup ras obj as enabled, | |
2119 | * then issue another TA disable cmd. | |
2120 | * See feature_enable_on_boot | |
2121 | */ | |
2122 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2123 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2124 | } |
108c6a63 | 2125 | } |
2126 | ||
511fdbc3 | 2127 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2128 | { | |
2129 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2130 | ||
2131 | if (!con) | |
2132 | return; | |
2133 | ||
2134 | amdgpu_ras_disable_all_features(adev, 0); | |
2135 | /* Make sure all ras objects are disabled. */ | |
2136 | if (con->features) | |
2137 | amdgpu_ras_disable_all_features(adev, 1); | |
2138 | } | |
2139 | ||
c030f2e4 | 2140 | /* do some fini work before IP fini as dependence */ |
2141 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2142 | { | |
2143 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2144 | ||
2145 | if (!con) | |
2146 | return 0; | |
2147 | ||
2148 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2149 | amdgpu_ras_disable_all_features(adev, 0); | |
2150 | amdgpu_ras_recovery_fini(adev); | |
2151 | return 0; | |
2152 | } | |
2153 | ||
2154 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2155 | { | |
2156 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2157 | ||
2158 | if (!con) | |
2159 | return 0; | |
2160 | ||
2161 | amdgpu_ras_fs_fini(adev); | |
2162 | amdgpu_ras_interrupt_remove_all(adev); | |
2163 | ||
2164 | WARN(con->features, "Feature mask is not cleared"); | |
2165 | ||
2166 | if (con->features) | |
2167 | amdgpu_ras_disable_all_features(adev, 1); | |
2168 | ||
2169 | amdgpu_ras_set_context(adev, NULL); | |
2170 | kfree(con); | |
2171 | ||
2172 | return 0; | |
2173 | } | |
7c6e68c7 AG |
2174 | |
2175 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2176 | { | |
ed606f8a AG |
2177 | uint32_t hw_supported, supported; |
2178 | ||
2179 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2180 | if (!hw_supported) | |
2181 | return; | |
2182 | ||
7c6e68c7 | 2183 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2184 | dev_info(adev->dev, "uncorrectable hardware error" |
2185 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2186 | |
61934624 | 2187 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2188 | } |
2189 | } | |
bb5c7235 WS |
2190 | |
2191 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2192 | { | |
2193 | if (adev->asic_type == CHIP_VEGA20 && | |
2194 | adev->pm.fw_version <= 0x283400) { | |
2195 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2196 | amdgpu_ras_intr_triggered(); | |
2197 | } | |
2198 | ||
2199 | return false; | |
2200 | } | |
e8fbaf03 GC |
2201 | |
2202 | bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev) | |
2203 | { | |
2204 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2205 | bool exc_err_limit = false; | |
2206 | ||
2207 | if (con && (amdgpu_bad_page_threshold != 0)) | |
2208 | amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control, | |
2209 | &exc_err_limit); | |
2210 | ||
2211 | /* | |
2212 | * We are only interested in variable exc_err_limit, | |
2213 | * as it says if GPU is in bad state or not. | |
2214 | */ | |
2215 | return exc_err_limit; | |
2216 | } |