Commit | Line | Data |
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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
eb0c3cd4 GC |
37 | static const char *RAS_FS_NAME = "ras"; |
38 | ||
c030f2e4 | 39 | const char *ras_error_string[] = { |
40 | "none", | |
41 | "parity", | |
42 | "single_correctable", | |
43 | "multi_uncorrectable", | |
44 | "poison", | |
45 | }; | |
46 | ||
47 | const char *ras_block_string[] = { | |
48 | "umc", | |
49 | "sdma", | |
50 | "gfx", | |
51 | "mmhub", | |
52 | "athub", | |
53 | "pcie_bif", | |
54 | "hdp", | |
55 | "xgmi_wafl", | |
56 | "df", | |
57 | "smn", | |
58 | "sem", | |
59 | "mp0", | |
60 | "mp1", | |
61 | "fuse", | |
62 | }; | |
63 | ||
64 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
65 | #define ras_block_str(i) (ras_block_string[i]) | |
66 | ||
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
c84d4670 GC |
72 | /* typical ECC bad page rate(1 bad page per 100MB VRAM) */ |
73 | #define RAS_BAD_PAGE_RATE (100 * 1024 * 1024ULL) | |
74 | ||
52dd95f2 GC |
75 | enum amdgpu_ras_retire_page_reservation { |
76 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
77 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
78 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
79 | }; | |
7c6e68c7 AG |
80 | |
81 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
82 | ||
6e4be987 TZ |
83 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
84 | uint64_t addr); | |
85 | ||
61380faa JC |
86 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
87 | { | |
a9d82d2f | 88 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
89 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
90 | } | |
91 | ||
f3167919 | 92 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 93 | { |
a9d82d2f | 94 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
95 | return amdgpu_ras_get_context(adev)->error_query_ready; |
96 | ||
97 | return false; | |
98 | } | |
99 | ||
c030f2e4 | 100 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
101 | size_t size, loff_t *pos) | |
102 | { | |
103 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
104 | struct ras_query_if info = { | |
105 | .head = obj->head, | |
106 | }; | |
107 | ssize_t s; | |
108 | char val[128]; | |
109 | ||
110 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
111 | return -EINVAL; | |
112 | ||
113 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
114 | "ue", info.ue_count, | |
115 | "ce", info.ce_count); | |
116 | if (*pos >= s) | |
117 | return 0; | |
118 | ||
119 | s -= *pos; | |
120 | s = min_t(u64, s, size); | |
121 | ||
122 | ||
123 | if (copy_to_user(buf, &val[*pos], s)) | |
124 | return -EINVAL; | |
125 | ||
126 | *pos += s; | |
127 | ||
128 | return s; | |
129 | } | |
130 | ||
c030f2e4 | 131 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
132 | .owner = THIS_MODULE, | |
133 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 134 | .write = NULL, |
c030f2e4 | 135 | .llseek = default_llseek |
136 | }; | |
137 | ||
96ebb307 | 138 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
139 | { | |
140 | int i; | |
141 | ||
142 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
143 | *block_id = i; | |
144 | if (strcmp(name, ras_block_str(i)) == 0) | |
145 | return 0; | |
146 | } | |
147 | return -EINVAL; | |
148 | } | |
149 | ||
150 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
151 | const char __user *buf, size_t size, | |
152 | loff_t *pos, struct ras_debug_if *data) | |
153 | { | |
154 | ssize_t s = min_t(u64, 64, size); | |
155 | char str[65]; | |
156 | char block_name[33]; | |
157 | char err[9] = "ue"; | |
158 | int op = -1; | |
159 | int block_id; | |
44494f96 | 160 | uint32_t sub_block; |
96ebb307 | 161 | u64 address, value; |
162 | ||
163 | if (*pos) | |
164 | return -EINVAL; | |
165 | *pos = size; | |
166 | ||
167 | memset(str, 0, sizeof(str)); | |
168 | memset(data, 0, sizeof(*data)); | |
169 | ||
170 | if (copy_from_user(str, buf, s)) | |
171 | return -EINVAL; | |
172 | ||
173 | if (sscanf(str, "disable %32s", block_name) == 1) | |
174 | op = 0; | |
175 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
176 | op = 1; | |
177 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
178 | op = 2; | |
b076296b | 179 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 180 | /* ascii string, but commands are not matched. */ |
181 | return -EINVAL; | |
182 | ||
183 | if (op != -1) { | |
184 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
185 | return -EINVAL; | |
186 | ||
187 | data->head.block = block_id; | |
e1063493 TZ |
188 | /* only ue and ce errors are supported */ |
189 | if (!memcmp("ue", err, 2)) | |
190 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
191 | else if (!memcmp("ce", err, 2)) | |
192 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
193 | else | |
194 | return -EINVAL; | |
195 | ||
96ebb307 | 196 | data->op = op; |
197 | ||
198 | if (op == 2) { | |
44494f96 TZ |
199 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
200 | &sub_block, &address, &value) != 3) | |
201 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
202 | &sub_block, &address, &value) != 3) | |
96ebb307 | 203 | return -EINVAL; |
44494f96 | 204 | data->head.sub_block_index = sub_block; |
96ebb307 | 205 | data->inject.address = address; |
206 | data->inject.value = value; | |
207 | } | |
208 | } else { | |
73aa8e1a | 209 | if (size < sizeof(*data)) |
96ebb307 | 210 | return -EINVAL; |
211 | ||
212 | if (copy_from_user(data, buf, sizeof(*data))) | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | return 0; | |
217 | } | |
7c6e68c7 | 218 | |
74abc221 TSD |
219 | /** |
220 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 221 | * |
222 | * It accepts struct ras_debug_if who has two members. | |
223 | * | |
224 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 225 | * |
226 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 227 | * |
228 | * head has four members, they are block, type, sub_block_index, name. | |
229 | * block: which IP will be under control. | |
230 | * type: what kind of error will be enabled/disabled/injected. | |
231 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
232 | * name: the name of IP. | |
233 | * | |
234 | * inject has two more members than head, they are address, value. | |
235 | * As their names indicate, inject operation will write the | |
236 | * value to the address. | |
237 | * | |
ef177d11 | 238 | * The second member: struct ras_debug_if::op. |
c688a06b | 239 | * It has three kinds of operations. |
879e723d AZ |
240 | * |
241 | * - 0: disable RAS on the block. Take ::head as its data. | |
242 | * - 1: enable RAS on the block. Take ::head as its data. | |
243 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 244 | * |
96ebb307 | 245 | * How to use the interface? |
ef177d11 AD |
246 | * |
247 | * Programs | |
248 | * | |
249 | * Copy the struct ras_debug_if in your codes and initialize it. | |
250 | * Write the struct to the control node. | |
251 | * | |
252 | * Shells | |
96ebb307 | 253 | * |
879e723d AZ |
254 | * .. code-block:: bash |
255 | * | |
a20bfd0f | 256 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 257 | * |
ef177d11 AD |
258 | * Parameters: |
259 | * | |
879e723d AZ |
260 | * op: disable, enable, inject |
261 | * disable: only block is needed | |
262 | * enable: block and error are needed | |
263 | * inject: error, address, value are needed | |
a20bfd0f | 264 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
265 | * see ras_block_string[] for details |
266 | * error: ue, ce | |
267 | * ue: multi_uncorrectable | |
268 | * ce: single_correctable | |
269 | * sub_block: | |
270 | * sub block index, pass 0 if there is no sub block | |
271 | * | |
272 | * here are some examples for bash commands: | |
273 | * | |
274 | * .. code-block:: bash | |
96ebb307 | 275 | * |
44494f96 TZ |
276 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
277 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 278 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
279 | * | |
36ea1bd2 | 280 | * How to check the result? |
281 | * | |
282 | * For disable/enable, please check ras features at | |
283 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
284 | * | |
285 | * For inject, please check corresponding err count at | |
286 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
287 | * | |
879e723d | 288 | * .. note:: |
ef177d11 | 289 | * Operations are only allowed on blocks which are supported. |
879e723d | 290 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
291 | * to see which blocks support RAS on a particular asic. |
292 | * | |
36ea1bd2 | 293 | */ |
294 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
295 | size_t size, loff_t *pos) | |
296 | { | |
297 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
298 | struct ras_debug_if data; | |
299 | int ret = 0; | |
300 | ||
61380faa | 301 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
302 | dev_warn(adev->dev, "RAS WARN: error injection " |
303 | "currently inaccessible\n"); | |
43c4d576 JC |
304 | return size; |
305 | } | |
306 | ||
96ebb307 | 307 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
308 | if (ret) | |
36ea1bd2 | 309 | return -EINVAL; |
310 | ||
36ea1bd2 | 311 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
312 | return -EINVAL; | |
313 | ||
314 | switch (data.op) { | |
315 | case 0: | |
316 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
317 | break; | |
318 | case 1: | |
319 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
320 | break; | |
321 | case 2: | |
7cdc2ee3 TZ |
322 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
323 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
b0d4783a GC |
324 | dev_warn(adev->dev, "RAS WARN: input address " |
325 | "0x%llx is invalid.", | |
326 | data.inject.address); | |
7cdc2ee3 TZ |
327 | ret = -EINVAL; |
328 | break; | |
329 | } | |
330 | ||
6e4be987 TZ |
331 | /* umc ce/ue error injection for a bad page is not allowed */ |
332 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
333 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
6952e99c GC |
334 | dev_warn(adev->dev, "RAS WARN: 0x%llx has been marked " |
335 | "as bad before error injection!\n", | |
6e4be987 TZ |
336 | data.inject.address); |
337 | break; | |
338 | } | |
339 | ||
7cdc2ee3 | 340 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 341 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
342 | break; | |
96ebb307 | 343 | default: |
344 | ret = -EINVAL; | |
345 | break; | |
374bf7bd | 346 | } |
36ea1bd2 | 347 | |
348 | if (ret) | |
349 | return -EINVAL; | |
350 | ||
351 | return size; | |
352 | } | |
353 | ||
084fe13b AG |
354 | /** |
355 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
356 | * | |
f77c7109 | 357 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 358 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
359 | * a way to reset the EEPROM, e.g., after testing error injection. |
360 | * | |
361 | * Usage: | |
362 | * | |
363 | * .. code-block:: bash | |
364 | * | |
365 | * echo 1 > ../ras/ras_eeprom_reset | |
366 | * | |
367 | * will reset EEPROM table to 0 entries. | |
368 | * | |
084fe13b AG |
369 | */ |
370 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
371 | size_t size, loff_t *pos) | |
372 | { | |
bf0b91b7 GC |
373 | struct amdgpu_device *adev = |
374 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
375 | int ret; |
376 | ||
bf0b91b7 GC |
377 | ret = amdgpu_ras_eeprom_reset_table( |
378 | &(amdgpu_ras_get_context(adev)->eeprom_control)); | |
084fe13b | 379 | |
bf0b91b7 GC |
380 | if (ret == 1) { |
381 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; | |
382 | return size; | |
383 | } else { | |
384 | return -EIO; | |
385 | } | |
084fe13b AG |
386 | } |
387 | ||
36ea1bd2 | 388 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
389 | .owner = THIS_MODULE, | |
390 | .read = NULL, | |
391 | .write = amdgpu_ras_debugfs_ctrl_write, | |
392 | .llseek = default_llseek | |
393 | }; | |
394 | ||
084fe13b AG |
395 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
396 | .owner = THIS_MODULE, | |
397 | .read = NULL, | |
398 | .write = amdgpu_ras_debugfs_eeprom_write, | |
399 | .llseek = default_llseek | |
400 | }; | |
401 | ||
f77c7109 AD |
402 | /** |
403 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
404 | * | |
ef177d11 | 405 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
406 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
407 | * | |
408 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
409 | * (ce) error counts. | |
410 | * | |
411 | * The format of one line is below, | |
412 | * | |
413 | * [ce|ue]: count | |
414 | * | |
415 | * Example: | |
416 | * | |
417 | * .. code-block:: bash | |
418 | * | |
419 | * ue: 0 | |
420 | * ce: 1 | |
421 | * | |
422 | */ | |
c030f2e4 | 423 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
424 | struct device_attribute *attr, char *buf) | |
425 | { | |
426 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
427 | struct ras_query_if info = { | |
428 | .head = obj->head, | |
429 | }; | |
430 | ||
61380faa | 431 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
43c4d576 JC |
432 | return snprintf(buf, PAGE_SIZE, |
433 | "Query currently inaccessible\n"); | |
434 | ||
c030f2e4 | 435 | if (amdgpu_ras_error_query(obj->adev, &info)) |
436 | return -EINVAL; | |
437 | ||
438 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
439 | "ue", info.ue_count, | |
440 | "ce", info.ce_count); | |
441 | } | |
442 | ||
443 | /* obj begin */ | |
444 | ||
445 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
446 | #define alive_obj(obj) ((obj)->use) | |
447 | ||
448 | static inline void put_obj(struct ras_manager *obj) | |
449 | { | |
450 | if (obj && --obj->use == 0) | |
451 | list_del(&obj->node); | |
452 | if (obj && obj->use < 0) { | |
453 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
454 | } | |
455 | } | |
456 | ||
457 | /* make one obj and return it. */ | |
458 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
459 | struct ras_common_if *head) | |
460 | { | |
461 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
462 | struct ras_manager *obj; | |
463 | ||
464 | if (!con) | |
465 | return NULL; | |
466 | ||
467 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
468 | return NULL; | |
469 | ||
470 | obj = &con->objs[head->block]; | |
471 | /* already exist. return obj? */ | |
472 | if (alive_obj(obj)) | |
473 | return NULL; | |
474 | ||
475 | obj->head = *head; | |
476 | obj->adev = adev; | |
477 | list_add(&obj->node, &con->head); | |
478 | get_obj(obj); | |
479 | ||
480 | return obj; | |
481 | } | |
482 | ||
483 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 484 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 485 | struct ras_common_if *head) |
486 | { | |
487 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
488 | struct ras_manager *obj; | |
489 | int i; | |
490 | ||
491 | if (!con) | |
492 | return NULL; | |
493 | ||
494 | if (head) { | |
495 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
496 | return NULL; | |
497 | ||
498 | obj = &con->objs[head->block]; | |
499 | ||
500 | if (alive_obj(obj)) { | |
501 | WARN_ON(head->block != obj->head.block); | |
502 | return obj; | |
503 | } | |
504 | } else { | |
505 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
506 | obj = &con->objs[i]; | |
507 | if (alive_obj(obj)) { | |
508 | WARN_ON(i != obj->head.block); | |
509 | return obj; | |
510 | } | |
511 | } | |
512 | } | |
513 | ||
514 | return NULL; | |
515 | } | |
516 | /* obj end */ | |
517 | ||
f3167919 | 518 | static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev, |
a200034b JC |
519 | const char* invoke_type, |
520 | const char* block_name, | |
521 | enum ta_ras_status ret) | |
522 | { | |
523 | switch (ret) { | |
524 | case TA_RAS_STATUS__SUCCESS: | |
525 | return; | |
526 | case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: | |
527 | dev_warn(adev->dev, | |
528 | "RAS WARN: %s %s currently unavailable\n", | |
529 | invoke_type, | |
530 | block_name); | |
531 | break; | |
532 | default: | |
533 | dev_err(adev->dev, | |
534 | "RAS ERROR: %s %s error failed ret 0x%X\n", | |
535 | invoke_type, | |
536 | block_name, | |
537 | ret); | |
538 | } | |
539 | } | |
540 | ||
c030f2e4 | 541 | /* feature ctl begin */ |
542 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
543 | struct ras_common_if *head) | |
544 | { | |
5caf466a | 545 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
546 | ||
547 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 548 | } |
549 | ||
550 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
551 | struct ras_common_if *head) | |
552 | { | |
553 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
554 | ||
555 | return con->features & BIT(head->block); | |
556 | } | |
557 | ||
558 | /* | |
559 | * if obj is not created, then create one. | |
560 | * set feature enable flag. | |
561 | */ | |
562 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
563 | struct ras_common_if *head, int enable) | |
564 | { | |
565 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
566 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
567 | ||
5caf466a | 568 | /* If hardware does not support ras, then do not create obj. |
569 | * But if hardware support ras, we can create the obj. | |
570 | * Ras framework checks con->hw_supported to see if it need do | |
571 | * corresponding initialization. | |
572 | * IP checks con->support to see if it need disable ras. | |
573 | */ | |
c030f2e4 | 574 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
575 | return 0; | |
576 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
577 | return 0; | |
578 | ||
579 | if (enable) { | |
580 | if (!obj) { | |
581 | obj = amdgpu_ras_create_obj(adev, head); | |
582 | if (!obj) | |
583 | return -EINVAL; | |
584 | } else { | |
585 | /* In case we create obj somewhere else */ | |
586 | get_obj(obj); | |
587 | } | |
588 | con->features |= BIT(head->block); | |
589 | } else { | |
590 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
591 | con->features &= ~BIT(head->block); | |
592 | put_obj(obj); | |
593 | } | |
594 | } | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | /* wrapper of psp_ras_enable_features */ | |
600 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
601 | struct ras_common_if *head, bool enable) | |
602 | { | |
603 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 604 | union ta_ras_cmd_input *info; |
c030f2e4 | 605 | int ret; |
606 | ||
607 | if (!con) | |
608 | return -EINVAL; | |
609 | ||
7fcffecf AB |
610 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
611 | if (!info) | |
612 | return -ENOMEM; | |
613 | ||
c030f2e4 | 614 | if (!enable) { |
7fcffecf | 615 | info->disable_features = (struct ta_ras_disable_features_input) { |
828cfa29 | 616 | .block_id = amdgpu_ras_block_to_ta(head->block), |
617 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 618 | }; |
619 | } else { | |
7fcffecf | 620 | info->enable_features = (struct ta_ras_enable_features_input) { |
828cfa29 | 621 | .block_id = amdgpu_ras_block_to_ta(head->block), |
622 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 623 | }; |
624 | } | |
625 | ||
626 | /* Do not enable if it is not allowed. */ | |
627 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
628 | /* Are we alerady in that state we are going to set? */ | |
7fcffecf AB |
629 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) { |
630 | ret = 0; | |
631 | goto out; | |
632 | } | |
c030f2e4 | 633 | |
bff77e86 | 634 | if (!amdgpu_ras_intr_triggered()) { |
7fcffecf | 635 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 636 | if (ret) { |
a200034b JC |
637 | amdgpu_ras_parse_status_code(adev, |
638 | enable ? "enable":"disable", | |
639 | ras_block_str(head->block), | |
640 | (enum ta_ras_status)ret); | |
bff77e86 | 641 | if (ret == TA_RAS_STATUS__RESET_NEEDED) |
7fcffecf AB |
642 | ret = -EAGAIN; |
643 | else | |
644 | ret = -EINVAL; | |
645 | ||
646 | goto out; | |
bff77e86 | 647 | } |
c030f2e4 | 648 | } |
649 | ||
650 | /* setup the obj */ | |
651 | __amdgpu_ras_feature_enable(adev, head, enable); | |
7fcffecf AB |
652 | ret = 0; |
653 | out: | |
654 | kfree(info); | |
655 | return ret; | |
c030f2e4 | 656 | } |
657 | ||
77de502b | 658 | /* Only used in device probe stage and called only once. */ |
659 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
660 | struct ras_common_if *head, bool enable) | |
661 | { | |
662 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
663 | int ret; | |
664 | ||
665 | if (!con) | |
666 | return -EINVAL; | |
667 | ||
668 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 669 | if (enable) { |
670 | /* There is no harm to issue a ras TA cmd regardless of | |
671 | * the currecnt ras state. | |
672 | * If current state == target state, it will do nothing | |
673 | * But sometimes it requests driver to reset and repost | |
674 | * with error code -EAGAIN. | |
675 | */ | |
676 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
677 | /* With old ras TA, we might fail to enable ras. | |
678 | * Log it and just setup the object. | |
679 | * TODO need remove this WA in the future. | |
680 | */ | |
681 | if (ret == -EINVAL) { | |
682 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
683 | if (!ret) | |
6952e99c GC |
684 | dev_info(adev->dev, |
685 | "RAS INFO: %s setup object\n", | |
7af23ebe | 686 | ras_block_str(head->block)); |
687 | } | |
688 | } else { | |
689 | /* setup the object then issue a ras TA disable cmd.*/ | |
690 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
691 | if (ret) | |
692 | return ret; | |
77de502b | 693 | |
77de502b | 694 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 695 | } |
77de502b | 696 | } else |
697 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
698 | ||
699 | return ret; | |
700 | } | |
701 | ||
c030f2e4 | 702 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
703 | bool bypass) | |
704 | { | |
705 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
706 | struct ras_manager *obj, *tmp; | |
707 | ||
708 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
709 | /* bypass psp. | |
710 | * aka just release the obj and corresponding flags | |
711 | */ | |
712 | if (bypass) { | |
713 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
714 | break; | |
715 | } else { | |
716 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
717 | break; | |
718 | } | |
289d513b | 719 | } |
c030f2e4 | 720 | |
721 | return con->features; | |
722 | } | |
723 | ||
724 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
725 | bool bypass) | |
726 | { | |
727 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
728 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
729 | int i; | |
191051a1 | 730 | const enum amdgpu_ras_error_type default_ras_type = |
731 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 732 | |
733 | for (i = 0; i < ras_block_count; i++) { | |
734 | struct ras_common_if head = { | |
735 | .block = i, | |
191051a1 | 736 | .type = default_ras_type, |
c030f2e4 | 737 | .sub_block_index = 0, |
738 | }; | |
739 | strcpy(head.name, ras_block_str(i)); | |
740 | if (bypass) { | |
741 | /* | |
742 | * bypass psp. vbios enable ras for us. | |
743 | * so just create the obj | |
744 | */ | |
745 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
746 | break; | |
747 | } else { | |
748 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
749 | break; | |
750 | } | |
289d513b | 751 | } |
c030f2e4 | 752 | |
753 | return con->features; | |
754 | } | |
755 | /* feature ctl end */ | |
756 | ||
757 | /* query/inject/cure begin */ | |
758 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
759 | struct ras_query_if *info) | |
760 | { | |
761 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 762 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 763 | int i; |
c030f2e4 | 764 | |
765 | if (!obj) | |
766 | return -EINVAL; | |
c030f2e4 | 767 | |
939e2258 HZ |
768 | switch (info->head.block) { |
769 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
770 | if (adev->umc.funcs->query_ras_error_count) |
771 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
772 | /* umc query_ras_error_address is also responsible for clearing |
773 | * error status | |
774 | */ | |
775 | if (adev->umc.funcs->query_ras_error_address) | |
776 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 777 | break; |
3e81ee9a HZ |
778 | case AMDGPU_RAS_BLOCK__SDMA: |
779 | if (adev->sdma.funcs->query_ras_error_count) { | |
780 | for (i = 0; i < adev->sdma.num_instances; i++) | |
781 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
782 | &err_data); | |
783 | } | |
784 | break; | |
83b0582c DL |
785 | case AMDGPU_RAS_BLOCK__GFX: |
786 | if (adev->gfx.funcs->query_ras_error_count) | |
787 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
788 | break; | |
9fb2d8de | 789 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
790 | if (adev->mmhub.funcs->query_ras_error_count) |
791 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 792 | break; |
d7bd680d GC |
793 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
794 | if (adev->nbio.funcs->query_ras_error_count) | |
795 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
796 | break; | |
ec01fe2d HZ |
797 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
798 | amdgpu_xgmi_query_ras_error_count(adev, &err_data); | |
799 | break; | |
939e2258 HZ |
800 | default: |
801 | break; | |
802 | } | |
05a58345 TZ |
803 | |
804 | obj->err_data.ue_count += err_data.ue_count; | |
805 | obj->err_data.ce_count += err_data.ce_count; | |
806 | ||
c030f2e4 | 807 | info->ue_count = obj->err_data.ue_count; |
808 | info->ce_count = obj->err_data.ce_count; | |
809 | ||
7c6e68c7 | 810 | if (err_data.ce_count) { |
6952e99c GC |
811 | dev_info(adev->dev, "%ld correctable hardware errors " |
812 | "detected in %s block, no user " | |
813 | "action is needed.\n", | |
814 | obj->err_data.ce_count, | |
815 | ras_block_str(info->head.block)); | |
7c6e68c7 AG |
816 | } |
817 | if (err_data.ue_count) { | |
6952e99c GC |
818 | dev_info(adev->dev, "%ld uncorrectable hardware errors " |
819 | "detected in %s block\n", | |
820 | obj->err_data.ue_count, | |
821 | ras_block_str(info->head.block)); | |
7c6e68c7 | 822 | } |
05a58345 | 823 | |
c030f2e4 | 824 | return 0; |
825 | } | |
826 | ||
5c23e9e0 | 827 | /* Trigger XGMI/WAFL error */ |
f3167919 | 828 | static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, |
5c23e9e0 JC |
829 | struct ta_ras_trigger_error_input *block_info) |
830 | { | |
831 | int ret; | |
832 | ||
833 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
834 | dev_warn(adev->dev, "Failed to disallow df cstate"); | |
835 | ||
836 | if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) | |
837 | dev_warn(adev->dev, "Failed to disallow XGMI power down"); | |
838 | ||
839 | ret = psp_ras_trigger_error(&adev->psp, block_info); | |
840 | ||
841 | if (amdgpu_ras_intr_triggered()) | |
842 | return ret; | |
843 | ||
844 | if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) | |
845 | dev_warn(adev->dev, "Failed to allow XGMI power down"); | |
846 | ||
847 | if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) | |
848 | dev_warn(adev->dev, "Failed to allow df cstate"); | |
849 | ||
850 | return ret; | |
851 | } | |
852 | ||
c030f2e4 | 853 | /* wrapper of psp_ras_trigger_error */ |
854 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
855 | struct ras_inject_if *info) | |
856 | { | |
857 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
858 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 859 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
860 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 861 | .sub_block_index = info->head.sub_block_index, |
862 | .address = info->address, | |
863 | .value = info->value, | |
864 | }; | |
865 | int ret = 0; | |
866 | ||
867 | if (!obj) | |
868 | return -EINVAL; | |
869 | ||
a6c44d25 JC |
870 | /* Calculate XGMI relative offset */ |
871 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
872 | block_info.address = |
873 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
874 | block_info.address); | |
a6c44d25 JC |
875 | } |
876 | ||
83b0582c DL |
877 | switch (info->head.block) { |
878 | case AMDGPU_RAS_BLOCK__GFX: | |
879 | if (adev->gfx.funcs->ras_error_inject) | |
880 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
881 | else | |
882 | ret = -EINVAL; | |
883 | break; | |
884 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 885 | case AMDGPU_RAS_BLOCK__MMHUB: |
d7bd680d | 886 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
887 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
888 | break; | |
5c23e9e0 JC |
889 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
890 | ret = amdgpu_ras_error_inject_xgmi(adev, &block_info); | |
891 | break; | |
83b0582c | 892 | default: |
6952e99c | 893 | dev_info(adev->dev, "%s error injection is not supported yet\n", |
a5dd40ca | 894 | ras_block_str(info->head.block)); |
83b0582c | 895 | ret = -EINVAL; |
a5dd40ca HZ |
896 | } |
897 | ||
a200034b JC |
898 | amdgpu_ras_parse_status_code(adev, |
899 | "inject", | |
900 | ras_block_str(info->head.block), | |
901 | (enum ta_ras_status)ret); | |
c030f2e4 | 902 | |
903 | return ret; | |
904 | } | |
905 | ||
906 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
907 | struct ras_cure_if *info) | |
908 | { | |
909 | /* psp fw has no cure interface for now. */ | |
910 | return 0; | |
911 | } | |
912 | ||
913 | /* get the total error counts on all IPs */ | |
64cc5414 | 914 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 915 | bool is_ce) |
916 | { | |
917 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
918 | struct ras_manager *obj; | |
919 | struct ras_err_data data = {0, 0}; | |
920 | ||
921 | if (!con) | |
64cc5414 | 922 | return 0; |
c030f2e4 | 923 | |
924 | list_for_each_entry(obj, &con->head, node) { | |
925 | struct ras_query_if info = { | |
926 | .head = obj->head, | |
927 | }; | |
928 | ||
929 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 930 | return 0; |
c030f2e4 | 931 | |
932 | data.ce_count += info.ce_count; | |
933 | data.ue_count += info.ue_count; | |
934 | } | |
935 | ||
936 | return is_ce ? data.ce_count : data.ue_count; | |
937 | } | |
938 | /* query/inject/cure end */ | |
939 | ||
940 | ||
941 | /* sysfs begin */ | |
942 | ||
466b1793 | 943 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
944 | struct ras_badpage **bps, unsigned int *count); | |
945 | ||
946 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
947 | { | |
948 | switch (flags) { | |
52dd95f2 | 949 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 950 | return "R"; |
52dd95f2 | 951 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 952 | return "P"; |
52dd95f2 | 953 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 954 | default: |
955 | return "F"; | |
956 | }; | |
957 | } | |
958 | ||
f77c7109 AD |
959 | /** |
960 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 961 | * |
962 | * It allows user to read the bad pages of vram on the gpu through | |
963 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
964 | * | |
965 | * It outputs multiple lines, and each line stands for one gpu page. | |
966 | * | |
967 | * The format of one line is below, | |
968 | * gpu pfn : gpu page size : flags | |
969 | * | |
970 | * gpu pfn and gpu page size are printed in hex format. | |
971 | * flags can be one of below character, | |
f77c7109 | 972 | * |
466b1793 | 973 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 974 | * |
466b1793 | 975 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
976 | * in next window of page_reserve. |
977 | * | |
466b1793 | 978 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
979 | * | |
f77c7109 AD |
980 | * Examples: |
981 | * | |
982 | * .. code-block:: bash | |
983 | * | |
984 | * 0x00000001 : 0x00001000 : R | |
985 | * 0x00000002 : 0x00001000 : P | |
986 | * | |
466b1793 | 987 | */ |
988 | ||
989 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
990 | struct kobject *kobj, struct bin_attribute *attr, | |
991 | char *buf, loff_t ppos, size_t count) | |
992 | { | |
993 | struct amdgpu_ras *con = | |
994 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
995 | struct amdgpu_device *adev = con->adev; | |
996 | const unsigned int element_size = | |
997 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
998 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
999 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1000 | ssize_t s = 0; |
1001 | struct ras_badpage *bps = NULL; | |
1002 | unsigned int bps_count = 0; | |
1003 | ||
1004 | memset(buf, 0, count); | |
1005 | ||
1006 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1007 | return 0; | |
1008 | ||
1009 | for (; start < end && start < bps_count; start++) | |
1010 | s += scnprintf(&buf[s], element_size + 1, | |
1011 | "0x%08x : 0x%08x : %1s\n", | |
1012 | bps[start].bp, | |
1013 | bps[start].size, | |
1014 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1015 | ||
1016 | kfree(bps); | |
1017 | ||
1018 | return s; | |
1019 | } | |
1020 | ||
c030f2e4 | 1021 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1022 | struct device_attribute *attr, char *buf) | |
1023 | { | |
1024 | struct amdgpu_ras *con = | |
1025 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1026 | |
5212a3bd | 1027 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1028 | } |
1029 | ||
f848159b GC |
1030 | static void amdgpu_ras_sysfs_add_bad_page_node(struct amdgpu_device *adev) |
1031 | { | |
1032 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1033 | struct attribute_group group; | |
1034 | struct bin_attribute *bin_attrs[] = { | |
1035 | &con->badpages_attr, | |
1036 | NULL, | |
1037 | }; | |
1038 | ||
1039 | con->badpages_attr = (struct bin_attribute) { | |
1040 | .attr = { | |
1041 | .name = "gpu_vram_bad_pages", | |
1042 | .mode = S_IRUGO, | |
1043 | }, | |
1044 | .size = 0, | |
1045 | .private = NULL, | |
1046 | .read = amdgpu_ras_sysfs_badpages_read, | |
1047 | }; | |
1048 | ||
1049 | group.name = RAS_FS_NAME; | |
1050 | group.bin_attrs = bin_attrs; | |
1051 | ||
1052 | sysfs_bin_attr_init(bin_attrs[0]); | |
1053 | ||
1054 | sysfs_update_group(&adev->dev->kobj, &group); | |
1055 | } | |
1056 | ||
c030f2e4 | 1057 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) |
1058 | { | |
1059 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1060 | struct attribute *attrs[] = { | |
1061 | &con->features_attr.attr, | |
1062 | NULL | |
1063 | }; | |
1064 | struct attribute_group group = { | |
eb0c3cd4 | 1065 | .name = RAS_FS_NAME, |
c030f2e4 | 1066 | .attrs = attrs, |
1067 | }; | |
1068 | ||
1069 | con->features_attr = (struct device_attribute) { | |
1070 | .attr = { | |
1071 | .name = "features", | |
1072 | .mode = S_IRUGO, | |
1073 | }, | |
1074 | .show = amdgpu_ras_sysfs_features_read, | |
1075 | }; | |
466b1793 | 1076 | |
163def43 | 1077 | sysfs_attr_init(attrs[0]); |
c030f2e4 | 1078 | |
1079 | return sysfs_create_group(&adev->dev->kobj, &group); | |
1080 | } | |
1081 | ||
f848159b GC |
1082 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1083 | { | |
1084 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1085 | ||
1086 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1087 | &con->badpages_attr.attr, | |
1088 | RAS_FS_NAME); | |
1089 | } | |
1090 | ||
c030f2e4 | 1091 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1092 | { | |
1093 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1094 | struct attribute *attrs[] = { | |
1095 | &con->features_attr.attr, | |
1096 | NULL | |
1097 | }; | |
1098 | struct attribute_group group = { | |
eb0c3cd4 | 1099 | .name = RAS_FS_NAME, |
c030f2e4 | 1100 | .attrs = attrs, |
1101 | }; | |
1102 | ||
1103 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
1109 | struct ras_fs_if *head) | |
1110 | { | |
1111 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
1112 | ||
1113 | if (!obj || obj->attr_inuse) | |
1114 | return -EINVAL; | |
1115 | ||
1116 | get_obj(obj); | |
1117 | ||
1118 | memcpy(obj->fs_data.sysfs_name, | |
1119 | head->sysfs_name, | |
1120 | sizeof(obj->fs_data.sysfs_name)); | |
1121 | ||
1122 | obj->sysfs_attr = (struct device_attribute){ | |
1123 | .attr = { | |
1124 | .name = obj->fs_data.sysfs_name, | |
1125 | .mode = S_IRUGO, | |
1126 | }, | |
1127 | .show = amdgpu_ras_sysfs_read, | |
1128 | }; | |
163def43 | 1129 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1130 | |
1131 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1132 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1133 | RAS_FS_NAME)) { |
c030f2e4 | 1134 | put_obj(obj); |
1135 | return -EINVAL; | |
1136 | } | |
1137 | ||
1138 | obj->attr_inuse = 1; | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1144 | struct ras_common_if *head) | |
1145 | { | |
1146 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1147 | ||
1148 | if (!obj || !obj->attr_inuse) | |
1149 | return -EINVAL; | |
1150 | ||
1151 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1152 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1153 | RAS_FS_NAME); |
c030f2e4 | 1154 | obj->attr_inuse = 0; |
1155 | put_obj(obj); | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
1160 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1161 | { | |
1162 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1163 | struct ras_manager *obj, *tmp; | |
1164 | ||
1165 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1166 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1167 | } | |
1168 | ||
f848159b GC |
1169 | if (amdgpu_bad_page_threshold != 0) |
1170 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1171 | ||
c030f2e4 | 1172 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | /* sysfs end */ | |
1177 | ||
ef177d11 AD |
1178 | /** |
1179 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1180 | * | |
1181 | * Normally when there is an uncorrectable error, the driver will reset | |
1182 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1183 | * the driver provides an interface to reboot the system automatically | |
1184 | * in that event. | |
1185 | * | |
1186 | * The following file in debugfs provides that interface: | |
1187 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1188 | * | |
1189 | * Usage: | |
1190 | * | |
1191 | * .. code-block:: bash | |
1192 | * | |
1193 | * echo true > .../ras/auto_reboot | |
1194 | * | |
1195 | */ | |
c030f2e4 | 1196 | /* debugfs begin */ |
450f30ea | 1197 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1198 | { |
1199 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1200 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 1201 | |
eb0c3cd4 | 1202 | con->dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
012dd14d GC |
1203 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1204 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1205 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1206 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1207 | |
1208 | /* | |
1209 | * After one uncorrectable error happens, usually GPU recovery will | |
1210 | * be scheduled. But due to the known problem in GPU recovery failing | |
1211 | * to bring GPU back, below interface provides one direct way to | |
1212 | * user to reboot system automatically in such case within | |
1213 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1214 | * will never be called. | |
1215 | */ | |
1216 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1217 | &con->reboot); | |
66459e1d GC |
1218 | |
1219 | /* | |
1220 | * User could set this not to clean up hardware's error count register | |
1221 | * of RAS IPs during ras recovery. | |
1222 | */ | |
1223 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, | |
1224 | con->dir, &con->disable_ras_err_cnt_harvest); | |
36ea1bd2 | 1225 | } |
1226 | ||
450f30ea | 1227 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1228 | struct ras_fs_if *head) |
1229 | { | |
1230 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1231 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1232 | |
1233 | if (!obj || obj->ent) | |
450f30ea | 1234 | return; |
c030f2e4 | 1235 | |
1236 | get_obj(obj); | |
1237 | ||
1238 | memcpy(obj->fs_data.debugfs_name, | |
1239 | head->debugfs_name, | |
1240 | sizeof(obj->fs_data.debugfs_name)); | |
1241 | ||
450f30ea GKH |
1242 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1243 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1244 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1245 | } |
1246 | ||
f9317014 TZ |
1247 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1248 | { | |
1249 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c1509f3f | 1250 | struct ras_manager *obj; |
f9317014 TZ |
1251 | struct ras_fs_if fs_info; |
1252 | ||
1253 | /* | |
1254 | * it won't be called in resume path, no need to check | |
1255 | * suspend and gpu reset status | |
1256 | */ | |
1257 | if (!con) | |
1258 | return; | |
1259 | ||
1260 | amdgpu_ras_debugfs_create_ctrl_node(adev); | |
1261 | ||
c1509f3f | 1262 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1263 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1264 | (obj->attr_inuse == 1)) { | |
1265 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
1266 | ras_block_str(obj->head.block)); | |
1267 | fs_info.head = obj->head; | |
1268 | amdgpu_ras_debugfs_create(adev, &fs_info); | |
1269 | } | |
1270 | } | |
1271 | } | |
1272 | ||
450f30ea | 1273 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1274 | struct ras_common_if *head) |
1275 | { | |
1276 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1277 | ||
1278 | if (!obj || !obj->ent) | |
450f30ea | 1279 | return; |
c030f2e4 | 1280 | |
c030f2e4 | 1281 | obj->ent = NULL; |
1282 | put_obj(obj); | |
c030f2e4 | 1283 | } |
1284 | ||
450f30ea | 1285 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1286 | { |
1287 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1288 | struct ras_manager *obj, *tmp; | |
1289 | ||
1290 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1291 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1292 | } | |
1293 | ||
c030f2e4 | 1294 | con->dir = NULL; |
c030f2e4 | 1295 | } |
1296 | /* debugfs end */ | |
1297 | ||
1298 | /* ras fs */ | |
1299 | ||
1300 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1301 | { | |
c030f2e4 | 1302 | amdgpu_ras_sysfs_create_feature_node(adev); |
1303 | ||
f848159b GC |
1304 | if (amdgpu_bad_page_threshold != 0) |
1305 | amdgpu_ras_sysfs_add_bad_page_node(adev); | |
1306 | ||
c030f2e4 | 1307 | return 0; |
1308 | } | |
1309 | ||
1310 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1311 | { | |
1312 | amdgpu_ras_debugfs_remove_all(adev); | |
1313 | amdgpu_ras_sysfs_remove_all(adev); | |
1314 | return 0; | |
1315 | } | |
1316 | /* ras fs end */ | |
1317 | ||
1318 | /* ih begin */ | |
1319 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1320 | { | |
1321 | struct ras_ih_data *data = &obj->ih_data; | |
1322 | struct amdgpu_iv_entry entry; | |
1323 | int ret; | |
cf04dfd0 | 1324 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1325 | |
1326 | while (data->rptr != data->wptr) { | |
1327 | rmb(); | |
1328 | memcpy(&entry, &data->ring[data->rptr], | |
1329 | data->element_size); | |
1330 | ||
1331 | wmb(); | |
1332 | data->rptr = (data->aligned_element_size + | |
1333 | data->rptr) % data->ring_size; | |
1334 | ||
1335 | /* Let IP handle its data, maybe we need get the output | |
1336 | * from the callback to udpate the error type/count, etc | |
1337 | */ | |
1338 | if (data->cb) { | |
cf04dfd0 | 1339 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1340 | /* ue will trigger an interrupt, and in that case |
1341 | * we need do a reset to recovery the whole system. | |
1342 | * But leave IP do that recovery, here we just dispatch | |
1343 | * the error. | |
1344 | */ | |
bd2280da | 1345 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1346 | /* these counts could be left as 0 if |
1347 | * some blocks do not count error number | |
1348 | */ | |
cf04dfd0 | 1349 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1350 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1351 | } |
c030f2e4 | 1352 | } |
1353 | } | |
1354 | } | |
1355 | ||
1356 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1357 | { | |
1358 | struct ras_ih_data *data = | |
1359 | container_of(work, struct ras_ih_data, ih_work); | |
1360 | struct ras_manager *obj = | |
1361 | container_of(data, struct ras_manager, ih_data); | |
1362 | ||
1363 | amdgpu_ras_interrupt_handler(obj); | |
1364 | } | |
1365 | ||
1366 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1367 | struct ras_dispatch_if *info) | |
1368 | { | |
1369 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1370 | struct ras_ih_data *data = &obj->ih_data; | |
1371 | ||
1372 | if (!obj) | |
1373 | return -EINVAL; | |
1374 | ||
1375 | if (data->inuse == 0) | |
1376 | return 0; | |
1377 | ||
1378 | /* Might be overflow... */ | |
1379 | memcpy(&data->ring[data->wptr], info->entry, | |
1380 | data->element_size); | |
1381 | ||
1382 | wmb(); | |
1383 | data->wptr = (data->aligned_element_size + | |
1384 | data->wptr) % data->ring_size; | |
1385 | ||
1386 | schedule_work(&data->ih_work); | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1392 | struct ras_ih_if *info) | |
1393 | { | |
1394 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1395 | struct ras_ih_data *data; | |
1396 | ||
1397 | if (!obj) | |
1398 | return -EINVAL; | |
1399 | ||
1400 | data = &obj->ih_data; | |
1401 | if (data->inuse == 0) | |
1402 | return 0; | |
1403 | ||
1404 | cancel_work_sync(&data->ih_work); | |
1405 | ||
1406 | kfree(data->ring); | |
1407 | memset(data, 0, sizeof(*data)); | |
1408 | put_obj(obj); | |
1409 | ||
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1414 | struct ras_ih_if *info) | |
1415 | { | |
1416 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1417 | struct ras_ih_data *data; | |
1418 | ||
1419 | if (!obj) { | |
1420 | /* in case we registe the IH before enable ras feature */ | |
1421 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1422 | if (!obj) | |
1423 | return -EINVAL; | |
1424 | } else | |
1425 | get_obj(obj); | |
1426 | ||
1427 | data = &obj->ih_data; | |
1428 | /* add the callback.etc */ | |
1429 | *data = (struct ras_ih_data) { | |
1430 | .inuse = 0, | |
1431 | .cb = info->cb, | |
1432 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1433 | .rptr = 0, | |
1434 | .wptr = 0, | |
1435 | }; | |
1436 | ||
1437 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1438 | ||
1439 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1440 | /* the ring can store 64 iv entries. */ | |
1441 | data->ring_size = 64 * data->aligned_element_size; | |
1442 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1443 | if (!data->ring) { | |
1444 | put_obj(obj); | |
1445 | return -ENOMEM; | |
1446 | } | |
1447 | ||
1448 | /* IH is ready */ | |
1449 | data->inuse = 1; | |
1450 | ||
1451 | return 0; | |
1452 | } | |
1453 | ||
1454 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1455 | { | |
1456 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1457 | struct ras_manager *obj, *tmp; | |
1458 | ||
1459 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1460 | struct ras_ih_if info = { | |
1461 | .head = obj->head, | |
1462 | }; | |
1463 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1464 | } | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | /* ih end */ | |
1469 | ||
313c8fd3 GC |
1470 | /* traversal all IPs except NBIO to query error counter */ |
1471 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1472 | { | |
1473 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1474 | struct ras_manager *obj; | |
1475 | ||
1476 | if (!con) | |
1477 | return; | |
1478 | ||
1479 | list_for_each_entry(obj, &con->head, node) { | |
1480 | struct ras_query_if info = { | |
1481 | .head = obj->head, | |
1482 | }; | |
1483 | ||
1484 | /* | |
1485 | * PCIE_BIF IP has one different isr by ras controller | |
1486 | * interrupt, the specific ras counter query will be | |
1487 | * done in that isr. So skip such block from common | |
1488 | * sync flood interrupt isr calling. | |
1489 | */ | |
1490 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1491 | continue; | |
1492 | ||
1493 | amdgpu_ras_error_query(adev, &info); | |
1494 | } | |
1495 | } | |
1496 | ||
c030f2e4 | 1497 | /* recovery begin */ |
466b1793 | 1498 | |
1499 | /* return 0 on success. | |
1500 | * caller need free bps. | |
1501 | */ | |
1502 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1503 | struct ras_badpage **bps, unsigned int *count) | |
1504 | { | |
1505 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1506 | struct ras_err_handler_data *data; | |
1507 | int i = 0; | |
1508 | int ret = 0; | |
1509 | ||
1510 | if (!con || !con->eh_data || !bps || !count) | |
1511 | return -EINVAL; | |
1512 | ||
1513 | mutex_lock(&con->recovery_lock); | |
1514 | data = con->eh_data; | |
1515 | if (!data || data->count == 0) { | |
1516 | *bps = NULL; | |
46cf2fec | 1517 | ret = -EINVAL; |
466b1793 | 1518 | goto out; |
1519 | } | |
1520 | ||
1521 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1522 | if (!*bps) { | |
1523 | ret = -ENOMEM; | |
1524 | goto out; | |
1525 | } | |
1526 | ||
1527 | for (; i < data->count; i++) { | |
1528 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1529 | .bp = data->bps[i].retired_page, |
466b1793 | 1530 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1531 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1532 | }; |
1533 | ||
1534 | if (data->last_reserved <= i) | |
52dd95f2 | 1535 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
9dc23a63 | 1536 | else if (data->bps_bo[i] == NULL) |
52dd95f2 | 1537 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1538 | } |
1539 | ||
1540 | *count = data->count; | |
1541 | out: | |
1542 | mutex_unlock(&con->recovery_lock); | |
1543 | return ret; | |
1544 | } | |
1545 | ||
c030f2e4 | 1546 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1547 | { | |
1548 | struct amdgpu_ras *ras = | |
1549 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
1550 | struct amdgpu_device *remote_adev = NULL; |
1551 | struct amdgpu_device *adev = ras->adev; | |
1552 | struct list_head device_list, *device_list_handle = NULL; | |
1553 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev, false); | |
1554 | ||
f75e94d8 GC |
1555 | if (!ras->disable_ras_err_cnt_harvest) { |
1556 | /* Build list of devices to query RAS related errors */ | |
1557 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
1558 | device_list_handle = &hive->device_list; | |
1559 | } else { | |
1560 | INIT_LIST_HEAD(&device_list); | |
1561 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
1562 | device_list_handle = &device_list; | |
1563 | } | |
c030f2e4 | 1564 | |
f75e94d8 GC |
1565 | list_for_each_entry(remote_adev, |
1566 | device_list_handle, gmc.xgmi.head) | |
1567 | amdgpu_ras_log_on_err_counter(remote_adev); | |
b3dbd6d3 | 1568 | } |
313c8fd3 | 1569 | |
93af20f7 | 1570 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
2f530724 | 1571 | amdgpu_device_gpu_recover(ras->adev, NULL); |
c030f2e4 | 1572 | atomic_set(&ras->in_recovery, 0); |
1573 | } | |
1574 | ||
c030f2e4 | 1575 | /* alloc/realloc bps array */ |
1576 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1577 | struct ras_err_handler_data *data, int pages) | |
1578 | { | |
1579 | unsigned int old_space = data->count + data->space_left; | |
1580 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1581 | unsigned int align_space = ALIGN(new_space, 512); |
1582 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1583 | struct amdgpu_bo **bps_bo = | |
1584 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1585 | ||
1586 | if (!bps || !bps_bo) { | |
1587 | kfree(bps); | |
1588 | kfree(bps_bo); | |
c030f2e4 | 1589 | return -ENOMEM; |
9dc23a63 | 1590 | } |
c030f2e4 | 1591 | |
1592 | if (data->bps) { | |
9dc23a63 | 1593 | memcpy(bps, data->bps, |
c030f2e4 | 1594 | data->count * sizeof(*data->bps)); |
1595 | kfree(data->bps); | |
1596 | } | |
9dc23a63 TZ |
1597 | if (data->bps_bo) { |
1598 | memcpy(bps_bo, data->bps_bo, | |
1599 | data->count * sizeof(*data->bps_bo)); | |
1600 | kfree(data->bps_bo); | |
1601 | } | |
c030f2e4 | 1602 | |
9dc23a63 TZ |
1603 | data->bps = bps; |
1604 | data->bps_bo = bps_bo; | |
c030f2e4 | 1605 | data->space_left += align_space - old_space; |
1606 | return 0; | |
1607 | } | |
1608 | ||
1609 | /* it deal with vram only. */ | |
1610 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1611 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1612 | { |
1613 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1614 | struct ras_err_handler_data *data; |
c030f2e4 | 1615 | int ret = 0; |
1616 | ||
73aa8e1a | 1617 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1618 | return 0; |
1619 | ||
1620 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1621 | data = con->eh_data; |
c030f2e4 | 1622 | if (!data) |
1623 | goto out; | |
1624 | ||
1625 | if (data->space_left <= pages) | |
1626 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1627 | ret = -ENOMEM; | |
1628 | goto out; | |
1629 | } | |
1630 | ||
9dc23a63 TZ |
1631 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1632 | data->count += pages; | |
c030f2e4 | 1633 | data->space_left -= pages; |
9dc23a63 | 1634 | |
c030f2e4 | 1635 | out: |
1636 | mutex_unlock(&con->recovery_lock); | |
1637 | ||
1638 | return ret; | |
1639 | } | |
1640 | ||
78ad00c9 TZ |
1641 | /* |
1642 | * write error record array to eeprom, the function should be | |
1643 | * protected by recovery_lock | |
1644 | */ | |
1645 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1646 | { | |
1647 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1648 | struct ras_err_handler_data *data; | |
8a3e801f | 1649 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1650 | int save_count; |
1651 | ||
1652 | if (!con || !con->eh_data) | |
1653 | return 0; | |
1654 | ||
8a3e801f | 1655 | control = &con->eeprom_control; |
78ad00c9 TZ |
1656 | data = con->eh_data; |
1657 | save_count = data->count - control->num_recs; | |
1658 | /* only new entries are saved */ | |
b1628425 | 1659 | if (save_count > 0) { |
0771b0bf | 1660 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1661 | &data->bps[control->num_recs], |
1662 | true, | |
1663 | save_count)) { | |
6952e99c | 1664 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
1665 | return -EIO; |
1666 | } | |
1667 | ||
b1628425 GC |
1668 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
1669 | } | |
1670 | ||
78ad00c9 TZ |
1671 | return 0; |
1672 | } | |
1673 | ||
1674 | /* | |
1675 | * read error record array in eeprom and reserve enough space for | |
1676 | * storing new bad pages | |
1677 | */ | |
1678 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1679 | { | |
1680 | struct amdgpu_ras_eeprom_control *control = | |
1681 | &adev->psp.ras.ras->eeprom_control; | |
1682 | struct eeprom_table_record *bps = NULL; | |
1683 | int ret = 0; | |
1684 | ||
1685 | /* no bad page record, skip eeprom access */ | |
a219ecbb | 1686 | if (!control->num_recs || (amdgpu_bad_page_threshold == 0)) |
78ad00c9 TZ |
1687 | return ret; |
1688 | ||
1689 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1690 | if (!bps) | |
1691 | return -ENOMEM; | |
1692 | ||
1693 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1694 | control->num_recs)) { | |
6952e99c | 1695 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
78ad00c9 TZ |
1696 | ret = -EIO; |
1697 | goto out; | |
1698 | } | |
1699 | ||
1700 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1701 | ||
1702 | out: | |
1703 | kfree(bps); | |
1704 | return ret; | |
1705 | } | |
1706 | ||
6e4be987 TZ |
1707 | /* |
1708 | * check if an address belongs to bad page | |
1709 | * | |
1710 | * Note: this check is only for umc block | |
1711 | */ | |
1712 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1713 | uint64_t addr) | |
1714 | { | |
1715 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1716 | struct ras_err_handler_data *data; | |
1717 | int i; | |
1718 | bool ret = false; | |
1719 | ||
1720 | if (!con || !con->eh_data) | |
1721 | return ret; | |
1722 | ||
1723 | mutex_lock(&con->recovery_lock); | |
1724 | data = con->eh_data; | |
1725 | if (!data) | |
1726 | goto out; | |
1727 | ||
1728 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1729 | for (i = 0; i < data->count; i++) | |
1730 | if (addr == data->bps[i].retired_page) { | |
1731 | ret = true; | |
1732 | goto out; | |
1733 | } | |
1734 | ||
1735 | out: | |
1736 | mutex_unlock(&con->recovery_lock); | |
1737 | return ret; | |
1738 | } | |
1739 | ||
c84d4670 GC |
1740 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
1741 | uint32_t max_length) | |
1742 | { | |
1743 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1744 | int tmp_threshold = amdgpu_bad_page_threshold; | |
1745 | u64 val; | |
1746 | ||
1747 | /* | |
1748 | * Justification of value bad_page_cnt_threshold in ras structure | |
1749 | * | |
1750 | * Generally, -1 <= amdgpu_bad_page_threshold <= max record length | |
1751 | * in eeprom, and introduce two scenarios accordingly. | |
1752 | * | |
1753 | * Bad page retirement enablement: | |
1754 | * - If amdgpu_bad_page_threshold = -1, | |
1755 | * bad_page_cnt_threshold = typical value by formula. | |
1756 | * | |
1757 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
1758 | * max record length in eeprom, use it directly. | |
1759 | * | |
1760 | * Bad page retirement disablement: | |
1761 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
1762 | * functionality is disabled, and bad_page_cnt_threshold will | |
1763 | * take no effect. | |
1764 | */ | |
1765 | ||
1766 | if (tmp_threshold < -1) | |
1767 | tmp_threshold = -1; | |
1768 | else if (tmp_threshold > max_length) | |
1769 | tmp_threshold = max_length; | |
1770 | ||
1771 | if (tmp_threshold == -1) { | |
1772 | val = adev->gmc.mc_vram_size; | |
1773 | do_div(val, RAS_BAD_PAGE_RATE); | |
1774 | con->bad_page_cnt_threshold = min(lower_32_bits(val), | |
1775 | max_length); | |
1776 | } else { | |
1777 | con->bad_page_cnt_threshold = tmp_threshold; | |
1778 | } | |
1779 | } | |
1780 | ||
c030f2e4 | 1781 | /* called in gpu recovery/init */ |
1782 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1783 | { | |
1784 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1785 | struct ras_err_handler_data *data; |
c030f2e4 | 1786 | uint64_t bp; |
de7b45ba | 1787 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1788 | int i, ret = 0; |
c030f2e4 | 1789 | |
a219ecbb GC |
1790 | /* Not reserve bad page when amdgpu_bad_page_threshold == 0. */ |
1791 | if (!con || !con->eh_data || (amdgpu_bad_page_threshold == 0)) | |
c030f2e4 | 1792 | return 0; |
1793 | ||
1794 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1795 | data = con->eh_data; |
1796 | if (!data) | |
1797 | goto out; | |
c030f2e4 | 1798 | /* reserve vram at driver post stage. */ |
1799 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1800 | bp = data->bps[i].retired_page; |
c030f2e4 | 1801 | |
ae115c81 TZ |
1802 | /* There are two cases of reserve error should be ignored: |
1803 | * 1) a ras bad page has been allocated (used by someone); | |
1804 | * 2) a ras bad page has been reserved (duplicate error injection | |
1805 | * for one page); | |
1806 | */ | |
a142ba88 AD |
1807 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, |
1808 | AMDGPU_GPU_PAGE_SIZE, | |
de7b45ba CK |
1809 | AMDGPU_GEM_DOMAIN_VRAM, |
1810 | &bo, NULL)) | |
6952e99c GC |
1811 | dev_warn(adev->dev, "RAS WARN: reserve vram for " |
1812 | "retired page %llx fail\n", bp); | |
c030f2e4 | 1813 | |
9dc23a63 | 1814 | data->bps_bo[i] = bo; |
c030f2e4 | 1815 | data->last_reserved = i + 1; |
de7b45ba | 1816 | bo = NULL; |
c030f2e4 | 1817 | } |
78ad00c9 TZ |
1818 | |
1819 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1820 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1821 | out: |
c030f2e4 | 1822 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1823 | return ret; |
c030f2e4 | 1824 | } |
1825 | ||
1826 | /* called when driver unload */ | |
1827 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1828 | { | |
1829 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1830 | struct ras_err_handler_data *data; |
c030f2e4 | 1831 | struct amdgpu_bo *bo; |
1832 | int i; | |
1833 | ||
73aa8e1a | 1834 | if (!con || !con->eh_data) |
c030f2e4 | 1835 | return 0; |
1836 | ||
1837 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1838 | data = con->eh_data; |
1839 | if (!data) | |
1840 | goto out; | |
1841 | ||
c030f2e4 | 1842 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1843 | bo = data->bps_bo[i]; |
c030f2e4 | 1844 | |
de7b45ba | 1845 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1846 | |
9dc23a63 | 1847 | data->bps_bo[i] = bo; |
c030f2e4 | 1848 | data->last_reserved = i; |
1849 | } | |
73aa8e1a | 1850 | out: |
c030f2e4 | 1851 | mutex_unlock(&con->recovery_lock); |
1852 | return 0; | |
1853 | } | |
1854 | ||
1a6fc071 | 1855 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1856 | { |
1857 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1858 | struct ras_err_handler_data **data; |
c84d4670 | 1859 | uint32_t max_eeprom_records_len = 0; |
b82e65a9 | 1860 | bool exc_err_limit = false; |
78ad00c9 | 1861 | int ret; |
c030f2e4 | 1862 | |
4d1337d2 AG |
1863 | if (con) |
1864 | data = &con->eh_data; | |
1865 | else | |
1866 | return 0; | |
1867 | ||
1a6fc071 TZ |
1868 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1869 | if (!*data) { | |
1870 | ret = -ENOMEM; | |
1871 | goto out; | |
1872 | } | |
c030f2e4 | 1873 | |
1874 | mutex_init(&con->recovery_lock); | |
1875 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1876 | atomic_set(&con->in_recovery, 0); | |
1877 | con->adev = adev; | |
1878 | ||
c84d4670 GC |
1879 | max_eeprom_records_len = amdgpu_ras_eeprom_get_record_max_length(); |
1880 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_len); | |
1881 | ||
b82e65a9 GC |
1882 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
1883 | /* | |
1884 | * This calling fails when exc_err_limit is true or | |
1885 | * ret != 0. | |
1886 | */ | |
1887 | if (exc_err_limit || ret) | |
1a6fc071 | 1888 | goto free; |
78ad00c9 | 1889 | |
0771b0bf | 1890 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1891 | ret = amdgpu_ras_load_bad_pages(adev); |
1892 | if (ret) | |
1a6fc071 | 1893 | goto free; |
78ad00c9 TZ |
1894 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1895 | if (ret) | |
1a6fc071 | 1896 | goto release; |
78ad00c9 | 1897 | } |
c030f2e4 | 1898 | |
1899 | return 0; | |
1a6fc071 TZ |
1900 | |
1901 | release: | |
1902 | amdgpu_ras_release_bad_pages(adev); | |
1903 | free: | |
1a6fc071 TZ |
1904 | kfree((*data)->bps); |
1905 | kfree((*data)->bps_bo); | |
1906 | kfree(*data); | |
1995b3a3 | 1907 | con->eh_data = NULL; |
1a6fc071 | 1908 | out: |
6952e99c | 1909 | dev_warn(adev->dev, "Failed to initialize ras recovery!\n"); |
1a6fc071 | 1910 | |
b82e65a9 GC |
1911 | /* |
1912 | * Except error threshold exceeding case, other failure cases in this | |
1913 | * function would not fail amdgpu driver init. | |
1914 | */ | |
1915 | if (!exc_err_limit) | |
1916 | ret = 0; | |
1917 | else | |
1918 | ret = -EINVAL; | |
1919 | ||
1a6fc071 | 1920 | return ret; |
c030f2e4 | 1921 | } |
1922 | ||
1923 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1924 | { | |
1925 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1926 | struct ras_err_handler_data *data = con->eh_data; | |
1927 | ||
1a6fc071 TZ |
1928 | /* recovery_init failed to init it, fini is useless */ |
1929 | if (!data) | |
1930 | return 0; | |
1931 | ||
c030f2e4 | 1932 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1933 | amdgpu_ras_release_bad_pages(adev); |
1934 | ||
1935 | mutex_lock(&con->recovery_lock); | |
1936 | con->eh_data = NULL; | |
1937 | kfree(data->bps); | |
1a6fc071 | 1938 | kfree(data->bps_bo); |
c030f2e4 | 1939 | kfree(data); |
1940 | mutex_unlock(&con->recovery_lock); | |
1941 | ||
1942 | return 0; | |
1943 | } | |
1944 | /* recovery end */ | |
1945 | ||
a564808e | 1946 | /* return 0 if ras will reset gpu and repost.*/ |
1947 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1948 | unsigned int block) | |
1949 | { | |
1950 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1951 | ||
1952 | if (!ras) | |
1953 | return -EINVAL; | |
1954 | ||
1955 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1956 | return 0; | |
1957 | } | |
1958 | ||
5caf466a | 1959 | /* |
1960 | * check hardware's ras ability which will be saved in hw_supported. | |
1961 | * if hardware does not support ras, we can skip some ras initializtion and | |
1962 | * forbid some ras operations from IP. | |
1963 | * if software itself, say boot parameter, limit the ras ability. We still | |
1964 | * need allow IP do some limited operations, like disable. In such case, | |
1965 | * we have to initialize ras as normal. but need check if operation is | |
1966 | * allowed or not in each function. | |
1967 | */ | |
1968 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1969 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1970 | { |
5caf466a | 1971 | *hw_supported = 0; |
1972 | *supported = 0; | |
c030f2e4 | 1973 | |
88474cca | 1974 | if (amdgpu_sriov_vf(adev) || !adev->is_atom_fw || |
0ad7a64d JC |
1975 | (adev->asic_type != CHIP_VEGA20 && |
1976 | adev->asic_type != CHIP_ARCTURUS && | |
1977 | adev->asic_type != CHIP_SIENNA_CICHLID)) | |
5caf466a | 1978 | return; |
b404ae82 | 1979 | |
88474cca | 1980 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
6952e99c | 1981 | dev_info(adev->dev, "HBM ECC is active.\n"); |
88474cca GC |
1982 | *hw_supported |= (1 << AMDGPU_RAS_BLOCK__UMC | |
1983 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1984 | } else | |
6952e99c | 1985 | dev_info(adev->dev, "HBM ECC is not presented.\n"); |
88474cca GC |
1986 | |
1987 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { | |
6952e99c | 1988 | dev_info(adev->dev, "SRAM ECC is active.\n"); |
88474cca GC |
1989 | *hw_supported |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
1990 | 1 << AMDGPU_RAS_BLOCK__DF); | |
1991 | } else | |
6952e99c | 1992 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); |
88474cca GC |
1993 | |
1994 | /* hw_supported needs to be aligned with RAS block mask. */ | |
1995 | *hw_supported &= AMDGPU_RAS_BLOCK_MASK; | |
b404ae82 | 1996 | |
5caf466a | 1997 | *supported = amdgpu_ras_enable == 0 ? |
88474cca | 1998 | 0 : *hw_supported & amdgpu_ras_mask; |
c030f2e4 | 1999 | } |
2000 | ||
2001 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
2002 | { | |
2003 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2004 | int r; |
c030f2e4 | 2005 | |
b404ae82 | 2006 | if (con) |
c030f2e4 | 2007 | return 0; |
2008 | ||
2009 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
2010 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
2011 | GFP_KERNEL|__GFP_ZERO); | |
2012 | if (!con) | |
2013 | return -ENOMEM; | |
2014 | ||
2015 | con->objs = (struct ras_manager *)(con + 1); | |
2016 | ||
2017 | amdgpu_ras_set_context(adev, con); | |
2018 | ||
5caf466a | 2019 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
2020 | &con->supported); | |
fb2a3607 | 2021 | if (!con->hw_supported) { |
5e91160a GC |
2022 | r = 0; |
2023 | goto err_out; | |
fb2a3607 HZ |
2024 | } |
2025 | ||
c030f2e4 | 2026 | con->features = 0; |
2027 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2028 | /* Might need get this flag from vbios. */ |
2029 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2030 | |
4e644fff HZ |
2031 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
2032 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
2033 | if (r) | |
5e91160a | 2034 | goto err_out; |
4e644fff HZ |
2035 | } |
2036 | ||
2037 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
2038 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
2039 | if (r) | |
5e91160a | 2040 | goto err_out; |
4e644fff HZ |
2041 | } |
2042 | ||
5e91160a GC |
2043 | if (amdgpu_ras_fs_init(adev)) { |
2044 | r = -EINVAL; | |
2045 | goto err_out; | |
2046 | } | |
c030f2e4 | 2047 | |
6952e99c | 2048 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
5d0f903f | 2049 | "hardware ability[%x] ras_mask[%x]\n", |
2050 | con->hw_supported, con->supported); | |
c030f2e4 | 2051 | return 0; |
5e91160a | 2052 | err_out: |
c030f2e4 | 2053 | amdgpu_ras_set_context(adev, NULL); |
2054 | kfree(con); | |
2055 | ||
5e91160a | 2056 | return r; |
c030f2e4 | 2057 | } |
2058 | ||
b293e891 HZ |
2059 | /* helper function to handle common stuff in ip late init phase */ |
2060 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
2061 | struct ras_common_if *ras_block, | |
2062 | struct ras_fs_if *fs_info, | |
2063 | struct ras_ih_if *ih_info) | |
2064 | { | |
2065 | int r; | |
2066 | ||
2067 | /* disable RAS feature per IP block if it is not supported */ | |
2068 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2069 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2074 | if (r) { | |
2075 | if (r == -EAGAIN) { | |
2076 | /* request gpu reset. will run again */ | |
2077 | amdgpu_ras_request_reset_on_boot(adev, | |
2078 | ras_block->block); | |
2079 | return 0; | |
f1403342 | 2080 | } else if (adev->in_suspend || adev->in_gpu_reset) { |
b293e891 HZ |
2081 | /* in resume phase, if fail to enable ras, |
2082 | * clean up all ras fs nodes, and disable ras */ | |
2083 | goto cleanup; | |
2084 | } else | |
2085 | return r; | |
2086 | } | |
2087 | ||
2088 | /* in resume phase, no need to create ras fs node */ | |
f1403342 | 2089 | if (adev->in_suspend || adev->in_gpu_reset) |
b293e891 HZ |
2090 | return 0; |
2091 | ||
2092 | if (ih_info->cb) { | |
2093 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
2094 | if (r) | |
2095 | goto interrupt; | |
2096 | } | |
2097 | ||
b293e891 HZ |
2098 | r = amdgpu_ras_sysfs_create(adev, fs_info); |
2099 | if (r) | |
2100 | goto sysfs; | |
2101 | ||
2102 | return 0; | |
2103 | cleanup: | |
2104 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
2105 | sysfs: | |
b293e891 HZ |
2106 | if (ih_info->cb) |
2107 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2108 | interrupt: | |
2109 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2110 | return r; | |
2111 | } | |
2112 | ||
2113 | /* helper function to remove ras fs node and interrupt handler */ | |
2114 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
2115 | struct ras_common_if *ras_block, | |
2116 | struct ras_ih_if *ih_info) | |
2117 | { | |
2118 | if (!ras_block || !ih_info) | |
2119 | return; | |
2120 | ||
2121 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
b293e891 HZ |
2122 | if (ih_info->cb) |
2123 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
2124 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
2125 | } | |
2126 | ||
a564808e | 2127 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2128 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2129 | */ |
511fdbc3 | 2130 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2131 | { |
2132 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2133 | struct ras_manager *obj, *tmp; | |
2134 | ||
2135 | if (!con) | |
2136 | return; | |
2137 | ||
108c6a63 | 2138 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2139 | /* Set up all other IPs which are not implemented. There is a |
2140 | * tricky thing that IP's actual ras error type should be | |
2141 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2142 | * ERROR_NONE make sense anyway. | |
2143 | */ | |
2144 | amdgpu_ras_enable_all_features(adev, 1); | |
2145 | ||
2146 | /* We enable ras on all hw_supported block, but as boot | |
2147 | * parameter might disable some of them and one or more IP has | |
2148 | * not implemented yet. So we disable them on behalf. | |
2149 | */ | |
108c6a63 | 2150 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2151 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2152 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2153 | /* there should be no any reference. */ | |
2154 | WARN_ON(alive_obj(obj)); | |
2155 | } | |
191051a1 | 2156 | } |
108c6a63 | 2157 | } |
a564808e | 2158 | |
2159 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
2160 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
2161 | /* setup ras obj state as disabled. | |
2162 | * for init_by_vbios case. | |
2163 | * if we want to enable ras, just enable it in a normal way. | |
2164 | * If we want do disable it, need setup ras obj as enabled, | |
2165 | * then issue another TA disable cmd. | |
2166 | * See feature_enable_on_boot | |
2167 | */ | |
2168 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 2169 | amdgpu_ras_reset_gpu(adev); |
a564808e | 2170 | } |
108c6a63 | 2171 | } |
2172 | ||
511fdbc3 | 2173 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2174 | { | |
2175 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2176 | ||
2177 | if (!con) | |
2178 | return; | |
2179 | ||
2180 | amdgpu_ras_disable_all_features(adev, 0); | |
2181 | /* Make sure all ras objects are disabled. */ | |
2182 | if (con->features) | |
2183 | amdgpu_ras_disable_all_features(adev, 1); | |
2184 | } | |
2185 | ||
c030f2e4 | 2186 | /* do some fini work before IP fini as dependence */ |
2187 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2188 | { | |
2189 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2190 | ||
2191 | if (!con) | |
2192 | return 0; | |
2193 | ||
2194 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
2195 | amdgpu_ras_disable_all_features(adev, 0); | |
2196 | amdgpu_ras_recovery_fini(adev); | |
2197 | return 0; | |
2198 | } | |
2199 | ||
2200 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2201 | { | |
2202 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2203 | ||
2204 | if (!con) | |
2205 | return 0; | |
2206 | ||
2207 | amdgpu_ras_fs_fini(adev); | |
2208 | amdgpu_ras_interrupt_remove_all(adev); | |
2209 | ||
2210 | WARN(con->features, "Feature mask is not cleared"); | |
2211 | ||
2212 | if (con->features) | |
2213 | amdgpu_ras_disable_all_features(adev, 1); | |
2214 | ||
2215 | amdgpu_ras_set_context(adev, NULL); | |
2216 | kfree(con); | |
2217 | ||
2218 | return 0; | |
2219 | } | |
7c6e68c7 AG |
2220 | |
2221 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2222 | { | |
ed606f8a AG |
2223 | uint32_t hw_supported, supported; |
2224 | ||
2225 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
2226 | if (!hw_supported) | |
2227 | return; | |
2228 | ||
7c6e68c7 | 2229 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
6952e99c GC |
2230 | dev_info(adev->dev, "uncorrectable hardware error" |
2231 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2232 | |
61934624 | 2233 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2234 | } |
2235 | } | |
bb5c7235 WS |
2236 | |
2237 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2238 | { | |
2239 | if (adev->asic_type == CHIP_VEGA20 && | |
2240 | adev->pm.fw_version <= 0x283400) { | |
2241 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
2242 | amdgpu_ras_intr_triggered(); | |
2243 | } | |
2244 | ||
2245 | return false; | |
2246 | } | |
e8fbaf03 GC |
2247 | |
2248 | bool amdgpu_ras_check_err_threshold(struct amdgpu_device *adev) | |
2249 | { | |
2250 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2251 | bool exc_err_limit = false; | |
2252 | ||
2253 | if (con && (amdgpu_bad_page_threshold != 0)) | |
2254 | amdgpu_ras_eeprom_check_err_threshold(&con->eeprom_control, | |
2255 | &exc_err_limit); | |
2256 | ||
2257 | /* | |
2258 | * We are only interested in variable exc_err_limit, | |
2259 | * as it says if GPU is in bad state or not. | |
2260 | */ | |
2261 | return exc_err_limit; | |
2262 | } |