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drm/amdgpu: fix ras supported check
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ras.c
CommitLineData
c030f2e4 1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
f867723b 27#include <linux/uaccess.h>
7c6e68c7
AG		 28#include <linux/reboot.h>
29#include <linux/syscalls.h>
05adfd80 30#include <linux/pm_runtime.h>
f867723b 31
c030f2e4 32#include "amdgpu.h"
33#include "amdgpu_ras.h"
b404ae82 34#include "amdgpu_atomfirmware.h"
19744f5f 35#include "amdgpu_xgmi.h"
4e644fff 36#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
f50160cf 37#include "atom.h"
12b2cab7
MJ		 38#ifdef CONFIG_X86_MCE_AMD
39#include <asm/mce.h>
c030f2e4 40
12b2cab7
MJ		 41static bool notifier_registered;
42#endif
eb0c3cd4
GC		 43static const char *RAS_FS_NAME = "ras";
44
c030f2e4 45const char *ras_error_string[] = {
46 "none",
47 "parity",
48 "single_correctable",
49 "multi_uncorrectable",
50 "poison",
51};
52
53const char *ras_block_string[] = {
54 "umc",
55 "sdma",
56 "gfx",
57 "mmhub",
58 "athub",
59 "pcie_bif",
60 "hdp",
61 "xgmi_wafl",
62 "df",
63 "smn",
64 "sem",
65 "mp0",
66 "mp1",
67 "fuse",
640ae42e 68 "mca",
a3d63c62
MZZ		 69 "vcn",
70 "jpeg",
c030f2e4 71};
72
640ae42e
JC		 73const char *ras_mca_block_string[] = {
74 "mca_mp0",
75 "mca_mp1",
76 "mca_mpio",
77 "mca_iohc",
78};
79
d5e8ff5f 80struct amdgpu_ras_block_list {
81 /* ras block link */
82 struct list_head node;
83
84 struct amdgpu_ras_block_object *ras_obj;
85};
86
640ae42e
JC		 87const char *get_ras_block_str(struct ras_common_if *ras_block)
88{
89 if (!ras_block)
90 return "NULL";
91
92 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT)
93 return "OUT OF RANGE";
94
95 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
96 return ras_mca_block_string[ras_block->sub_block_index];
97
98 return ras_block_string[ras_block->block];
99}
100
954ea6aa 101#define ras_block_str(_BLOCK_) \
102 (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range")
8b0fb0e9 103
c030f2e4 104#define ras_err_str(i) (ras_error_string[ffs(i)])
c030f2e4 105
108c6a63 106#define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS)
107
7cdc2ee3
TZ		 108/* inject address is 52 bits */
109#define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52)
110
e4e6a589
LT		 111/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
112#define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL)
c84d4670 113
52dd95f2
GC		 114enum amdgpu_ras_retire_page_reservation {
115 AMDGPU_RAS_RETIRE_PAGE_RESERVED,
116 AMDGPU_RAS_RETIRE_PAGE_PENDING,
117 AMDGPU_RAS_RETIRE_PAGE_FAULT,
118};
7c6e68c7
AG		 119
120atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0);
121
676deb38
DL		 122static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
123 uint64_t addr);
6e4be987
TZ		 124static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
125 uint64_t addr);
12b2cab7 126#ifdef CONFIG_X86_MCE_AMD
91a1a52d
MJ		 127static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
128struct mce_notifier_adev_list {
129 struct amdgpu_device *devs[MAX_GPU_INSTANCE];
130 int num_gpu;
131};
132static struct mce_notifier_adev_list mce_adev_list;
12b2cab7 133#endif
6e4be987 134
61380faa
JC		 135void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
136{
a9d82d2f 137 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 138 amdgpu_ras_get_context(adev)->error_query_ready = ready;
139}
140
f3167919 141static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
61380faa 142{
a9d82d2f 143 if (adev && amdgpu_ras_get_context(adev))
61380faa
JC		 144 return amdgpu_ras_get_context(adev)->error_query_ready;
145
146 return false;
147}
148
cbb8f989
JC		 149static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
150{
151 struct ras_err_data err_data = {0, 0, 0, NULL};
152 struct eeprom_table_record err_rec;
153
154 if ((address >= adev->gmc.mc_vram_size) ||
155 (address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
156 dev_warn(adev->dev,
157 "RAS WARN: input address 0x%llx is invalid.\n",
158 address);
159 return -EINVAL;
160 }
161
162 if (amdgpu_ras_check_bad_page(adev, address)) {
163 dev_warn(adev->dev,
80b0cd0f 164 "RAS WARN: 0x%llx has already been marked as bad page!\n",
cbb8f989
JC		 165 address);
166 return 0;
167 }
168
169 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
cbb8f989 170 err_data.err_addr = &err_rec;
400013b2
TZ		 171 amdgpu_umc_fill_error_record(&err_data, address,
172 (address >> AMDGPU_GPU_PAGE_SHIFT), 0, 0);
cbb8f989
JC		 173
174 if (amdgpu_bad_page_threshold != 0) {
175 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
176 err_data.err_addr_cnt);
177 amdgpu_ras_save_bad_pages(adev);
178 }
179
180 dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n");
181 dev_warn(adev->dev, "Clear EEPROM:\n");
182 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n");
183
184 return 0;
185}
186
c030f2e4 187static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
188 size_t size, loff_t *pos)
189{
190 struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
191 struct ras_query_if info = {
192 .head = obj->head,
193 };
194 ssize_t s;
195 char val[128];
196
761d86d3 197 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 198 return -EINVAL;
199
200 s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
201 "ue", info.ue_count,
202 "ce", info.ce_count);
203 if (*pos >= s)
204 return 0;
205
206 s -= *pos;
207 s = min_t(u64, s, size);
208
209
210 if (copy_to_user(buf, &val[*pos], s))
211 return -EINVAL;
212
213 *pos += s;
214
215 return s;
216}
217
c030f2e4 218static const struct file_operations amdgpu_ras_debugfs_ops = {
219 .owner = THIS_MODULE,
220 .read = amdgpu_ras_debugfs_read,
190211ab 221 .write = NULL,
c030f2e4 222 .llseek = default_llseek
223};
224
96ebb307 225static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
226{
227 int i;
228
229 for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
230 *block_id = i;
640ae42e 231 if (strcmp(name, ras_block_string[i]) == 0)
96ebb307 232 return 0;
233 }
234 return -EINVAL;
235}
236
237static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
238 const char __user *buf, size_t size,
239 loff_t *pos, struct ras_debug_if *data)
240{
241 ssize_t s = min_t(u64, 64, size);
242 char str[65];
243 char block_name[33];
244 char err[9] = "ue";
245 int op = -1;
246 int block_id;
44494f96 247 uint32_t sub_block;
96ebb307 248 u64 address, value;
249
250 if (*pos)
251 return -EINVAL;
252 *pos = size;
253
254 memset(str, 0, sizeof(str));
255 memset(data, 0, sizeof(*data));
256
257 if (copy_from_user(str, buf, s))
258 return -EINVAL;
259
260 if (sscanf(str, "disable %32s", block_name) == 1)
261 op = 0;
262 else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
263 op = 1;
264 else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
265 op = 2;
6df23f4c 266 else if (strstr(str, "retire_page") != NULL)
cbb8f989 267 op = 3;
b076296b 268 else if (str[0] && str[1] && str[2] && str[3])
96ebb307 269 /* ascii string, but commands are not matched. */
270 return -EINVAL;
271
272 if (op != -1) {
cbb8f989 273 if (op == 3) {
546aa546
LT		 274 if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
275 sscanf(str, "%*s %llu", &address) != 1)
6cb7a1d4 276 return -EINVAL;
cbb8f989
JC		 277
278 data->op = op;
279 data->inject.address = address;
280
281 return 0;
282 }
283
96ebb307 284 if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
285 return -EINVAL;
286
287 data->head.block = block_id;
e1063493
TZ		 288 /* only ue and ce errors are supported */
289 if (!memcmp("ue", err, 2))
290 data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
291 else if (!memcmp("ce", err, 2))
292 data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
293 else
294 return -EINVAL;
295
96ebb307 296 data->op = op;
297
298 if (op == 2) {
546aa546
LT		 299 if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
300 &sub_block, &address, &value) != 3 &&
301 sscanf(str, "%*s %*s %*s %u %llu %llu",
6cb7a1d4
LT		 302 &sub_block, &address, &value) != 3)
303 return -EINVAL;
44494f96 304 data->head.sub_block_index = sub_block;
96ebb307 305 data->inject.address = address;
306 data->inject.value = value;
307 }
308 } else {
73aa8e1a 309 if (size < sizeof(*data))
96ebb307 310 return -EINVAL;
311
312 if (copy_from_user(data, buf, sizeof(*data)))
313 return -EINVAL;
314 }
315
316 return 0;
317}
7c6e68c7 318
74abc221
TSD		 319/**
320 * DOC: AMDGPU RAS debugfs control interface
36ea1bd2 321 *
737c375b 322 * The control interface accepts struct ras_debug_if which has two members.
36ea1bd2 323 *
324 * First member: ras_debug_if::head or ras_debug_if::inject.
96ebb307 325 *
326 * head is used to indicate which IP block will be under control.
36ea1bd2 327 *
328 * head has four members, they are block, type, sub_block_index, name.
329 * block: which IP will be under control.
330 * type: what kind of error will be enabled/disabled/injected.
331 * sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
332 * name: the name of IP.
333 *
334 * inject has two more members than head, they are address, value.
335 * As their names indicate, inject operation will write the
336 * value to the address.
337 *
ef177d11 338 * The second member: struct ras_debug_if::op.
c688a06b 339 * It has three kinds of operations.
879e723d
AZ		 340 *
341 * - 0: disable RAS on the block. Take ::head as its data.
342 * - 1: enable RAS on the block. Take ::head as its data.
343 * - 2: inject errors on the block. Take ::inject as its data.
36ea1bd2 344 *
96ebb307 345 * How to use the interface?
ef177d11 346 *
737c375b 347 * In a program
ef177d11 348 *
737c375b
LT		 349 * Copy the struct ras_debug_if in your code and initialize it.
350 * Write the struct to the control interface.
ef177d11 351 *
737c375b 352 * From shell
96ebb307 353 *
879e723d
AZ		 354 * .. code-block:: bash
355 *
737c375b
LT		 356 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
357 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
358 * echo "inject <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
879e723d 359 *
737c375b 360 * Where N, is the card which you want to affect.
ef177d11 361 *
737c375b
LT		 362 * "disable" requires only the block.
363 * "enable" requires the block and error type.
364 * "inject" requires the block, error type, address, and value.
c666bbf0 365 *
737c375b 366 * The block is one of: umc, sdma, gfx, etc.
879e723d 367 * see ras_block_string[] for details
c666bbf0 368 *
737c375b
LT		 369 * The error type is one of: ue, ce, where,
370 * ue is multi-uncorrectable
371 * ce is single-correctable
c666bbf0 372 *
737c375b
LT		 373 * The sub-block is a the sub-block index, pass 0 if there is no sub-block.
374 * The address and value are hexadecimal numbers, leading 0x is optional.
879e723d 375 *
737c375b 376 * For instance,
879e723d
AZ		 377 *
378 * .. code-block:: bash
96ebb307 379 *
44494f96
TZ		 380 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
381 * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
96ebb307 382 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
383 *
737c375b 384 * How to check the result of the operation?
36ea1bd2 385 *
737c375b 386 * To check disable/enable, see "ras" features at,
36ea1bd2 387 * /sys/class/drm/card[0/1/2...]/device/ras/features
388 *
737c375b
LT		 389 * To check inject, see the corresponding error count at,
390 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
36ea1bd2 391 *
879e723d 392 * .. note::
ef177d11 393 * Operations are only allowed on blocks which are supported.
737c375b 394 * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
ef177d11
AD		 395 * to see which blocks support RAS on a particular asic.
396 *
36ea1bd2 397 */
cf696091
LT		 398static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
399 const char __user *buf,
400 size_t size, loff_t *pos)
36ea1bd2 401{
402 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
403 struct ras_debug_if data;
404 int ret = 0;
405
61380faa 406 if (!amdgpu_ras_get_error_query_ready(adev)) {
6952e99c
GC		 407 dev_warn(adev->dev, "RAS WARN: error injection "
408 "currently inaccessible\n");
43c4d576
JC		 409 return size;
410 }
411
96ebb307 412 ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
413 if (ret)
cf696091 414 return ret;
36ea1bd2 415
80b0cd0f 416 if (data.op == 3) {
cbb8f989 417 ret = amdgpu_reserve_page_direct(adev, data.inject.address);
80b0cd0f 418 if (!ret)
cbb8f989
JC		 419 return size;
420 else
421 return ret;
422 }
423
36ea1bd2 424 if (!amdgpu_ras_is_supported(adev, data.head.block))
425 return -EINVAL;
426
427 switch (data.op) {
428 case 0:
429 ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
430 break;
431 case 1:
432 ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
433 break;
434 case 2:
7cdc2ee3
TZ		 435 if ((data.inject.address >= adev->gmc.mc_vram_size) ||
436 (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) {
b0d4783a
GC		 437 dev_warn(adev->dev, "RAS WARN: input address "
438 "0x%llx is invalid.",
439 data.inject.address);
7cdc2ee3
TZ		 440 ret = -EINVAL;
441 break;
442 }
443
6e4be987
TZ		 444 /* umc ce/ue error injection for a bad page is not allowed */
445 if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
446 amdgpu_ras_check_bad_page(adev, data.inject.address)) {
c65b0805
LT		 447 dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "
448 "already been marked as bad!\n",
449 data.inject.address);
6e4be987
TZ		 450 break;
451 }
452
7cdc2ee3 453 /* data.inject.address is offset instead of absolute gpu address */
36ea1bd2 454 ret = amdgpu_ras_error_inject(adev, &data.inject);
455 break;
96ebb307 456 default:
457 ret = -EINVAL;
458 break;
374bf7bd 459 }
36ea1bd2 460
461 if (ret)
79c04621 462 return ret;
36ea1bd2 463
464 return size;
465}
466
084fe13b
AG		 467/**
468 * DOC: AMDGPU RAS debugfs EEPROM table reset interface
469 *
f77c7109 470 * Some boards contain an EEPROM which is used to persistently store a list of
ef177d11 471 * bad pages which experiences ECC errors in vram. This interface provides
f77c7109
AD		 472 * a way to reset the EEPROM, e.g., after testing error injection.
473 *
474 * Usage:
475 *
476 * .. code-block:: bash
477 *
478 * echo 1 > ../ras/ras_eeprom_reset
479 *
480 * will reset EEPROM table to 0 entries.
481 *
084fe13b 482 */
cf696091
LT		 483static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
484 const char __user *buf,
485 size_t size, loff_t *pos)
084fe13b 486{
bf0b91b7
GC		 487 struct amdgpu_device *adev =
488 (struct amdgpu_device *)file_inode(f)->i_private;
084fe13b
AG		 489 int ret;
490
bf0b91b7 491 ret = amdgpu_ras_eeprom_reset_table(
cf696091 492 &(amdgpu_ras_get_context(adev)->eeprom_control));
084fe13b 493
63d4c081 494 if (!ret) {
cf696091
LT		 495 /* Something was written to EEPROM.
496 */
bf0b91b7
GC		 497 amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS;
498 return size;
499 } else {
cf696091 500 return ret;
bf0b91b7 501 }
084fe13b
AG		 502}
503
36ea1bd2 504static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
505 .owner = THIS_MODULE,
506 .read = NULL,
507 .write = amdgpu_ras_debugfs_ctrl_write,
508 .llseek = default_llseek
509};
510
084fe13b
AG		 511static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
512 .owner = THIS_MODULE,
513 .read = NULL,
514 .write = amdgpu_ras_debugfs_eeprom_write,
515 .llseek = default_llseek
516};
517
f77c7109
AD		 518/**
519 * DOC: AMDGPU RAS sysfs Error Count Interface
520 *
ef177d11 521 * It allows the user to read the error count for each IP block on the gpu through
f77c7109
AD		 522 * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
523 *
524 * It outputs the multiple lines which report the uncorrected (ue) and corrected
525 * (ce) error counts.
526 *
527 * The format of one line is below,
528 *
529 * [ce|ue]: count
530 *
531 * Example:
532 *
533 * .. code-block:: bash
534 *
535 * ue: 0
536 * ce: 1
537 *
538 */
c030f2e4 539static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
540 struct device_attribute *attr, char *buf)
541{
542 struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr);
543 struct ras_query_if info = {
544 .head = obj->head,
545 };
546
61380faa 547 if (!amdgpu_ras_get_error_query_ready(obj->adev))
36000c7a 548 return sysfs_emit(buf, "Query currently inaccessible\n");
43c4d576 549
761d86d3 550 if (amdgpu_ras_query_error_status(obj->adev, &info))
c030f2e4 551 return -EINVAL;
552
1f0d8e37
MJ		 553 if (obj->adev->asic_type == CHIP_ALDEBARAN) {
554 if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
555 DRM_WARN("Failed to reset error counter and error status");
556 }
557
36000c7a
TT		 558 return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
559 "ce", info.ce_count);
c030f2e4 560}
561
562/* obj begin */
563
564#define get_obj(obj) do { (obj)->use++; } while (0)
565#define alive_obj(obj) ((obj)->use)
566
567static inline void put_obj(struct ras_manager *obj)
568{
f0872686 569 if (obj && (--obj->use == 0))
c030f2e4 570 list_del(&obj->node);
f0872686 571 if (obj && (obj->use < 0))
640ae42e 572 DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head));
c030f2e4 573}
574
575/* make one obj and return it. */
576static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
577 struct ras_common_if *head)
578{
579 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
580 struct ras_manager *obj;
581
8ab0d6f0 582 if (!adev->ras_enabled || !con)
c030f2e4 583 return NULL;
584
585 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
586 return NULL;
587
640ae42e
JC		 588 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
589 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
590 return NULL;
591
592 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
593 } else
594 obj = &con->objs[head->block];
595
c030f2e4 596 /* already exist. return obj? */
597 if (alive_obj(obj))
598 return NULL;
599
600 obj->head = *head;
601 obj->adev = adev;
602 list_add(&obj->node, &con->head);
603 get_obj(obj);
604
605 return obj;
606}
607
608/* return an obj equal to head, or the first when head is NULL */
f2a79be1 609struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
c030f2e4 610 struct ras_common_if *head)
611{
612 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
613 struct ras_manager *obj;
614 int i;
615
8ab0d6f0 616 if (!adev->ras_enabled || !con)
c030f2e4 617 return NULL;
618
619 if (head) {
620 if (head->block >= AMDGPU_RAS_BLOCK_COUNT)
621 return NULL;
622
640ae42e
JC		 623 if (head->block == AMDGPU_RAS_BLOCK__MCA) {
624 if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
625 return NULL;
626
627 obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
628 } else
629 obj = &con->objs[head->block];
c030f2e4 630
640ae42e 631 if (alive_obj(obj))
c030f2e4 632 return obj;
c030f2e4 633 } else {
640ae42e 634 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
c030f2e4 635 obj = &con->objs[i];
640ae42e 636 if (alive_obj(obj))
c030f2e4 637 return obj;
c030f2e4 638 }
639 }
640
641 return NULL;
642}
643/* obj end */
644
645/* feature ctl begin */
646static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
e509965e 647 struct ras_common_if *head)
c030f2e4 648{
8ab0d6f0 649 return adev->ras_hw_enabled & BIT(head->block);
c030f2e4 650}
651
652static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
653 struct ras_common_if *head)
654{
655 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
656
657 return con->features & BIT(head->block);
658}
659
660/*
661 * if obj is not created, then create one.
662 * set feature enable flag.
663 */
664static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
665 struct ras_common_if *head, int enable)
666{
667 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
668 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
669
5caf466a 670 /* If hardware does not support ras, then do not create obj.
671 * But if hardware support ras, we can create the obj.
672 * Ras framework checks con->hw_supported to see if it need do
673 * corresponding initialization.
674 * IP checks con->support to see if it need disable ras.
675 */
c030f2e4 676 if (!amdgpu_ras_is_feature_allowed(adev, head))
677 return 0;
c030f2e4 678
679 if (enable) {
680 if (!obj) {
681 obj = amdgpu_ras_create_obj(adev, head);
682 if (!obj)
683 return -EINVAL;
684 } else {
685 /* In case we create obj somewhere else */
686 get_obj(obj);
687 }
688 con->features |= BIT(head->block);
689 } else {
690 if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
19d0dfda 691 con->features &= ~BIT(head->block);
c030f2e4 692 put_obj(obj);
693 }
694 }
695
696 return 0;
697}
698
699/* wrapper of psp_ras_enable_features */
700int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
701 struct ras_common_if *head, bool enable)
702{
703 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
7fcffecf 704 union ta_ras_cmd_input *info;
c030f2e4 705 int ret;
706
707 if (!con)
708 return -EINVAL;
709
f3729f7b 710 info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL);
7fcffecf
AB		 711 if (!info)
712 return -ENOMEM;
713
c030f2e4 714 if (!enable) {
7fcffecf 715 info->disable_features = (struct ta_ras_disable_features_input) {
828cfa29 716 .block_id = amdgpu_ras_block_to_ta(head->block),
717 .error_type = amdgpu_ras_error_to_ta(head->type),
c030f2e4 718 };
719 } else {
7fcffecf 720 info->enable_features = (struct ta_ras_enable_features_input) {
828cfa29 721 .block_id = amdgpu_ras_block_to_ta(head->block),
722 .error_type = amdgpu_ras_error_to_ta(head->type),
c030f2e4 723 };
724 }
725
726 /* Do not enable if it is not allowed. */
727 WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head));
c030f2e4 728
950d6425
SY		 729 /* Only enable ras feature operation handle on host side */
730 if (!amdgpu_sriov_vf(adev) &&
731 !amdgpu_ras_intr_triggered()) {
7fcffecf 732 ret = psp_ras_enable_features(&adev->psp, info, enable);
bff77e86 733 if (ret) {
e4348849 734 dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",
011907fd 735 enable ? "enable":"disable",
640ae42e 736 get_ras_block_str(head),
e4348849 737 amdgpu_ras_is_poison_mode_supported(adev), ret);
7fcffecf 738 goto out;
bff77e86 739 }
c030f2e4 740 }
741
742 /* setup the obj */
743 __amdgpu_ras_feature_enable(adev, head, enable);
7fcffecf
AB		 744 ret = 0;
745out:
746 kfree(info);
747 return ret;
c030f2e4 748}
749
77de502b 750/* Only used in device probe stage and called only once. */
751int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
752 struct ras_common_if *head, bool enable)
753{
754 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
755 int ret;
756
757 if (!con)
758 return -EINVAL;
759
760 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
7af23ebe 761 if (enable) {
762 /* There is no harm to issue a ras TA cmd regardless of
763 * the currecnt ras state.
764 * If current state == target state, it will do nothing
765 * But sometimes it requests driver to reset and repost
766 * with error code -EAGAIN.
767 */
768 ret = amdgpu_ras_feature_enable(adev, head, 1);
769 /* With old ras TA, we might fail to enable ras.
770 * Log it and just setup the object.
771 * TODO need remove this WA in the future.
772 */
773 if (ret == -EINVAL) {
774 ret = __amdgpu_ras_feature_enable(adev, head, 1);
775 if (!ret)
6952e99c
GC		 776 dev_info(adev->dev,
777 "RAS INFO: %s setup object\n",
640ae42e 778 get_ras_block_str(head));
7af23ebe 779 }
780 } else {
781 /* setup the object then issue a ras TA disable cmd.*/
782 ret = __amdgpu_ras_feature_enable(adev, head, 1);
783 if (ret)
784 return ret;
77de502b 785
970fd197
SY		 786 /* gfx block ras dsiable cmd must send to ras-ta */
787 if (head->block == AMDGPU_RAS_BLOCK__GFX)
788 con->features |= BIT(head->block);
789
77de502b 790 ret = amdgpu_ras_feature_enable(adev, head, 0);
19d0dfda
SY		 791
792 /* clean gfx block ras features flag */
8ab0d6f0 793 if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
19d0dfda 794 con->features &= ~BIT(head->block);
7af23ebe 795 }
77de502b 796 } else
797 ret = amdgpu_ras_feature_enable(adev, head, enable);
798
799 return ret;
800}
801
c030f2e4 802static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
803 bool bypass)
804{
805 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
806 struct ras_manager *obj, *tmp;
807
808 list_for_each_entry_safe(obj, tmp, &con->head, node) {
809 /* bypass psp.
810 * aka just release the obj and corresponding flags
811 */
812 if (bypass) {
813 if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
814 break;
815 } else {
816 if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
817 break;
818 }
289d513b 819 }
c030f2e4 820
821 return con->features;
822}
823
824static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
825 bool bypass)
826{
827 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c030f2e4 828 int i;
640ae42e 829 const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;
c030f2e4 830
640ae42e 831 for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) {
c030f2e4 832 struct ras_common_if head = {
833 .block = i,
191051a1 834 .type = default_ras_type,
c030f2e4 835 .sub_block_index = 0,
836 };
640ae42e
JC		 837
838 if (i == AMDGPU_RAS_BLOCK__MCA)
839 continue;
840
841 if (bypass) {
842 /*
843 * bypass psp. vbios enable ras for us.
844 * so just create the obj
845 */
846 if (__amdgpu_ras_feature_enable(adev, &head, 1))
847 break;
848 } else {
849 if (amdgpu_ras_feature_enable(adev, &head, 1))
850 break;
851 }
852 }
853
854 for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) {
855 struct ras_common_if head = {
856 .block = AMDGPU_RAS_BLOCK__MCA,
857 .type = default_ras_type,
858 .sub_block_index = i,
859 };
860
c030f2e4 861 if (bypass) {
862 /*
863 * bypass psp. vbios enable ras for us.
864 * so just create the obj
865 */
866 if (__amdgpu_ras_feature_enable(adev, &head, 1))
867 break;
868 } else {
869 if (amdgpu_ras_feature_enable(adev, &head, 1))
870 break;
871 }
289d513b 872 }
c030f2e4 873
874 return con->features;
875}
876/* feature ctl end */
877
e3d833f4 878static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
879 enum amdgpu_ras_block block)
6492e1b0 880{
b6efdb02 881 if (!block_obj)
6492e1b0 882 return -EINVAL;
883
bdb3489c 884 if (block_obj->ras_comm.block == block)
6492e1b0 885 return 0;
640ae42e 886
6492e1b0 887 return -EINVAL;
888}
889
b6efdb02 890static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
6492e1b0 891 enum amdgpu_ras_block block, uint32_t sub_block_index)
640ae42e 892{
d5e8ff5f 893 struct amdgpu_ras_block_list *node, *tmp;
894 struct amdgpu_ras_block_object *obj;
6492e1b0 895
896 if (block >= AMDGPU_RAS_BLOCK__LAST)
897 return NULL;
898
899 if (!amdgpu_ras_is_supported(adev, block))
900 return NULL;
901
d5e8ff5f 902 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
903 if (!node->ras_obj) {
904 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
905 continue;
906 }
907
908 obj = node->ras_obj;
6492e1b0 909 if (obj->ras_block_match) {
910 if (obj->ras_block_match(obj, block, sub_block_index) == 0)
911 return obj;
912 } else {
913 if (amdgpu_ras_block_match_default(obj, block) == 0)
914 return obj;
915 }
640ae42e 916 }
6492e1b0 917
918 return NULL;
640ae42e
JC		 919}
920
fdcb279d
SY		 921static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
922{
923 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
924 int ret = 0;
925
926 /*
927 * choosing right query method according to
928 * whether smu support query error information
929 */
bc143d8b 930 ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
fdcb279d 931 if (ret == -EOPNOTSUPP) {
efe17d5a 932 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
933 adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
934 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
fdcb279d
SY		 935
936 /* umc query_ras_error_address is also responsible for clearing
937 * error status
938 */
efe17d5a 939 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
940 adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
941 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
fdcb279d 942 } else if (!ret) {
efe17d5a 943 if (adev->umc.ras &&
944 adev->umc.ras->ecc_info_query_ras_error_count)
945 adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);
fdcb279d 946
efe17d5a 947 if (adev->umc.ras &&
948 adev->umc.ras->ecc_info_query_ras_error_address)
949 adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
fdcb279d
SY		 950 }
951}
952
c030f2e4 953/* query/inject/cure begin */
761d86d3 954int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
4d9f771e 955 struct ras_query_if *info)
c030f2e4 956{
b6efdb02 957 struct amdgpu_ras_block_object *block_obj = NULL;
c030f2e4 958 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
6f102dba 959 struct ras_err_data err_data = {0, 0, 0, NULL};
c030f2e4 960
961 if (!obj)
962 return -EINVAL;
c030f2e4 963
7389a5b8 964 if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
fdcb279d 965 amdgpu_ras_get_ecc_info(adev, &err_data);
7389a5b8 966 } else {
967 block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
8b0fb0e9 968 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 969 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
970 get_ras_block_str(&info->head));
8b0fb0e9 971 return -EINVAL;
3e81ee9a 972 }
761d86d3 973
6c245386 974 if (block_obj->hw_ops->query_ras_error_count)
975 block_obj->hw_ops->query_ras_error_count(adev, &err_data);
7389a5b8 976
977 if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
978 (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
979 (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
980 if (block_obj->hw_ops->query_ras_error_status)
981 block_obj->hw_ops->query_ras_error_status(adev);
982 }
939e2258 983 }
05a58345
TZ		 984
985 obj->err_data.ue_count += err_data.ue_count;
986 obj->err_data.ce_count += err_data.ce_count;
987
c030f2e4 988 info->ue_count = obj->err_data.ue_count;
989 info->ce_count = obj->err_data.ce_count;
990
7c6e68c7 991 if (err_data.ce_count) {
a30f1286
HZ		 992 if (adev->smuio.funcs &&
993 adev->smuio.funcs->get_socket_id &&
994 adev->smuio.funcs->get_die_id) {
995 dev_info(adev->dev, "socket: %d, die: %d "
996 "%ld correctable hardware errors "
6952e99c
GC		 997 "detected in %s block, no user "
998 "action is needed.\n",
a30f1286
HZ		 999 adev->smuio.funcs->get_socket_id(adev),
1000 adev->smuio.funcs->get_die_id(adev),
6952e99c 1001 obj->err_data.ce_count,
640ae42e 1002 get_ras_block_str(&info->head));
a30f1286
HZ		 1003 } else {
1004 dev_info(adev->dev, "%ld correctable hardware errors "
6952e99c
GC		 1005 "detected in %s block, no user "
1006 "action is needed.\n",
1007 obj->err_data.ce_count,
640ae42e 1008 get_ras_block_str(&info->head));
a30f1286 1009 }
7c6e68c7
AG		 1010 }
1011 if (err_data.ue_count) {
a30f1286
HZ		 1012 if (adev->smuio.funcs &&
1013 adev->smuio.funcs->get_socket_id &&
1014 adev->smuio.funcs->get_die_id) {
1015 dev_info(adev->dev, "socket: %d, die: %d "
1016 "%ld uncorrectable hardware errors "
6952e99c 1017 "detected in %s block\n",
a30f1286
HZ		 1018 adev->smuio.funcs->get_socket_id(adev),
1019 adev->smuio.funcs->get_die_id(adev),
6952e99c 1020 obj->err_data.ue_count,
640ae42e 1021 get_ras_block_str(&info->head));
a30f1286
HZ		 1022 } else {
1023 dev_info(adev->dev, "%ld uncorrectable hardware errors "
6952e99c
GC		 1024 "detected in %s block\n",
1025 obj->err_data.ue_count,
640ae42e 1026 get_ras_block_str(&info->head));
a30f1286 1027 }
7c6e68c7 1028 }
05a58345 1029
eb601e61
JC		 1030 if (!amdgpu_persistent_edc_harvesting_supported(adev))
1031 amdgpu_ras_reset_error_status(adev, info->head.block);
1032
c030f2e4 1033 return 0;
1034}
1035
761d86d3
DL		 1036int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
1037 enum amdgpu_ras_block block)
1038{
b6efdb02 1039 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);
8b0fb0e9 1040
761d86d3
DL		 1041 if (!amdgpu_ras_is_supported(adev, block))
1042 return -EINVAL;
1043
7389a5b8 1044 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1045 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1046 ras_block_str(block));
7389a5b8 1047 return -EINVAL;
761d86d3
DL		 1048 }
1049
7389a5b8 1050 if (block_obj->hw_ops->reset_ras_error_count)
1051 block_obj->hw_ops->reset_ras_error_count(adev);
5c23e9e0 1052
7389a5b8 1053 if ((block == AMDGPU_RAS_BLOCK__GFX) ||
1054 (block == AMDGPU_RAS_BLOCK__MMHUB)) {
8b0fb0e9 1055 if (block_obj->hw_ops->reset_ras_error_status)
1056 block_obj->hw_ops->reset_ras_error_status(adev);
761d86d3 1057 }
5c23e9e0 1058
761d86d3 1059 return 0;
5c23e9e0
JC		 1060}
1061
c030f2e4 1062/* wrapper of psp_ras_trigger_error */
1063int amdgpu_ras_error_inject(struct amdgpu_device *adev,
1064 struct ras_inject_if *info)
1065{
1066 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1067 struct ta_ras_trigger_error_input block_info = {
828cfa29 1068 .block_id = amdgpu_ras_block_to_ta(info->head.block),
1069 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
c030f2e4 1070 .sub_block_index = info->head.sub_block_index,
1071 .address = info->address,
1072 .value = info->value,
1073 };
ab3b9de6
YL		 1074 int ret = -EINVAL;
1075 struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
1076 info->head.block,
1077 info->head.sub_block_index);
c030f2e4 1078
1079 if (!obj)
1080 return -EINVAL;
1081
22d4ba53 1082 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1083 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1084 get_ras_block_str(&info->head));
22d4ba53 1085 return -EINVAL;
1086 }
1087
a6c44d25
JC		 1088 /* Calculate XGMI relative offset */
1089 if (adev->gmc.xgmi.num_physical_nodes > 1) {
19744f5f
HZ		 1090 block_info.address =
1091 amdgpu_xgmi_get_relative_phy_addr(adev,
1092 block_info.address);
a6c44d25
JC		 1093 }
1094
22d4ba53 1095 if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
8b0fb0e9 1096 if (block_obj->hw_ops->ras_error_inject)
1097 ret = block_obj->hw_ops->ras_error_inject(adev, info);
22d4ba53 1098 } else {
1099 /* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
1100 if (block_obj->hw_ops->ras_error_inject)
1101 ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
1102 else /*If not defined .ras_error_inject, use default ras_error_inject*/
1103 ret = psp_ras_trigger_error(&adev->psp, &block_info);
a5dd40ca
HZ		 1104 }
1105
011907fd
DL		 1106 if (ret)
1107 dev_err(adev->dev, "ras inject %s failed %d\n",
640ae42e 1108 get_ras_block_str(&info->head), ret);
c030f2e4 1109
1110 return ret;
1111}
1112
4d9f771e
LT		 1113/**
1114 * amdgpu_ras_query_error_count -- Get error counts of all IPs
bbe04dec
IB		 1115 * @adev: pointer to AMD GPU device
1116 * @ce_count: pointer to an integer to be set to the count of correctible errors.
1117 * @ue_count: pointer to an integer to be set to the count of uncorrectible
4d9f771e
LT		 1118 * errors.
1119 *
1120 * If set, @ce_count or @ue_count, count and return the corresponding
1121 * error counts in those integer pointers. Return 0 if the device
1122 * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
1123 */
1124int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
1125 unsigned long *ce_count,
1126 unsigned long *ue_count)
c030f2e4 1127{
1128 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1129 struct ras_manager *obj;
a46751fb 1130 unsigned long ce, ue;
c030f2e4 1131
8ab0d6f0 1132 if (!adev->ras_enabled || !con)
4d9f771e
LT		 1133 return -EOPNOTSUPP;
1134
1135 /* Don't count since no reporting.
1136 */
1137 if (!ce_count && !ue_count)
1138 return 0;
c030f2e4 1139
a46751fb
LT		 1140 ce = 0;
1141 ue = 0;
c030f2e4 1142 list_for_each_entry(obj, &con->head, node) {
1143 struct ras_query_if info = {
1144 .head = obj->head,
1145 };
4d9f771e 1146 int res;
c030f2e4 1147
4d9f771e
LT		 1148 res = amdgpu_ras_query_error_status(adev, &info);
1149 if (res)
1150 return res;
c030f2e4 1151
a46751fb
LT		 1152 ce += info.ce_count;
1153 ue += info.ue_count;
c030f2e4 1154 }
1155
a46751fb
LT		 1156 if (ce_count)
1157 *ce_count = ce;
1158
1159 if (ue_count)
1160 *ue_count = ue;
4d9f771e
LT		 1161
1162 return 0;
c030f2e4 1163}
1164/* query/inject/cure end */
1165
1166
1167/* sysfs begin */
1168
466b1793 1169static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1170 struct ras_badpage **bps, unsigned int *count);
1171
1172static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1173{
1174 switch (flags) {
52dd95f2 1175 case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
466b1793 1176 return "R";
52dd95f2 1177 case AMDGPU_RAS_RETIRE_PAGE_PENDING:
466b1793 1178 return "P";
52dd95f2 1179 case AMDGPU_RAS_RETIRE_PAGE_FAULT:
466b1793 1180 default:
1181 return "F";
aec576f9 1182 }
466b1793 1183}
1184
f77c7109
AD		 1185/**
1186 * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
466b1793 1187 *
1188 * It allows user to read the bad pages of vram on the gpu through
1189 * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
1190 *
1191 * It outputs multiple lines, and each line stands for one gpu page.
1192 *
1193 * The format of one line is below,
1194 * gpu pfn : gpu page size : flags
1195 *
1196 * gpu pfn and gpu page size are printed in hex format.
1197 * flags can be one of below character,
f77c7109 1198 *
466b1793 1199 * R: reserved, this gpu page is reserved and not able to use.
f77c7109 1200 *
466b1793 1201 * P: pending for reserve, this gpu page is marked as bad, will be reserved
f77c7109
AD		 1202 * in next window of page_reserve.
1203 *
466b1793 1204 * F: unable to reserve. this gpu page can't be reserved due to some reasons.
1205 *
f77c7109
AD		 1206 * Examples:
1207 *
1208 * .. code-block:: bash
1209 *
1210 * 0x00000001 : 0x00001000 : R
1211 * 0x00000002 : 0x00001000 : P
1212 *
466b1793 1213 */
1214
1215static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
1216 struct kobject *kobj, struct bin_attribute *attr,
1217 char *buf, loff_t ppos, size_t count)
1218{
1219 struct amdgpu_ras *con =
1220 container_of(attr, struct amdgpu_ras, badpages_attr);
1221 struct amdgpu_device *adev = con->adev;
1222 const unsigned int element_size =
1223 sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
d6ee400e
SA		 1224 unsigned int start = div64_ul(ppos + element_size - 1, element_size);
1225 unsigned int end = div64_ul(ppos + count - 1, element_size);
466b1793 1226 ssize_t s = 0;
1227 struct ras_badpage *bps = NULL;
1228 unsigned int bps_count = 0;
1229
1230 memset(buf, 0, count);
1231
1232 if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
1233 return 0;
1234
1235 for (; start < end && start < bps_count; start++)
1236 s += scnprintf(&buf[s], element_size + 1,
1237 "0x%08x : 0x%08x : %1s\n",
1238 bps[start].bp,
1239 bps[start].size,
1240 amdgpu_ras_badpage_flags_str(bps[start].flags));
1241
1242 kfree(bps);
1243
1244 return s;
1245}
1246
c030f2e4 1247static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
1248 struct device_attribute *attr, char *buf)
1249{
1250 struct amdgpu_ras *con =
1251 container_of(attr, struct amdgpu_ras, features_attr);
c030f2e4 1252
5212a3bd 1253 return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features);
c030f2e4 1254}
1255
f848159b
GC		 1256static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1257{
1258 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1259
1260 sysfs_remove_file_from_group(&adev->dev->kobj,
1261 &con->badpages_attr.attr,
1262 RAS_FS_NAME);
1263}
1264
c030f2e4 1265static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1266{
1267 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1268 struct attribute *attrs[] = {
1269 &con->features_attr.attr,
1270 NULL
1271 };
1272 struct attribute_group group = {
eb0c3cd4 1273 .name = RAS_FS_NAME,
c030f2e4 1274 .attrs = attrs,
1275 };
1276
1277 sysfs_remove_group(&adev->dev->kobj, &group);
1278
1279 return 0;
1280}
1281
1282int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
9252d33d 1283 struct ras_common_if *head)
c030f2e4 1284{
9252d33d 1285 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1286
1287 if (!obj || obj->attr_inuse)
1288 return -EINVAL;
1289
1290 get_obj(obj);
1291
9252d33d 1292 snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
1293 "%s_err_count", head->name);
c030f2e4 1294
1295 obj->sysfs_attr = (struct device_attribute){
1296 .attr = {
1297 .name = obj->fs_data.sysfs_name,
1298 .mode = S_IRUGO,
1299 },
1300 .show = amdgpu_ras_sysfs_read,
1301 };
163def43 1302 sysfs_attr_init(&obj->sysfs_attr.attr);
c030f2e4 1303
1304 if (sysfs_add_file_to_group(&adev->dev->kobj,
1305 &obj->sysfs_attr.attr,
eb0c3cd4 1306 RAS_FS_NAME)) {
c030f2e4 1307 put_obj(obj);
1308 return -EINVAL;
1309 }
1310
1311 obj->attr_inuse = 1;
1312
1313 return 0;
1314}
1315
1316int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
1317 struct ras_common_if *head)
1318{
1319 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
1320
1321 if (!obj || !obj->attr_inuse)
1322 return -EINVAL;
1323
1324 sysfs_remove_file_from_group(&adev->dev->kobj,
1325 &obj->sysfs_attr.attr,
eb0c3cd4 1326 RAS_FS_NAME);
c030f2e4 1327 obj->attr_inuse = 0;
1328 put_obj(obj);
1329
1330 return 0;
1331}
1332
1333static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1334{
1335 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1336 struct ras_manager *obj, *tmp;
1337
1338 list_for_each_entry_safe(obj, tmp, &con->head, node) {
1339 amdgpu_ras_sysfs_remove(adev, &obj->head);
1340 }
1341
f848159b
GC		 1342 if (amdgpu_bad_page_threshold != 0)
1343 amdgpu_ras_sysfs_remove_bad_page_node(adev);
1344
c030f2e4 1345 amdgpu_ras_sysfs_remove_feature_node(adev);
1346
1347 return 0;
1348}
1349/* sysfs end */
1350
ef177d11
AD		 1351/**
1352 * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
1353 *
1354 * Normally when there is an uncorrectable error, the driver will reset
1355 * the GPU to recover. However, in the event of an unrecoverable error,
1356 * the driver provides an interface to reboot the system automatically
1357 * in that event.
1358 *
1359 * The following file in debugfs provides that interface:
1360 * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
1361 *
1362 * Usage:
1363 *
1364 * .. code-block:: bash
1365 *
1366 * echo true > .../ras/auto_reboot
1367 *
1368 */
c030f2e4 1369/* debugfs begin */
ea1b8c9b 1370static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
36ea1bd2 1371{
1372 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
ef0d7d20
LT		 1373 struct drm_minor *minor = adev_to_drm(adev)->primary;
1374 struct dentry *dir;
36ea1bd2 1375
88293c03
ND		 1376 dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root);
1377 debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,
1378 &amdgpu_ras_debugfs_ctrl_ops);
1379 debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,
1380 &amdgpu_ras_debugfs_eeprom_ops);
7fb64071
LT		 1381 debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
1382 &con->bad_page_cnt_threshold);
ef0d7d20
LT		 1383 debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
1384 debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
c65b0805
LT		 1385 debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,
1386 &amdgpu_ras_debugfs_eeprom_size_ops);
1387 con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",
1388 S_IRUGO, dir, adev,
1389 &amdgpu_ras_debugfs_eeprom_table_ops);
1390 amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);
c688a06b
GC		 1391
1392 /*
1393 * After one uncorrectable error happens, usually GPU recovery will
1394 * be scheduled. But due to the known problem in GPU recovery failing
1395 * to bring GPU back, below interface provides one direct way to
1396 * user to reboot system automatically in such case within
1397 * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
1398 * will never be called.
1399 */
88293c03 1400 debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);
66459e1d
GC		 1401
1402 /*
1403 * User could set this not to clean up hardware's error count register
1404 * of RAS IPs during ras recovery.
1405 */
88293c03
ND		 1406 debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
1407 &con->disable_ras_err_cnt_harvest);
1408 return dir;
36ea1bd2 1409}
1410
cedf7884 1411static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
88293c03
ND		 1412 struct ras_fs_if *head,
1413 struct dentry *dir)
c030f2e4 1414{
c030f2e4 1415 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);
c030f2e4 1416
88293c03 1417 if (!obj || !dir)
450f30ea 1418 return;
c030f2e4 1419
1420 get_obj(obj);
1421
1422 memcpy(obj->fs_data.debugfs_name,
1423 head->debugfs_name,
1424 sizeof(obj->fs_data.debugfs_name));
1425
88293c03
ND		 1426 debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,
1427 obj, &amdgpu_ras_debugfs_ops);
c030f2e4 1428}
1429
f9317014
TZ		 1430void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1431{
1432 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
88293c03 1433 struct dentry *dir;
c1509f3f 1434 struct ras_manager *obj;
f9317014
TZ		 1435 struct ras_fs_if fs_info;
1436
1437 /*
1438 * it won't be called in resume path, no need to check
1439 * suspend and gpu reset status
1440 */
cedf7884 1441 if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con)
f9317014
TZ		 1442 return;
1443
88293c03 1444 dir = amdgpu_ras_debugfs_create_ctrl_node(adev);
f9317014 1445
c1509f3f 1446 list_for_each_entry(obj, &con->head, node) {
f9317014
TZ		 1447 if (amdgpu_ras_is_supported(adev, obj->head.block) &&
1448 (obj->attr_inuse == 1)) {
1449 sprintf(fs_info.debugfs_name, "%s_err_inject",
640ae42e 1450 get_ras_block_str(&obj->head));
f9317014 1451 fs_info.head = obj->head;
88293c03 1452 amdgpu_ras_debugfs_create(adev, &fs_info, dir);
f9317014
TZ		 1453 }
1454 }
1455}
1456
c030f2e4 1457/* debugfs end */
1458
1459/* ras fs */
c3d4d45d
GC		 1460static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
1461 amdgpu_ras_sysfs_badpages_read, NULL, 0);
1462static DEVICE_ATTR(features, S_IRUGO,
1463 amdgpu_ras_sysfs_features_read, NULL);
c030f2e4 1464static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1465{
c3d4d45d
GC		 1466 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1467 struct attribute_group group = {
1468 .name = RAS_FS_NAME,
1469 };
1470 struct attribute *attrs[] = {
1471 &con->features_attr.attr,
1472 NULL
1473 };
1474 struct bin_attribute *bin_attrs[] = {
1475 NULL,
1476 NULL,
1477 };
a069a9eb 1478 int r;
c030f2e4 1479
c3d4d45d
GC		 1480 /* add features entry */
1481 con->features_attr = dev_attr_features;
1482 group.attrs = attrs;
1483 sysfs_attr_init(attrs[0]);
1484
1485 if (amdgpu_bad_page_threshold != 0) {
1486 /* add bad_page_features entry */
1487 bin_attr_gpu_vram_bad_pages.private = NULL;
1488 con->badpages_attr = bin_attr_gpu_vram_bad_pages;
1489 bin_attrs[0] = &con->badpages_attr;
1490 group.bin_attrs = bin_attrs;
1491 sysfs_bin_attr_init(bin_attrs[0]);
1492 }
1493
a069a9eb
AD		 1494 r = sysfs_create_group(&adev->dev->kobj, &group);
1495 if (r)
1496 dev_err(adev->dev, "Failed to create RAS sysfs group!");
f848159b 1497
c030f2e4 1498 return 0;
1499}
1500
1501static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1502{
88293c03
ND		 1503 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1504 struct ras_manager *con_obj, *ip_obj, *tmp;
1505
1506 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1507 list_for_each_entry_safe(con_obj, tmp, &con->head, node) {
1508 ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
1509 if (ip_obj)
1510 put_obj(ip_obj);
1511 }
1512 }
1513
c030f2e4 1514 amdgpu_ras_sysfs_remove_all(adev);
1515 return 0;
1516}
1517/* ras fs end */
1518
1519/* ih begin */
b3c76814
TZ		 1520
1521/* For the hardware that cannot enable bif ring for both ras_controller_irq
1522 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
1523 * register to check whether the interrupt is triggered or not, and properly
1524 * ack the interrupt if it is there
1525 */
1526void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1527{
950d6425
SY		 1528 /* Fatal error events are handled on host side */
1529 if (amdgpu_sriov_vf(adev) ||
1530 !amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF))
b3c76814
TZ		 1531 return;
1532
1533 if (adev->nbio.ras &&
1534 adev->nbio.ras->handle_ras_controller_intr_no_bifring)
1535 adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);
1536
1537 if (adev->nbio.ras &&
1538 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
1539 adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1540}
1541
66f87949
TZ		 1542static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
1543 struct amdgpu_iv_entry *entry)
1544{
b63ac5d3 1545 bool poison_stat = false;
66f87949
TZ		 1546 struct amdgpu_device *adev = obj->adev;
1547 struct ras_err_data err_data = {0, 0, 0, NULL};
1548 struct amdgpu_ras_block_object *block_obj =
1549 amdgpu_ras_get_ras_block(adev, obj->head.block, 0);
1550
b63ac5d3
TZ		 1551 if (!block_obj || !block_obj->hw_ops)
1552 return;
66f87949 1553
b63ac5d3
TZ		 1554 /* both query_poison_status and handle_poison_consumption are optional,
1555 * but at least one of them should be implemented if we need poison
1556 * consumption handler
1557 */
1558 if (block_obj->hw_ops->query_poison_status) {
1559 poison_stat = block_obj->hw_ops->query_poison_status(adev);
1560 if (!poison_stat) {
1561 /* Not poison consumption interrupt, no need to handle it */
1562 dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",
1563 block_obj->ras_comm.name);
1564
1565 return;
66f87949
TZ		 1566 }
1567 }
1568
b63ac5d3
TZ		 1569 if (!adev->gmc.xgmi.connected_to_cpu)
1570 amdgpu_umc_poison_handler(adev, &err_data, false);
1571
1572 if (block_obj->hw_ops->handle_poison_consumption)
1573 poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);
1574
1575 /* gpu reset is fallback for failed and default cases */
1576 if (poison_stat) {
1577 dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",
1578 block_obj->ras_comm.name);
66f87949 1579 amdgpu_ras_reset_gpu(adev);
b63ac5d3 1580 }
66f87949
TZ		 1581}
1582
50a7d025
TZ		 1583static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
1584 struct amdgpu_iv_entry *entry)
1585{
1586 dev_info(obj->adev->dev,
1587 "Poison is created, no user action is needed.\n");
1588}
1589
1590static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
1591 struct amdgpu_iv_entry *entry)
1592{
1593 struct ras_ih_data *data = &obj->ih_data;
1594 struct ras_err_data err_data = {0, 0, 0, NULL};
1595 int ret;
1596
1597 if (!data->cb)
1598 return;
1599
1600 /* Let IP handle its data, maybe we need get the output
1601 * from the callback to update the error type/count, etc
1602 */
1603 ret = data->cb(obj->adev, &err_data, entry);
1604 /* ue will trigger an interrupt, and in that case
1605 * we need do a reset to recovery the whole system.
1606 * But leave IP do that recovery, here we just dispatch
1607 * the error.
1608 */
1609 if (ret == AMDGPU_RAS_SUCCESS) {
1610 /* these counts could be left as 0 if
1611 * some blocks do not count error number
1612 */
1613 obj->err_data.ue_count += err_data.ue_count;
1614 obj->err_data.ce_count += err_data.ce_count;
1615 }
1616}
1617
c030f2e4 1618static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1619{
1620 struct ras_ih_data *data = &obj->ih_data;
1621 struct amdgpu_iv_entry entry;
c030f2e4 1622
1623 while (data->rptr != data->wptr) {
1624 rmb();
1625 memcpy(&entry, &data->ring[data->rptr],
1626 data->element_size);
1627
1628 wmb();
1629 data->rptr = (data->aligned_element_size +
1630 data->rptr) % data->ring_size;
1631
50a7d025
TZ		 1632 if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
1633 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1634 amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
66f87949
TZ		 1635 else
1636 amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
50a7d025
TZ		 1637 } else {
1638 if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
1639 amdgpu_ras_interrupt_umc_handler(obj, &entry);
1640 else
1641 dev_warn(obj->adev->dev,
1642 "No RAS interrupt handler for non-UMC block with poison disabled.\n");
c030f2e4 1643 }
1644 }
1645}
1646
1647static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1648{
1649 struct ras_ih_data *data =
1650 container_of(work, struct ras_ih_data, ih_work);
1651 struct ras_manager *obj =
1652 container_of(data, struct ras_manager, ih_data);
1653
1654 amdgpu_ras_interrupt_handler(obj);
1655}
1656
1657int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
1658 struct ras_dispatch_if *info)
1659{
1660 struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
1661 struct ras_ih_data *data = &obj->ih_data;
1662
1663 if (!obj)
1664 return -EINVAL;
1665
1666 if (data->inuse == 0)
1667 return 0;
1668
1669 /* Might be overflow... */
1670 memcpy(&data->ring[data->wptr], info->entry,
1671 data->element_size);
1672
1673 wmb();
1674 data->wptr = (data->aligned_element_size +
1675 data->wptr) % data->ring_size;
1676
1677 schedule_work(&data->ih_work);
1678
1679 return 0;
1680}
1681
1682int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
9252d33d 1683 struct ras_common_if *head)
c030f2e4 1684{
9252d33d 1685 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1686 struct ras_ih_data *data;
1687
1688 if (!obj)
1689 return -EINVAL;
1690
1691 data = &obj->ih_data;
1692 if (data->inuse == 0)
1693 return 0;
1694
1695 cancel_work_sync(&data->ih_work);
1696
1697 kfree(data->ring);
1698 memset(data, 0, sizeof(*data));
1699 put_obj(obj);
1700
1701 return 0;
1702}
1703
1704int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
9252d33d 1705 struct ras_common_if *head)
c030f2e4 1706{
9252d33d 1707 struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
c030f2e4 1708 struct ras_ih_data *data;
9252d33d 1709 struct amdgpu_ras_block_object *ras_obj;
c030f2e4 1710
1711 if (!obj) {
1712 /* in case we registe the IH before enable ras feature */
9252d33d 1713 obj = amdgpu_ras_create_obj(adev, head);
c030f2e4 1714 if (!obj)
1715 return -EINVAL;
1716 } else
1717 get_obj(obj);
1718
9252d33d 1719 ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm);
1720
c030f2e4 1721 data = &obj->ih_data;
1722 /* add the callback.etc */
1723 *data = (struct ras_ih_data) {
1724 .inuse = 0,
9252d33d 1725 .cb = ras_obj->ras_cb,
c030f2e4 1726 .element_size = sizeof(struct amdgpu_iv_entry),
1727 .rptr = 0,
1728 .wptr = 0,
1729 };
1730
1731 INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);
1732
1733 data->aligned_element_size = ALIGN(data->element_size, 8);
1734 /* the ring can store 64 iv entries. */
1735 data->ring_size = 64 * data->aligned_element_size;
1736 data->ring = kmalloc(data->ring_size, GFP_KERNEL);
1737 if (!data->ring) {
1738 put_obj(obj);
1739 return -ENOMEM;
1740 }
1741
1742 /* IH is ready */
1743 data->inuse = 1;
1744
1745 return 0;
1746}
1747
1748static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1749{
1750 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1751 struct ras_manager *obj, *tmp;
1752
1753 list_for_each_entry_safe(obj, tmp, &con->head, node) {
9252d33d 1754 amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
c030f2e4 1755 }
1756
1757 return 0;
1758}
1759/* ih end */
1760
313c8fd3
GC		 1761/* traversal all IPs except NBIO to query error counter */
1762static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1763{
1764 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1765 struct ras_manager *obj;
1766
8ab0d6f0 1767 if (!adev->ras_enabled || !con)
313c8fd3
GC		 1768 return;
1769
1770 list_for_each_entry(obj, &con->head, node) {
1771 struct ras_query_if info = {
1772 .head = obj->head,
1773 };
1774
1775 /*
1776 * PCIE_BIF IP has one different isr by ras controller
1777 * interrupt, the specific ras counter query will be
1778 * done in that isr. So skip such block from common
1779 * sync flood interrupt isr calling.
1780 */
1781 if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
1782 continue;
1783
cf63b702
SY		 1784 /*
1785 * this is a workaround for aldebaran, skip send msg to
1786 * smu to get ecc_info table due to smu handle get ecc
1787 * info table failed temporarily.
1788 * should be removed until smu fix handle ecc_info table.
1789 */
1790 if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
1791 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)))
1792 continue;
1793
761d86d3 1794 amdgpu_ras_query_error_status(adev, &info);
313c8fd3
GC		 1795 }
1796}
1797
3f975d0f 1798/* Parse RdRspStatus and WrRspStatus */
cd92df93
LJ		 1799static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
1800 struct ras_query_if *info)
3f975d0f 1801{
8eb53bb2 1802 struct amdgpu_ras_block_object *block_obj;
3f975d0f
SY		 1803 /*
1804 * Only two block need to query read/write
1805 * RspStatus at current state
1806 */
5e67bba3 1807 if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
1808 (info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
b6efdb02 1809 return;
1810
1811 block_obj = amdgpu_ras_get_ras_block(adev,
1812 info->head.block,
1813 info->head.sub_block_index);
5e67bba3 1814
5e67bba3 1815 if (!block_obj || !block_obj->hw_ops) {
afa37315
LT		 1816 dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",
1817 get_ras_block_str(&info->head));
b6efdb02 1818 return;
3f975d0f 1819 }
5e67bba3 1820
1821 if (block_obj->hw_ops->query_ras_error_status)
ab3b9de6 1822 block_obj->hw_ops->query_ras_error_status(adev);
5e67bba3 1823
3f975d0f
SY		 1824}
1825
1826static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1827{
1828 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1829 struct ras_manager *obj;
1830
8ab0d6f0 1831 if (!adev->ras_enabled || !con)
3f975d0f
SY		 1832 return;
1833
1834 list_for_each_entry(obj, &con->head, node) {
1835 struct ras_query_if info = {
1836 .head = obj->head,
1837 };
1838
1839 amdgpu_ras_error_status_query(adev, &info);
1840 }
1841}
1842
c030f2e4 1843/* recovery begin */
466b1793 1844
1845/* return 0 on success.
1846 * caller need free bps.
1847 */
1848static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
1849 struct ras_badpage **bps, unsigned int *count)
1850{
1851 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1852 struct ras_err_handler_data *data;
1853 int i = 0;
732f2a30 1854 int ret = 0, status;
466b1793 1855
1856 if (!con || !con->eh_data || !bps || !count)
1857 return -EINVAL;
1858
1859 mutex_lock(&con->recovery_lock);
1860 data = con->eh_data;
1861 if (!data || data->count == 0) {
1862 *bps = NULL;
46cf2fec 1863 ret = -EINVAL;
466b1793 1864 goto out;
1865 }
1866
1867 *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL);
1868 if (!*bps) {
1869 ret = -ENOMEM;
1870 goto out;
1871 }
1872
1873 for (; i < data->count; i++) {
1874 (*bps)[i] = (struct ras_badpage){
9dc23a63 1875 .bp = data->bps[i].retired_page,
466b1793 1876 .size = AMDGPU_GPU_PAGE_SIZE,
52dd95f2 1877 .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
466b1793 1878 };
ec6aae97 1879 status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
676deb38 1880 data->bps[i].retired_page);
732f2a30 1881 if (status == -EBUSY)
52dd95f2 1882 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
732f2a30 1883 else if (status == -ENOENT)
52dd95f2 1884 (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
466b1793 1885 }
1886
1887 *count = data->count;
1888out:
1889 mutex_unlock(&con->recovery_lock);
1890 return ret;
1891}
1892
c030f2e4 1893static void amdgpu_ras_do_recovery(struct work_struct *work)
1894{
1895 struct amdgpu_ras *ras =
1896 container_of(work, struct amdgpu_ras, recovery_work);
b3dbd6d3
JC		 1897 struct amdgpu_device *remote_adev = NULL;
1898 struct amdgpu_device *adev = ras->adev;
1899 struct list_head device_list, *device_list_handle = NULL;
b3dbd6d3 1900
f75e94d8 1901 if (!ras->disable_ras_err_cnt_harvest) {
d95e8e97
DL		 1902 struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
1903
f75e94d8
GC		 1904 /* Build list of devices to query RAS related errors */
1905 if (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
1906 device_list_handle = &hive->device_list;
1907 } else {
1908 INIT_LIST_HEAD(&device_list);
1909 list_add_tail(&adev->gmc.xgmi.head, &device_list);
1910 device_list_handle = &device_list;
1911 }
c030f2e4 1912
f75e94d8 1913 list_for_each_entry(remote_adev,
3f975d0f
SY		 1914 device_list_handle, gmc.xgmi.head) {
1915 amdgpu_ras_query_err_status(remote_adev);
f75e94d8 1916 amdgpu_ras_log_on_err_counter(remote_adev);
3f975d0f 1917 }
d95e8e97
DL		 1918
1919 amdgpu_put_xgmi_hive(hive);
b3dbd6d3 1920 }
313c8fd3 1921
93af20f7 1922 if (amdgpu_device_should_recover_gpu(ras->adev))
2f530724 1923 amdgpu_device_gpu_recover(ras->adev, NULL);
c030f2e4 1924 atomic_set(&ras->in_recovery, 0);
1925}
1926
c030f2e4 1927/* alloc/realloc bps array */
1928static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
1929 struct ras_err_handler_data *data, int pages)
1930{
1931 unsigned int old_space = data->count + data->space_left;
1932 unsigned int new_space = old_space + pages;
9dc23a63
TZ		 1933 unsigned int align_space = ALIGN(new_space, 512);
1934 void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL);
9dc23a63 1935
676deb38 1936 if (!bps) {
c030f2e4 1937 return -ENOMEM;
9dc23a63 1938 }
c030f2e4 1939
1940 if (data->bps) {
9dc23a63 1941 memcpy(bps, data->bps,
c030f2e4 1942 data->count * sizeof(*data->bps));
1943 kfree(data->bps);
1944 }
1945
9dc23a63 1946 data->bps = bps;
c030f2e4 1947 data->space_left += align_space - old_space;
1948 return 0;
1949}
1950
1951/* it deal with vram only. */
1952int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
9dc23a63 1953 struct eeprom_table_record *bps, int pages)
c030f2e4 1954{
1955 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
73aa8e1a 1956 struct ras_err_handler_data *data;
c030f2e4 1957 int ret = 0;
676deb38 1958 uint32_t i;
c030f2e4 1959
73aa8e1a 1960 if (!con || !con->eh_data || !bps || pages <= 0)
c030f2e4 1961 return 0;
1962
1963 mutex_lock(&con->recovery_lock);
73aa8e1a 1964 data = con->eh_data;
c030f2e4 1965 if (!data)
1966 goto out;
1967
676deb38
DL		 1968 for (i = 0; i < pages; i++) {
1969 if (amdgpu_ras_check_bad_page_unlock(con,
1970 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT))
1971 continue;
1972
1973 if (!data->space_left &&
1974 amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
c030f2e4 1975 ret = -ENOMEM;
1976 goto out;
1977 }
1978
ec6aae97 1979 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
676deb38
DL		 1980 bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT,
1981 AMDGPU_GPU_PAGE_SIZE);
9dc23a63 1982
676deb38
DL		 1983 memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps));
1984 data->count++;
1985 data->space_left--;
1986 }
c030f2e4 1987out:
1988 mutex_unlock(&con->recovery_lock);
1989
1990 return ret;
1991}
1992
78ad00c9
TZ		 1993/*
1994 * write error record array to eeprom, the function should be
1995 * protected by recovery_lock
1996 */
22503d80 1997int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
78ad00c9
TZ		 1998{
1999 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2000 struct ras_err_handler_data *data;
8a3e801f 2001 struct amdgpu_ras_eeprom_control *control;
78ad00c9
TZ		 2002 int save_count;
2003
2004 if (!con || !con->eh_data)
2005 return 0;
2006
d9a69fe5 2007 mutex_lock(&con->recovery_lock);
8a3e801f 2008 control = &con->eeprom_control;
78ad00c9 2009 data = con->eh_data;
0686627b 2010 save_count = data->count - control->ras_num_recs;
d9a69fe5 2011 mutex_unlock(&con->recovery_lock);
78ad00c9 2012 /* only new entries are saved */
b1628425 2013 if (save_count > 0) {
63d4c081
LT		 2014 if (amdgpu_ras_eeprom_append(control,
2015 &data->bps[control->ras_num_recs],
2016 save_count)) {
6952e99c 2017 dev_err(adev->dev, "Failed to save EEPROM table data!");
78ad00c9
TZ		 2018 return -EIO;
2019 }
2020
b1628425
GC		 2021 dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count);
2022 }
2023
78ad00c9
TZ		 2024 return 0;
2025}
2026
2027/*
2028 * read error record array in eeprom and reserve enough space for
2029 * storing new bad pages
2030 */
2031static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2032{
2033 struct amdgpu_ras_eeprom_control *control =
6457205c 2034 &adev->psp.ras_context.ras->eeprom_control;
e4e6a589
LT		 2035 struct eeprom_table_record *bps;
2036 int ret;
78ad00c9
TZ		 2037
2038 /* no bad page record, skip eeprom access */
0686627b 2039 if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
e4e6a589 2040 return 0;
78ad00c9 2041
0686627b 2042 bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL);
78ad00c9
TZ		 2043 if (!bps)
2044 return -ENOMEM;
2045
0686627b 2046 ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
e4e6a589 2047 if (ret)
6952e99c 2048 dev_err(adev->dev, "Failed to load EEPROM table records!");
e4e6a589 2049 else
0686627b 2050 ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);
78ad00c9 2051
78ad00c9
TZ		 2052 kfree(bps);
2053 return ret;
2054}
2055
676deb38
DL		 2056static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
2057 uint64_t addr)
2058{
2059 struct ras_err_handler_data *data = con->eh_data;
2060 int i;
2061
2062 addr >>= AMDGPU_GPU_PAGE_SHIFT;
2063 for (i = 0; i < data->count; i++)
2064 if (addr == data->bps[i].retired_page)
2065 return true;
2066
2067 return false;
2068}
2069
6e4be987
TZ		 2070/*
2071 * check if an address belongs to bad page
2072 *
2073 * Note: this check is only for umc block
2074 */
2075static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
2076 uint64_t addr)
2077{
2078 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
6e4be987
TZ		 2079 bool ret = false;
2080
2081 if (!con || !con->eh_data)
2082 return ret;
2083
2084 mutex_lock(&con->recovery_lock);
676deb38 2085 ret = amdgpu_ras_check_bad_page_unlock(con, addr);
6e4be987
TZ		 2086 mutex_unlock(&con->recovery_lock);
2087 return ret;
2088}
2089
e5c04edf 2090static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
e4e6a589 2091 uint32_t max_count)
c84d4670 2092{
e5c04edf 2093 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
c84d4670
GC		 2094
2095 /*
2096 * Justification of value bad_page_cnt_threshold in ras structure
2097 *
2098 * Generally, -1 <= amdgpu_bad_page_threshold <= max record length
2099 * in eeprom, and introduce two scenarios accordingly.
2100 *
2101 * Bad page retirement enablement:
2102 * - If amdgpu_bad_page_threshold = -1,
2103 * bad_page_cnt_threshold = typical value by formula.
2104 *
2105 * - When the value from user is 0 < amdgpu_bad_page_threshold <
2106 * max record length in eeprom, use it directly.
2107 *
2108 * Bad page retirement disablement:
2109 * - If amdgpu_bad_page_threshold = 0, bad page retirement
2110 * functionality is disabled, and bad_page_cnt_threshold will
2111 * take no effect.
2112 */
2113
e4e6a589
LT		 2114 if (amdgpu_bad_page_threshold < 0) {
2115 u64 val = adev->gmc.mc_vram_size;
c84d4670 2116
e4e6a589 2117 do_div(val, RAS_BAD_PAGE_COVER);
e5c04edf 2118 con->bad_page_cnt_threshold = min(lower_32_bits(val),
e4e6a589 2119 max_count);
e5c04edf 2120 } else {
e4e6a589
LT		 2121 con->bad_page_cnt_threshold = min_t(int, max_count,
2122 amdgpu_bad_page_threshold);
c84d4670
GC		 2123 }
2124}
2125
1a6fc071 2126int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
c030f2e4 2127{
2128 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4d1337d2 2129 struct ras_err_handler_data **data;
e4e6a589 2130 u32 max_eeprom_records_count = 0;
b82e65a9 2131 bool exc_err_limit = false;
78ad00c9 2132 int ret;
c030f2e4 2133
1d9d2ca8
LT		 2134 if (!con)
2135 return 0;
2136
2137 /* Allow access to RAS EEPROM via debugfs, when the ASIC
2138 * supports RAS and debugfs is enabled, but when
2139 * adev->ras_enabled is unset, i.e. when "ras_enable"
2140 * module parameter is set to 0.
2141 */
2142 con->adev = adev;
2143
2144 if (!adev->ras_enabled)
4d1337d2
AG		 2145 return 0;
2146
1d9d2ca8 2147 data = &con->eh_data;
1a6fc071
TZ		 2148 *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO);
2149 if (!*data) {
2150 ret = -ENOMEM;
2151 goto out;
2152 }
c030f2e4 2153
2154 mutex_init(&con->recovery_lock);
2155 INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
2156 atomic_set(&con->in_recovery, 0);
69691c82 2157 con->eeprom_control.bad_channel_bitmap = 0;
c030f2e4 2158
e4e6a589
LT		 2159 max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
2160 amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);
c84d4670 2161
e5086659 2162 /* Todo: During test the SMU might fail to read the eeprom through I2C
2163 * when the GPU is pending on XGMI reset during probe time
2164 * (Mostly after second bus reset), skip it now
2165 */
2166 if (adev->gmc.xgmi.pending_reset)
2167 return 0;
b82e65a9
GC		 2168 ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
2169 /*
2170 * This calling fails when exc_err_limit is true or
2171 * ret != 0.
2172 */
2173 if (exc_err_limit || ret)
1a6fc071 2174 goto free;
78ad00c9 2175
0686627b 2176 if (con->eeprom_control.ras_num_recs) {
78ad00c9
TZ		 2177 ret = amdgpu_ras_load_bad_pages(adev);
2178 if (ret)
1a6fc071 2179 goto free;
513befa6 2180
bc143d8b 2181 amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);
69691c82
SY		 2182
2183 if (con->update_channel_flag == true) {
2184 amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
2185 con->update_channel_flag = false;
2186 }
78ad00c9 2187 }
c030f2e4 2188
12b2cab7
MJ		 2189#ifdef CONFIG_X86_MCE_AMD
2190 if ((adev->asic_type == CHIP_ALDEBARAN) &&
2191 (adev->gmc.xgmi.connected_to_cpu))
91a1a52d 2192 amdgpu_register_bad_pages_mca_notifier(adev);
12b2cab7 2193#endif
c030f2e4 2194 return 0;
1a6fc071 2195
1a6fc071 2196free:
1a6fc071 2197 kfree((*data)->bps);
1a6fc071 2198 kfree(*data);
1995b3a3 2199 con->eh_data = NULL;
1a6fc071 2200out:
cf696091 2201 dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret);
1a6fc071 2202
b82e65a9
GC		 2203 /*
2204 * Except error threshold exceeding case, other failure cases in this
2205 * function would not fail amdgpu driver init.
2206 */
2207 if (!exc_err_limit)
2208 ret = 0;
2209 else
2210 ret = -EINVAL;
2211
1a6fc071 2212 return ret;
c030f2e4 2213}
2214
2215static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2216{
2217 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2218 struct ras_err_handler_data *data = con->eh_data;
2219
1a6fc071
TZ		 2220 /* recovery_init failed to init it, fini is useless */
2221 if (!data)
2222 return 0;
2223
c030f2e4 2224 cancel_work_sync(&con->recovery_work);
c030f2e4 2225
2226 mutex_lock(&con->recovery_lock);
2227 con->eh_data = NULL;
2228 kfree(data->bps);
2229 kfree(data);
2230 mutex_unlock(&con->recovery_lock);
2231
2232 return 0;
2233}
2234/* recovery end */
2235
084e2640 2236static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
5436ab94 2237{
084e2640
LT		 2238 return adev->asic_type == CHIP_VEGA10 ||
2239 adev->asic_type == CHIP_VEGA20 ||
2240 adev->asic_type == CHIP_ARCTURUS ||
75f06251 2241 adev->asic_type == CHIP_ALDEBARAN ||
084e2640 2242 adev->asic_type == CHIP_SIENNA_CICHLID;
5436ab94
SY		 2243}
2244
f50160cf
SY		 2245/*
2246 * this is workaround for vega20 workstation sku,
2247 * force enable gfx ras, ignore vbios gfx ras flag
2248 * due to GC EDC can not write
2249 */
e509965e 2250static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
f50160cf
SY		 2251{
2252 struct atom_context *ctx = adev->mode_info.atom_context;
2253
2254 if (!ctx)
2255 return;
2256
2257 if (strnstr(ctx->vbios_version, "D16406",
e11d5e0d
SY		 2258 sizeof(ctx->vbios_version)) ||
2259 strnstr(ctx->vbios_version, "D36002",
2260 sizeof(ctx->vbios_version)))
8ab0d6f0 2261 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
f50160cf
SY		 2262}
2263
5caf466a 2264/*
2265 * check hardware's ras ability which will be saved in hw_supported.
2266 * if hardware does not support ras, we can skip some ras initializtion and
2267 * forbid some ras operations from IP.
2268 * if software itself, say boot parameter, limit the ras ability. We still
2269 * need allow IP do some limited operations, like disable. In such case,
2270 * we have to initialize ras as normal. but need check if operation is
2271 * allowed or not in each function.
2272 */
e509965e 2273static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
c030f2e4 2274{
8ab0d6f0 2275 adev->ras_hw_enabled = adev->ras_enabled = 0;
c030f2e4 2276
950d6425 2277 if (!adev->is_atom_fw ||
084e2640 2278 !amdgpu_ras_asic_supported(adev))
5caf466a 2279 return;
b404ae82 2280
28caf8c4
SY		 2281 /* If driver run on sriov guest side, only enable ras for aldebaran */
2282 if (amdgpu_sriov_vf(adev) &&
2283 adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 2))
950d6425
SY		 2284 return;
2285
75f06251
HZ		 2286 if (!adev->gmc.xgmi.connected_to_cpu) {
2287 if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
2288 dev_info(adev->dev, "MEM ECC is active.\n");
8ab0d6f0 2289 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
e509965e 2290 1 << AMDGPU_RAS_BLOCK__DF);
75f06251
HZ		 2291 } else {
2292 dev_info(adev->dev, "MEM ECC is not presented.\n");
2293 }
88474cca 2294
75f06251
HZ		 2295 if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
2296 dev_info(adev->dev, "SRAM ECC is active.\n");
950d6425
SY		 2297 if (!amdgpu_sriov_vf(adev)) {
2298 adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
2299 1 << AMDGPU_RAS_BLOCK__DF);
2300
2301 if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0))
2302 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
2303 1 << AMDGPU_RAS_BLOCK__JPEG);
2304 else
2305 adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
2306 1 << AMDGPU_RAS_BLOCK__JPEG);
2307 } else {
2308 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
2309 1 << AMDGPU_RAS_BLOCK__SDMA |
2310 1 << AMDGPU_RAS_BLOCK__GFX);
2311 }
75f06251
HZ		 2312 } else {
2313 dev_info(adev->dev, "SRAM ECC is not presented.\n");
2314 }
2315 } else {
2316 /* driver only manages a few IP blocks RAS feature
2317 * when GPU is connected cpu through XGMI */
8ab0d6f0 2318 adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
e509965e
LT		 2319 1 << AMDGPU_RAS_BLOCK__SDMA |
2320 1 << AMDGPU_RAS_BLOCK__MMHUB);
75f06251 2321 }
88474cca 2322
e509965e 2323 amdgpu_ras_get_quirks(adev);
f50160cf 2324
88474cca 2325 /* hw_supported needs to be aligned with RAS block mask. */
8ab0d6f0 2326 adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK;
b404ae82 2327
8ab0d6f0
LT		 2328 adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
2329 adev->ras_hw_enabled & amdgpu_ras_mask;
c030f2e4 2330}
2331
05adfd80
LT		 2332static void amdgpu_ras_counte_dw(struct work_struct *work)
2333{
2334 struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,
2335 ras_counte_delay_work.work);
2336 struct amdgpu_device *adev = con->adev;
a3fbb0d8 2337 struct drm_device *dev = adev_to_drm(adev);
05adfd80
LT		 2338 unsigned long ce_count, ue_count;
2339 int res;
2340
2341 res = pm_runtime_get_sync(dev->dev);
2342 if (res < 0)
2343 goto Out;
2344
2345 /* Cache new values.
2346 */
4d9f771e
LT		 2347 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2348 atomic_set(&con->ras_ce_count, ce_count);
2349 atomic_set(&con->ras_ue_count, ue_count);
2350 }
05adfd80
LT		 2351
2352 pm_runtime_mark_last_busy(dev->dev);
2353Out:
2354 pm_runtime_put_autosuspend(dev->dev);
2355}
2356
c030f2e4 2357int amdgpu_ras_init(struct amdgpu_device *adev)
2358{
2359 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
4e644fff 2360 int r;
e4348849 2361 bool df_poison, umc_poison;
c030f2e4 2362
b404ae82 2363 if (con)
c030f2e4 2364 return 0;
2365
2366 con = kmalloc(sizeof(struct amdgpu_ras) +
640ae42e
JC		 2367 sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT +
2368 sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT,
c030f2e4 2369 GFP_KERNEL|__GFP_ZERO);
2370 if (!con)
2371 return -ENOMEM;
2372
05adfd80
LT		 2373 con->adev = adev;
2374 INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
2375 atomic_set(&con->ras_ce_count, 0);
2376 atomic_set(&con->ras_ue_count, 0);
2377
c030f2e4 2378 con->objs = (struct ras_manager *)(con + 1);
2379
2380 amdgpu_ras_set_context(adev, con);
2381
e509965e
LT		 2382 amdgpu_ras_check_supported(adev);
2383
7ddd9770 2384 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
970fd197
SY		 2385 /* set gfx block ras context feature for VEGA20 Gaming
2386 * send ras disable cmd to ras ta during ras late init.
2387 */
8ab0d6f0 2388 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
970fd197
SY		 2389 con->features |= BIT(AMDGPU_RAS_BLOCK__GFX);
2390
2391 return 0;
2392 }
2393
5e91160a 2394 r = 0;
5436ab94 2395 goto release_con;
fb2a3607
HZ		 2396 }
2397
69691c82 2398 con->update_channel_flag = false;
c030f2e4 2399 con->features = 0;
2400 INIT_LIST_HEAD(&con->head);
108c6a63 2401 /* Might need get this flag from vbios. */
2402 con->flags = RAS_DEFAULT_FLAGS;
c030f2e4 2403
6e36f231
HZ		 2404 /* initialize nbio ras function ahead of any other
2405 * ras functions so hardware fatal error interrupt
2406 * can be enabled as early as possible */
2407 switch (adev->asic_type) {
2408 case CHIP_VEGA20:
2409 case CHIP_ARCTURUS:
2410 case CHIP_ALDEBARAN:
2e54fe5d 2411 if (!adev->gmc.xgmi.connected_to_cpu) {
2412 adev->nbio.ras = &nbio_v7_4_ras;
2413 amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
80ed77f9 2414 adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
2e54fe5d 2415 }
6e36f231
HZ		 2416 break;
2417 default:
2418 /* nbio ras is not available */
2419 break;
2420 }
2421
2e54fe5d 2422 if (adev->nbio.ras &&
2423 adev->nbio.ras->init_ras_controller_interrupt) {
2424 r = adev->nbio.ras->init_ras_controller_interrupt(adev);
4e644fff 2425 if (r)
5436ab94 2426 goto release_con;
4e644fff
HZ		 2427 }
2428
2e54fe5d 2429 if (adev->nbio.ras &&
2430 adev->nbio.ras->init_ras_err_event_athub_interrupt) {
2431 r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
4e644fff 2432 if (r)
5436ab94 2433 goto release_con;
4e644fff
HZ		 2434 }
2435
e4348849 2436 /* Init poison supported flag, the default value is false */
655ff353
TZ		 2437 if (adev->gmc.xgmi.connected_to_cpu) {
2438 /* enabled by default when GPU is connected to CPU */
2439 con->poison_supported = true;
2440 }
2441 else if (adev->df.funcs &&
e4348849 2442 adev->df.funcs->query_ras_poison_mode &&
efe17d5a 2443 adev->umc.ras &&
2444 adev->umc.ras->query_ras_poison_mode) {
e4348849
TZ		 2445 df_poison =
2446 adev->df.funcs->query_ras_poison_mode(adev);
2447 umc_poison =
efe17d5a 2448 adev->umc.ras->query_ras_poison_mode(adev);
e4348849
TZ		 2449 /* Only poison is set in both DF and UMC, we can support it */
2450 if (df_poison && umc_poison)
2451 con->poison_supported = true;
2452 else if (df_poison != umc_poison)
2453 dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",
2454 df_poison, umc_poison);
2455 }
2456
5e91160a
GC		 2457 if (amdgpu_ras_fs_init(adev)) {
2458 r = -EINVAL;
5436ab94 2459 goto release_con;
5e91160a 2460 }
c030f2e4 2461
6952e99c 2462 dev_info(adev->dev, "RAS INFO: ras initialized successfully, "
e509965e 2463 "hardware ability[%x] ras_mask[%x]\n",
8ab0d6f0 2464 adev->ras_hw_enabled, adev->ras_enabled);
e509965e 2465
c030f2e4 2466 return 0;
5436ab94 2467release_con:
c030f2e4 2468 amdgpu_ras_set_context(adev, NULL);
2469 kfree(con);
2470
5e91160a 2471 return r;
c030f2e4 2472}
2473
8f6368a9 2474int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
134d16d5
JC		 2475{
2476 if (adev->gmc.xgmi.connected_to_cpu)
2477 return 1;
2478 return 0;
2479}
2480
2481static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
2482 struct ras_common_if *ras_block)
2483{
2484 struct ras_query_if info = {
2485 .head = *ras_block,
2486 };
2487
2488 if (!amdgpu_persistent_edc_harvesting_supported(adev))
2489 return 0;
2490
2491 if (amdgpu_ras_query_error_status(adev, &info) != 0)
2492 DRM_WARN("RAS init harvest failure");
2493
2494 if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
2495 DRM_WARN("RAS init harvest reset failure");
2496
2497 return 0;
2498}
2499
e4348849
TZ		 2500bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2501{
2502 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2503
2504 if (!con)
2505 return false;
2506
2507 return con->poison_supported;
2508}
2509
b293e891 2510/* helper function to handle common stuff in ip late init phase */
563285c8 2511int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
2512 struct ras_common_if *ras_block)
b293e891 2513{
29c9b6cd 2514 struct amdgpu_ras_block_object *ras_obj = NULL;
05adfd80
LT		 2515 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2516 unsigned long ue_count, ce_count;
b293e891
HZ		 2517 int r;
2518
2519 /* disable RAS feature per IP block if it is not supported */
2520 if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
2521 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
2522 return 0;
2523 }
2524
2525 r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
2526 if (r) {
9080a18f 2527 if (adev->in_suspend || amdgpu_in_reset(adev)) {
b293e891
HZ		 2528 /* in resume phase, if fail to enable ras,
2529 * clean up all ras fs nodes, and disable ras */
2530 goto cleanup;
2531 } else
2532 return r;
2533 }
2534
134d16d5
JC		 2535 /* check for errors on warm reset edc persisant supported ASIC */
2536 amdgpu_persistent_edc_harvesting(adev, ras_block);
2537
b293e891 2538 /* in resume phase, no need to create ras fs node */
53b3f8f4 2539 if (adev->in_suspend || amdgpu_in_reset(adev))
b293e891
HZ		 2540 return 0;
2541
563285c8 2542 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
36780606
TZ		 2543 if (ras_obj->ras_cb || (ras_obj->hw_ops &&
2544 (ras_obj->hw_ops->query_poison_status ||
2545 ras_obj->hw_ops->handle_poison_consumption))) {
9252d33d 2546 r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
b293e891 2547 if (r)
779596ce 2548 goto cleanup;
b293e891
HZ		 2549 }
2550
9252d33d 2551 r = amdgpu_ras_sysfs_create(adev, ras_block);
b293e891 2552 if (r)
779596ce 2553 goto interrupt;
b293e891 2554
05adfd80
LT		 2555 /* Those are the cached values at init.
2556 */
4d9f771e
LT		 2557 if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
2558 atomic_set(&con->ras_ce_count, ce_count);
2559 atomic_set(&con->ras_ue_count, ue_count);
2560 }
05adfd80 2561
b293e891 2562 return 0;
779596ce
TR		 2563
2564interrupt:
563285c8 2565 if (ras_obj->ras_cb)
9252d33d 2566 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
779596ce 2567cleanup:
b293e891
HZ		 2568 amdgpu_ras_feature_enable(adev, ras_block, 0);
2569 return r;
2570}
2571
d41ff22a 2572static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
418abce2 2573 struct ras_common_if *ras_block)
2574{
2575 return amdgpu_ras_block_late_init(adev, ras_block);
2576}
2577
b293e891 2578/* helper function to remove ras fs node and interrupt handler */
bdb3489c 2579void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
2580 struct ras_common_if *ras_block)
2581{
563285c8 2582 struct amdgpu_ras_block_object *ras_obj;
bdb3489c 2583 if (!ras_block)
2584 return;
2585
563285c8 2586 amdgpu_ras_sysfs_remove(adev, ras_block);
bdb3489c 2587
563285c8 2588 ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm);
2589 if (ras_obj->ras_cb)
2590 amdgpu_ras_interrupt_remove_handler(adev, ras_block);
bdb3489c 2591}
2592
80e0c2cb 2593static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
2594 struct ras_common_if *ras_block)
2595{
2596 return amdgpu_ras_block_late_fini(adev, ras_block);
2597}
2598
a564808e 2599/* do some init work after IP late init as dependence.
511fdbc3 2600 * and it runs in resume/gpu reset/booting up cases.
a564808e 2601 */
511fdbc3 2602void amdgpu_ras_resume(struct amdgpu_device *adev)
108c6a63 2603{
2604 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2605 struct ras_manager *obj, *tmp;
2606
8ab0d6f0 2607 if (!adev->ras_enabled || !con) {
970fd197
SY		 2608 /* clean ras context for VEGA20 Gaming after send ras disable cmd */
2609 amdgpu_release_ras_context(adev);
2610
108c6a63 2611 return;
970fd197 2612 }
108c6a63 2613
108c6a63 2614 if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) {
191051a1 2615 /* Set up all other IPs which are not implemented. There is a
2616 * tricky thing that IP's actual ras error type should be
2617 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
2618 * ERROR_NONE make sense anyway.
2619 */
2620 amdgpu_ras_enable_all_features(adev, 1);
2621
2622 /* We enable ras on all hw_supported block, but as boot
2623 * parameter might disable some of them and one or more IP has
2624 * not implemented yet. So we disable them on behalf.
2625 */
108c6a63 2626 list_for_each_entry_safe(obj, tmp, &con->head, node) {
2627 if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
2628 amdgpu_ras_feature_enable(adev, &obj->head, 0);
2629 /* there should be no any reference. */
2630 WARN_ON(alive_obj(obj));
2631 }
191051a1 2632 }
108c6a63 2633 }
2634}
2635
511fdbc3 2636void amdgpu_ras_suspend(struct amdgpu_device *adev)
2637{
2638 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2639
8ab0d6f0 2640 if (!adev->ras_enabled || !con)
511fdbc3 2641 return;
2642
2643 amdgpu_ras_disable_all_features(adev, 0);
2644 /* Make sure all ras objects are disabled. */
2645 if (con->features)
2646 amdgpu_ras_disable_all_features(adev, 1);
2647}
2648
867e24ca 2649int amdgpu_ras_late_init(struct amdgpu_device *adev)
2650{
2651 struct amdgpu_ras_block_list *node, *tmp;
2652 struct amdgpu_ras_block_object *obj;
2653 int r;
2654
950d6425
SY		 2655 /* Guest side doesn't need init ras feature */
2656 if (amdgpu_sriov_vf(adev))
2657 return 0;
2658
867e24ca 2659 list_for_each_entry_safe(node, tmp, &adev->ras_list, node) {
2660 if (!node->ras_obj) {
2661 dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
2662 continue;
2663 }
418abce2 2664
867e24ca 2665 obj = node->ras_obj;
2666 if (obj->ras_late_init) {
2667 r = obj->ras_late_init(adev, &obj->ras_comm);
2668 if (r) {
2669 dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",
2670 obj->ras_comm.name, r);
2671 return r;
2672 }
418abce2 2673 } else
2674 amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
867e24ca 2675 }
2676
2677 return 0;
2678}
2679
c030f2e4 2680/* do some fini work before IP fini as dependence */
2681int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2682{
2683 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2684
8ab0d6f0 2685 if (!adev->ras_enabled || !con)
c030f2e4 2686 return 0;
2687
72c8c97b 2688
c030f2e4 2689 /* Need disable ras on all IPs here before ip [hw/sw]fini */
2690 amdgpu_ras_disable_all_features(adev, 0);
2691 amdgpu_ras_recovery_fini(adev);
2692 return 0;
2693}
2694
2695int amdgpu_ras_fini(struct amdgpu_device *adev)
2696{
d5e8ff5f 2697 struct amdgpu_ras_block_list *ras_node, *tmp;
1f211a82 2698 struct amdgpu_ras_block_object *obj = NULL;
c030f2e4 2699 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2700
8ab0d6f0 2701 if (!adev->ras_enabled || !con)
c030f2e4 2702 return 0;
2703
1f211a82 2704 list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) {
2705 if (ras_node->ras_obj) {
2706 obj = ras_node->ras_obj;
2707 if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
2708 obj->ras_fini)
2709 obj->ras_fini(adev, &obj->ras_comm);
80e0c2cb 2710 else
2711 amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
1f211a82 2712 }
2713
2714 /* Clear ras blocks from ras_list and free ras block list node */
2715 list_del(&ras_node->node);
2716 kfree(ras_node);
2717 }
2718
c030f2e4 2719 amdgpu_ras_fs_fini(adev);
2720 amdgpu_ras_interrupt_remove_all(adev);
2721
2722 WARN(con->features, "Feature mask is not cleared");
2723
2724 if (con->features)
2725 amdgpu_ras_disable_all_features(adev, 1);
2726
05adfd80
LT		 2727 cancel_delayed_work_sync(&con->ras_counte_delay_work);
2728
c030f2e4 2729 amdgpu_ras_set_context(adev, NULL);
2730 kfree(con);
2731
2732 return 0;
2733}
7c6e68c7
AG		 2734
2735void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2736{
e509965e 2737 amdgpu_ras_check_supported(adev);
8ab0d6f0 2738 if (!adev->ras_hw_enabled)
ed606f8a
AG		 2739 return;
2740
7c6e68c7 2741 if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) {
6952e99c
GC		 2742 dev_info(adev->dev, "uncorrectable hardware error"
2743 "(ERREVENT_ATHUB_INTERRUPT) detected!\n");
d5ea093e 2744
61934624 2745 amdgpu_ras_reset_gpu(adev);
7c6e68c7
AG		 2746 }
2747}
bb5c7235
WS		 2748
2749bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2750{
2751 if (adev->asic_type == CHIP_VEGA20 &&
2752 adev->pm.fw_version <= 0x283400) {
2753 return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) &&
2754 amdgpu_ras_intr_triggered();
2755 }
2756
2757 return false;
2758}
970fd197
SY		 2759
2760void amdgpu_release_ras_context(struct amdgpu_device *adev)
2761{
2762 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
2763
2764 if (!con)
2765 return;
2766
8ab0d6f0 2767 if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) {
970fd197
SY		 2768 con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX);
2769 amdgpu_ras_set_context(adev, NULL);
2770 kfree(con);
2771 }
2772}
12b2cab7
MJ		 2773
2774#ifdef CONFIG_X86_MCE_AMD
2775static struct amdgpu_device *find_adev(uint32_t node_id)
2776{
12b2cab7
MJ		 2777 int i;
2778 struct amdgpu_device *adev = NULL;
2779
91a1a52d
MJ		 2780 for (i = 0; i < mce_adev_list.num_gpu; i++) {
2781 adev = mce_adev_list.devs[i];
12b2cab7 2782
91a1a52d 2783 if (adev && adev->gmc.xgmi.connected_to_cpu &&
12b2cab7
MJ		 2784 adev->gmc.xgmi.physical_node_id == node_id)
2785 break;
2786 adev = NULL;
2787 }
2788
12b2cab7
MJ		 2789 return adev;
2790}
2791
2792#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
2793#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
2794#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2795#define GPU_ID_OFFSET 8
2796
2797static int amdgpu_bad_page_notifier(struct notifier_block *nb,
2798 unsigned long val, void *data)
2799{
2800 struct mce *m = (struct mce *)data;
2801 struct amdgpu_device *adev = NULL;
2802 uint32_t gpu_id = 0;
2803 uint32_t umc_inst = 0;
2804 uint32_t ch_inst, channel_index = 0;
2805 struct ras_err_data err_data = {0, 0, 0, NULL};
2806 struct eeprom_table_record err_rec;
2807 uint64_t retired_page;
2808
2809 /*
2810 * If the error was generated in UMC_V2, which belongs to GPU UMCs,
2811 * and error occurred in DramECC (Extended error code = 0) then only
2812 * process the error, else bail out.
2813 */
91f75eb4 2814 if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
12b2cab7
MJ		 2815 (XEC(m->status, 0x3f) == 0x0)))
2816 return NOTIFY_DONE;
2817
2818 /*
2819 * If it is correctable error, return.
2820 */
2821 if (mce_is_correctable(m))
2822 return NOTIFY_OK;
2823
2824 /*
2825 * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
2826 */
2827 gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
2828
2829 adev = find_adev(gpu_id);
2830 if (!adev) {
2831 DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
2832 gpu_id);
2833 return NOTIFY_DONE;
2834 }
2835
2836 /*
2837 * If it is uncorrectable error, then find out UMC instance and
2838 * channel index.
2839 */
2840 umc_inst = GET_UMC_INST(m->ipid);
2841 ch_inst = GET_CHAN_INDEX(m->ipid);
2842
2843 dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
2844 umc_inst, ch_inst);
2845
12b2cab7
MJ		 2846 /*
2847 * Translate UMC channel address to Physical address
2848 */
2849 channel_index =
2850 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
2851 + ch_inst];
2852
2853 retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
2854 ADDR_OF_256B_BLOCK(channel_index) |
2855 OFFSET_IN_256B_BLOCK(m->addr);
2856
400013b2 2857 memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
12b2cab7 2858 err_data.err_addr = &err_rec;
400013b2
TZ		 2859 amdgpu_umc_fill_error_record(&err_data, m->addr,
2860 retired_page, channel_index, umc_inst);
12b2cab7
MJ		 2861
2862 if (amdgpu_bad_page_threshold != 0) {
2863 amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
2864 err_data.err_addr_cnt);
2865 amdgpu_ras_save_bad_pages(adev);
2866 }
2867
2868 return NOTIFY_OK;
2869}
2870
2871static struct notifier_block amdgpu_bad_page_nb = {
2872 .notifier_call = amdgpu_bad_page_notifier,
2873 .priority = MCE_PRIO_UC,
2874};
2875
91a1a52d 2876static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
12b2cab7 2877{
91a1a52d
MJ		 2878 /*
2879 * Add the adev to the mce_adev_list.
2880 * During mode2 reset, amdgpu device is temporarily
2881 * removed from the mgpu_info list which can cause
2882 * page retirement to fail.
2883 * Use this list instead of mgpu_info to find the amdgpu
2884 * device on which the UMC error was reported.
2885 */
2886 mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;
2887
12b2cab7
MJ		 2888 /*
2889 * Register the x86 notifier only once
2890 * with MCE subsystem.
2891 */
2892 if (notifier_registered == false) {
2893 mce_register_decode_chain(&amdgpu_bad_page_nb);
2894 notifier_registered = true;
2895 }
2896}
2897#endif
7cab2124 2898
b6efdb02 2899struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
7cab2124 2900{
2901 if (!adev)
2902 return NULL;
2903
2904 return adev->psp.ras_context.ras;
2905}
2906
b6efdb02 2907int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
7cab2124 2908{
2909 if (!adev)
69f91d32 2910 return -EINVAL;
7cab2124 2911
2912 adev->psp.ras_context.ras = ras_con;
2913 return 0;
2914}
2915
2916/* check if ras is supported on block, say, sdma, gfx */
2917int amdgpu_ras_is_supported(struct amdgpu_device *adev,
2918 unsigned int block)
2919{
2920 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2921
2922 if (block >= AMDGPU_RAS_BLOCK_COUNT)
2923 return 0;
2924 return ras && (adev->ras_enabled & (1 << block));
2925}
2926
2927int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2928{
2929 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
2930
2931 if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0)
2932 schedule_work(&ras->recovery_work);
2933 return 0;
2934}
2935
2936
6492e1b0 2937/* Register each ip ras block into amdgpu ras */
2938int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
b6efdb02 2939 struct amdgpu_ras_block_object *ras_block_obj)
6492e1b0 2940{
d5e8ff5f 2941 struct amdgpu_ras_block_list *ras_node;
6492e1b0 2942 if (!adev || !ras_block_obj)
2943 return -EINVAL;
2944
df01fe73 2945 if (!amdgpu_ras_asic_supported(adev))
2946 return 0;
2947
d5e8ff5f 2948 ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL);
2949 if (!ras_node)
2950 return -ENOMEM;
2951
2952 INIT_LIST_HEAD(&ras_node->node);
2953 ras_node->ras_obj = ras_block_obj;
2954 list_add_tail(&ras_node->node, &adev->ras_list);
6492e1b0 2955
2956 return 0;
2957}
Linux 6.x block layer and io_uring tree(s)