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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
05adfd80 | 30 | #include <linux/pm_runtime.h> |
f867723b | 31 | |
c030f2e4 | 32 | #include "amdgpu.h" |
33 | #include "amdgpu_ras.h" | |
b404ae82 | 34 | #include "amdgpu_atomfirmware.h" |
19744f5f | 35 | #include "amdgpu_xgmi.h" |
4e644fff | 36 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
9af357bc | 37 | #include "nbio_v4_3.h" |
7692e1ee | 38 | #include "nbio_v7_9.h" |
f50160cf | 39 | #include "atom.h" |
25a2b22e AG |
40 | #include "amdgpu_reset.h" |
41 | ||
12b2cab7 MJ |
42 | #ifdef CONFIG_X86_MCE_AMD |
43 | #include <asm/mce.h> | |
c030f2e4 | 44 | |
12b2cab7 MJ |
45 | static bool notifier_registered; |
46 | #endif | |
eb0c3cd4 GC |
47 | static const char *RAS_FS_NAME = "ras"; |
48 | ||
c030f2e4 | 49 | const char *ras_error_string[] = { |
50 | "none", | |
51 | "parity", | |
52 | "single_correctable", | |
53 | "multi_uncorrectable", | |
54 | "poison", | |
55 | }; | |
56 | ||
57 | const char *ras_block_string[] = { | |
58 | "umc", | |
59 | "sdma", | |
60 | "gfx", | |
61 | "mmhub", | |
62 | "athub", | |
63 | "pcie_bif", | |
64 | "hdp", | |
65 | "xgmi_wafl", | |
66 | "df", | |
67 | "smn", | |
68 | "sem", | |
69 | "mp0", | |
70 | "mp1", | |
71 | "fuse", | |
640ae42e | 72 | "mca", |
a3d63c62 MZZ |
73 | "vcn", |
74 | "jpeg", | |
c030f2e4 | 75 | }; |
76 | ||
640ae42e JC |
77 | const char *ras_mca_block_string[] = { |
78 | "mca_mp0", | |
79 | "mca_mp1", | |
80 | "mca_mpio", | |
81 | "mca_iohc", | |
82 | }; | |
83 | ||
d5e8ff5f | 84 | struct amdgpu_ras_block_list { |
85 | /* ras block link */ | |
86 | struct list_head node; | |
87 | ||
88 | struct amdgpu_ras_block_object *ras_obj; | |
89 | }; | |
90 | ||
640ae42e JC |
91 | const char *get_ras_block_str(struct ras_common_if *ras_block) |
92 | { | |
93 | if (!ras_block) | |
94 | return "NULL"; | |
95 | ||
96 | if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT) | |
97 | return "OUT OF RANGE"; | |
98 | ||
99 | if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) | |
100 | return ras_mca_block_string[ras_block->sub_block_index]; | |
101 | ||
102 | return ras_block_string[ras_block->block]; | |
103 | } | |
104 | ||
954ea6aa | 105 | #define ras_block_str(_BLOCK_) \ |
106 | (((_BLOCK_) < ARRAY_SIZE(ras_block_string)) ? ras_block_string[_BLOCK_] : "Out Of Range") | |
8b0fb0e9 | 107 | |
c030f2e4 | 108 | #define ras_err_str(i) (ras_error_string[ffs(i)]) |
c030f2e4 | 109 | |
108c6a63 | 110 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
111 | ||
7cdc2ee3 TZ |
112 | /* inject address is 52 bits */ |
113 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
114 | ||
e4e6a589 LT |
115 | /* typical ECC bad page rate is 1 bad page per 100MB VRAM */ |
116 | #define RAS_BAD_PAGE_COVER (100 * 1024 * 1024ULL) | |
c84d4670 | 117 | |
52dd95f2 GC |
118 | enum amdgpu_ras_retire_page_reservation { |
119 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
120 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
121 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
122 | }; | |
7c6e68c7 AG |
123 | |
124 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
125 | ||
676deb38 DL |
126 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
127 | uint64_t addr); | |
6e4be987 TZ |
128 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
129 | uint64_t addr); | |
12b2cab7 | 130 | #ifdef CONFIG_X86_MCE_AMD |
91a1a52d MJ |
131 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); |
132 | struct mce_notifier_adev_list { | |
133 | struct amdgpu_device *devs[MAX_GPU_INSTANCE]; | |
134 | int num_gpu; | |
135 | }; | |
136 | static struct mce_notifier_adev_list mce_adev_list; | |
12b2cab7 | 137 | #endif |
6e4be987 | 138 | |
61380faa JC |
139 | void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) |
140 | { | |
a9d82d2f | 141 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
142 | amdgpu_ras_get_context(adev)->error_query_ready = ready; |
143 | } | |
144 | ||
f3167919 | 145 | static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev) |
61380faa | 146 | { |
a9d82d2f | 147 | if (adev && amdgpu_ras_get_context(adev)) |
61380faa JC |
148 | return amdgpu_ras_get_context(adev)->error_query_ready; |
149 | ||
150 | return false; | |
151 | } | |
152 | ||
cbb8f989 JC |
153 | static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address) |
154 | { | |
155 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
156 | struct eeprom_table_record err_rec; | |
157 | ||
158 | if ((address >= adev->gmc.mc_vram_size) || | |
159 | (address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
160 | dev_warn(adev->dev, | |
161 | "RAS WARN: input address 0x%llx is invalid.\n", | |
162 | address); | |
163 | return -EINVAL; | |
164 | } | |
165 | ||
166 | if (amdgpu_ras_check_bad_page(adev, address)) { | |
167 | dev_warn(adev->dev, | |
80b0cd0f | 168 | "RAS WARN: 0x%llx has already been marked as bad page!\n", |
cbb8f989 JC |
169 | address); |
170 | return 0; | |
171 | } | |
172 | ||
173 | memset(&err_rec, 0x0, sizeof(struct eeprom_table_record)); | |
cbb8f989 | 174 | err_data.err_addr = &err_rec; |
71344a71 | 175 | amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0); |
cbb8f989 JC |
176 | |
177 | if (amdgpu_bad_page_threshold != 0) { | |
178 | amdgpu_ras_add_bad_pages(adev, err_data.err_addr, | |
179 | err_data.err_addr_cnt); | |
4d33e0f1 | 180 | amdgpu_ras_save_bad_pages(adev, NULL); |
cbb8f989 JC |
181 | } |
182 | ||
183 | dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"); | |
184 | dev_warn(adev->dev, "Clear EEPROM:\n"); | |
185 | dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
c030f2e4 | 190 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
191 | size_t size, loff_t *pos) | |
192 | { | |
193 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
194 | struct ras_query_if info = { | |
195 | .head = obj->head, | |
196 | }; | |
197 | ssize_t s; | |
198 | char val[128]; | |
199 | ||
761d86d3 | 200 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 201 | return -EINVAL; |
202 | ||
2a460963 | 203 | /* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */ |
4e8303cf LL |
204 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
205 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
2a460963 CL |
206 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
207 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); | |
208 | } | |
209 | ||
c030f2e4 | 210 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", |
211 | "ue", info.ue_count, | |
212 | "ce", info.ce_count); | |
213 | if (*pos >= s) | |
214 | return 0; | |
215 | ||
216 | s -= *pos; | |
217 | s = min_t(u64, s, size); | |
218 | ||
219 | ||
220 | if (copy_to_user(buf, &val[*pos], s)) | |
221 | return -EINVAL; | |
222 | ||
223 | *pos += s; | |
224 | ||
225 | return s; | |
226 | } | |
227 | ||
c030f2e4 | 228 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
229 | .owner = THIS_MODULE, | |
230 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 231 | .write = NULL, |
c030f2e4 | 232 | .llseek = default_llseek |
233 | }; | |
234 | ||
96ebb307 | 235 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
236 | { | |
237 | int i; | |
238 | ||
239 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
240 | *block_id = i; | |
640ae42e | 241 | if (strcmp(name, ras_block_string[i]) == 0) |
96ebb307 | 242 | return 0; |
243 | } | |
244 | return -EINVAL; | |
245 | } | |
246 | ||
247 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
248 | const char __user *buf, size_t size, | |
249 | loff_t *pos, struct ras_debug_if *data) | |
250 | { | |
251 | ssize_t s = min_t(u64, 64, size); | |
252 | char str[65]; | |
253 | char block_name[33]; | |
254 | char err[9] = "ue"; | |
255 | int op = -1; | |
256 | int block_id; | |
44494f96 | 257 | uint32_t sub_block; |
96ebb307 | 258 | u64 address, value; |
2c22ed0b TZ |
259 | /* default value is 0 if the mask is not set by user */ |
260 | u32 instance_mask = 0; | |
96ebb307 | 261 | |
262 | if (*pos) | |
263 | return -EINVAL; | |
264 | *pos = size; | |
265 | ||
266 | memset(str, 0, sizeof(str)); | |
267 | memset(data, 0, sizeof(*data)); | |
268 | ||
269 | if (copy_from_user(str, buf, s)) | |
270 | return -EINVAL; | |
271 | ||
272 | if (sscanf(str, "disable %32s", block_name) == 1) | |
273 | op = 0; | |
274 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
275 | op = 1; | |
276 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
277 | op = 2; | |
6df23f4c | 278 | else if (strstr(str, "retire_page") != NULL) |
cbb8f989 | 279 | op = 3; |
b076296b | 280 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 281 | /* ascii string, but commands are not matched. */ |
282 | return -EINVAL; | |
283 | ||
284 | if (op != -1) { | |
cbb8f989 | 285 | if (op == 3) { |
546aa546 LT |
286 | if (sscanf(str, "%*s 0x%llx", &address) != 1 && |
287 | sscanf(str, "%*s %llu", &address) != 1) | |
6cb7a1d4 | 288 | return -EINVAL; |
cbb8f989 JC |
289 | |
290 | data->op = op; | |
291 | data->inject.address = address; | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
96ebb307 | 296 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) |
297 | return -EINVAL; | |
298 | ||
299 | data->head.block = block_id; | |
e1063493 TZ |
300 | /* only ue and ce errors are supported */ |
301 | if (!memcmp("ue", err, 2)) | |
302 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
303 | else if (!memcmp("ce", err, 2)) | |
304 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
305 | else | |
306 | return -EINVAL; | |
307 | ||
96ebb307 | 308 | data->op = op; |
309 | ||
310 | if (op == 2) { | |
2c22ed0b TZ |
311 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx 0x%x", |
312 | &sub_block, &address, &value, &instance_mask) != 4 && | |
313 | sscanf(str, "%*s %*s %*s %u %llu %llu %u", | |
314 | &sub_block, &address, &value, &instance_mask) != 4 && | |
315 | sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
546aa546 LT |
316 | &sub_block, &address, &value) != 3 && |
317 | sscanf(str, "%*s %*s %*s %u %llu %llu", | |
6cb7a1d4 LT |
318 | &sub_block, &address, &value) != 3) |
319 | return -EINVAL; | |
44494f96 | 320 | data->head.sub_block_index = sub_block; |
96ebb307 | 321 | data->inject.address = address; |
322 | data->inject.value = value; | |
2c22ed0b | 323 | data->inject.instance_mask = instance_mask; |
96ebb307 | 324 | } |
325 | } else { | |
73aa8e1a | 326 | if (size < sizeof(*data)) |
96ebb307 | 327 | return -EINVAL; |
328 | ||
329 | if (copy_from_user(data, buf, sizeof(*data))) | |
330 | return -EINVAL; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
7c6e68c7 | 335 | |
f464c5dd TZ |
336 | static void amdgpu_ras_instance_mask_check(struct amdgpu_device *adev, |
337 | struct ras_debug_if *data) | |
338 | { | |
339 | int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; | |
340 | uint32_t mask, inst_mask = data->inject.instance_mask; | |
341 | ||
342 | /* no need to set instance mask if there is only one instance */ | |
343 | if (num_xcc <= 1 && inst_mask) { | |
344 | data->inject.instance_mask = 0; | |
345 | dev_dbg(adev->dev, | |
346 | "RAS inject mask(0x%x) isn't supported and force it to 0.\n", | |
347 | inst_mask); | |
348 | ||
349 | return; | |
350 | } | |
351 | ||
352 | switch (data->head.block) { | |
353 | case AMDGPU_RAS_BLOCK__GFX: | |
354 | mask = GENMASK(num_xcc - 1, 0); | |
355 | break; | |
356 | case AMDGPU_RAS_BLOCK__SDMA: | |
357 | mask = GENMASK(adev->sdma.num_instances - 1, 0); | |
358 | break; | |
e3959cb5 SY |
359 | case AMDGPU_RAS_BLOCK__VCN: |
360 | case AMDGPU_RAS_BLOCK__JPEG: | |
361 | mask = GENMASK(adev->vcn.num_vcn_inst - 1, 0); | |
362 | break; | |
f464c5dd | 363 | default: |
e3959cb5 | 364 | mask = inst_mask; |
f464c5dd TZ |
365 | break; |
366 | } | |
367 | ||
368 | /* remove invalid bits in instance mask */ | |
369 | data->inject.instance_mask &= mask; | |
370 | if (inst_mask != data->inject.instance_mask) | |
371 | dev_dbg(adev->dev, | |
372 | "Adjust RAS inject mask 0x%x to 0x%x\n", | |
373 | inst_mask, data->inject.instance_mask); | |
374 | } | |
375 | ||
74abc221 TSD |
376 | /** |
377 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 378 | * |
737c375b | 379 | * The control interface accepts struct ras_debug_if which has two members. |
36ea1bd2 | 380 | * |
381 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 382 | * |
383 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 384 | * |
385 | * head has four members, they are block, type, sub_block_index, name. | |
386 | * block: which IP will be under control. | |
387 | * type: what kind of error will be enabled/disabled/injected. | |
388 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
389 | * name: the name of IP. | |
390 | * | |
2c22ed0b | 391 | * inject has three more members than head, they are address, value and mask. |
36ea1bd2 | 392 | * As their names indicate, inject operation will write the |
393 | * value to the address. | |
394 | * | |
ef177d11 | 395 | * The second member: struct ras_debug_if::op. |
c688a06b | 396 | * It has three kinds of operations. |
879e723d AZ |
397 | * |
398 | * - 0: disable RAS on the block. Take ::head as its data. | |
399 | * - 1: enable RAS on the block. Take ::head as its data. | |
400 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 401 | * |
96ebb307 | 402 | * How to use the interface? |
ef177d11 | 403 | * |
737c375b | 404 | * In a program |
ef177d11 | 405 | * |
737c375b LT |
406 | * Copy the struct ras_debug_if in your code and initialize it. |
407 | * Write the struct to the control interface. | |
ef177d11 | 408 | * |
737c375b | 409 | * From shell |
96ebb307 | 410 | * |
879e723d AZ |
411 | * .. code-block:: bash |
412 | * | |
737c375b LT |
413 | * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
414 | * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl | |
2c22ed0b | 415 | * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl |
879e723d | 416 | * |
737c375b | 417 | * Where N, is the card which you want to affect. |
ef177d11 | 418 | * |
737c375b LT |
419 | * "disable" requires only the block. |
420 | * "enable" requires the block and error type. | |
421 | * "inject" requires the block, error type, address, and value. | |
c666bbf0 | 422 | * |
737c375b | 423 | * The block is one of: umc, sdma, gfx, etc. |
879e723d | 424 | * see ras_block_string[] for details |
c666bbf0 | 425 | * |
737c375b LT |
426 | * The error type is one of: ue, ce, where, |
427 | * ue is multi-uncorrectable | |
428 | * ce is single-correctable | |
c666bbf0 | 429 | * |
737c375b LT |
430 | * The sub-block is a the sub-block index, pass 0 if there is no sub-block. |
431 | * The address and value are hexadecimal numbers, leading 0x is optional. | |
2c22ed0b | 432 | * The mask means instance mask, is optional, default value is 0x1. |
879e723d | 433 | * |
737c375b | 434 | * For instance, |
879e723d AZ |
435 | * |
436 | * .. code-block:: bash | |
96ebb307 | 437 | * |
44494f96 | 438 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
2c22ed0b | 439 | * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
96ebb307 | 440 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
441 | * | |
737c375b | 442 | * How to check the result of the operation? |
36ea1bd2 | 443 | * |
737c375b | 444 | * To check disable/enable, see "ras" features at, |
36ea1bd2 | 445 | * /sys/class/drm/card[0/1/2...]/device/ras/features |
446 | * | |
737c375b LT |
447 | * To check inject, see the corresponding error count at, |
448 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count | |
36ea1bd2 | 449 | * |
879e723d | 450 | * .. note:: |
ef177d11 | 451 | * Operations are only allowed on blocks which are supported. |
737c375b | 452 | * Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
453 | * to see which blocks support RAS on a particular asic. |
454 | * | |
36ea1bd2 | 455 | */ |
cf696091 LT |
456 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, |
457 | const char __user *buf, | |
458 | size_t size, loff_t *pos) | |
36ea1bd2 | 459 | { |
460 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
461 | struct ras_debug_if data; | |
462 | int ret = 0; | |
463 | ||
61380faa | 464 | if (!amdgpu_ras_get_error_query_ready(adev)) { |
6952e99c GC |
465 | dev_warn(adev->dev, "RAS WARN: error injection " |
466 | "currently inaccessible\n"); | |
43c4d576 JC |
467 | return size; |
468 | } | |
469 | ||
96ebb307 | 470 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
471 | if (ret) | |
cf696091 | 472 | return ret; |
36ea1bd2 | 473 | |
80b0cd0f | 474 | if (data.op == 3) { |
cbb8f989 | 475 | ret = amdgpu_reserve_page_direct(adev, data.inject.address); |
80b0cd0f | 476 | if (!ret) |
cbb8f989 JC |
477 | return size; |
478 | else | |
479 | return ret; | |
480 | } | |
481 | ||
36ea1bd2 | 482 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
483 | return -EINVAL; | |
484 | ||
485 | switch (data.op) { | |
486 | case 0: | |
487 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
488 | break; | |
489 | case 1: | |
490 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
491 | break; | |
492 | case 2: | |
43aedbf4 SY |
493 | if ((data.inject.address >= adev->gmc.mc_vram_size && |
494 | adev->gmc.mc_vram_size) || | |
7cdc2ee3 | 495 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { |
b0d4783a GC |
496 | dev_warn(adev->dev, "RAS WARN: input address " |
497 | "0x%llx is invalid.", | |
498 | data.inject.address); | |
7cdc2ee3 TZ |
499 | ret = -EINVAL; |
500 | break; | |
501 | } | |
502 | ||
6e4be987 TZ |
503 | /* umc ce/ue error injection for a bad page is not allowed */ |
504 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
505 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
c65b0805 LT |
506 | dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has " |
507 | "already been marked as bad!\n", | |
508 | data.inject.address); | |
6e4be987 TZ |
509 | break; |
510 | } | |
511 | ||
f464c5dd TZ |
512 | amdgpu_ras_instance_mask_check(adev, &data); |
513 | ||
7cdc2ee3 | 514 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 515 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
516 | break; | |
96ebb307 | 517 | default: |
518 | ret = -EINVAL; | |
519 | break; | |
374bf7bd | 520 | } |
36ea1bd2 | 521 | |
522 | if (ret) | |
79c04621 | 523 | return ret; |
36ea1bd2 | 524 | |
525 | return size; | |
526 | } | |
527 | ||
084fe13b AG |
528 | /** |
529 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
530 | * | |
f77c7109 | 531 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 532 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
533 | * a way to reset the EEPROM, e.g., after testing error injection. |
534 | * | |
535 | * Usage: | |
536 | * | |
537 | * .. code-block:: bash | |
538 | * | |
539 | * echo 1 > ../ras/ras_eeprom_reset | |
540 | * | |
541 | * will reset EEPROM table to 0 entries. | |
542 | * | |
084fe13b | 543 | */ |
cf696091 LT |
544 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, |
545 | const char __user *buf, | |
546 | size_t size, loff_t *pos) | |
084fe13b | 547 | { |
bf0b91b7 GC |
548 | struct amdgpu_device *adev = |
549 | (struct amdgpu_device *)file_inode(f)->i_private; | |
084fe13b AG |
550 | int ret; |
551 | ||
bf0b91b7 | 552 | ret = amdgpu_ras_eeprom_reset_table( |
cf696091 | 553 | &(amdgpu_ras_get_context(adev)->eeprom_control)); |
084fe13b | 554 | |
63d4c081 | 555 | if (!ret) { |
cf696091 LT |
556 | /* Something was written to EEPROM. |
557 | */ | |
bf0b91b7 GC |
558 | amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS; |
559 | return size; | |
560 | } else { | |
cf696091 | 561 | return ret; |
bf0b91b7 | 562 | } |
084fe13b AG |
563 | } |
564 | ||
36ea1bd2 | 565 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
566 | .owner = THIS_MODULE, | |
567 | .read = NULL, | |
568 | .write = amdgpu_ras_debugfs_ctrl_write, | |
569 | .llseek = default_llseek | |
570 | }; | |
571 | ||
084fe13b AG |
572 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
573 | .owner = THIS_MODULE, | |
574 | .read = NULL, | |
575 | .write = amdgpu_ras_debugfs_eeprom_write, | |
576 | .llseek = default_llseek | |
577 | }; | |
578 | ||
f77c7109 AD |
579 | /** |
580 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
581 | * | |
ef177d11 | 582 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
583 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
584 | * | |
585 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
586 | * (ce) error counts. | |
587 | * | |
588 | * The format of one line is below, | |
589 | * | |
590 | * [ce|ue]: count | |
591 | * | |
592 | * Example: | |
593 | * | |
594 | * .. code-block:: bash | |
595 | * | |
596 | * ue: 0 | |
597 | * ce: 1 | |
598 | * | |
599 | */ | |
c030f2e4 | 600 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
601 | struct device_attribute *attr, char *buf) | |
602 | { | |
603 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
604 | struct ras_query_if info = { | |
605 | .head = obj->head, | |
606 | }; | |
607 | ||
61380faa | 608 | if (!amdgpu_ras_get_error_query_ready(obj->adev)) |
36000c7a | 609 | return sysfs_emit(buf, "Query currently inaccessible\n"); |
43c4d576 | 610 | |
761d86d3 | 611 | if (amdgpu_ras_query_error_status(obj->adev, &info)) |
c030f2e4 | 612 | return -EINVAL; |
613 | ||
4e8303cf LL |
614 | if (amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
615 | amdgpu_ip_version(obj->adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
1f0d8e37 | 616 | if (amdgpu_ras_reset_error_status(obj->adev, info.head.block)) |
2a460963 | 617 | dev_warn(obj->adev->dev, "Failed to reset error counter and error status"); |
1f0d8e37 MJ |
618 | } |
619 | ||
36000c7a TT |
620 | return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count, |
621 | "ce", info.ce_count); | |
c030f2e4 | 622 | } |
623 | ||
624 | /* obj begin */ | |
625 | ||
626 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
627 | #define alive_obj(obj) ((obj)->use) | |
628 | ||
629 | static inline void put_obj(struct ras_manager *obj) | |
630 | { | |
f0872686 | 631 | if (obj && (--obj->use == 0)) |
c030f2e4 | 632 | list_del(&obj->node); |
f0872686 | 633 | if (obj && (obj->use < 0)) |
640ae42e | 634 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head)); |
c030f2e4 | 635 | } |
636 | ||
637 | /* make one obj and return it. */ | |
638 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
639 | struct ras_common_if *head) | |
640 | { | |
641 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
642 | struct ras_manager *obj; | |
643 | ||
8ab0d6f0 | 644 | if (!adev->ras_enabled || !con) |
c030f2e4 | 645 | return NULL; |
646 | ||
647 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
648 | return NULL; | |
649 | ||
640ae42e JC |
650 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
651 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
652 | return NULL; | |
653 | ||
654 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
655 | } else | |
656 | obj = &con->objs[head->block]; | |
657 | ||
c030f2e4 | 658 | /* already exist. return obj? */ |
659 | if (alive_obj(obj)) | |
660 | return NULL; | |
661 | ||
662 | obj->head = *head; | |
663 | obj->adev = adev; | |
664 | list_add(&obj->node, &con->head); | |
665 | get_obj(obj); | |
666 | ||
667 | return obj; | |
668 | } | |
669 | ||
670 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 671 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 672 | struct ras_common_if *head) |
673 | { | |
674 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
675 | struct ras_manager *obj; | |
676 | int i; | |
677 | ||
8ab0d6f0 | 678 | if (!adev->ras_enabled || !con) |
c030f2e4 | 679 | return NULL; |
680 | ||
681 | if (head) { | |
682 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
683 | return NULL; | |
684 | ||
640ae42e JC |
685 | if (head->block == AMDGPU_RAS_BLOCK__MCA) { |
686 | if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST) | |
687 | return NULL; | |
688 | ||
689 | obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index]; | |
690 | } else | |
691 | obj = &con->objs[head->block]; | |
c030f2e4 | 692 | |
640ae42e | 693 | if (alive_obj(obj)) |
c030f2e4 | 694 | return obj; |
c030f2e4 | 695 | } else { |
640ae42e | 696 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT + AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { |
c030f2e4 | 697 | obj = &con->objs[i]; |
640ae42e | 698 | if (alive_obj(obj)) |
c030f2e4 | 699 | return obj; |
c030f2e4 | 700 | } |
701 | } | |
702 | ||
703 | return NULL; | |
704 | } | |
705 | /* obj end */ | |
706 | ||
707 | /* feature ctl begin */ | |
708 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
e509965e | 709 | struct ras_common_if *head) |
c030f2e4 | 710 | { |
8ab0d6f0 | 711 | return adev->ras_hw_enabled & BIT(head->block); |
c030f2e4 | 712 | } |
713 | ||
714 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
715 | struct ras_common_if *head) | |
716 | { | |
717 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
718 | ||
719 | return con->features & BIT(head->block); | |
720 | } | |
721 | ||
722 | /* | |
723 | * if obj is not created, then create one. | |
724 | * set feature enable flag. | |
725 | */ | |
726 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
727 | struct ras_common_if *head, int enable) | |
728 | { | |
729 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
730 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
731 | ||
5caf466a | 732 | /* If hardware does not support ras, then do not create obj. |
733 | * But if hardware support ras, we can create the obj. | |
734 | * Ras framework checks con->hw_supported to see if it need do | |
735 | * corresponding initialization. | |
736 | * IP checks con->support to see if it need disable ras. | |
737 | */ | |
c030f2e4 | 738 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
739 | return 0; | |
c030f2e4 | 740 | |
741 | if (enable) { | |
742 | if (!obj) { | |
743 | obj = amdgpu_ras_create_obj(adev, head); | |
744 | if (!obj) | |
745 | return -EINVAL; | |
746 | } else { | |
747 | /* In case we create obj somewhere else */ | |
748 | get_obj(obj); | |
749 | } | |
750 | con->features |= BIT(head->block); | |
751 | } else { | |
752 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
19d0dfda | 753 | con->features &= ~BIT(head->block); |
c030f2e4 | 754 | put_obj(obj); |
755 | } | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | /* wrapper of psp_ras_enable_features */ | |
762 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
763 | struct ras_common_if *head, bool enable) | |
764 | { | |
765 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
7fcffecf | 766 | union ta_ras_cmd_input *info; |
bf7aa8be | 767 | int ret; |
c030f2e4 | 768 | |
769 | if (!con) | |
770 | return -EINVAL; | |
771 | ||
ec70578c HZ |
772 | /* For non-gfx ip, do not enable ras feature if it is not allowed */ |
773 | /* For gfx ip, regardless of feature support status, */ | |
774 | /* Force issue enable or disable ras feature commands */ | |
775 | if (head->block != AMDGPU_RAS_BLOCK__GFX && | |
6fc9d92c | 776 | !amdgpu_ras_is_feature_allowed(adev, head)) |
bf7aa8be | 777 | return 0; |
6fc9d92c HZ |
778 | |
779 | /* Only enable gfx ras feature from host side */ | |
780 | if (head->block == AMDGPU_RAS_BLOCK__GFX && | |
781 | !amdgpu_sriov_vf(adev) && | |
782 | !amdgpu_ras_intr_triggered()) { | |
26093ce1 SY |
783 | info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL); |
784 | if (!info) | |
785 | return -ENOMEM; | |
786 | ||
787 | if (!enable) { | |
788 | info->disable_features = (struct ta_ras_disable_features_input) { | |
789 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
790 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
791 | }; | |
792 | } else { | |
793 | info->enable_features = (struct ta_ras_enable_features_input) { | |
794 | .block_id = amdgpu_ras_block_to_ta(head->block), | |
795 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
796 | }; | |
797 | } | |
c030f2e4 | 798 | |
7fcffecf | 799 | ret = psp_ras_enable_features(&adev->psp, info, enable); |
bff77e86 | 800 | if (ret) { |
e4348849 | 801 | dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n", |
011907fd | 802 | enable ? "enable":"disable", |
640ae42e | 803 | get_ras_block_str(head), |
e4348849 | 804 | amdgpu_ras_is_poison_mode_supported(adev), ret); |
bf7aa8be | 805 | return ret; |
bff77e86 | 806 | } |
bf7aa8be HZ |
807 | |
808 | kfree(info); | |
c030f2e4 | 809 | } |
810 | ||
811 | /* setup the obj */ | |
812 | __amdgpu_ras_feature_enable(adev, head, enable); | |
bf7aa8be HZ |
813 | |
814 | return 0; | |
c030f2e4 | 815 | } |
816 | ||
77de502b | 817 | /* Only used in device probe stage and called only once. */ |
818 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
819 | struct ras_common_if *head, bool enable) | |
820 | { | |
821 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
822 | int ret; | |
823 | ||
824 | if (!con) | |
825 | return -EINVAL; | |
826 | ||
827 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 828 | if (enable) { |
829 | /* There is no harm to issue a ras TA cmd regardless of | |
830 | * the currecnt ras state. | |
831 | * If current state == target state, it will do nothing | |
832 | * But sometimes it requests driver to reset and repost | |
833 | * with error code -EAGAIN. | |
834 | */ | |
835 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
836 | /* With old ras TA, we might fail to enable ras. | |
837 | * Log it and just setup the object. | |
838 | * TODO need remove this WA in the future. | |
839 | */ | |
840 | if (ret == -EINVAL) { | |
841 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
842 | if (!ret) | |
6952e99c GC |
843 | dev_info(adev->dev, |
844 | "RAS INFO: %s setup object\n", | |
640ae42e | 845 | get_ras_block_str(head)); |
7af23ebe | 846 | } |
847 | } else { | |
848 | /* setup the object then issue a ras TA disable cmd.*/ | |
849 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
850 | if (ret) | |
851 | return ret; | |
77de502b | 852 | |
970fd197 SY |
853 | /* gfx block ras dsiable cmd must send to ras-ta */ |
854 | if (head->block == AMDGPU_RAS_BLOCK__GFX) | |
855 | con->features |= BIT(head->block); | |
856 | ||
77de502b | 857 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
19d0dfda SY |
858 | |
859 | /* clean gfx block ras features flag */ | |
8ab0d6f0 | 860 | if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX) |
19d0dfda | 861 | con->features &= ~BIT(head->block); |
7af23ebe | 862 | } |
77de502b | 863 | } else |
864 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
865 | ||
866 | return ret; | |
867 | } | |
868 | ||
c030f2e4 | 869 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
870 | bool bypass) | |
871 | { | |
872 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
873 | struct ras_manager *obj, *tmp; | |
874 | ||
875 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
876 | /* bypass psp. | |
877 | * aka just release the obj and corresponding flags | |
878 | */ | |
879 | if (bypass) { | |
880 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
881 | break; | |
882 | } else { | |
883 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
884 | break; | |
885 | } | |
289d513b | 886 | } |
c030f2e4 | 887 | |
888 | return con->features; | |
889 | } | |
890 | ||
891 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
892 | bool bypass) | |
893 | { | |
894 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
c030f2e4 | 895 | int i; |
640ae42e | 896 | const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE; |
c030f2e4 | 897 | |
640ae42e | 898 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { |
c030f2e4 | 899 | struct ras_common_if head = { |
900 | .block = i, | |
191051a1 | 901 | .type = default_ras_type, |
c030f2e4 | 902 | .sub_block_index = 0, |
903 | }; | |
640ae42e JC |
904 | |
905 | if (i == AMDGPU_RAS_BLOCK__MCA) | |
906 | continue; | |
907 | ||
908 | if (bypass) { | |
909 | /* | |
910 | * bypass psp. vbios enable ras for us. | |
911 | * so just create the obj | |
912 | */ | |
913 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
914 | break; | |
915 | } else { | |
916 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
917 | break; | |
918 | } | |
919 | } | |
920 | ||
921 | for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNT; i++) { | |
922 | struct ras_common_if head = { | |
923 | .block = AMDGPU_RAS_BLOCK__MCA, | |
924 | .type = default_ras_type, | |
925 | .sub_block_index = i, | |
926 | }; | |
927 | ||
c030f2e4 | 928 | if (bypass) { |
929 | /* | |
930 | * bypass psp. vbios enable ras for us. | |
931 | * so just create the obj | |
932 | */ | |
933 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
934 | break; | |
935 | } else { | |
936 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
937 | break; | |
938 | } | |
289d513b | 939 | } |
c030f2e4 | 940 | |
941 | return con->features; | |
942 | } | |
943 | /* feature ctl end */ | |
944 | ||
e3d833f4 | 945 | static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj, |
946 | enum amdgpu_ras_block block) | |
6492e1b0 | 947 | { |
b6efdb02 | 948 | if (!block_obj) |
6492e1b0 | 949 | return -EINVAL; |
950 | ||
bdb3489c | 951 | if (block_obj->ras_comm.block == block) |
6492e1b0 | 952 | return 0; |
640ae42e | 953 | |
6492e1b0 | 954 | return -EINVAL; |
955 | } | |
956 | ||
b6efdb02 | 957 | static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev, |
6492e1b0 | 958 | enum amdgpu_ras_block block, uint32_t sub_block_index) |
640ae42e | 959 | { |
d5e8ff5f | 960 | struct amdgpu_ras_block_list *node, *tmp; |
961 | struct amdgpu_ras_block_object *obj; | |
6492e1b0 | 962 | |
963 | if (block >= AMDGPU_RAS_BLOCK__LAST) | |
964 | return NULL; | |
965 | ||
d5e8ff5f | 966 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
967 | if (!node->ras_obj) { | |
968 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
969 | continue; | |
970 | } | |
971 | ||
972 | obj = node->ras_obj; | |
6492e1b0 | 973 | if (obj->ras_block_match) { |
974 | if (obj->ras_block_match(obj, block, sub_block_index) == 0) | |
975 | return obj; | |
976 | } else { | |
977 | if (amdgpu_ras_block_match_default(obj, block) == 0) | |
978 | return obj; | |
979 | } | |
640ae42e | 980 | } |
6492e1b0 | 981 | |
982 | return NULL; | |
640ae42e JC |
983 | } |
984 | ||
fdcb279d SY |
985 | static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data) |
986 | { | |
987 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
988 | int ret = 0; | |
989 | ||
990 | /* | |
991 | * choosing right query method according to | |
992 | * whether smu support query error information | |
993 | */ | |
bc143d8b | 994 | ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc)); |
fdcb279d | 995 | if (ret == -EOPNOTSUPP) { |
efe17d5a | 996 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
997 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count) | |
998 | adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); | |
fdcb279d SY |
999 | |
1000 | /* umc query_ras_error_address is also responsible for clearing | |
1001 | * error status | |
1002 | */ | |
efe17d5a | 1003 | if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && |
1004 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address) | |
1005 | adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data); | |
fdcb279d | 1006 | } else if (!ret) { |
efe17d5a | 1007 | if (adev->umc.ras && |
1008 | adev->umc.ras->ecc_info_query_ras_error_count) | |
1009 | adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data); | |
fdcb279d | 1010 | |
efe17d5a | 1011 | if (adev->umc.ras && |
1012 | adev->umc.ras->ecc_info_query_ras_error_address) | |
1013 | adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data); | |
fdcb279d SY |
1014 | } |
1015 | } | |
1016 | ||
c030f2e4 | 1017 | /* query/inject/cure begin */ |
761d86d3 | 1018 | int amdgpu_ras_query_error_status(struct amdgpu_device *adev, |
4d9f771e | 1019 | struct ras_query_if *info) |
c030f2e4 | 1020 | { |
b6efdb02 | 1021 | struct amdgpu_ras_block_object *block_obj = NULL; |
c030f2e4 | 1022 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); |
6f102dba | 1023 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1024 | |
1025 | if (!obj) | |
1026 | return -EINVAL; | |
c030f2e4 | 1027 | |
7389a5b8 | 1028 | if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { |
fdcb279d | 1029 | amdgpu_ras_get_ecc_info(adev, &err_data); |
7389a5b8 | 1030 | } else { |
1031 | block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0); | |
8b0fb0e9 | 1032 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1033 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1034 | get_ras_block_str(&info->head)); | |
8b0fb0e9 | 1035 | return -EINVAL; |
3e81ee9a | 1036 | } |
761d86d3 | 1037 | |
6c245386 | 1038 | if (block_obj->hw_ops->query_ras_error_count) |
1039 | block_obj->hw_ops->query_ras_error_count(adev, &err_data); | |
7389a5b8 | 1040 | |
1041 | if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) || | |
1042 | (info->head.block == AMDGPU_RAS_BLOCK__GFX) || | |
1043 | (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
1044 | if (block_obj->hw_ops->query_ras_error_status) | |
1045 | block_obj->hw_ops->query_ras_error_status(adev); | |
1046 | } | |
939e2258 | 1047 | } |
05a58345 TZ |
1048 | |
1049 | obj->err_data.ue_count += err_data.ue_count; | |
1050 | obj->err_data.ce_count += err_data.ce_count; | |
1051 | ||
c030f2e4 | 1052 | info->ue_count = obj->err_data.ue_count; |
1053 | info->ce_count = obj->err_data.ce_count; | |
1054 | ||
7c6e68c7 | 1055 | if (err_data.ce_count) { |
9f9d4651 HZ |
1056 | if (!adev->aid_mask && |
1057 | adev->smuio.funcs && | |
a30f1286 HZ |
1058 | adev->smuio.funcs->get_socket_id && |
1059 | adev->smuio.funcs->get_die_id) { | |
1060 | dev_info(adev->dev, "socket: %d, die: %d " | |
1061 | "%ld correctable hardware errors " | |
6952e99c GC |
1062 | "detected in %s block, no user " |
1063 | "action is needed.\n", | |
a30f1286 HZ |
1064 | adev->smuio.funcs->get_socket_id(adev), |
1065 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 1066 | obj->err_data.ce_count, |
640ae42e | 1067 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
1068 | } else { |
1069 | dev_info(adev->dev, "%ld correctable hardware errors " | |
6952e99c GC |
1070 | "detected in %s block, no user " |
1071 | "action is needed.\n", | |
1072 | obj->err_data.ce_count, | |
640ae42e | 1073 | get_ras_block_str(&info->head)); |
a30f1286 | 1074 | } |
7c6e68c7 AG |
1075 | } |
1076 | if (err_data.ue_count) { | |
9f9d4651 HZ |
1077 | if (!adev->aid_mask && |
1078 | adev->smuio.funcs && | |
a30f1286 HZ |
1079 | adev->smuio.funcs->get_socket_id && |
1080 | adev->smuio.funcs->get_die_id) { | |
1081 | dev_info(adev->dev, "socket: %d, die: %d " | |
1082 | "%ld uncorrectable hardware errors " | |
6952e99c | 1083 | "detected in %s block\n", |
a30f1286 HZ |
1084 | adev->smuio.funcs->get_socket_id(adev), |
1085 | adev->smuio.funcs->get_die_id(adev), | |
6952e99c | 1086 | obj->err_data.ue_count, |
640ae42e | 1087 | get_ras_block_str(&info->head)); |
a30f1286 HZ |
1088 | } else { |
1089 | dev_info(adev->dev, "%ld uncorrectable hardware errors " | |
6952e99c GC |
1090 | "detected in %s block\n", |
1091 | obj->err_data.ue_count, | |
640ae42e | 1092 | get_ras_block_str(&info->head)); |
a30f1286 | 1093 | } |
7c6e68c7 | 1094 | } |
05a58345 | 1095 | |
c030f2e4 | 1096 | return 0; |
1097 | } | |
1098 | ||
761d86d3 DL |
1099 | int amdgpu_ras_reset_error_status(struct amdgpu_device *adev, |
1100 | enum amdgpu_ras_block block) | |
1101 | { | |
b6efdb02 | 1102 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0); |
8b0fb0e9 | 1103 | |
761d86d3 DL |
1104 | if (!amdgpu_ras_is_supported(adev, block)) |
1105 | return -EINVAL; | |
1106 | ||
7389a5b8 | 1107 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1108 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1109 | ras_block_str(block)); | |
7389a5b8 | 1110 | return -EINVAL; |
761d86d3 DL |
1111 | } |
1112 | ||
7389a5b8 | 1113 | if (block_obj->hw_ops->reset_ras_error_count) |
1114 | block_obj->hw_ops->reset_ras_error_count(adev); | |
5c23e9e0 | 1115 | |
7389a5b8 | 1116 | if ((block == AMDGPU_RAS_BLOCK__GFX) || |
1117 | (block == AMDGPU_RAS_BLOCK__MMHUB)) { | |
8b0fb0e9 | 1118 | if (block_obj->hw_ops->reset_ras_error_status) |
1119 | block_obj->hw_ops->reset_ras_error_status(adev); | |
761d86d3 | 1120 | } |
5c23e9e0 | 1121 | |
761d86d3 | 1122 | return 0; |
5c23e9e0 JC |
1123 | } |
1124 | ||
c030f2e4 | 1125 | /* wrapper of psp_ras_trigger_error */ |
1126 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
1127 | struct ras_inject_if *info) | |
1128 | { | |
1129 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1130 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 1131 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
1132 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 1133 | .sub_block_index = info->head.sub_block_index, |
1134 | .address = info->address, | |
1135 | .value = info->value, | |
1136 | }; | |
ab3b9de6 YL |
1137 | int ret = -EINVAL; |
1138 | struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, | |
1139 | info->head.block, | |
1140 | info->head.sub_block_index); | |
c030f2e4 | 1141 | |
248c9635 TZ |
1142 | /* inject on guest isn't allowed, return success directly */ |
1143 | if (amdgpu_sriov_vf(adev)) | |
1144 | return 0; | |
1145 | ||
c030f2e4 | 1146 | if (!obj) |
1147 | return -EINVAL; | |
1148 | ||
22d4ba53 | 1149 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1150 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1151 | get_ras_block_str(&info->head)); | |
22d4ba53 | 1152 | return -EINVAL; |
1153 | } | |
1154 | ||
a6c44d25 | 1155 | /* Calculate XGMI relative offset */ |
a80fe1a6 TZ |
1156 | if (adev->gmc.xgmi.num_physical_nodes > 1 && |
1157 | info->head.block != AMDGPU_RAS_BLOCK__GFX) { | |
19744f5f HZ |
1158 | block_info.address = |
1159 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
1160 | block_info.address); | |
a6c44d25 JC |
1161 | } |
1162 | ||
27c5f295 TZ |
1163 | if (block_obj->hw_ops->ras_error_inject) { |
1164 | if (info->head.block == AMDGPU_RAS_BLOCK__GFX) | |
2c22ed0b | 1165 | ret = block_obj->hw_ops->ras_error_inject(adev, info, info->instance_mask); |
27c5f295 | 1166 | else /* Special ras_error_inject is defined (e.g: xgmi) */ |
2c22ed0b TZ |
1167 | ret = block_obj->hw_ops->ras_error_inject(adev, &block_info, |
1168 | info->instance_mask); | |
27c5f295 TZ |
1169 | } else { |
1170 | /* default path */ | |
1171 | ret = psp_ras_trigger_error(&adev->psp, &block_info, info->instance_mask); | |
a5dd40ca HZ |
1172 | } |
1173 | ||
011907fd DL |
1174 | if (ret) |
1175 | dev_err(adev->dev, "ras inject %s failed %d\n", | |
640ae42e | 1176 | get_ras_block_str(&info->head), ret); |
c030f2e4 | 1177 | |
1178 | return ret; | |
1179 | } | |
1180 | ||
4d9f771e | 1181 | /** |
4a1c9a44 HZ |
1182 | * amdgpu_ras_query_error_count_helper -- Get error counter for specific IP |
1183 | * @adev: pointer to AMD GPU device | |
1184 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1185 | * @ue_count: pointer to an integer to be set to the count of uncorrectible errors. | |
1186 | * @query_info: pointer to ras_query_if | |
1187 | * | |
1188 | * Return 0 for query success or do nothing, otherwise return an error | |
1189 | * on failures | |
1190 | */ | |
1191 | static int amdgpu_ras_query_error_count_helper(struct amdgpu_device *adev, | |
1192 | unsigned long *ce_count, | |
1193 | unsigned long *ue_count, | |
1194 | struct ras_query_if *query_info) | |
1195 | { | |
1196 | int ret; | |
1197 | ||
1198 | if (!query_info) | |
1199 | /* do nothing if query_info is not specified */ | |
1200 | return 0; | |
1201 | ||
1202 | ret = amdgpu_ras_query_error_status(adev, query_info); | |
1203 | if (ret) | |
1204 | return ret; | |
1205 | ||
1206 | *ce_count += query_info->ce_count; | |
1207 | *ue_count += query_info->ue_count; | |
1208 | ||
1209 | /* some hardware/IP supports read to clear | |
1210 | * no need to explictly reset the err status after the query call */ | |
4e8303cf LL |
1211 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && |
1212 | amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { | |
4a1c9a44 HZ |
1213 | if (amdgpu_ras_reset_error_status(adev, query_info->head.block)) |
1214 | dev_warn(adev->dev, | |
1215 | "Failed to reset error counter and error status\n"); | |
1216 | } | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * amdgpu_ras_query_error_count -- Get error counts of all IPs or specific IP | |
bbe04dec IB |
1223 | * @adev: pointer to AMD GPU device |
1224 | * @ce_count: pointer to an integer to be set to the count of correctible errors. | |
1225 | * @ue_count: pointer to an integer to be set to the count of uncorrectible | |
4d9f771e | 1226 | * errors. |
4a1c9a44 HZ |
1227 | * @query_info: pointer to ras_query_if if the query request is only for |
1228 | * specific ip block; if info is NULL, then the qurey request is for | |
1229 | * all the ip blocks that support query ras error counters/status | |
4d9f771e LT |
1230 | * |
1231 | * If set, @ce_count or @ue_count, count and return the corresponding | |
1232 | * error counts in those integer pointers. Return 0 if the device | |
1233 | * supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS. | |
1234 | */ | |
1235 | int amdgpu_ras_query_error_count(struct amdgpu_device *adev, | |
1236 | unsigned long *ce_count, | |
4a1c9a44 HZ |
1237 | unsigned long *ue_count, |
1238 | struct ras_query_if *query_info) | |
c030f2e4 | 1239 | { |
1240 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1241 | struct ras_manager *obj; | |
a46751fb | 1242 | unsigned long ce, ue; |
4a1c9a44 | 1243 | int ret; |
c030f2e4 | 1244 | |
8ab0d6f0 | 1245 | if (!adev->ras_enabled || !con) |
4d9f771e LT |
1246 | return -EOPNOTSUPP; |
1247 | ||
1248 | /* Don't count since no reporting. | |
1249 | */ | |
1250 | if (!ce_count && !ue_count) | |
1251 | return 0; | |
c030f2e4 | 1252 | |
a46751fb LT |
1253 | ce = 0; |
1254 | ue = 0; | |
4a1c9a44 HZ |
1255 | if (!query_info) { |
1256 | /* query all the ip blocks that support ras query interface */ | |
1257 | list_for_each_entry(obj, &con->head, node) { | |
1258 | struct ras_query_if info = { | |
1259 | .head = obj->head, | |
1260 | }; | |
c030f2e4 | 1261 | |
4a1c9a44 | 1262 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, &info); |
2a460963 | 1263 | } |
4a1c9a44 HZ |
1264 | } else { |
1265 | /* query specific ip block */ | |
1266 | ret = amdgpu_ras_query_error_count_helper(adev, &ce, &ue, query_info); | |
c030f2e4 | 1267 | } |
1268 | ||
4a1c9a44 HZ |
1269 | if (ret) |
1270 | return ret; | |
1271 | ||
a46751fb LT |
1272 | if (ce_count) |
1273 | *ce_count = ce; | |
1274 | ||
1275 | if (ue_count) | |
1276 | *ue_count = ue; | |
4d9f771e LT |
1277 | |
1278 | return 0; | |
c030f2e4 | 1279 | } |
1280 | /* query/inject/cure end */ | |
1281 | ||
1282 | ||
1283 | /* sysfs begin */ | |
1284 | ||
466b1793 | 1285 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
1286 | struct ras_badpage **bps, unsigned int *count); | |
1287 | ||
1288 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
1289 | { | |
1290 | switch (flags) { | |
52dd95f2 | 1291 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 1292 | return "R"; |
52dd95f2 | 1293 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 1294 | return "P"; |
52dd95f2 | 1295 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 1296 | default: |
1297 | return "F"; | |
aec576f9 | 1298 | } |
466b1793 | 1299 | } |
1300 | ||
f77c7109 AD |
1301 | /** |
1302 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 1303 | * |
1304 | * It allows user to read the bad pages of vram on the gpu through | |
1305 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
1306 | * | |
1307 | * It outputs multiple lines, and each line stands for one gpu page. | |
1308 | * | |
1309 | * The format of one line is below, | |
1310 | * gpu pfn : gpu page size : flags | |
1311 | * | |
1312 | * gpu pfn and gpu page size are printed in hex format. | |
1313 | * flags can be one of below character, | |
f77c7109 | 1314 | * |
466b1793 | 1315 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 1316 | * |
466b1793 | 1317 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
1318 | * in next window of page_reserve. |
1319 | * | |
466b1793 | 1320 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
1321 | * | |
f77c7109 AD |
1322 | * Examples: |
1323 | * | |
1324 | * .. code-block:: bash | |
1325 | * | |
1326 | * 0x00000001 : 0x00001000 : R | |
1327 | * 0x00000002 : 0x00001000 : P | |
1328 | * | |
466b1793 | 1329 | */ |
1330 | ||
1331 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
1332 | struct kobject *kobj, struct bin_attribute *attr, | |
1333 | char *buf, loff_t ppos, size_t count) | |
1334 | { | |
1335 | struct amdgpu_ras *con = | |
1336 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
1337 | struct amdgpu_device *adev = con->adev; | |
1338 | const unsigned int element_size = | |
1339 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
1340 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
1341 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 1342 | ssize_t s = 0; |
1343 | struct ras_badpage *bps = NULL; | |
1344 | unsigned int bps_count = 0; | |
1345 | ||
1346 | memset(buf, 0, count); | |
1347 | ||
1348 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
1349 | return 0; | |
1350 | ||
1351 | for (; start < end && start < bps_count; start++) | |
1352 | s += scnprintf(&buf[s], element_size + 1, | |
1353 | "0x%08x : 0x%08x : %1s\n", | |
1354 | bps[start].bp, | |
1355 | bps[start].size, | |
1356 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
1357 | ||
1358 | kfree(bps); | |
1359 | ||
1360 | return s; | |
1361 | } | |
1362 | ||
c030f2e4 | 1363 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
1364 | struct device_attribute *attr, char *buf) | |
1365 | { | |
1366 | struct amdgpu_ras *con = | |
1367 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 1368 | |
2cffcb66 | 1369 | return sysfs_emit(buf, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 1370 | } |
1371 | ||
f848159b GC |
1372 | static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev) |
1373 | { | |
1374 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1375 | ||
1376 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1377 | &con->badpages_attr.attr, | |
1378 | RAS_FS_NAME); | |
1379 | } | |
1380 | ||
c030f2e4 | 1381 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) |
1382 | { | |
1383 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1384 | struct attribute *attrs[] = { | |
1385 | &con->features_attr.attr, | |
1386 | NULL | |
1387 | }; | |
1388 | struct attribute_group group = { | |
eb0c3cd4 | 1389 | .name = RAS_FS_NAME, |
c030f2e4 | 1390 | .attrs = attrs, |
1391 | }; | |
1392 | ||
1393 | sysfs_remove_group(&adev->dev->kobj, &group); | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
9252d33d | 1399 | struct ras_common_if *head) |
c030f2e4 | 1400 | { |
9252d33d | 1401 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1402 | |
1403 | if (!obj || obj->attr_inuse) | |
1404 | return -EINVAL; | |
1405 | ||
1406 | get_obj(obj); | |
1407 | ||
9252d33d | 1408 | snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name), |
1409 | "%s_err_count", head->name); | |
c030f2e4 | 1410 | |
1411 | obj->sysfs_attr = (struct device_attribute){ | |
1412 | .attr = { | |
1413 | .name = obj->fs_data.sysfs_name, | |
1414 | .mode = S_IRUGO, | |
1415 | }, | |
1416 | .show = amdgpu_ras_sysfs_read, | |
1417 | }; | |
163def43 | 1418 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1419 | |
1420 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1421 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1422 | RAS_FS_NAME)) { |
c030f2e4 | 1423 | put_obj(obj); |
1424 | return -EINVAL; | |
1425 | } | |
1426 | ||
1427 | obj->attr_inuse = 1; | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
1432 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1433 | struct ras_common_if *head) | |
1434 | { | |
1435 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1436 | ||
1437 | if (!obj || !obj->attr_inuse) | |
1438 | return -EINVAL; | |
1439 | ||
1440 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1441 | &obj->sysfs_attr.attr, | |
eb0c3cd4 | 1442 | RAS_FS_NAME); |
c030f2e4 | 1443 | obj->attr_inuse = 0; |
1444 | put_obj(obj); | |
1445 | ||
1446 | return 0; | |
1447 | } | |
1448 | ||
1449 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1450 | { | |
1451 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1452 | struct ras_manager *obj, *tmp; | |
1453 | ||
1454 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1455 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1456 | } | |
1457 | ||
f848159b GC |
1458 | if (amdgpu_bad_page_threshold != 0) |
1459 | amdgpu_ras_sysfs_remove_bad_page_node(adev); | |
1460 | ||
c030f2e4 | 1461 | amdgpu_ras_sysfs_remove_feature_node(adev); |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | /* sysfs end */ | |
1466 | ||
ef177d11 AD |
1467 | /** |
1468 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1469 | * | |
1470 | * Normally when there is an uncorrectable error, the driver will reset | |
1471 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1472 | * the driver provides an interface to reboot the system automatically | |
1473 | * in that event. | |
1474 | * | |
1475 | * The following file in debugfs provides that interface: | |
1476 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1477 | * | |
1478 | * Usage: | |
1479 | * | |
1480 | * .. code-block:: bash | |
1481 | * | |
1482 | * echo true > .../ras/auto_reboot | |
1483 | * | |
1484 | */ | |
c030f2e4 | 1485 | /* debugfs begin */ |
ea1b8c9b | 1486 | static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1487 | { |
1488 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
740f42a2 | 1489 | struct amdgpu_ras_eeprom_control *eeprom = &con->eeprom_control; |
ef0d7d20 LT |
1490 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1491 | struct dentry *dir; | |
36ea1bd2 | 1492 | |
88293c03 ND |
1493 | dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root); |
1494 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev, | |
1495 | &amdgpu_ras_debugfs_ctrl_ops); | |
1496 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev, | |
1497 | &amdgpu_ras_debugfs_eeprom_ops); | |
7fb64071 LT |
1498 | debugfs_create_u32("bad_page_cnt_threshold", 0444, dir, |
1499 | &con->bad_page_cnt_threshold); | |
740f42a2 | 1500 | debugfs_create_u32("ras_num_recs", 0444, dir, &eeprom->ras_num_recs); |
ef0d7d20 LT |
1501 | debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled); |
1502 | debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled); | |
c65b0805 LT |
1503 | debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev, |
1504 | &amdgpu_ras_debugfs_eeprom_size_ops); | |
1505 | con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table", | |
1506 | S_IRUGO, dir, adev, | |
1507 | &amdgpu_ras_debugfs_eeprom_table_ops); | |
1508 | amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control); | |
c688a06b GC |
1509 | |
1510 | /* | |
1511 | * After one uncorrectable error happens, usually GPU recovery will | |
1512 | * be scheduled. But due to the known problem in GPU recovery failing | |
1513 | * to bring GPU back, below interface provides one direct way to | |
1514 | * user to reboot system automatically in such case within | |
1515 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1516 | * will never be called. | |
1517 | */ | |
88293c03 | 1518 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot); |
66459e1d GC |
1519 | |
1520 | /* | |
1521 | * User could set this not to clean up hardware's error count register | |
1522 | * of RAS IPs during ras recovery. | |
1523 | */ | |
88293c03 ND |
1524 | debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir, |
1525 | &con->disable_ras_err_cnt_harvest); | |
1526 | return dir; | |
36ea1bd2 | 1527 | } |
1528 | ||
cedf7884 | 1529 | static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
88293c03 ND |
1530 | struct ras_fs_if *head, |
1531 | struct dentry *dir) | |
c030f2e4 | 1532 | { |
c030f2e4 | 1533 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); |
c030f2e4 | 1534 | |
88293c03 | 1535 | if (!obj || !dir) |
450f30ea | 1536 | return; |
c030f2e4 | 1537 | |
1538 | get_obj(obj); | |
1539 | ||
1540 | memcpy(obj->fs_data.debugfs_name, | |
1541 | head->debugfs_name, | |
1542 | sizeof(obj->fs_data.debugfs_name)); | |
1543 | ||
88293c03 ND |
1544 | debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir, |
1545 | obj, &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1546 | } |
1547 | ||
f9317014 TZ |
1548 | void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev) |
1549 | { | |
1550 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
88293c03 | 1551 | struct dentry *dir; |
c1509f3f | 1552 | struct ras_manager *obj; |
f9317014 TZ |
1553 | struct ras_fs_if fs_info; |
1554 | ||
1555 | /* | |
1556 | * it won't be called in resume path, no need to check | |
1557 | * suspend and gpu reset status | |
1558 | */ | |
cedf7884 | 1559 | if (!IS_ENABLED(CONFIG_DEBUG_FS) || !con) |
f9317014 TZ |
1560 | return; |
1561 | ||
88293c03 | 1562 | dir = amdgpu_ras_debugfs_create_ctrl_node(adev); |
f9317014 | 1563 | |
c1509f3f | 1564 | list_for_each_entry(obj, &con->head, node) { |
f9317014 TZ |
1565 | if (amdgpu_ras_is_supported(adev, obj->head.block) && |
1566 | (obj->attr_inuse == 1)) { | |
1567 | sprintf(fs_info.debugfs_name, "%s_err_inject", | |
640ae42e | 1568 | get_ras_block_str(&obj->head)); |
f9317014 | 1569 | fs_info.head = obj->head; |
88293c03 | 1570 | amdgpu_ras_debugfs_create(adev, &fs_info, dir); |
f9317014 TZ |
1571 | } |
1572 | } | |
4051844c YW |
1573 | |
1574 | amdgpu_mca_smu_debugfs_init(adev, dir); | |
f9317014 TZ |
1575 | } |
1576 | ||
c030f2e4 | 1577 | /* debugfs end */ |
1578 | ||
1579 | /* ras fs */ | |
c3d4d45d GC |
1580 | static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO, |
1581 | amdgpu_ras_sysfs_badpages_read, NULL, 0); | |
1582 | static DEVICE_ATTR(features, S_IRUGO, | |
1583 | amdgpu_ras_sysfs_features_read, NULL); | |
c030f2e4 | 1584 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) |
1585 | { | |
c3d4d45d GC |
1586 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1587 | struct attribute_group group = { | |
1588 | .name = RAS_FS_NAME, | |
1589 | }; | |
1590 | struct attribute *attrs[] = { | |
1591 | &con->features_attr.attr, | |
1592 | NULL | |
1593 | }; | |
1594 | struct bin_attribute *bin_attrs[] = { | |
1595 | NULL, | |
1596 | NULL, | |
1597 | }; | |
a069a9eb | 1598 | int r; |
c030f2e4 | 1599 | |
c3d4d45d GC |
1600 | /* add features entry */ |
1601 | con->features_attr = dev_attr_features; | |
1602 | group.attrs = attrs; | |
1603 | sysfs_attr_init(attrs[0]); | |
1604 | ||
1605 | if (amdgpu_bad_page_threshold != 0) { | |
1606 | /* add bad_page_features entry */ | |
1607 | bin_attr_gpu_vram_bad_pages.private = NULL; | |
1608 | con->badpages_attr = bin_attr_gpu_vram_bad_pages; | |
1609 | bin_attrs[0] = &con->badpages_attr; | |
1610 | group.bin_attrs = bin_attrs; | |
1611 | sysfs_bin_attr_init(bin_attrs[0]); | |
1612 | } | |
1613 | ||
a069a9eb AD |
1614 | r = sysfs_create_group(&adev->dev->kobj, &group); |
1615 | if (r) | |
1616 | dev_err(adev->dev, "Failed to create RAS sysfs group!"); | |
f848159b | 1617 | |
c030f2e4 | 1618 | return 0; |
1619 | } | |
1620 | ||
1621 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1622 | { | |
88293c03 ND |
1623 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1624 | struct ras_manager *con_obj, *ip_obj, *tmp; | |
1625 | ||
1626 | if (IS_ENABLED(CONFIG_DEBUG_FS)) { | |
1627 | list_for_each_entry_safe(con_obj, tmp, &con->head, node) { | |
1628 | ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head); | |
1629 | if (ip_obj) | |
1630 | put_obj(ip_obj); | |
1631 | } | |
1632 | } | |
1633 | ||
c030f2e4 | 1634 | amdgpu_ras_sysfs_remove_all(adev); |
1635 | return 0; | |
1636 | } | |
1637 | /* ras fs end */ | |
1638 | ||
1639 | /* ih begin */ | |
b3c76814 TZ |
1640 | |
1641 | /* For the hardware that cannot enable bif ring for both ras_controller_irq | |
1642 | * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status | |
1643 | * register to check whether the interrupt is triggered or not, and properly | |
1644 | * ack the interrupt if it is there | |
1645 | */ | |
1646 | void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) | |
1647 | { | |
950d6425 | 1648 | /* Fatal error events are handled on host side */ |
8eba7205 | 1649 | if (amdgpu_sriov_vf(adev)) |
b3c76814 TZ |
1650 | return; |
1651 | ||
1652 | if (adev->nbio.ras && | |
1653 | adev->nbio.ras->handle_ras_controller_intr_no_bifring) | |
1654 | adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev); | |
1655 | ||
1656 | if (adev->nbio.ras && | |
1657 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring) | |
1658 | adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev); | |
1659 | } | |
1660 | ||
66f87949 TZ |
1661 | static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj, |
1662 | struct amdgpu_iv_entry *entry) | |
1663 | { | |
b63ac5d3 | 1664 | bool poison_stat = false; |
66f87949 | 1665 | struct amdgpu_device *adev = obj->adev; |
66f87949 TZ |
1666 | struct amdgpu_ras_block_object *block_obj = |
1667 | amdgpu_ras_get_ras_block(adev, obj->head.block, 0); | |
1668 | ||
ac7b25d9 | 1669 | if (!block_obj) |
b63ac5d3 | 1670 | return; |
66f87949 | 1671 | |
b63ac5d3 TZ |
1672 | /* both query_poison_status and handle_poison_consumption are optional, |
1673 | * but at least one of them should be implemented if we need poison | |
1674 | * consumption handler | |
1675 | */ | |
ac7b25d9 | 1676 | if (block_obj->hw_ops && block_obj->hw_ops->query_poison_status) { |
b63ac5d3 TZ |
1677 | poison_stat = block_obj->hw_ops->query_poison_status(adev); |
1678 | if (!poison_stat) { | |
1679 | /* Not poison consumption interrupt, no need to handle it */ | |
1680 | dev_info(adev->dev, "No RAS poison status in %s poison IH.\n", | |
1681 | block_obj->ras_comm.name); | |
1682 | ||
1683 | return; | |
66f87949 TZ |
1684 | } |
1685 | } | |
1686 | ||
38298ce6 | 1687 | amdgpu_umc_poison_handler(adev, false); |
b63ac5d3 | 1688 | |
ac7b25d9 | 1689 | if (block_obj->hw_ops && block_obj->hw_ops->handle_poison_consumption) |
b63ac5d3 TZ |
1690 | poison_stat = block_obj->hw_ops->handle_poison_consumption(adev); |
1691 | ||
1692 | /* gpu reset is fallback for failed and default cases */ | |
1693 | if (poison_stat) { | |
1694 | dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n", | |
1695 | block_obj->ras_comm.name); | |
66f87949 | 1696 | amdgpu_ras_reset_gpu(adev); |
ac7b25d9 YC |
1697 | } else { |
1698 | amdgpu_gfx_poison_consumption_handler(adev, entry); | |
b63ac5d3 | 1699 | } |
66f87949 TZ |
1700 | } |
1701 | ||
50a7d025 TZ |
1702 | static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj, |
1703 | struct amdgpu_iv_entry *entry) | |
1704 | { | |
1705 | dev_info(obj->adev->dev, | |
1706 | "Poison is created, no user action is needed.\n"); | |
1707 | } | |
1708 | ||
1709 | static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, | |
1710 | struct amdgpu_iv_entry *entry) | |
1711 | { | |
1712 | struct ras_ih_data *data = &obj->ih_data; | |
1713 | struct ras_err_data err_data = {0, 0, 0, NULL}; | |
1714 | int ret; | |
1715 | ||
1716 | if (!data->cb) | |
1717 | return; | |
1718 | ||
1719 | /* Let IP handle its data, maybe we need get the output | |
1720 | * from the callback to update the error type/count, etc | |
1721 | */ | |
1722 | ret = data->cb(obj->adev, &err_data, entry); | |
1723 | /* ue will trigger an interrupt, and in that case | |
1724 | * we need do a reset to recovery the whole system. | |
1725 | * But leave IP do that recovery, here we just dispatch | |
1726 | * the error. | |
1727 | */ | |
1728 | if (ret == AMDGPU_RAS_SUCCESS) { | |
1729 | /* these counts could be left as 0 if | |
1730 | * some blocks do not count error number | |
1731 | */ | |
1732 | obj->err_data.ue_count += err_data.ue_count; | |
1733 | obj->err_data.ce_count += err_data.ce_count; | |
1734 | } | |
1735 | } | |
1736 | ||
c030f2e4 | 1737 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) |
1738 | { | |
1739 | struct ras_ih_data *data = &obj->ih_data; | |
1740 | struct amdgpu_iv_entry entry; | |
c030f2e4 | 1741 | |
1742 | while (data->rptr != data->wptr) { | |
1743 | rmb(); | |
1744 | memcpy(&entry, &data->ring[data->rptr], | |
1745 | data->element_size); | |
1746 | ||
1747 | wmb(); | |
1748 | data->rptr = (data->aligned_element_size + | |
1749 | data->rptr) % data->ring_size; | |
1750 | ||
50a7d025 TZ |
1751 | if (amdgpu_ras_is_poison_mode_supported(obj->adev)) { |
1752 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
1753 | amdgpu_ras_interrupt_poison_creation_handler(obj, &entry); | |
66f87949 TZ |
1754 | else |
1755 | amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry); | |
50a7d025 TZ |
1756 | } else { |
1757 | if (obj->head.block == AMDGPU_RAS_BLOCK__UMC) | |
1758 | amdgpu_ras_interrupt_umc_handler(obj, &entry); | |
1759 | else | |
1760 | dev_warn(obj->adev->dev, | |
1761 | "No RAS interrupt handler for non-UMC block with poison disabled.\n"); | |
c030f2e4 | 1762 | } |
1763 | } | |
1764 | } | |
1765 | ||
1766 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1767 | { | |
1768 | struct ras_ih_data *data = | |
1769 | container_of(work, struct ras_ih_data, ih_work); | |
1770 | struct ras_manager *obj = | |
1771 | container_of(data, struct ras_manager, ih_data); | |
1772 | ||
1773 | amdgpu_ras_interrupt_handler(obj); | |
1774 | } | |
1775 | ||
1776 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1777 | struct ras_dispatch_if *info) | |
1778 | { | |
1779 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1780 | struct ras_ih_data *data = &obj->ih_data; | |
1781 | ||
1782 | if (!obj) | |
1783 | return -EINVAL; | |
1784 | ||
1785 | if (data->inuse == 0) | |
1786 | return 0; | |
1787 | ||
1788 | /* Might be overflow... */ | |
1789 | memcpy(&data->ring[data->wptr], info->entry, | |
1790 | data->element_size); | |
1791 | ||
1792 | wmb(); | |
1793 | data->wptr = (data->aligned_element_size + | |
1794 | data->wptr) % data->ring_size; | |
1795 | ||
1796 | schedule_work(&data->ih_work); | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
1801 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
9252d33d | 1802 | struct ras_common_if *head) |
c030f2e4 | 1803 | { |
9252d33d | 1804 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1805 | struct ras_ih_data *data; |
1806 | ||
1807 | if (!obj) | |
1808 | return -EINVAL; | |
1809 | ||
1810 | data = &obj->ih_data; | |
1811 | if (data->inuse == 0) | |
1812 | return 0; | |
1813 | ||
1814 | cancel_work_sync(&data->ih_work); | |
1815 | ||
1816 | kfree(data->ring); | |
1817 | memset(data, 0, sizeof(*data)); | |
1818 | put_obj(obj); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
9252d33d | 1824 | struct ras_common_if *head) |
c030f2e4 | 1825 | { |
9252d33d | 1826 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); |
c030f2e4 | 1827 | struct ras_ih_data *data; |
9252d33d | 1828 | struct amdgpu_ras_block_object *ras_obj; |
c030f2e4 | 1829 | |
1830 | if (!obj) { | |
1831 | /* in case we registe the IH before enable ras feature */ | |
9252d33d | 1832 | obj = amdgpu_ras_create_obj(adev, head); |
c030f2e4 | 1833 | if (!obj) |
1834 | return -EINVAL; | |
1835 | } else | |
1836 | get_obj(obj); | |
1837 | ||
9252d33d | 1838 | ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm); |
1839 | ||
c030f2e4 | 1840 | data = &obj->ih_data; |
1841 | /* add the callback.etc */ | |
1842 | *data = (struct ras_ih_data) { | |
1843 | .inuse = 0, | |
9252d33d | 1844 | .cb = ras_obj->ras_cb, |
c030f2e4 | 1845 | .element_size = sizeof(struct amdgpu_iv_entry), |
1846 | .rptr = 0, | |
1847 | .wptr = 0, | |
1848 | }; | |
1849 | ||
1850 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1851 | ||
1852 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1853 | /* the ring can store 64 iv entries. */ | |
1854 | data->ring_size = 64 * data->aligned_element_size; | |
1855 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1856 | if (!data->ring) { | |
1857 | put_obj(obj); | |
1858 | return -ENOMEM; | |
1859 | } | |
1860 | ||
1861 | /* IH is ready */ | |
1862 | data->inuse = 1; | |
1863 | ||
1864 | return 0; | |
1865 | } | |
1866 | ||
1867 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1868 | { | |
1869 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1870 | struct ras_manager *obj, *tmp; | |
1871 | ||
1872 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
9252d33d | 1873 | amdgpu_ras_interrupt_remove_handler(adev, &obj->head); |
c030f2e4 | 1874 | } |
1875 | ||
1876 | return 0; | |
1877 | } | |
1878 | /* ih end */ | |
1879 | ||
313c8fd3 GC |
1880 | /* traversal all IPs except NBIO to query error counter */ |
1881 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1882 | { | |
1883 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1884 | struct ras_manager *obj; | |
1885 | ||
8ab0d6f0 | 1886 | if (!adev->ras_enabled || !con) |
313c8fd3 GC |
1887 | return; |
1888 | ||
1889 | list_for_each_entry(obj, &con->head, node) { | |
1890 | struct ras_query_if info = { | |
1891 | .head = obj->head, | |
1892 | }; | |
1893 | ||
1894 | /* | |
1895 | * PCIE_BIF IP has one different isr by ras controller | |
1896 | * interrupt, the specific ras counter query will be | |
1897 | * done in that isr. So skip such block from common | |
1898 | * sync flood interrupt isr calling. | |
1899 | */ | |
1900 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1901 | continue; | |
1902 | ||
cf63b702 SY |
1903 | /* |
1904 | * this is a workaround for aldebaran, skip send msg to | |
1905 | * smu to get ecc_info table due to smu handle get ecc | |
1906 | * info table failed temporarily. | |
1907 | * should be removed until smu fix handle ecc_info table. | |
1908 | */ | |
1909 | if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
4e8303cf LL |
1910 | (amdgpu_ip_version(adev, MP1_HWIP, 0) == |
1911 | IP_VERSION(13, 0, 2))) | |
cf63b702 SY |
1912 | continue; |
1913 | ||
761d86d3 | 1914 | amdgpu_ras_query_error_status(adev, &info); |
2a460963 | 1915 | |
4e8303cf LL |
1916 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) != |
1917 | IP_VERSION(11, 0, 2) && | |
1918 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
1919 | IP_VERSION(11, 0, 4) && | |
1920 | amdgpu_ip_version(adev, MP0_HWIP, 0) != | |
1921 | IP_VERSION(13, 0, 0)) { | |
2a460963 CL |
1922 | if (amdgpu_ras_reset_error_status(adev, info.head.block)) |
1923 | dev_warn(adev->dev, "Failed to reset error counter and error status"); | |
1924 | } | |
313c8fd3 GC |
1925 | } |
1926 | } | |
1927 | ||
3f975d0f | 1928 | /* Parse RdRspStatus and WrRspStatus */ |
cd92df93 LJ |
1929 | static void amdgpu_ras_error_status_query(struct amdgpu_device *adev, |
1930 | struct ras_query_if *info) | |
3f975d0f | 1931 | { |
8eb53bb2 | 1932 | struct amdgpu_ras_block_object *block_obj; |
3f975d0f SY |
1933 | /* |
1934 | * Only two block need to query read/write | |
1935 | * RspStatus at current state | |
1936 | */ | |
5e67bba3 | 1937 | if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) && |
1938 | (info->head.block != AMDGPU_RAS_BLOCK__MMHUB)) | |
b6efdb02 | 1939 | return; |
1940 | ||
1941 | block_obj = amdgpu_ras_get_ras_block(adev, | |
1942 | info->head.block, | |
1943 | info->head.sub_block_index); | |
5e67bba3 | 1944 | |
5e67bba3 | 1945 | if (!block_obj || !block_obj->hw_ops) { |
afa37315 LT |
1946 | dev_dbg_once(adev->dev, "%s doesn't config RAS function\n", |
1947 | get_ras_block_str(&info->head)); | |
b6efdb02 | 1948 | return; |
3f975d0f | 1949 | } |
5e67bba3 | 1950 | |
1951 | if (block_obj->hw_ops->query_ras_error_status) | |
ab3b9de6 | 1952 | block_obj->hw_ops->query_ras_error_status(adev); |
5e67bba3 | 1953 | |
3f975d0f SY |
1954 | } |
1955 | ||
1956 | static void amdgpu_ras_query_err_status(struct amdgpu_device *adev) | |
1957 | { | |
1958 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1959 | struct ras_manager *obj; | |
1960 | ||
8ab0d6f0 | 1961 | if (!adev->ras_enabled || !con) |
3f975d0f SY |
1962 | return; |
1963 | ||
1964 | list_for_each_entry(obj, &con->head, node) { | |
1965 | struct ras_query_if info = { | |
1966 | .head = obj->head, | |
1967 | }; | |
1968 | ||
1969 | amdgpu_ras_error_status_query(adev, &info); | |
1970 | } | |
1971 | } | |
1972 | ||
c030f2e4 | 1973 | /* recovery begin */ |
466b1793 | 1974 | |
1975 | /* return 0 on success. | |
1976 | * caller need free bps. | |
1977 | */ | |
1978 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1979 | struct ras_badpage **bps, unsigned int *count) | |
1980 | { | |
1981 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1982 | struct ras_err_handler_data *data; | |
1983 | int i = 0; | |
732f2a30 | 1984 | int ret = 0, status; |
466b1793 | 1985 | |
1986 | if (!con || !con->eh_data || !bps || !count) | |
1987 | return -EINVAL; | |
1988 | ||
1989 | mutex_lock(&con->recovery_lock); | |
1990 | data = con->eh_data; | |
1991 | if (!data || data->count == 0) { | |
1992 | *bps = NULL; | |
46cf2fec | 1993 | ret = -EINVAL; |
466b1793 | 1994 | goto out; |
1995 | } | |
1996 | ||
1997 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1998 | if (!*bps) { | |
1999 | ret = -ENOMEM; | |
2000 | goto out; | |
2001 | } | |
2002 | ||
2003 | for (; i < data->count; i++) { | |
2004 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 2005 | .bp = data->bps[i].retired_page, |
466b1793 | 2006 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 2007 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 2008 | }; |
ec6aae97 | 2009 | status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr, |
676deb38 | 2010 | data->bps[i].retired_page); |
732f2a30 | 2011 | if (status == -EBUSY) |
52dd95f2 | 2012 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
732f2a30 | 2013 | else if (status == -ENOENT) |
52dd95f2 | 2014 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 2015 | } |
2016 | ||
2017 | *count = data->count; | |
2018 | out: | |
2019 | mutex_unlock(&con->recovery_lock); | |
2020 | return ret; | |
2021 | } | |
2022 | ||
c030f2e4 | 2023 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
2024 | { | |
2025 | struct amdgpu_ras *ras = | |
2026 | container_of(work, struct amdgpu_ras, recovery_work); | |
b3dbd6d3 JC |
2027 | struct amdgpu_device *remote_adev = NULL; |
2028 | struct amdgpu_device *adev = ras->adev; | |
2029 | struct list_head device_list, *device_list_handle = NULL; | |
b3dbd6d3 | 2030 | |
f75e94d8 | 2031 | if (!ras->disable_ras_err_cnt_harvest) { |
d95e8e97 DL |
2032 | struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); |
2033 | ||
f75e94d8 GC |
2034 | /* Build list of devices to query RAS related errors */ |
2035 | if (hive && adev->gmc.xgmi.num_physical_nodes > 1) { | |
2036 | device_list_handle = &hive->device_list; | |
2037 | } else { | |
2038 | INIT_LIST_HEAD(&device_list); | |
2039 | list_add_tail(&adev->gmc.xgmi.head, &device_list); | |
2040 | device_list_handle = &device_list; | |
2041 | } | |
c030f2e4 | 2042 | |
f75e94d8 | 2043 | list_for_each_entry(remote_adev, |
3f975d0f SY |
2044 | device_list_handle, gmc.xgmi.head) { |
2045 | amdgpu_ras_query_err_status(remote_adev); | |
f75e94d8 | 2046 | amdgpu_ras_log_on_err_counter(remote_adev); |
3f975d0f | 2047 | } |
d95e8e97 DL |
2048 | |
2049 | amdgpu_put_xgmi_hive(hive); | |
b3dbd6d3 | 2050 | } |
313c8fd3 | 2051 | |
f1549c09 LG |
2052 | if (amdgpu_device_should_recover_gpu(ras->adev)) { |
2053 | struct amdgpu_reset_context reset_context; | |
2054 | memset(&reset_context, 0, sizeof(reset_context)); | |
2055 | ||
2056 | reset_context.method = AMD_RESET_METHOD_NONE; | |
2057 | reset_context.reset_req_dev = adev; | |
1a11a65d YC |
2058 | |
2059 | /* Perform full reset in fatal error mode */ | |
2060 | if (!amdgpu_ras_is_poison_mode_supported(ras->adev)) | |
2061 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
6c47a79b | 2062 | else { |
1a11a65d | 2063 | clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
f1549c09 | 2064 | |
6c47a79b YC |
2065 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE2_RESET) { |
2066 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE2_RESET; | |
2067 | reset_context.method = AMD_RESET_METHOD_MODE2; | |
2068 | } | |
2c7cd280 YC |
2069 | |
2070 | /* Fatal error occurs in poison mode, mode1 reset is used to | |
2071 | * recover gpu. | |
2072 | */ | |
2073 | if (ras->gpu_reset_flags & AMDGPU_RAS_GPU_RESET_MODE1_RESET) { | |
2074 | ras->gpu_reset_flags &= ~AMDGPU_RAS_GPU_RESET_MODE1_RESET; | |
2075 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); | |
1b98a5f8 YC |
2076 | |
2077 | psp_fatal_error_recovery_quirk(&adev->psp); | |
2c7cd280 | 2078 | } |
6c47a79b YC |
2079 | } |
2080 | ||
f1549c09 LG |
2081 | amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context); |
2082 | } | |
c030f2e4 | 2083 | atomic_set(&ras->in_recovery, 0); |
2084 | } | |
2085 | ||
c030f2e4 | 2086 | /* alloc/realloc bps array */ |
2087 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
2088 | struct ras_err_handler_data *data, int pages) | |
2089 | { | |
2090 | unsigned int old_space = data->count + data->space_left; | |
2091 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
2092 | unsigned int align_space = ALIGN(new_space, 512); |
2093 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
9dc23a63 | 2094 | |
676deb38 | 2095 | if (!bps) { |
c030f2e4 | 2096 | return -ENOMEM; |
9dc23a63 | 2097 | } |
c030f2e4 | 2098 | |
2099 | if (data->bps) { | |
9dc23a63 | 2100 | memcpy(bps, data->bps, |
c030f2e4 | 2101 | data->count * sizeof(*data->bps)); |
2102 | kfree(data->bps); | |
2103 | } | |
2104 | ||
9dc23a63 | 2105 | data->bps = bps; |
c030f2e4 | 2106 | data->space_left += align_space - old_space; |
2107 | return 0; | |
2108 | } | |
2109 | ||
2110 | /* it deal with vram only. */ | |
2111 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 2112 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 2113 | { |
2114 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 2115 | struct ras_err_handler_data *data; |
c030f2e4 | 2116 | int ret = 0; |
676deb38 | 2117 | uint32_t i; |
c030f2e4 | 2118 | |
73aa8e1a | 2119 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 2120 | return 0; |
2121 | ||
2122 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 2123 | data = con->eh_data; |
c030f2e4 | 2124 | if (!data) |
2125 | goto out; | |
2126 | ||
676deb38 DL |
2127 | for (i = 0; i < pages; i++) { |
2128 | if (amdgpu_ras_check_bad_page_unlock(con, | |
2129 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT)) | |
2130 | continue; | |
2131 | ||
2132 | if (!data->space_left && | |
2133 | amdgpu_ras_realloc_eh_data_space(adev, data, 256)) { | |
c030f2e4 | 2134 | ret = -ENOMEM; |
2135 | goto out; | |
2136 | } | |
2137 | ||
ec6aae97 | 2138 | amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, |
676deb38 DL |
2139 | bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT, |
2140 | AMDGPU_GPU_PAGE_SIZE); | |
9dc23a63 | 2141 | |
676deb38 DL |
2142 | memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps)); |
2143 | data->count++; | |
2144 | data->space_left--; | |
2145 | } | |
c030f2e4 | 2146 | out: |
2147 | mutex_unlock(&con->recovery_lock); | |
2148 | ||
2149 | return ret; | |
2150 | } | |
2151 | ||
78ad00c9 TZ |
2152 | /* |
2153 | * write error record array to eeprom, the function should be | |
2154 | * protected by recovery_lock | |
4d33e0f1 | 2155 | * new_cnt: new added UE count, excluding reserved bad pages, can be NULL |
78ad00c9 | 2156 | */ |
4d33e0f1 TZ |
2157 | int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev, |
2158 | unsigned long *new_cnt) | |
78ad00c9 TZ |
2159 | { |
2160 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2161 | struct ras_err_handler_data *data; | |
8a3e801f | 2162 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
2163 | int save_count; |
2164 | ||
4d33e0f1 TZ |
2165 | if (!con || !con->eh_data) { |
2166 | if (new_cnt) | |
2167 | *new_cnt = 0; | |
2168 | ||
78ad00c9 | 2169 | return 0; |
4d33e0f1 | 2170 | } |
78ad00c9 | 2171 | |
d9a69fe5 | 2172 | mutex_lock(&con->recovery_lock); |
8a3e801f | 2173 | control = &con->eeprom_control; |
78ad00c9 | 2174 | data = con->eh_data; |
0686627b | 2175 | save_count = data->count - control->ras_num_recs; |
d9a69fe5 | 2176 | mutex_unlock(&con->recovery_lock); |
4d33e0f1 TZ |
2177 | |
2178 | if (new_cnt) | |
2179 | *new_cnt = save_count / adev->umc.retire_unit; | |
2180 | ||
78ad00c9 | 2181 | /* only new entries are saved */ |
b1628425 | 2182 | if (save_count > 0) { |
63d4c081 LT |
2183 | if (amdgpu_ras_eeprom_append(control, |
2184 | &data->bps[control->ras_num_recs], | |
2185 | save_count)) { | |
6952e99c | 2186 | dev_err(adev->dev, "Failed to save EEPROM table data!"); |
78ad00c9 TZ |
2187 | return -EIO; |
2188 | } | |
2189 | ||
b1628425 GC |
2190 | dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count); |
2191 | } | |
2192 | ||
78ad00c9 TZ |
2193 | return 0; |
2194 | } | |
2195 | ||
2196 | /* | |
2197 | * read error record array in eeprom and reserve enough space for | |
2198 | * storing new bad pages | |
2199 | */ | |
2200 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
2201 | { | |
2202 | struct amdgpu_ras_eeprom_control *control = | |
6457205c | 2203 | &adev->psp.ras_context.ras->eeprom_control; |
e4e6a589 LT |
2204 | struct eeprom_table_record *bps; |
2205 | int ret; | |
78ad00c9 TZ |
2206 | |
2207 | /* no bad page record, skip eeprom access */ | |
0686627b | 2208 | if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0) |
e4e6a589 | 2209 | return 0; |
78ad00c9 | 2210 | |
0686627b | 2211 | bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL); |
78ad00c9 TZ |
2212 | if (!bps) |
2213 | return -ENOMEM; | |
2214 | ||
0686627b | 2215 | ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs); |
e4e6a589 | 2216 | if (ret) |
6952e99c | 2217 | dev_err(adev->dev, "Failed to load EEPROM table records!"); |
e4e6a589 | 2218 | else |
0686627b | 2219 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs); |
78ad00c9 | 2220 | |
78ad00c9 TZ |
2221 | kfree(bps); |
2222 | return ret; | |
2223 | } | |
2224 | ||
676deb38 DL |
2225 | static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, |
2226 | uint64_t addr) | |
2227 | { | |
2228 | struct ras_err_handler_data *data = con->eh_data; | |
2229 | int i; | |
2230 | ||
2231 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
2232 | for (i = 0; i < data->count; i++) | |
2233 | if (addr == data->bps[i].retired_page) | |
2234 | return true; | |
2235 | ||
2236 | return false; | |
2237 | } | |
2238 | ||
6e4be987 TZ |
2239 | /* |
2240 | * check if an address belongs to bad page | |
2241 | * | |
2242 | * Note: this check is only for umc block | |
2243 | */ | |
2244 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
2245 | uint64_t addr) | |
2246 | { | |
2247 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
6e4be987 TZ |
2248 | bool ret = false; |
2249 | ||
2250 | if (!con || !con->eh_data) | |
2251 | return ret; | |
2252 | ||
2253 | mutex_lock(&con->recovery_lock); | |
676deb38 | 2254 | ret = amdgpu_ras_check_bad_page_unlock(con, addr); |
6e4be987 TZ |
2255 | mutex_unlock(&con->recovery_lock); |
2256 | return ret; | |
2257 | } | |
2258 | ||
e5c04edf | 2259 | static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, |
e4e6a589 | 2260 | uint32_t max_count) |
c84d4670 | 2261 | { |
e5c04edf | 2262 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
c84d4670 GC |
2263 | |
2264 | /* | |
2265 | * Justification of value bad_page_cnt_threshold in ras structure | |
2266 | * | |
f3cbe70e TZ |
2267 | * Generally, 0 <= amdgpu_bad_page_threshold <= max record length |
2268 | * in eeprom or amdgpu_bad_page_threshold == -2, introduce two | |
2269 | * scenarios accordingly. | |
c84d4670 GC |
2270 | * |
2271 | * Bad page retirement enablement: | |
f3cbe70e | 2272 | * - If amdgpu_bad_page_threshold = -2, |
c84d4670 GC |
2273 | * bad_page_cnt_threshold = typical value by formula. |
2274 | * | |
2275 | * - When the value from user is 0 < amdgpu_bad_page_threshold < | |
2276 | * max record length in eeprom, use it directly. | |
2277 | * | |
2278 | * Bad page retirement disablement: | |
2279 | * - If amdgpu_bad_page_threshold = 0, bad page retirement | |
2280 | * functionality is disabled, and bad_page_cnt_threshold will | |
2281 | * take no effect. | |
2282 | */ | |
2283 | ||
e4e6a589 LT |
2284 | if (amdgpu_bad_page_threshold < 0) { |
2285 | u64 val = adev->gmc.mc_vram_size; | |
c84d4670 | 2286 | |
e4e6a589 | 2287 | do_div(val, RAS_BAD_PAGE_COVER); |
e5c04edf | 2288 | con->bad_page_cnt_threshold = min(lower_32_bits(val), |
e4e6a589 | 2289 | max_count); |
e5c04edf | 2290 | } else { |
e4e6a589 LT |
2291 | con->bad_page_cnt_threshold = min_t(int, max_count, |
2292 | amdgpu_bad_page_threshold); | |
c84d4670 GC |
2293 | } |
2294 | } | |
2295 | ||
1a6fc071 | 2296 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 2297 | { |
2298 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 2299 | struct ras_err_handler_data **data; |
e4e6a589 | 2300 | u32 max_eeprom_records_count = 0; |
b82e65a9 | 2301 | bool exc_err_limit = false; |
78ad00c9 | 2302 | int ret; |
c030f2e4 | 2303 | |
e0e146d5 | 2304 | if (!con || amdgpu_sriov_vf(adev)) |
1d9d2ca8 LT |
2305 | return 0; |
2306 | ||
2307 | /* Allow access to RAS EEPROM via debugfs, when the ASIC | |
2308 | * supports RAS and debugfs is enabled, but when | |
2309 | * adev->ras_enabled is unset, i.e. when "ras_enable" | |
2310 | * module parameter is set to 0. | |
2311 | */ | |
2312 | con->adev = adev; | |
2313 | ||
2314 | if (!adev->ras_enabled) | |
4d1337d2 AG |
2315 | return 0; |
2316 | ||
1d9d2ca8 | 2317 | data = &con->eh_data; |
1a6fc071 TZ |
2318 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
2319 | if (!*data) { | |
2320 | ret = -ENOMEM; | |
2321 | goto out; | |
2322 | } | |
c030f2e4 | 2323 | |
2324 | mutex_init(&con->recovery_lock); | |
2325 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
2326 | atomic_set(&con->in_recovery, 0); | |
69691c82 | 2327 | con->eeprom_control.bad_channel_bitmap = 0; |
c030f2e4 | 2328 | |
7f599fed | 2329 | max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); |
e4e6a589 | 2330 | amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); |
c84d4670 | 2331 | |
e5086659 | 2332 | /* Todo: During test the SMU might fail to read the eeprom through I2C |
2333 | * when the GPU is pending on XGMI reset during probe time | |
2334 | * (Mostly after second bus reset), skip it now | |
2335 | */ | |
2336 | if (adev->gmc.xgmi.pending_reset) | |
2337 | return 0; | |
b82e65a9 GC |
2338 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit); |
2339 | /* | |
2340 | * This calling fails when exc_err_limit is true or | |
2341 | * ret != 0. | |
2342 | */ | |
2343 | if (exc_err_limit || ret) | |
1a6fc071 | 2344 | goto free; |
78ad00c9 | 2345 | |
0686627b | 2346 | if (con->eeprom_control.ras_num_recs) { |
78ad00c9 TZ |
2347 | ret = amdgpu_ras_load_bad_pages(adev); |
2348 | if (ret) | |
1a6fc071 | 2349 | goto free; |
513befa6 | 2350 | |
bc143d8b | 2351 | amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); |
69691c82 SY |
2352 | |
2353 | if (con->update_channel_flag == true) { | |
2354 | amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); | |
2355 | con->update_channel_flag = false; | |
2356 | } | |
78ad00c9 | 2357 | } |
c030f2e4 | 2358 | |
12b2cab7 MJ |
2359 | #ifdef CONFIG_X86_MCE_AMD |
2360 | if ((adev->asic_type == CHIP_ALDEBARAN) && | |
2361 | (adev->gmc.xgmi.connected_to_cpu)) | |
91a1a52d | 2362 | amdgpu_register_bad_pages_mca_notifier(adev); |
12b2cab7 | 2363 | #endif |
c030f2e4 | 2364 | return 0; |
1a6fc071 | 2365 | |
1a6fc071 | 2366 | free: |
1a6fc071 | 2367 | kfree((*data)->bps); |
1a6fc071 | 2368 | kfree(*data); |
1995b3a3 | 2369 | con->eh_data = NULL; |
1a6fc071 | 2370 | out: |
cf696091 | 2371 | dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret); |
1a6fc071 | 2372 | |
b82e65a9 GC |
2373 | /* |
2374 | * Except error threshold exceeding case, other failure cases in this | |
2375 | * function would not fail amdgpu driver init. | |
2376 | */ | |
2377 | if (!exc_err_limit) | |
2378 | ret = 0; | |
2379 | else | |
2380 | ret = -EINVAL; | |
2381 | ||
1a6fc071 | 2382 | return ret; |
c030f2e4 | 2383 | } |
2384 | ||
2385 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
2386 | { | |
2387 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2388 | struct ras_err_handler_data *data = con->eh_data; | |
2389 | ||
1a6fc071 TZ |
2390 | /* recovery_init failed to init it, fini is useless */ |
2391 | if (!data) | |
2392 | return 0; | |
2393 | ||
c030f2e4 | 2394 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 2395 | |
2396 | mutex_lock(&con->recovery_lock); | |
2397 | con->eh_data = NULL; | |
2398 | kfree(data->bps); | |
2399 | kfree(data); | |
2400 | mutex_unlock(&con->recovery_lock); | |
2401 | ||
2402 | return 0; | |
2403 | } | |
2404 | /* recovery end */ | |
2405 | ||
084e2640 | 2406 | static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) |
5436ab94 | 2407 | { |
82835055 | 2408 | if (amdgpu_sriov_vf(adev)) { |
4e8303cf | 2409 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
82835055 | 2410 | case IP_VERSION(13, 0, 2): |
80578f16 | 2411 | case IP_VERSION(13, 0, 6): |
82835055 YC |
2412 | return true; |
2413 | default: | |
2414 | return false; | |
2415 | } | |
2416 | } | |
2417 | ||
073285ef | 2418 | if (adev->asic_type == CHIP_IP_DISCOVERY) { |
4e8303cf | 2419 | switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { |
073285ef | 2420 | case IP_VERSION(13, 0, 0): |
cb906ce3 | 2421 | case IP_VERSION(13, 0, 6): |
073285ef YC |
2422 | case IP_VERSION(13, 0, 10): |
2423 | return true; | |
2424 | default: | |
2425 | return false; | |
2426 | } | |
2427 | } | |
2428 | ||
084e2640 LT |
2429 | return adev->asic_type == CHIP_VEGA10 || |
2430 | adev->asic_type == CHIP_VEGA20 || | |
2431 | adev->asic_type == CHIP_ARCTURUS || | |
75f06251 | 2432 | adev->asic_type == CHIP_ALDEBARAN || |
084e2640 | 2433 | adev->asic_type == CHIP_SIENNA_CICHLID; |
5436ab94 SY |
2434 | } |
2435 | ||
f50160cf SY |
2436 | /* |
2437 | * this is workaround for vega20 workstation sku, | |
2438 | * force enable gfx ras, ignore vbios gfx ras flag | |
2439 | * due to GC EDC can not write | |
2440 | */ | |
e509965e | 2441 | static void amdgpu_ras_get_quirks(struct amdgpu_device *adev) |
f50160cf SY |
2442 | { |
2443 | struct atom_context *ctx = adev->mode_info.atom_context; | |
2444 | ||
2445 | if (!ctx) | |
2446 | return; | |
2447 | ||
adf64e21 ML |
2448 | if (strnstr(ctx->vbios_pn, "D16406", |
2449 | sizeof(ctx->vbios_pn)) || | |
2450 | strnstr(ctx->vbios_pn, "D36002", | |
2451 | sizeof(ctx->vbios_pn))) | |
8ab0d6f0 | 2452 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX); |
f50160cf SY |
2453 | } |
2454 | ||
5caf466a | 2455 | /* |
2456 | * check hardware's ras ability which will be saved in hw_supported. | |
2457 | * if hardware does not support ras, we can skip some ras initializtion and | |
2458 | * forbid some ras operations from IP. | |
2459 | * if software itself, say boot parameter, limit the ras ability. We still | |
2460 | * need allow IP do some limited operations, like disable. In such case, | |
2461 | * we have to initialize ras as normal. but need check if operation is | |
2462 | * allowed or not in each function. | |
2463 | */ | |
e509965e | 2464 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev) |
c030f2e4 | 2465 | { |
8ab0d6f0 | 2466 | adev->ras_hw_enabled = adev->ras_enabled = 0; |
c030f2e4 | 2467 | |
38298ce6 | 2468 | if (!amdgpu_ras_asic_supported(adev)) |
5caf466a | 2469 | return; |
b404ae82 | 2470 | |
38298ce6 | 2471 | if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { |
75f06251 HZ |
2472 | if (amdgpu_atomfirmware_mem_ecc_supported(adev)) { |
2473 | dev_info(adev->dev, "MEM ECC is active.\n"); | |
8ab0d6f0 | 2474 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC | |
e509965e | 2475 | 1 << AMDGPU_RAS_BLOCK__DF); |
75f06251 HZ |
2476 | } else { |
2477 | dev_info(adev->dev, "MEM ECC is not presented.\n"); | |
2478 | } | |
88474cca | 2479 | |
75f06251 HZ |
2480 | if (amdgpu_atomfirmware_sram_ecc_supported(adev)) { |
2481 | dev_info(adev->dev, "SRAM ECC is active.\n"); | |
3189501e | 2482 | if (!amdgpu_sriov_vf(adev)) |
950d6425 SY |
2483 | adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC | |
2484 | 1 << AMDGPU_RAS_BLOCK__DF); | |
3189501e | 2485 | else |
950d6425 SY |
2486 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF | |
2487 | 1 << AMDGPU_RAS_BLOCK__SDMA | | |
2488 | 1 << AMDGPU_RAS_BLOCK__GFX); | |
3189501e TZ |
2489 | |
2490 | /* VCN/JPEG RAS can be supported on both bare metal and | |
2491 | * SRIOV environment | |
2492 | */ | |
4e8303cf LL |
2493 | if (amdgpu_ip_version(adev, VCN_HWIP, 0) == |
2494 | IP_VERSION(2, 6, 0) || | |
2495 | amdgpu_ip_version(adev, VCN_HWIP, 0) == | |
2496 | IP_VERSION(4, 0, 0)) | |
3189501e TZ |
2497 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN | |
2498 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
2499 | else | |
2500 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN | | |
2501 | 1 << AMDGPU_RAS_BLOCK__JPEG); | |
58bc2a9c SY |
2502 | |
2503 | /* | |
2504 | * XGMI RAS is not supported if xgmi num physical nodes | |
2505 | * is zero | |
2506 | */ | |
2507 | if (!adev->gmc.xgmi.num_physical_nodes) | |
2508 | adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__XGMI_WAFL); | |
75f06251 HZ |
2509 | } else { |
2510 | dev_info(adev->dev, "SRAM ECC is not presented.\n"); | |
2511 | } | |
2512 | } else { | |
2513 | /* driver only manages a few IP blocks RAS feature | |
2514 | * when GPU is connected cpu through XGMI */ | |
8ab0d6f0 | 2515 | adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | |
e509965e LT |
2516 | 1 << AMDGPU_RAS_BLOCK__SDMA | |
2517 | 1 << AMDGPU_RAS_BLOCK__MMHUB); | |
75f06251 | 2518 | } |
88474cca | 2519 | |
e509965e | 2520 | amdgpu_ras_get_quirks(adev); |
f50160cf | 2521 | |
88474cca | 2522 | /* hw_supported needs to be aligned with RAS block mask. */ |
8ab0d6f0 | 2523 | adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 2524 | |
276f6e8c SY |
2525 | |
2526 | /* | |
2527 | * Disable ras feature for aqua vanjaram | |
2528 | * by default on apu platform. | |
2529 | */ | |
4e8303cf | 2530 | if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) && |
fcb7a184 | 2531 | adev->gmc.is_app_apu) |
276f6e8c SY |
2532 | adev->ras_enabled = amdgpu_ras_enable != 1 ? 0 : |
2533 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
2534 | else | |
2535 | adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 : | |
2536 | adev->ras_hw_enabled & amdgpu_ras_mask; | |
c030f2e4 | 2537 | } |
2538 | ||
05adfd80 LT |
2539 | static void amdgpu_ras_counte_dw(struct work_struct *work) |
2540 | { | |
2541 | struct amdgpu_ras *con = container_of(work, struct amdgpu_ras, | |
2542 | ras_counte_delay_work.work); | |
2543 | struct amdgpu_device *adev = con->adev; | |
a3fbb0d8 | 2544 | struct drm_device *dev = adev_to_drm(adev); |
05adfd80 LT |
2545 | unsigned long ce_count, ue_count; |
2546 | int res; | |
2547 | ||
2548 | res = pm_runtime_get_sync(dev->dev); | |
2549 | if (res < 0) | |
2550 | goto Out; | |
2551 | ||
2552 | /* Cache new values. | |
2553 | */ | |
4a1c9a44 | 2554 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL) == 0) { |
4d9f771e LT |
2555 | atomic_set(&con->ras_ce_count, ce_count); |
2556 | atomic_set(&con->ras_ue_count, ue_count); | |
2557 | } | |
05adfd80 LT |
2558 | |
2559 | pm_runtime_mark_last_busy(dev->dev); | |
2560 | Out: | |
2561 | pm_runtime_put_autosuspend(dev->dev); | |
2562 | } | |
2563 | ||
2dd9032b TZ |
2564 | static void amdgpu_ras_query_poison_mode(struct amdgpu_device *adev) |
2565 | { | |
2566 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2567 | bool df_poison, umc_poison; | |
2568 | ||
2569 | /* poison setting is useless on SRIOV guest */ | |
2570 | if (amdgpu_sriov_vf(adev) || !con) | |
2571 | return; | |
2572 | ||
2573 | /* Init poison supported flag, the default value is false */ | |
2574 | if (adev->gmc.xgmi.connected_to_cpu) { | |
2575 | /* enabled by default when GPU is connected to CPU */ | |
2576 | con->poison_supported = true; | |
2577 | } else if (adev->df.funcs && | |
2578 | adev->df.funcs->query_ras_poison_mode && | |
2579 | adev->umc.ras && | |
2580 | adev->umc.ras->query_ras_poison_mode) { | |
2581 | df_poison = | |
2582 | adev->df.funcs->query_ras_poison_mode(adev); | |
2583 | umc_poison = | |
2584 | adev->umc.ras->query_ras_poison_mode(adev); | |
2585 | ||
2586 | /* Only poison is set in both DF and UMC, we can support it */ | |
2587 | if (df_poison && umc_poison) | |
2588 | con->poison_supported = true; | |
2589 | else if (df_poison != umc_poison) | |
2590 | dev_warn(adev->dev, | |
2591 | "Poison setting is inconsistent in DF/UMC(%d:%d)!\n", | |
2592 | df_poison, umc_poison); | |
2593 | } | |
2594 | } | |
2595 | ||
c030f2e4 | 2596 | int amdgpu_ras_init(struct amdgpu_device *adev) |
2597 | { | |
2598 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 2599 | int r; |
c030f2e4 | 2600 | |
b404ae82 | 2601 | if (con) |
c030f2e4 | 2602 | return 0; |
2603 | ||
2604 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
640ae42e JC |
2605 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT + |
2606 | sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNT, | |
c030f2e4 | 2607 | GFP_KERNEL|__GFP_ZERO); |
2608 | if (!con) | |
2609 | return -ENOMEM; | |
2610 | ||
05adfd80 LT |
2611 | con->adev = adev; |
2612 | INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw); | |
2613 | atomic_set(&con->ras_ce_count, 0); | |
2614 | atomic_set(&con->ras_ue_count, 0); | |
2615 | ||
c030f2e4 | 2616 | con->objs = (struct ras_manager *)(con + 1); |
2617 | ||
2618 | amdgpu_ras_set_context(adev, con); | |
2619 | ||
e509965e LT |
2620 | amdgpu_ras_check_supported(adev); |
2621 | ||
7ddd9770 | 2622 | if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { |
970fd197 SY |
2623 | /* set gfx block ras context feature for VEGA20 Gaming |
2624 | * send ras disable cmd to ras ta during ras late init. | |
2625 | */ | |
8ab0d6f0 | 2626 | if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { |
970fd197 SY |
2627 | con->features |= BIT(AMDGPU_RAS_BLOCK__GFX); |
2628 | ||
2629 | return 0; | |
2630 | } | |
2631 | ||
5e91160a | 2632 | r = 0; |
5436ab94 | 2633 | goto release_con; |
fb2a3607 HZ |
2634 | } |
2635 | ||
69691c82 | 2636 | con->update_channel_flag = false; |
c030f2e4 | 2637 | con->features = 0; |
2638 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 2639 | /* Might need get this flag from vbios. */ |
2640 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 2641 | |
6e36f231 HZ |
2642 | /* initialize nbio ras function ahead of any other |
2643 | * ras functions so hardware fatal error interrupt | |
2644 | * can be enabled as early as possible */ | |
4e8303cf | 2645 | switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { |
fdc94d3a HZ |
2646 | case IP_VERSION(7, 4, 0): |
2647 | case IP_VERSION(7, 4, 1): | |
2648 | case IP_VERSION(7, 4, 4): | |
2649 | if (!adev->gmc.xgmi.connected_to_cpu) | |
2e54fe5d | 2650 | adev->nbio.ras = &nbio_v7_4_ras; |
6e36f231 | 2651 | break; |
9af357bc HZ |
2652 | case IP_VERSION(4, 3, 0): |
2653 | if (adev->ras_hw_enabled & (1 << AMDGPU_RAS_BLOCK__DF)) | |
2654 | /* unlike other generation of nbio ras, | |
2655 | * nbio v4_3 only support fatal error interrupt | |
2656 | * to inform software that DF is freezed due to | |
2657 | * system fatal error event. driver should not | |
2658 | * enable nbio ras in such case. Instead, | |
2659 | * check DF RAS */ | |
2660 | adev->nbio.ras = &nbio_v4_3_ras; | |
2661 | break; | |
7692e1ee TZ |
2662 | case IP_VERSION(7, 9, 0): |
2663 | if (!adev->gmc.is_app_apu) | |
2664 | adev->nbio.ras = &nbio_v7_9_ras; | |
2665 | break; | |
6e36f231 HZ |
2666 | default: |
2667 | /* nbio ras is not available */ | |
2668 | break; | |
2669 | } | |
2670 | ||
fdc94d3a HZ |
2671 | /* nbio ras block needs to be enabled ahead of other ras blocks |
2672 | * to handle fatal error */ | |
2673 | r = amdgpu_nbio_ras_sw_init(adev); | |
2674 | if (r) | |
2675 | return r; | |
2676 | ||
2e54fe5d | 2677 | if (adev->nbio.ras && |
2678 | adev->nbio.ras->init_ras_controller_interrupt) { | |
2679 | r = adev->nbio.ras->init_ras_controller_interrupt(adev); | |
4e644fff | 2680 | if (r) |
5436ab94 | 2681 | goto release_con; |
4e644fff HZ |
2682 | } |
2683 | ||
2e54fe5d | 2684 | if (adev->nbio.ras && |
2685 | adev->nbio.ras->init_ras_err_event_athub_interrupt) { | |
2686 | r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev); | |
4e644fff | 2687 | if (r) |
5436ab94 | 2688 | goto release_con; |
4e644fff HZ |
2689 | } |
2690 | ||
2dd9032b | 2691 | amdgpu_ras_query_poison_mode(adev); |
e4348849 | 2692 | |
5e91160a GC |
2693 | if (amdgpu_ras_fs_init(adev)) { |
2694 | r = -EINVAL; | |
5436ab94 | 2695 | goto release_con; |
5e91160a | 2696 | } |
c030f2e4 | 2697 | |
6952e99c | 2698 | dev_info(adev->dev, "RAS INFO: ras initialized successfully, " |
e509965e | 2699 | "hardware ability[%x] ras_mask[%x]\n", |
8ab0d6f0 | 2700 | adev->ras_hw_enabled, adev->ras_enabled); |
e509965e | 2701 | |
c030f2e4 | 2702 | return 0; |
5436ab94 | 2703 | release_con: |
c030f2e4 | 2704 | amdgpu_ras_set_context(adev, NULL); |
2705 | kfree(con); | |
2706 | ||
5e91160a | 2707 | return r; |
c030f2e4 | 2708 | } |
2709 | ||
8f6368a9 | 2710 | int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev) |
134d16d5 | 2711 | { |
8107e499 HZ |
2712 | if (adev->gmc.xgmi.connected_to_cpu || |
2713 | adev->gmc.is_app_apu) | |
134d16d5 JC |
2714 | return 1; |
2715 | return 0; | |
2716 | } | |
2717 | ||
2718 | static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev, | |
2719 | struct ras_common_if *ras_block) | |
2720 | { | |
2721 | struct ras_query_if info = { | |
2722 | .head = *ras_block, | |
2723 | }; | |
2724 | ||
2725 | if (!amdgpu_persistent_edc_harvesting_supported(adev)) | |
2726 | return 0; | |
2727 | ||
2728 | if (amdgpu_ras_query_error_status(adev, &info) != 0) | |
2729 | DRM_WARN("RAS init harvest failure"); | |
2730 | ||
2731 | if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0) | |
2732 | DRM_WARN("RAS init harvest reset failure"); | |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | ||
e4348849 TZ |
2737 | bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev) |
2738 | { | |
2739 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2740 | ||
2741 | if (!con) | |
2742 | return false; | |
2743 | ||
2744 | return con->poison_supported; | |
2745 | } | |
2746 | ||
b293e891 | 2747 | /* helper function to handle common stuff in ip late init phase */ |
563285c8 | 2748 | int amdgpu_ras_block_late_init(struct amdgpu_device *adev, |
2749 | struct ras_common_if *ras_block) | |
b293e891 | 2750 | { |
29c9b6cd | 2751 | struct amdgpu_ras_block_object *ras_obj = NULL; |
05adfd80 | 2752 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
4a1c9a44 | 2753 | struct ras_query_if *query_info; |
05adfd80 | 2754 | unsigned long ue_count, ce_count; |
b293e891 HZ |
2755 | int r; |
2756 | ||
2757 | /* disable RAS feature per IP block if it is not supported */ | |
2758 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
2759 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
2760 | return 0; | |
2761 | } | |
2762 | ||
2763 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
2764 | if (r) { | |
9080a18f | 2765 | if (adev->in_suspend || amdgpu_in_reset(adev)) { |
b293e891 HZ |
2766 | /* in resume phase, if fail to enable ras, |
2767 | * clean up all ras fs nodes, and disable ras */ | |
2768 | goto cleanup; | |
2769 | } else | |
2770 | return r; | |
2771 | } | |
2772 | ||
134d16d5 JC |
2773 | /* check for errors on warm reset edc persisant supported ASIC */ |
2774 | amdgpu_persistent_edc_harvesting(adev, ras_block); | |
2775 | ||
b293e891 | 2776 | /* in resume phase, no need to create ras fs node */ |
53b3f8f4 | 2777 | if (adev->in_suspend || amdgpu_in_reset(adev)) |
b293e891 HZ |
2778 | return 0; |
2779 | ||
563285c8 | 2780 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
36780606 TZ |
2781 | if (ras_obj->ras_cb || (ras_obj->hw_ops && |
2782 | (ras_obj->hw_ops->query_poison_status || | |
2783 | ras_obj->hw_ops->handle_poison_consumption))) { | |
9252d33d | 2784 | r = amdgpu_ras_interrupt_add_handler(adev, ras_block); |
b293e891 | 2785 | if (r) |
779596ce | 2786 | goto cleanup; |
b293e891 HZ |
2787 | } |
2788 | ||
f957138c HZ |
2789 | if (ras_obj->hw_ops && |
2790 | (ras_obj->hw_ops->query_ras_error_count || | |
2791 | ras_obj->hw_ops->query_ras_error_status)) { | |
2792 | r = amdgpu_ras_sysfs_create(adev, ras_block); | |
2793 | if (r) | |
2794 | goto interrupt; | |
b293e891 | 2795 | |
f957138c HZ |
2796 | /* Those are the cached values at init. |
2797 | */ | |
2798 | query_info = kzalloc(sizeof(*query_info), GFP_KERNEL); | |
2799 | if (!query_info) | |
2800 | return -ENOMEM; | |
2801 | memcpy(&query_info->head, ras_block, sizeof(struct ras_common_if)); | |
4a1c9a44 | 2802 | |
f957138c HZ |
2803 | if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, query_info) == 0) { |
2804 | atomic_set(&con->ras_ce_count, ce_count); | |
2805 | atomic_set(&con->ras_ue_count, ue_count); | |
2806 | } | |
2807 | ||
2808 | kfree(query_info); | |
4d9f771e | 2809 | } |
05adfd80 | 2810 | |
b293e891 | 2811 | return 0; |
779596ce TR |
2812 | |
2813 | interrupt: | |
563285c8 | 2814 | if (ras_obj->ras_cb) |
9252d33d | 2815 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); |
779596ce | 2816 | cleanup: |
b293e891 HZ |
2817 | amdgpu_ras_feature_enable(adev, ras_block, 0); |
2818 | return r; | |
2819 | } | |
2820 | ||
d41ff22a | 2821 | static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev, |
418abce2 | 2822 | struct ras_common_if *ras_block) |
2823 | { | |
2824 | return amdgpu_ras_block_late_init(adev, ras_block); | |
2825 | } | |
2826 | ||
b293e891 | 2827 | /* helper function to remove ras fs node and interrupt handler */ |
bdb3489c | 2828 | void amdgpu_ras_block_late_fini(struct amdgpu_device *adev, |
2829 | struct ras_common_if *ras_block) | |
2830 | { | |
563285c8 | 2831 | struct amdgpu_ras_block_object *ras_obj; |
bdb3489c | 2832 | if (!ras_block) |
2833 | return; | |
2834 | ||
563285c8 | 2835 | amdgpu_ras_sysfs_remove(adev, ras_block); |
bdb3489c | 2836 | |
563285c8 | 2837 | ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm); |
2838 | if (ras_obj->ras_cb) | |
2839 | amdgpu_ras_interrupt_remove_handler(adev, ras_block); | |
bdb3489c | 2840 | } |
2841 | ||
80e0c2cb | 2842 | static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev, |
2843 | struct ras_common_if *ras_block) | |
2844 | { | |
2845 | return amdgpu_ras_block_late_fini(adev, ras_block); | |
2846 | } | |
2847 | ||
a564808e | 2848 | /* do some init work after IP late init as dependence. |
511fdbc3 | 2849 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 2850 | */ |
511fdbc3 | 2851 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 2852 | { |
2853 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2854 | struct ras_manager *obj, *tmp; | |
2855 | ||
8ab0d6f0 | 2856 | if (!adev->ras_enabled || !con) { |
970fd197 SY |
2857 | /* clean ras context for VEGA20 Gaming after send ras disable cmd */ |
2858 | amdgpu_release_ras_context(adev); | |
2859 | ||
108c6a63 | 2860 | return; |
970fd197 | 2861 | } |
108c6a63 | 2862 | |
108c6a63 | 2863 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 2864 | /* Set up all other IPs which are not implemented. There is a |
2865 | * tricky thing that IP's actual ras error type should be | |
2866 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
2867 | * ERROR_NONE make sense anyway. | |
2868 | */ | |
2869 | amdgpu_ras_enable_all_features(adev, 1); | |
2870 | ||
2871 | /* We enable ras on all hw_supported block, but as boot | |
2872 | * parameter might disable some of them and one or more IP has | |
2873 | * not implemented yet. So we disable them on behalf. | |
2874 | */ | |
108c6a63 | 2875 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
2876 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
2877 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
2878 | /* there should be no any reference. */ | |
2879 | WARN_ON(alive_obj(obj)); | |
2880 | } | |
191051a1 | 2881 | } |
108c6a63 | 2882 | } |
2883 | } | |
2884 | ||
511fdbc3 | 2885 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
2886 | { | |
2887 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2888 | ||
8ab0d6f0 | 2889 | if (!adev->ras_enabled || !con) |
511fdbc3 | 2890 | return; |
2891 | ||
2892 | amdgpu_ras_disable_all_features(adev, 0); | |
2893 | /* Make sure all ras objects are disabled. */ | |
2894 | if (con->features) | |
2895 | amdgpu_ras_disable_all_features(adev, 1); | |
2896 | } | |
2897 | ||
867e24ca | 2898 | int amdgpu_ras_late_init(struct amdgpu_device *adev) |
2899 | { | |
2900 | struct amdgpu_ras_block_list *node, *tmp; | |
2901 | struct amdgpu_ras_block_object *obj; | |
2902 | int r; | |
2903 | ||
950d6425 SY |
2904 | /* Guest side doesn't need init ras feature */ |
2905 | if (amdgpu_sriov_vf(adev)) | |
2906 | return 0; | |
2907 | ||
867e24ca | 2908 | list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { |
2909 | if (!node->ras_obj) { | |
2910 | dev_warn(adev->dev, "Warning: abnormal ras list node.\n"); | |
2911 | continue; | |
2912 | } | |
418abce2 | 2913 | |
867e24ca | 2914 | obj = node->ras_obj; |
2915 | if (obj->ras_late_init) { | |
2916 | r = obj->ras_late_init(adev, &obj->ras_comm); | |
2917 | if (r) { | |
2918 | dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n", | |
2919 | obj->ras_comm.name, r); | |
2920 | return r; | |
2921 | } | |
418abce2 | 2922 | } else |
2923 | amdgpu_ras_block_late_init_default(adev, &obj->ras_comm); | |
867e24ca | 2924 | } |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
c030f2e4 | 2929 | /* do some fini work before IP fini as dependence */ |
2930 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
2931 | { | |
2932 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
2933 | ||
8ab0d6f0 | 2934 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2935 | return 0; |
2936 | ||
72c8c97b | 2937 | |
c030f2e4 | 2938 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ |
642c0401 YC |
2939 | if (con->features) |
2940 | amdgpu_ras_disable_all_features(adev, 0); | |
c030f2e4 | 2941 | amdgpu_ras_recovery_fini(adev); |
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
2946 | { | |
d5e8ff5f | 2947 | struct amdgpu_ras_block_list *ras_node, *tmp; |
1f211a82 | 2948 | struct amdgpu_ras_block_object *obj = NULL; |
c030f2e4 | 2949 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
2950 | ||
8ab0d6f0 | 2951 | if (!adev->ras_enabled || !con) |
c030f2e4 | 2952 | return 0; |
2953 | ||
1f211a82 | 2954 | list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node) { |
2955 | if (ras_node->ras_obj) { | |
2956 | obj = ras_node->ras_obj; | |
2957 | if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) && | |
2958 | obj->ras_fini) | |
2959 | obj->ras_fini(adev, &obj->ras_comm); | |
80e0c2cb | 2960 | else |
2961 | amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm); | |
1f211a82 | 2962 | } |
2963 | ||
2964 | /* Clear ras blocks from ras_list and free ras block list node */ | |
2965 | list_del(&ras_node->node); | |
2966 | kfree(ras_node); | |
2967 | } | |
2968 | ||
c030f2e4 | 2969 | amdgpu_ras_fs_fini(adev); |
2970 | amdgpu_ras_interrupt_remove_all(adev); | |
2971 | ||
2972 | WARN(con->features, "Feature mask is not cleared"); | |
2973 | ||
2974 | if (con->features) | |
2975 | amdgpu_ras_disable_all_features(adev, 1); | |
2976 | ||
05adfd80 LT |
2977 | cancel_delayed_work_sync(&con->ras_counte_delay_work); |
2978 | ||
c030f2e4 | 2979 | amdgpu_ras_set_context(adev, NULL); |
2980 | kfree(con); | |
2981 | ||
2982 | return 0; | |
2983 | } | |
7c6e68c7 AG |
2984 | |
2985 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
2986 | { | |
2987 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { | |
2c7cd280 YC |
2988 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
2989 | ||
6952e99c GC |
2990 | dev_info(adev->dev, "uncorrectable hardware error" |
2991 | "(ERREVENT_ATHUB_INTERRUPT) detected!\n"); | |
d5ea093e | 2992 | |
2c7cd280 | 2993 | ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; |
61934624 | 2994 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
2995 | } |
2996 | } | |
bb5c7235 WS |
2997 | |
2998 | bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev) | |
2999 | { | |
3000 | if (adev->asic_type == CHIP_VEGA20 && | |
3001 | adev->pm.fw_version <= 0x283400) { | |
3002 | return !(amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) && | |
3003 | amdgpu_ras_intr_triggered(); | |
3004 | } | |
3005 | ||
3006 | return false; | |
3007 | } | |
970fd197 SY |
3008 | |
3009 | void amdgpu_release_ras_context(struct amdgpu_device *adev) | |
3010 | { | |
3011 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
3012 | ||
3013 | if (!con) | |
3014 | return; | |
3015 | ||
8ab0d6f0 | 3016 | if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)) { |
970fd197 SY |
3017 | con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX); |
3018 | amdgpu_ras_set_context(adev, NULL); | |
3019 | kfree(con); | |
3020 | } | |
3021 | } | |
12b2cab7 MJ |
3022 | |
3023 | #ifdef CONFIG_X86_MCE_AMD | |
3024 | static struct amdgpu_device *find_adev(uint32_t node_id) | |
3025 | { | |
12b2cab7 MJ |
3026 | int i; |
3027 | struct amdgpu_device *adev = NULL; | |
3028 | ||
91a1a52d MJ |
3029 | for (i = 0; i < mce_adev_list.num_gpu; i++) { |
3030 | adev = mce_adev_list.devs[i]; | |
12b2cab7 | 3031 | |
91a1a52d | 3032 | if (adev && adev->gmc.xgmi.connected_to_cpu && |
12b2cab7 MJ |
3033 | adev->gmc.xgmi.physical_node_id == node_id) |
3034 | break; | |
3035 | adev = NULL; | |
3036 | } | |
3037 | ||
12b2cab7 MJ |
3038 | return adev; |
3039 | } | |
3040 | ||
3041 | #define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) | |
3042 | #define GET_UMC_INST(m) (((m) >> 21) & 0x7) | |
3043 | #define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4)) | |
3044 | #define GPU_ID_OFFSET 8 | |
3045 | ||
3046 | static int amdgpu_bad_page_notifier(struct notifier_block *nb, | |
3047 | unsigned long val, void *data) | |
3048 | { | |
3049 | struct mce *m = (struct mce *)data; | |
3050 | struct amdgpu_device *adev = NULL; | |
3051 | uint32_t gpu_id = 0; | |
cd4c99f1 | 3052 | uint32_t umc_inst = 0, ch_inst = 0; |
12b2cab7 MJ |
3053 | |
3054 | /* | |
3055 | * If the error was generated in UMC_V2, which belongs to GPU UMCs, | |
3056 | * and error occurred in DramECC (Extended error code = 0) then only | |
3057 | * process the error, else bail out. | |
3058 | */ | |
91f75eb4 | 3059 | if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && |
12b2cab7 MJ |
3060 | (XEC(m->status, 0x3f) == 0x0))) |
3061 | return NOTIFY_DONE; | |
3062 | ||
3063 | /* | |
3064 | * If it is correctable error, return. | |
3065 | */ | |
3066 | if (mce_is_correctable(m)) | |
3067 | return NOTIFY_OK; | |
3068 | ||
3069 | /* | |
3070 | * GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register. | |
3071 | */ | |
3072 | gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET; | |
3073 | ||
3074 | adev = find_adev(gpu_id); | |
3075 | if (!adev) { | |
3076 | DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__, | |
3077 | gpu_id); | |
3078 | return NOTIFY_DONE; | |
3079 | } | |
3080 | ||
3081 | /* | |
3082 | * If it is uncorrectable error, then find out UMC instance and | |
3083 | * channel index. | |
3084 | */ | |
3085 | umc_inst = GET_UMC_INST(m->ipid); | |
3086 | ch_inst = GET_CHAN_INDEX(m->ipid); | |
3087 | ||
3088 | dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d", | |
3089 | umc_inst, ch_inst); | |
3090 | ||
24b82292 TZ |
3091 | if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst)) |
3092 | return NOTIFY_OK; | |
3093 | else | |
6c0ca748 | 3094 | return NOTIFY_DONE; |
12b2cab7 MJ |
3095 | } |
3096 | ||
3097 | static struct notifier_block amdgpu_bad_page_nb = { | |
3098 | .notifier_call = amdgpu_bad_page_notifier, | |
3099 | .priority = MCE_PRIO_UC, | |
3100 | }; | |
3101 | ||
91a1a52d | 3102 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) |
12b2cab7 | 3103 | { |
91a1a52d MJ |
3104 | /* |
3105 | * Add the adev to the mce_adev_list. | |
3106 | * During mode2 reset, amdgpu device is temporarily | |
3107 | * removed from the mgpu_info list which can cause | |
3108 | * page retirement to fail. | |
3109 | * Use this list instead of mgpu_info to find the amdgpu | |
3110 | * device on which the UMC error was reported. | |
3111 | */ | |
3112 | mce_adev_list.devs[mce_adev_list.num_gpu++] = adev; | |
3113 | ||
12b2cab7 MJ |
3114 | /* |
3115 | * Register the x86 notifier only once | |
3116 | * with MCE subsystem. | |
3117 | */ | |
3118 | if (notifier_registered == false) { | |
3119 | mce_register_decode_chain(&amdgpu_bad_page_nb); | |
3120 | notifier_registered = true; | |
3121 | } | |
3122 | } | |
3123 | #endif | |
7cab2124 | 3124 | |
b6efdb02 | 3125 | struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) |
7cab2124 | 3126 | { |
3127 | if (!adev) | |
3128 | return NULL; | |
3129 | ||
3130 | return adev->psp.ras_context.ras; | |
3131 | } | |
3132 | ||
b6efdb02 | 3133 | int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con) |
7cab2124 | 3134 | { |
3135 | if (!adev) | |
69f91d32 | 3136 | return -EINVAL; |
7cab2124 | 3137 | |
3138 | adev->psp.ras_context.ras = ras_con; | |
3139 | return 0; | |
3140 | } | |
3141 | ||
3142 | /* check if ras is supported on block, say, sdma, gfx */ | |
3143 | int amdgpu_ras_is_supported(struct amdgpu_device *adev, | |
3144 | unsigned int block) | |
3145 | { | |
8f453c51 | 3146 | int ret = 0; |
7cab2124 | 3147 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); |
3148 | ||
3149 | if (block >= AMDGPU_RAS_BLOCK_COUNT) | |
3150 | return 0; | |
8f453c51 YC |
3151 | |
3152 | ret = ras && (adev->ras_enabled & (1 << block)); | |
3153 | ||
3154 | /* For the special asic with mem ecc enabled but sram ecc | |
3155 | * not enabled, even if the ras block is not supported on | |
3156 | * .ras_enabled, if the asic supports poison mode and the | |
3157 | * ras block has ras configuration, it can be considered | |
3158 | * that the ras block supports ras function. | |
3159 | */ | |
3160 | if (!ret && | |
bc0f8080 CL |
3161 | (block == AMDGPU_RAS_BLOCK__GFX || |
3162 | block == AMDGPU_RAS_BLOCK__SDMA || | |
3163 | block == AMDGPU_RAS_BLOCK__VCN || | |
3164 | block == AMDGPU_RAS_BLOCK__JPEG) && | |
8f453c51 YC |
3165 | amdgpu_ras_is_poison_mode_supported(adev) && |
3166 | amdgpu_ras_get_ras_block(adev, block, 0)) | |
3167 | ret = 1; | |
3168 | ||
3169 | return ret; | |
7cab2124 | 3170 | } |
3171 | ||
3172 | int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) | |
3173 | { | |
3174 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
3175 | ||
3176 | if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) | |
25a2b22e | 3177 | amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); |
7cab2124 | 3178 | return 0; |
3179 | } | |
3180 | ||
3181 | ||
6492e1b0 | 3182 | /* Register each ip ras block into amdgpu ras */ |
3183 | int amdgpu_ras_register_ras_block(struct amdgpu_device *adev, | |
b6efdb02 | 3184 | struct amdgpu_ras_block_object *ras_block_obj) |
6492e1b0 | 3185 | { |
d5e8ff5f | 3186 | struct amdgpu_ras_block_list *ras_node; |
6492e1b0 | 3187 | if (!adev || !ras_block_obj) |
3188 | return -EINVAL; | |
3189 | ||
d5e8ff5f | 3190 | ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL); |
3191 | if (!ras_node) | |
3192 | return -ENOMEM; | |
3193 | ||
3194 | INIT_LIST_HEAD(&ras_node->node); | |
3195 | ras_node->ras_obj = ras_block_obj; | |
3196 | list_add_tail(&ras_node->node, &adev->ras_list); | |
6492e1b0 | 3197 | |
3198 | return 0; | |
3199 | } | |
322a7e00 HZ |
3200 | |
3201 | void amdgpu_ras_get_error_type_name(uint32_t err_type, char *err_type_name) | |
3202 | { | |
3203 | if (!err_type_name) | |
3204 | return; | |
3205 | ||
3206 | switch (err_type) { | |
3207 | case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: | |
3208 | sprintf(err_type_name, "correctable"); | |
3209 | break; | |
3210 | case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: | |
3211 | sprintf(err_type_name, "uncorrectable"); | |
3212 | break; | |
3213 | default: | |
3214 | sprintf(err_type_name, "unknown"); | |
3215 | break; | |
3216 | } | |
3217 | } | |
3218 | ||
3219 | bool amdgpu_ras_inst_get_memory_id_field(struct amdgpu_device *adev, | |
3220 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3221 | uint32_t instance, | |
3222 | uint32_t *memory_id) | |
3223 | { | |
3224 | uint32_t err_status_lo_data, err_status_lo_offset; | |
3225 | ||
3226 | if (!reg_entry) | |
3227 | return false; | |
3228 | ||
3229 | err_status_lo_offset = | |
3230 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3231 | reg_entry->seg_lo, reg_entry->reg_lo); | |
3232 | err_status_lo_data = RREG32(err_status_lo_offset); | |
3233 | ||
3234 | if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && | |
3235 | !REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, ERR_STATUS_VALID_FLAG)) | |
3236 | return false; | |
3237 | ||
3238 | *memory_id = REG_GET_FIELD(err_status_lo_data, ERR_STATUS_LO, MEMORY_ID); | |
3239 | ||
3240 | return true; | |
3241 | } | |
3242 | ||
3243 | bool amdgpu_ras_inst_get_err_cnt_field(struct amdgpu_device *adev, | |
3244 | const struct amdgpu_ras_err_status_reg_entry *reg_entry, | |
3245 | uint32_t instance, | |
3246 | unsigned long *err_cnt) | |
3247 | { | |
3248 | uint32_t err_status_hi_data, err_status_hi_offset; | |
3249 | ||
3250 | if (!reg_entry) | |
3251 | return false; | |
3252 | ||
3253 | err_status_hi_offset = | |
3254 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, | |
3255 | reg_entry->seg_hi, reg_entry->reg_hi); | |
3256 | err_status_hi_data = RREG32(err_status_hi_offset); | |
3257 | ||
3258 | if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && | |
3259 | !REG_GET_FIELD(err_status_hi_data, ERR_STATUS_HI, ERR_INFO_VALID_FLAG)) | |
9b337b7d HZ |
3260 | /* keep the check here in case we need to refer to the result later */ |
3261 | dev_dbg(adev->dev, "Invalid err_info field\n"); | |
322a7e00 HZ |
3262 | |
3263 | /* read err count */ | |
3264 | *err_cnt = REG_GET_FIELD(err_status_hi_data, ERR_STATUS, ERR_CNT); | |
3265 | ||
3266 | return true; | |
3267 | } | |
3268 | ||
3269 | void amdgpu_ras_inst_query_ras_error_count(struct amdgpu_device *adev, | |
3270 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3271 | uint32_t reg_list_size, | |
3272 | const struct amdgpu_ras_memory_id_entry *mem_list, | |
3273 | uint32_t mem_list_size, | |
3274 | uint32_t instance, | |
3275 | uint32_t err_type, | |
3276 | unsigned long *err_count) | |
3277 | { | |
3278 | uint32_t memory_id; | |
3279 | unsigned long err_cnt; | |
3280 | char err_type_name[16]; | |
3281 | uint32_t i, j; | |
3282 | ||
3283 | for (i = 0; i < reg_list_size; i++) { | |
9b337b7d HZ |
3284 | /* query memory_id from err_status_lo */ |
3285 | if (!amdgpu_ras_inst_get_memory_id_field(adev, ®_list[i], | |
3286 | instance, &memory_id)) | |
3287 | continue; | |
3288 | ||
322a7e00 HZ |
3289 | /* query err_cnt from err_status_hi */ |
3290 | if (!amdgpu_ras_inst_get_err_cnt_field(adev, ®_list[i], | |
3291 | instance, &err_cnt) || | |
3292 | !err_cnt) | |
3293 | continue; | |
3294 | ||
322a7e00 HZ |
3295 | *err_count += err_cnt; |
3296 | ||
3297 | /* log the errors */ | |
3298 | amdgpu_ras_get_error_type_name(err_type, err_type_name); | |
3299 | if (!mem_list) { | |
3300 | /* memory_list is not supported */ | |
3301 | dev_info(adev->dev, | |
3302 | "%ld %s hardware errors detected in %s, instance: %d, memory_id: %d\n", | |
3303 | err_cnt, err_type_name, | |
3304 | reg_list[i].block_name, | |
3305 | instance, memory_id); | |
3306 | } else { | |
3307 | for (j = 0; j < mem_list_size; j++) { | |
3308 | if (memory_id == mem_list[j].memory_id) { | |
3309 | dev_info(adev->dev, | |
3310 | "%ld %s hardware errors detected in %s, instance: %d, memory block: %s\n", | |
3311 | err_cnt, err_type_name, | |
3312 | reg_list[i].block_name, | |
3313 | instance, mem_list[j].name); | |
3314 | break; | |
3315 | } | |
3316 | } | |
3317 | } | |
3318 | } | |
3319 | } | |
e53a3250 HZ |
3320 | |
3321 | void amdgpu_ras_inst_reset_ras_error_count(struct amdgpu_device *adev, | |
3322 | const struct amdgpu_ras_err_status_reg_entry *reg_list, | |
3323 | uint32_t reg_list_size, | |
3324 | uint32_t instance) | |
3325 | { | |
3326 | uint32_t err_status_lo_offset, err_status_hi_offset; | |
3327 | uint32_t i; | |
3328 | ||
3329 | for (i = 0; i < reg_list_size; i++) { | |
3330 | err_status_lo_offset = | |
3331 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3332 | reg_list[i].seg_lo, reg_list[i].reg_lo); | |
3333 | err_status_hi_offset = | |
3334 | AMDGPU_RAS_REG_ENTRY_OFFSET(reg_list[i].hwip, instance, | |
3335 | reg_list[i].seg_hi, reg_list[i].reg_hi); | |
3336 | WREG32(err_status_lo_offset, 0); | |
3337 | WREG32(err_status_hi_offset, 0); | |
3338 | } | |
3339 | } |