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c030f2e4 | 1 | /* |
2 | * Copyright 2018 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * | |
23 | */ | |
24 | #include <linux/debugfs.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/module.h> | |
f867723b | 27 | #include <linux/uaccess.h> |
7c6e68c7 AG |
28 | #include <linux/reboot.h> |
29 | #include <linux/syscalls.h> | |
f867723b | 30 | |
c030f2e4 | 31 | #include "amdgpu.h" |
32 | #include "amdgpu_ras.h" | |
b404ae82 | 33 | #include "amdgpu_atomfirmware.h" |
19744f5f | 34 | #include "amdgpu_xgmi.h" |
4e644fff | 35 | #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h" |
c030f2e4 | 36 | |
c030f2e4 | 37 | const char *ras_error_string[] = { |
38 | "none", | |
39 | "parity", | |
40 | "single_correctable", | |
41 | "multi_uncorrectable", | |
42 | "poison", | |
43 | }; | |
44 | ||
45 | const char *ras_block_string[] = { | |
46 | "umc", | |
47 | "sdma", | |
48 | "gfx", | |
49 | "mmhub", | |
50 | "athub", | |
51 | "pcie_bif", | |
52 | "hdp", | |
53 | "xgmi_wafl", | |
54 | "df", | |
55 | "smn", | |
56 | "sem", | |
57 | "mp0", | |
58 | "mp1", | |
59 | "fuse", | |
60 | }; | |
61 | ||
62 | #define ras_err_str(i) (ras_error_string[ffs(i)]) | |
63 | #define ras_block_str(i) (ras_block_string[i]) | |
64 | ||
a564808e | 65 | #define AMDGPU_RAS_FLAG_INIT_BY_VBIOS 1 |
66 | #define AMDGPU_RAS_FLAG_INIT_NEED_RESET 2 | |
108c6a63 | 67 | #define RAS_DEFAULT_FLAGS (AMDGPU_RAS_FLAG_INIT_BY_VBIOS) |
68 | ||
7cdc2ee3 TZ |
69 | /* inject address is 52 bits */ |
70 | #define RAS_UMC_INJECT_ADDR_LIMIT (0x1ULL << 52) | |
71 | ||
52dd95f2 GC |
72 | enum amdgpu_ras_retire_page_reservation { |
73 | AMDGPU_RAS_RETIRE_PAGE_RESERVED, | |
74 | AMDGPU_RAS_RETIRE_PAGE_PENDING, | |
75 | AMDGPU_RAS_RETIRE_PAGE_FAULT, | |
76 | }; | |
7c6e68c7 AG |
77 | |
78 | atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0); | |
79 | ||
6e4be987 TZ |
80 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, |
81 | uint64_t addr); | |
82 | ||
c030f2e4 | 83 | static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf, |
84 | size_t size, loff_t *pos) | |
85 | { | |
86 | struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private; | |
87 | struct ras_query_if info = { | |
88 | .head = obj->head, | |
89 | }; | |
90 | ssize_t s; | |
91 | char val[128]; | |
92 | ||
93 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
94 | return -EINVAL; | |
95 | ||
96 | s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n", | |
97 | "ue", info.ue_count, | |
98 | "ce", info.ce_count); | |
99 | if (*pos >= s) | |
100 | return 0; | |
101 | ||
102 | s -= *pos; | |
103 | s = min_t(u64, s, size); | |
104 | ||
105 | ||
106 | if (copy_to_user(buf, &val[*pos], s)) | |
107 | return -EINVAL; | |
108 | ||
109 | *pos += s; | |
110 | ||
111 | return s; | |
112 | } | |
113 | ||
c030f2e4 | 114 | static const struct file_operations amdgpu_ras_debugfs_ops = { |
115 | .owner = THIS_MODULE, | |
116 | .read = amdgpu_ras_debugfs_read, | |
190211ab | 117 | .write = NULL, |
c030f2e4 | 118 | .llseek = default_llseek |
119 | }; | |
120 | ||
96ebb307 | 121 | static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id) |
122 | { | |
123 | int i; | |
124 | ||
125 | for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { | |
126 | *block_id = i; | |
127 | if (strcmp(name, ras_block_str(i)) == 0) | |
128 | return 0; | |
129 | } | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f, | |
134 | const char __user *buf, size_t size, | |
135 | loff_t *pos, struct ras_debug_if *data) | |
136 | { | |
137 | ssize_t s = min_t(u64, 64, size); | |
138 | char str[65]; | |
139 | char block_name[33]; | |
140 | char err[9] = "ue"; | |
141 | int op = -1; | |
142 | int block_id; | |
44494f96 | 143 | uint32_t sub_block; |
96ebb307 | 144 | u64 address, value; |
145 | ||
146 | if (*pos) | |
147 | return -EINVAL; | |
148 | *pos = size; | |
149 | ||
150 | memset(str, 0, sizeof(str)); | |
151 | memset(data, 0, sizeof(*data)); | |
152 | ||
153 | if (copy_from_user(str, buf, s)) | |
154 | return -EINVAL; | |
155 | ||
156 | if (sscanf(str, "disable %32s", block_name) == 1) | |
157 | op = 0; | |
158 | else if (sscanf(str, "enable %32s %8s", block_name, err) == 2) | |
159 | op = 1; | |
160 | else if (sscanf(str, "inject %32s %8s", block_name, err) == 2) | |
161 | op = 2; | |
b076296b | 162 | else if (str[0] && str[1] && str[2] && str[3]) |
96ebb307 | 163 | /* ascii string, but commands are not matched. */ |
164 | return -EINVAL; | |
165 | ||
166 | if (op != -1) { | |
167 | if (amdgpu_ras_find_block_id_by_name(block_name, &block_id)) | |
168 | return -EINVAL; | |
169 | ||
170 | data->head.block = block_id; | |
e1063493 TZ |
171 | /* only ue and ce errors are supported */ |
172 | if (!memcmp("ue", err, 2)) | |
173 | data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; | |
174 | else if (!memcmp("ce", err, 2)) | |
175 | data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE; | |
176 | else | |
177 | return -EINVAL; | |
178 | ||
96ebb307 | 179 | data->op = op; |
180 | ||
181 | if (op == 2) { | |
44494f96 TZ |
182 | if (sscanf(str, "%*s %*s %*s %u %llu %llu", |
183 | &sub_block, &address, &value) != 3) | |
184 | if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx", | |
185 | &sub_block, &address, &value) != 3) | |
96ebb307 | 186 | return -EINVAL; |
44494f96 | 187 | data->head.sub_block_index = sub_block; |
96ebb307 | 188 | data->inject.address = address; |
189 | data->inject.value = value; | |
190 | } | |
191 | } else { | |
73aa8e1a | 192 | if (size < sizeof(*data)) |
96ebb307 | 193 | return -EINVAL; |
194 | ||
195 | if (copy_from_user(data, buf, sizeof(*data))) | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
199 | return 0; | |
200 | } | |
7c6e68c7 | 201 | |
74abc221 TSD |
202 | /** |
203 | * DOC: AMDGPU RAS debugfs control interface | |
36ea1bd2 | 204 | * |
205 | * It accepts struct ras_debug_if who has two members. | |
206 | * | |
207 | * First member: ras_debug_if::head or ras_debug_if::inject. | |
96ebb307 | 208 | * |
209 | * head is used to indicate which IP block will be under control. | |
36ea1bd2 | 210 | * |
211 | * head has four members, they are block, type, sub_block_index, name. | |
212 | * block: which IP will be under control. | |
213 | * type: what kind of error will be enabled/disabled/injected. | |
214 | * sub_block_index: some IPs have subcomponets. say, GFX, sDMA. | |
215 | * name: the name of IP. | |
216 | * | |
217 | * inject has two more members than head, they are address, value. | |
218 | * As their names indicate, inject operation will write the | |
219 | * value to the address. | |
220 | * | |
ef177d11 | 221 | * The second member: struct ras_debug_if::op. |
c688a06b | 222 | * It has three kinds of operations. |
879e723d AZ |
223 | * |
224 | * - 0: disable RAS on the block. Take ::head as its data. | |
225 | * - 1: enable RAS on the block. Take ::head as its data. | |
226 | * - 2: inject errors on the block. Take ::inject as its data. | |
36ea1bd2 | 227 | * |
96ebb307 | 228 | * How to use the interface? |
ef177d11 AD |
229 | * |
230 | * Programs | |
231 | * | |
232 | * Copy the struct ras_debug_if in your codes and initialize it. | |
233 | * Write the struct to the control node. | |
234 | * | |
235 | * Shells | |
96ebb307 | 236 | * |
879e723d AZ |
237 | * .. code-block:: bash |
238 | * | |
a20bfd0f | 239 | * echo op block [error [sub_block address value]] > .../ras/ras_ctrl |
879e723d | 240 | * |
ef177d11 AD |
241 | * Parameters: |
242 | * | |
879e723d AZ |
243 | * op: disable, enable, inject |
244 | * disable: only block is needed | |
245 | * enable: block and error are needed | |
246 | * inject: error, address, value are needed | |
a20bfd0f | 247 | * block: umc, sdma, gfx, ......... |
879e723d AZ |
248 | * see ras_block_string[] for details |
249 | * error: ue, ce | |
250 | * ue: multi_uncorrectable | |
251 | * ce: single_correctable | |
252 | * sub_block: | |
253 | * sub block index, pass 0 if there is no sub block | |
254 | * | |
255 | * here are some examples for bash commands: | |
256 | * | |
257 | * .. code-block:: bash | |
96ebb307 | 258 | * |
44494f96 TZ |
259 | * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl |
260 | * echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl | |
96ebb307 | 261 | * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl |
262 | * | |
36ea1bd2 | 263 | * How to check the result? |
264 | * | |
265 | * For disable/enable, please check ras features at | |
266 | * /sys/class/drm/card[0/1/2...]/device/ras/features | |
267 | * | |
268 | * For inject, please check corresponding err count at | |
269 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count | |
270 | * | |
879e723d | 271 | * .. note:: |
ef177d11 | 272 | * Operations are only allowed on blocks which are supported. |
879e723d | 273 | * Please check ras mask at /sys/module/amdgpu/parameters/ras_mask |
ef177d11 AD |
274 | * to see which blocks support RAS on a particular asic. |
275 | * | |
36ea1bd2 | 276 | */ |
277 | static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f, const char __user *buf, | |
278 | size_t size, loff_t *pos) | |
279 | { | |
280 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
281 | struct ras_debug_if data; | |
282 | int ret = 0; | |
283 | ||
96ebb307 | 284 | ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data); |
285 | if (ret) | |
36ea1bd2 | 286 | return -EINVAL; |
287 | ||
36ea1bd2 | 288 | if (!amdgpu_ras_is_supported(adev, data.head.block)) |
289 | return -EINVAL; | |
290 | ||
291 | switch (data.op) { | |
292 | case 0: | |
293 | ret = amdgpu_ras_feature_enable(adev, &data.head, 0); | |
294 | break; | |
295 | case 1: | |
296 | ret = amdgpu_ras_feature_enable(adev, &data.head, 1); | |
297 | break; | |
298 | case 2: | |
7cdc2ee3 TZ |
299 | if ((data.inject.address >= adev->gmc.mc_vram_size) || |
300 | (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT)) { | |
301 | ret = -EINVAL; | |
302 | break; | |
303 | } | |
304 | ||
6e4be987 TZ |
305 | /* umc ce/ue error injection for a bad page is not allowed */ |
306 | if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) && | |
307 | amdgpu_ras_check_bad_page(adev, data.inject.address)) { | |
308 | DRM_WARN("RAS WARN: 0x%llx has been marked as bad before error injection!\n", | |
309 | data.inject.address); | |
310 | break; | |
311 | } | |
312 | ||
7cdc2ee3 | 313 | /* data.inject.address is offset instead of absolute gpu address */ |
36ea1bd2 | 314 | ret = amdgpu_ras_error_inject(adev, &data.inject); |
315 | break; | |
96ebb307 | 316 | default: |
317 | ret = -EINVAL; | |
318 | break; | |
374bf7bd | 319 | } |
36ea1bd2 | 320 | |
321 | if (ret) | |
322 | return -EINVAL; | |
323 | ||
324 | return size; | |
325 | } | |
326 | ||
084fe13b AG |
327 | /** |
328 | * DOC: AMDGPU RAS debugfs EEPROM table reset interface | |
329 | * | |
f77c7109 | 330 | * Some boards contain an EEPROM which is used to persistently store a list of |
ef177d11 | 331 | * bad pages which experiences ECC errors in vram. This interface provides |
f77c7109 AD |
332 | * a way to reset the EEPROM, e.g., after testing error injection. |
333 | * | |
334 | * Usage: | |
335 | * | |
336 | * .. code-block:: bash | |
337 | * | |
338 | * echo 1 > ../ras/ras_eeprom_reset | |
339 | * | |
340 | * will reset EEPROM table to 0 entries. | |
341 | * | |
084fe13b AG |
342 | */ |
343 | static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f, const char __user *buf, | |
344 | size_t size, loff_t *pos) | |
345 | { | |
346 | struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; | |
347 | int ret; | |
348 | ||
349 | ret = amdgpu_ras_eeprom_reset_table(&adev->psp.ras.ras->eeprom_control); | |
350 | ||
351 | return ret == 1 ? size : -EIO; | |
352 | } | |
353 | ||
36ea1bd2 | 354 | static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = { |
355 | .owner = THIS_MODULE, | |
356 | .read = NULL, | |
357 | .write = amdgpu_ras_debugfs_ctrl_write, | |
358 | .llseek = default_llseek | |
359 | }; | |
360 | ||
084fe13b AG |
361 | static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = { |
362 | .owner = THIS_MODULE, | |
363 | .read = NULL, | |
364 | .write = amdgpu_ras_debugfs_eeprom_write, | |
365 | .llseek = default_llseek | |
366 | }; | |
367 | ||
f77c7109 AD |
368 | /** |
369 | * DOC: AMDGPU RAS sysfs Error Count Interface | |
370 | * | |
ef177d11 | 371 | * It allows the user to read the error count for each IP block on the gpu through |
f77c7109 AD |
372 | * /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count |
373 | * | |
374 | * It outputs the multiple lines which report the uncorrected (ue) and corrected | |
375 | * (ce) error counts. | |
376 | * | |
377 | * The format of one line is below, | |
378 | * | |
379 | * [ce|ue]: count | |
380 | * | |
381 | * Example: | |
382 | * | |
383 | * .. code-block:: bash | |
384 | * | |
385 | * ue: 0 | |
386 | * ce: 1 | |
387 | * | |
388 | */ | |
c030f2e4 | 389 | static ssize_t amdgpu_ras_sysfs_read(struct device *dev, |
390 | struct device_attribute *attr, char *buf) | |
391 | { | |
392 | struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr); | |
393 | struct ras_query_if info = { | |
394 | .head = obj->head, | |
395 | }; | |
396 | ||
397 | if (amdgpu_ras_error_query(obj->adev, &info)) | |
398 | return -EINVAL; | |
399 | ||
400 | return snprintf(buf, PAGE_SIZE, "%s: %lu\n%s: %lu\n", | |
401 | "ue", info.ue_count, | |
402 | "ce", info.ce_count); | |
403 | } | |
404 | ||
405 | /* obj begin */ | |
406 | ||
407 | #define get_obj(obj) do { (obj)->use++; } while (0) | |
408 | #define alive_obj(obj) ((obj)->use) | |
409 | ||
410 | static inline void put_obj(struct ras_manager *obj) | |
411 | { | |
412 | if (obj && --obj->use == 0) | |
413 | list_del(&obj->node); | |
414 | if (obj && obj->use < 0) { | |
415 | DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", obj->head.name); | |
416 | } | |
417 | } | |
418 | ||
419 | /* make one obj and return it. */ | |
420 | static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev, | |
421 | struct ras_common_if *head) | |
422 | { | |
423 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
424 | struct ras_manager *obj; | |
425 | ||
426 | if (!con) | |
427 | return NULL; | |
428 | ||
429 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
430 | return NULL; | |
431 | ||
432 | obj = &con->objs[head->block]; | |
433 | /* already exist. return obj? */ | |
434 | if (alive_obj(obj)) | |
435 | return NULL; | |
436 | ||
437 | obj->head = *head; | |
438 | obj->adev = adev; | |
439 | list_add(&obj->node, &con->head); | |
440 | get_obj(obj); | |
441 | ||
442 | return obj; | |
443 | } | |
444 | ||
445 | /* return an obj equal to head, or the first when head is NULL */ | |
f2a79be1 | 446 | struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev, |
c030f2e4 | 447 | struct ras_common_if *head) |
448 | { | |
449 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
450 | struct ras_manager *obj; | |
451 | int i; | |
452 | ||
453 | if (!con) | |
454 | return NULL; | |
455 | ||
456 | if (head) { | |
457 | if (head->block >= AMDGPU_RAS_BLOCK_COUNT) | |
458 | return NULL; | |
459 | ||
460 | obj = &con->objs[head->block]; | |
461 | ||
462 | if (alive_obj(obj)) { | |
463 | WARN_ON(head->block != obj->head.block); | |
464 | return obj; | |
465 | } | |
466 | } else { | |
467 | for (i = 0; i < AMDGPU_RAS_BLOCK_COUNT; i++) { | |
468 | obj = &con->objs[i]; | |
469 | if (alive_obj(obj)) { | |
470 | WARN_ON(i != obj->head.block); | |
471 | return obj; | |
472 | } | |
473 | } | |
474 | } | |
475 | ||
476 | return NULL; | |
477 | } | |
478 | /* obj end */ | |
479 | ||
480 | /* feature ctl begin */ | |
481 | static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev, | |
482 | struct ras_common_if *head) | |
483 | { | |
5caf466a | 484 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
485 | ||
486 | return con->hw_supported & BIT(head->block); | |
c030f2e4 | 487 | } |
488 | ||
489 | static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev, | |
490 | struct ras_common_if *head) | |
491 | { | |
492 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
493 | ||
494 | return con->features & BIT(head->block); | |
495 | } | |
496 | ||
497 | /* | |
498 | * if obj is not created, then create one. | |
499 | * set feature enable flag. | |
500 | */ | |
501 | static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
502 | struct ras_common_if *head, int enable) | |
503 | { | |
504 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
505 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
506 | ||
5caf466a | 507 | /* If hardware does not support ras, then do not create obj. |
508 | * But if hardware support ras, we can create the obj. | |
509 | * Ras framework checks con->hw_supported to see if it need do | |
510 | * corresponding initialization. | |
511 | * IP checks con->support to see if it need disable ras. | |
512 | */ | |
c030f2e4 | 513 | if (!amdgpu_ras_is_feature_allowed(adev, head)) |
514 | return 0; | |
515 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
516 | return 0; | |
517 | ||
518 | if (enable) { | |
519 | if (!obj) { | |
520 | obj = amdgpu_ras_create_obj(adev, head); | |
521 | if (!obj) | |
522 | return -EINVAL; | |
523 | } else { | |
524 | /* In case we create obj somewhere else */ | |
525 | get_obj(obj); | |
526 | } | |
527 | con->features |= BIT(head->block); | |
528 | } else { | |
529 | if (obj && amdgpu_ras_is_feature_enabled(adev, head)) { | |
530 | con->features &= ~BIT(head->block); | |
531 | put_obj(obj); | |
532 | } | |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | /* wrapper of psp_ras_enable_features */ | |
539 | int amdgpu_ras_feature_enable(struct amdgpu_device *adev, | |
540 | struct ras_common_if *head, bool enable) | |
541 | { | |
542 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
543 | union ta_ras_cmd_input info; | |
544 | int ret; | |
545 | ||
546 | if (!con) | |
547 | return -EINVAL; | |
548 | ||
549 | if (!enable) { | |
550 | info.disable_features = (struct ta_ras_disable_features_input) { | |
828cfa29 | 551 | .block_id = amdgpu_ras_block_to_ta(head->block), |
552 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 553 | }; |
554 | } else { | |
555 | info.enable_features = (struct ta_ras_enable_features_input) { | |
828cfa29 | 556 | .block_id = amdgpu_ras_block_to_ta(head->block), |
557 | .error_type = amdgpu_ras_error_to_ta(head->type), | |
c030f2e4 | 558 | }; |
559 | } | |
560 | ||
561 | /* Do not enable if it is not allowed. */ | |
562 | WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head)); | |
563 | /* Are we alerady in that state we are going to set? */ | |
564 | if (!(!!enable ^ !!amdgpu_ras_is_feature_enabled(adev, head))) | |
565 | return 0; | |
566 | ||
bff77e86 LM |
567 | if (!amdgpu_ras_intr_triggered()) { |
568 | ret = psp_ras_enable_features(&adev->psp, &info, enable); | |
569 | if (ret) { | |
570 | DRM_ERROR("RAS ERROR: %s %s feature failed ret %d\n", | |
571 | enable ? "enable":"disable", | |
572 | ras_block_str(head->block), | |
573 | ret); | |
574 | if (ret == TA_RAS_STATUS__RESET_NEEDED) | |
575 | return -EAGAIN; | |
576 | return -EINVAL; | |
577 | } | |
c030f2e4 | 578 | } |
579 | ||
580 | /* setup the obj */ | |
581 | __amdgpu_ras_feature_enable(adev, head, enable); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
77de502b | 586 | /* Only used in device probe stage and called only once. */ |
587 | int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, | |
588 | struct ras_common_if *head, bool enable) | |
589 | { | |
590 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
591 | int ret; | |
592 | ||
593 | if (!con) | |
594 | return -EINVAL; | |
595 | ||
596 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { | |
7af23ebe | 597 | if (enable) { |
598 | /* There is no harm to issue a ras TA cmd regardless of | |
599 | * the currecnt ras state. | |
600 | * If current state == target state, it will do nothing | |
601 | * But sometimes it requests driver to reset and repost | |
602 | * with error code -EAGAIN. | |
603 | */ | |
604 | ret = amdgpu_ras_feature_enable(adev, head, 1); | |
605 | /* With old ras TA, we might fail to enable ras. | |
606 | * Log it and just setup the object. | |
607 | * TODO need remove this WA in the future. | |
608 | */ | |
609 | if (ret == -EINVAL) { | |
610 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
611 | if (!ret) | |
612 | DRM_INFO("RAS INFO: %s setup object\n", | |
613 | ras_block_str(head->block)); | |
614 | } | |
615 | } else { | |
616 | /* setup the object then issue a ras TA disable cmd.*/ | |
617 | ret = __amdgpu_ras_feature_enable(adev, head, 1); | |
618 | if (ret) | |
619 | return ret; | |
77de502b | 620 | |
77de502b | 621 | ret = amdgpu_ras_feature_enable(adev, head, 0); |
7af23ebe | 622 | } |
77de502b | 623 | } else |
624 | ret = amdgpu_ras_feature_enable(adev, head, enable); | |
625 | ||
626 | return ret; | |
627 | } | |
628 | ||
c030f2e4 | 629 | static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev, |
630 | bool bypass) | |
631 | { | |
632 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
633 | struct ras_manager *obj, *tmp; | |
634 | ||
635 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
636 | /* bypass psp. | |
637 | * aka just release the obj and corresponding flags | |
638 | */ | |
639 | if (bypass) { | |
640 | if (__amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
641 | break; | |
642 | } else { | |
643 | if (amdgpu_ras_feature_enable(adev, &obj->head, 0)) | |
644 | break; | |
645 | } | |
289d513b | 646 | } |
c030f2e4 | 647 | |
648 | return con->features; | |
649 | } | |
650 | ||
651 | static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev, | |
652 | bool bypass) | |
653 | { | |
654 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
655 | int ras_block_count = AMDGPU_RAS_BLOCK_COUNT; | |
656 | int i; | |
191051a1 | 657 | const enum amdgpu_ras_error_type default_ras_type = |
658 | AMDGPU_RAS_ERROR__NONE; | |
c030f2e4 | 659 | |
660 | for (i = 0; i < ras_block_count; i++) { | |
661 | struct ras_common_if head = { | |
662 | .block = i, | |
191051a1 | 663 | .type = default_ras_type, |
c030f2e4 | 664 | .sub_block_index = 0, |
665 | }; | |
666 | strcpy(head.name, ras_block_str(i)); | |
667 | if (bypass) { | |
668 | /* | |
669 | * bypass psp. vbios enable ras for us. | |
670 | * so just create the obj | |
671 | */ | |
672 | if (__amdgpu_ras_feature_enable(adev, &head, 1)) | |
673 | break; | |
674 | } else { | |
675 | if (amdgpu_ras_feature_enable(adev, &head, 1)) | |
676 | break; | |
677 | } | |
289d513b | 678 | } |
c030f2e4 | 679 | |
680 | return con->features; | |
681 | } | |
682 | /* feature ctl end */ | |
683 | ||
684 | /* query/inject/cure begin */ | |
685 | int amdgpu_ras_error_query(struct amdgpu_device *adev, | |
686 | struct ras_query_if *info) | |
687 | { | |
688 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
6f102dba | 689 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
3e81ee9a | 690 | int i; |
c030f2e4 | 691 | |
692 | if (!obj) | |
693 | return -EINVAL; | |
c030f2e4 | 694 | |
939e2258 HZ |
695 | switch (info->head.block) { |
696 | case AMDGPU_RAS_BLOCK__UMC: | |
045c0216 TZ |
697 | if (adev->umc.funcs->query_ras_error_count) |
698 | adev->umc.funcs->query_ras_error_count(adev, &err_data); | |
13b7c46c TZ |
699 | /* umc query_ras_error_address is also responsible for clearing |
700 | * error status | |
701 | */ | |
702 | if (adev->umc.funcs->query_ras_error_address) | |
703 | adev->umc.funcs->query_ras_error_address(adev, &err_data); | |
939e2258 | 704 | break; |
3e81ee9a HZ |
705 | case AMDGPU_RAS_BLOCK__SDMA: |
706 | if (adev->sdma.funcs->query_ras_error_count) { | |
707 | for (i = 0; i < adev->sdma.num_instances; i++) | |
708 | adev->sdma.funcs->query_ras_error_count(adev, i, | |
709 | &err_data); | |
710 | } | |
711 | break; | |
83b0582c DL |
712 | case AMDGPU_RAS_BLOCK__GFX: |
713 | if (adev->gfx.funcs->query_ras_error_count) | |
714 | adev->gfx.funcs->query_ras_error_count(adev, &err_data); | |
715 | break; | |
9fb2d8de | 716 | case AMDGPU_RAS_BLOCK__MMHUB: |
d65bf1f8 TZ |
717 | if (adev->mmhub.funcs->query_ras_error_count) |
718 | adev->mmhub.funcs->query_ras_error_count(adev, &err_data); | |
9fb2d8de | 719 | break; |
d7bd680d GC |
720 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
721 | if (adev->nbio.funcs->query_ras_error_count) | |
722 | adev->nbio.funcs->query_ras_error_count(adev, &err_data); | |
723 | break; | |
939e2258 HZ |
724 | default: |
725 | break; | |
726 | } | |
05a58345 TZ |
727 | |
728 | obj->err_data.ue_count += err_data.ue_count; | |
729 | obj->err_data.ce_count += err_data.ce_count; | |
730 | ||
c030f2e4 | 731 | info->ue_count = obj->err_data.ue_count; |
732 | info->ce_count = obj->err_data.ce_count; | |
733 | ||
7c6e68c7 | 734 | if (err_data.ce_count) { |
05a58345 TZ |
735 | dev_info(adev->dev, "%ld correctable errors detected in %s block\n", |
736 | obj->err_data.ce_count, ras_block_str(info->head.block)); | |
7c6e68c7 AG |
737 | } |
738 | if (err_data.ue_count) { | |
05a58345 TZ |
739 | dev_info(adev->dev, "%ld uncorrectable errors detected in %s block\n", |
740 | obj->err_data.ue_count, ras_block_str(info->head.block)); | |
7c6e68c7 | 741 | } |
05a58345 | 742 | |
c030f2e4 | 743 | return 0; |
744 | } | |
745 | ||
746 | /* wrapper of psp_ras_trigger_error */ | |
747 | int amdgpu_ras_error_inject(struct amdgpu_device *adev, | |
748 | struct ras_inject_if *info) | |
749 | { | |
750 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
751 | struct ta_ras_trigger_error_input block_info = { | |
828cfa29 | 752 | .block_id = amdgpu_ras_block_to_ta(info->head.block), |
753 | .inject_error_type = amdgpu_ras_error_to_ta(info->head.type), | |
c030f2e4 | 754 | .sub_block_index = info->head.sub_block_index, |
755 | .address = info->address, | |
756 | .value = info->value, | |
757 | }; | |
758 | int ret = 0; | |
759 | ||
760 | if (!obj) | |
761 | return -EINVAL; | |
762 | ||
a6c44d25 JC |
763 | /* Calculate XGMI relative offset */ |
764 | if (adev->gmc.xgmi.num_physical_nodes > 1) { | |
19744f5f HZ |
765 | block_info.address = |
766 | amdgpu_xgmi_get_relative_phy_addr(adev, | |
767 | block_info.address); | |
a6c44d25 JC |
768 | } |
769 | ||
83b0582c DL |
770 | switch (info->head.block) { |
771 | case AMDGPU_RAS_BLOCK__GFX: | |
772 | if (adev->gfx.funcs->ras_error_inject) | |
773 | ret = adev->gfx.funcs->ras_error_inject(adev, info); | |
774 | else | |
775 | ret = -EINVAL; | |
776 | break; | |
777 | case AMDGPU_RAS_BLOCK__UMC: | |
9fb2d8de | 778 | case AMDGPU_RAS_BLOCK__MMHUB: |
f3170352 | 779 | case AMDGPU_RAS_BLOCK__XGMI_WAFL: |
d7bd680d | 780 | case AMDGPU_RAS_BLOCK__PCIE_BIF: |
83b0582c DL |
781 | ret = psp_ras_trigger_error(&adev->psp, &block_info); |
782 | break; | |
783 | default: | |
a5dd40ca HZ |
784 | DRM_INFO("%s error injection is not supported yet\n", |
785 | ras_block_str(info->head.block)); | |
83b0582c | 786 | ret = -EINVAL; |
a5dd40ca HZ |
787 | } |
788 | ||
c030f2e4 | 789 | if (ret) |
790 | DRM_ERROR("RAS ERROR: inject %s error failed ret %d\n", | |
791 | ras_block_str(info->head.block), | |
792 | ret); | |
793 | ||
794 | return ret; | |
795 | } | |
796 | ||
797 | int amdgpu_ras_error_cure(struct amdgpu_device *adev, | |
798 | struct ras_cure_if *info) | |
799 | { | |
800 | /* psp fw has no cure interface for now. */ | |
801 | return 0; | |
802 | } | |
803 | ||
804 | /* get the total error counts on all IPs */ | |
64cc5414 | 805 | unsigned long amdgpu_ras_query_error_count(struct amdgpu_device *adev, |
c030f2e4 | 806 | bool is_ce) |
807 | { | |
808 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
809 | struct ras_manager *obj; | |
810 | struct ras_err_data data = {0, 0}; | |
811 | ||
812 | if (!con) | |
64cc5414 | 813 | return 0; |
c030f2e4 | 814 | |
815 | list_for_each_entry(obj, &con->head, node) { | |
816 | struct ras_query_if info = { | |
817 | .head = obj->head, | |
818 | }; | |
819 | ||
820 | if (amdgpu_ras_error_query(adev, &info)) | |
64cc5414 | 821 | return 0; |
c030f2e4 | 822 | |
823 | data.ce_count += info.ce_count; | |
824 | data.ue_count += info.ue_count; | |
825 | } | |
826 | ||
827 | return is_ce ? data.ce_count : data.ue_count; | |
828 | } | |
829 | /* query/inject/cure end */ | |
830 | ||
831 | ||
832 | /* sysfs begin */ | |
833 | ||
466b1793 | 834 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, |
835 | struct ras_badpage **bps, unsigned int *count); | |
836 | ||
837 | static char *amdgpu_ras_badpage_flags_str(unsigned int flags) | |
838 | { | |
839 | switch (flags) { | |
52dd95f2 | 840 | case AMDGPU_RAS_RETIRE_PAGE_RESERVED: |
466b1793 | 841 | return "R"; |
52dd95f2 | 842 | case AMDGPU_RAS_RETIRE_PAGE_PENDING: |
466b1793 | 843 | return "P"; |
52dd95f2 | 844 | case AMDGPU_RAS_RETIRE_PAGE_FAULT: |
466b1793 | 845 | default: |
846 | return "F"; | |
847 | }; | |
848 | } | |
849 | ||
f77c7109 AD |
850 | /** |
851 | * DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface | |
466b1793 | 852 | * |
853 | * It allows user to read the bad pages of vram on the gpu through | |
854 | * /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages | |
855 | * | |
856 | * It outputs multiple lines, and each line stands for one gpu page. | |
857 | * | |
858 | * The format of one line is below, | |
859 | * gpu pfn : gpu page size : flags | |
860 | * | |
861 | * gpu pfn and gpu page size are printed in hex format. | |
862 | * flags can be one of below character, | |
f77c7109 | 863 | * |
466b1793 | 864 | * R: reserved, this gpu page is reserved and not able to use. |
f77c7109 | 865 | * |
466b1793 | 866 | * P: pending for reserve, this gpu page is marked as bad, will be reserved |
f77c7109 AD |
867 | * in next window of page_reserve. |
868 | * | |
466b1793 | 869 | * F: unable to reserve. this gpu page can't be reserved due to some reasons. |
870 | * | |
f77c7109 AD |
871 | * Examples: |
872 | * | |
873 | * .. code-block:: bash | |
874 | * | |
875 | * 0x00000001 : 0x00001000 : R | |
876 | * 0x00000002 : 0x00001000 : P | |
877 | * | |
466b1793 | 878 | */ |
879 | ||
880 | static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f, | |
881 | struct kobject *kobj, struct bin_attribute *attr, | |
882 | char *buf, loff_t ppos, size_t count) | |
883 | { | |
884 | struct amdgpu_ras *con = | |
885 | container_of(attr, struct amdgpu_ras, badpages_attr); | |
886 | struct amdgpu_device *adev = con->adev; | |
887 | const unsigned int element_size = | |
888 | sizeof("0xabcdabcd : 0x12345678 : R\n") - 1; | |
d6ee400e SA |
889 | unsigned int start = div64_ul(ppos + element_size - 1, element_size); |
890 | unsigned int end = div64_ul(ppos + count - 1, element_size); | |
466b1793 | 891 | ssize_t s = 0; |
892 | struct ras_badpage *bps = NULL; | |
893 | unsigned int bps_count = 0; | |
894 | ||
895 | memset(buf, 0, count); | |
896 | ||
897 | if (amdgpu_ras_badpages_read(adev, &bps, &bps_count)) | |
898 | return 0; | |
899 | ||
900 | for (; start < end && start < bps_count; start++) | |
901 | s += scnprintf(&buf[s], element_size + 1, | |
902 | "0x%08x : 0x%08x : %1s\n", | |
903 | bps[start].bp, | |
904 | bps[start].size, | |
905 | amdgpu_ras_badpage_flags_str(bps[start].flags)); | |
906 | ||
907 | kfree(bps); | |
908 | ||
909 | return s; | |
910 | } | |
911 | ||
c030f2e4 | 912 | static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev, |
913 | struct device_attribute *attr, char *buf) | |
914 | { | |
915 | struct amdgpu_ras *con = | |
916 | container_of(attr, struct amdgpu_ras, features_attr); | |
c030f2e4 | 917 | |
5212a3bd | 918 | return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features); |
c030f2e4 | 919 | } |
920 | ||
921 | static int amdgpu_ras_sysfs_create_feature_node(struct amdgpu_device *adev) | |
922 | { | |
923 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
924 | struct attribute *attrs[] = { | |
925 | &con->features_attr.attr, | |
926 | NULL | |
927 | }; | |
466b1793 | 928 | struct bin_attribute *bin_attrs[] = { |
929 | &con->badpages_attr, | |
930 | NULL | |
931 | }; | |
c030f2e4 | 932 | struct attribute_group group = { |
933 | .name = "ras", | |
934 | .attrs = attrs, | |
466b1793 | 935 | .bin_attrs = bin_attrs, |
c030f2e4 | 936 | }; |
937 | ||
938 | con->features_attr = (struct device_attribute) { | |
939 | .attr = { | |
940 | .name = "features", | |
941 | .mode = S_IRUGO, | |
942 | }, | |
943 | .show = amdgpu_ras_sysfs_features_read, | |
944 | }; | |
466b1793 | 945 | |
946 | con->badpages_attr = (struct bin_attribute) { | |
947 | .attr = { | |
948 | .name = "gpu_vram_bad_pages", | |
949 | .mode = S_IRUGO, | |
950 | }, | |
951 | .size = 0, | |
952 | .private = NULL, | |
953 | .read = amdgpu_ras_sysfs_badpages_read, | |
954 | }; | |
955 | ||
163def43 | 956 | sysfs_attr_init(attrs[0]); |
466b1793 | 957 | sysfs_bin_attr_init(bin_attrs[0]); |
c030f2e4 | 958 | |
959 | return sysfs_create_group(&adev->dev->kobj, &group); | |
960 | } | |
961 | ||
962 | static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev) | |
963 | { | |
964 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
965 | struct attribute *attrs[] = { | |
966 | &con->features_attr.attr, | |
967 | NULL | |
968 | }; | |
466b1793 | 969 | struct bin_attribute *bin_attrs[] = { |
970 | &con->badpages_attr, | |
971 | NULL | |
972 | }; | |
c030f2e4 | 973 | struct attribute_group group = { |
974 | .name = "ras", | |
975 | .attrs = attrs, | |
466b1793 | 976 | .bin_attrs = bin_attrs, |
c030f2e4 | 977 | }; |
978 | ||
979 | sysfs_remove_group(&adev->dev->kobj, &group); | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | int amdgpu_ras_sysfs_create(struct amdgpu_device *adev, | |
985 | struct ras_fs_if *head) | |
986 | { | |
987 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
988 | ||
989 | if (!obj || obj->attr_inuse) | |
990 | return -EINVAL; | |
991 | ||
992 | get_obj(obj); | |
993 | ||
994 | memcpy(obj->fs_data.sysfs_name, | |
995 | head->sysfs_name, | |
996 | sizeof(obj->fs_data.sysfs_name)); | |
997 | ||
998 | obj->sysfs_attr = (struct device_attribute){ | |
999 | .attr = { | |
1000 | .name = obj->fs_data.sysfs_name, | |
1001 | .mode = S_IRUGO, | |
1002 | }, | |
1003 | .show = amdgpu_ras_sysfs_read, | |
1004 | }; | |
163def43 | 1005 | sysfs_attr_init(&obj->sysfs_attr.attr); |
c030f2e4 | 1006 | |
1007 | if (sysfs_add_file_to_group(&adev->dev->kobj, | |
1008 | &obj->sysfs_attr.attr, | |
1009 | "ras")) { | |
1010 | put_obj(obj); | |
1011 | return -EINVAL; | |
1012 | } | |
1013 | ||
1014 | obj->attr_inuse = 1; | |
1015 | ||
1016 | return 0; | |
1017 | } | |
1018 | ||
1019 | int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev, | |
1020 | struct ras_common_if *head) | |
1021 | { | |
1022 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1023 | ||
1024 | if (!obj || !obj->attr_inuse) | |
1025 | return -EINVAL; | |
1026 | ||
1027 | sysfs_remove_file_from_group(&adev->dev->kobj, | |
1028 | &obj->sysfs_attr.attr, | |
1029 | "ras"); | |
1030 | obj->attr_inuse = 0; | |
1031 | put_obj(obj); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev) | |
1037 | { | |
1038 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1039 | struct ras_manager *obj, *tmp; | |
1040 | ||
1041 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1042 | amdgpu_ras_sysfs_remove(adev, &obj->head); | |
1043 | } | |
1044 | ||
1045 | amdgpu_ras_sysfs_remove_feature_node(adev); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | /* sysfs end */ | |
1050 | ||
ef177d11 AD |
1051 | /** |
1052 | * DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors | |
1053 | * | |
1054 | * Normally when there is an uncorrectable error, the driver will reset | |
1055 | * the GPU to recover. However, in the event of an unrecoverable error, | |
1056 | * the driver provides an interface to reboot the system automatically | |
1057 | * in that event. | |
1058 | * | |
1059 | * The following file in debugfs provides that interface: | |
1060 | * /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot | |
1061 | * | |
1062 | * Usage: | |
1063 | * | |
1064 | * .. code-block:: bash | |
1065 | * | |
1066 | * echo true > .../ras/auto_reboot | |
1067 | * | |
1068 | */ | |
c030f2e4 | 1069 | /* debugfs begin */ |
450f30ea | 1070 | static void amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev) |
36ea1bd2 | 1071 | { |
1072 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1073 | struct drm_minor *minor = adev->ddev->primary; | |
36ea1bd2 | 1074 | |
450f30ea | 1075 | con->dir = debugfs_create_dir("ras", minor->debugfs_root); |
012dd14d GC |
1076 | debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, con->dir, |
1077 | adev, &amdgpu_ras_debugfs_ctrl_ops); | |
1078 | debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, con->dir, | |
1079 | adev, &amdgpu_ras_debugfs_eeprom_ops); | |
c688a06b GC |
1080 | |
1081 | /* | |
1082 | * After one uncorrectable error happens, usually GPU recovery will | |
1083 | * be scheduled. But due to the known problem in GPU recovery failing | |
1084 | * to bring GPU back, below interface provides one direct way to | |
1085 | * user to reboot system automatically in such case within | |
1086 | * ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine | |
1087 | * will never be called. | |
1088 | */ | |
1089 | debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, con->dir, | |
1090 | &con->reboot); | |
36ea1bd2 | 1091 | } |
1092 | ||
450f30ea | 1093 | void amdgpu_ras_debugfs_create(struct amdgpu_device *adev, |
c030f2e4 | 1094 | struct ras_fs_if *head) |
1095 | { | |
1096 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1097 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head); | |
c030f2e4 | 1098 | |
1099 | if (!obj || obj->ent) | |
450f30ea | 1100 | return; |
c030f2e4 | 1101 | |
1102 | get_obj(obj); | |
1103 | ||
1104 | memcpy(obj->fs_data.debugfs_name, | |
1105 | head->debugfs_name, | |
1106 | sizeof(obj->fs_data.debugfs_name)); | |
1107 | ||
450f30ea GKH |
1108 | obj->ent = debugfs_create_file(obj->fs_data.debugfs_name, |
1109 | S_IWUGO | S_IRUGO, con->dir, obj, | |
1110 | &amdgpu_ras_debugfs_ops); | |
c030f2e4 | 1111 | } |
1112 | ||
450f30ea | 1113 | void amdgpu_ras_debugfs_remove(struct amdgpu_device *adev, |
c030f2e4 | 1114 | struct ras_common_if *head) |
1115 | { | |
1116 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, head); | |
1117 | ||
1118 | if (!obj || !obj->ent) | |
450f30ea | 1119 | return; |
c030f2e4 | 1120 | |
1121 | debugfs_remove(obj->ent); | |
1122 | obj->ent = NULL; | |
1123 | put_obj(obj); | |
c030f2e4 | 1124 | } |
1125 | ||
450f30ea | 1126 | static void amdgpu_ras_debugfs_remove_all(struct amdgpu_device *adev) |
c030f2e4 | 1127 | { |
1128 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1129 | struct ras_manager *obj, *tmp; | |
1130 | ||
1131 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1132 | amdgpu_ras_debugfs_remove(adev, &obj->head); | |
1133 | } | |
1134 | ||
012dd14d | 1135 | debugfs_remove_recursive(con->dir); |
c030f2e4 | 1136 | con->dir = NULL; |
c030f2e4 | 1137 | } |
1138 | /* debugfs end */ | |
1139 | ||
1140 | /* ras fs */ | |
1141 | ||
1142 | static int amdgpu_ras_fs_init(struct amdgpu_device *adev) | |
1143 | { | |
c030f2e4 | 1144 | amdgpu_ras_sysfs_create_feature_node(adev); |
36ea1bd2 | 1145 | amdgpu_ras_debugfs_create_ctrl_node(adev); |
c030f2e4 | 1146 | |
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static int amdgpu_ras_fs_fini(struct amdgpu_device *adev) | |
1151 | { | |
1152 | amdgpu_ras_debugfs_remove_all(adev); | |
1153 | amdgpu_ras_sysfs_remove_all(adev); | |
1154 | return 0; | |
1155 | } | |
1156 | /* ras fs end */ | |
1157 | ||
1158 | /* ih begin */ | |
1159 | static void amdgpu_ras_interrupt_handler(struct ras_manager *obj) | |
1160 | { | |
1161 | struct ras_ih_data *data = &obj->ih_data; | |
1162 | struct amdgpu_iv_entry entry; | |
1163 | int ret; | |
cf04dfd0 | 1164 | struct ras_err_data err_data = {0, 0, 0, NULL}; |
c030f2e4 | 1165 | |
1166 | while (data->rptr != data->wptr) { | |
1167 | rmb(); | |
1168 | memcpy(&entry, &data->ring[data->rptr], | |
1169 | data->element_size); | |
1170 | ||
1171 | wmb(); | |
1172 | data->rptr = (data->aligned_element_size + | |
1173 | data->rptr) % data->ring_size; | |
1174 | ||
1175 | /* Let IP handle its data, maybe we need get the output | |
1176 | * from the callback to udpate the error type/count, etc | |
1177 | */ | |
1178 | if (data->cb) { | |
cf04dfd0 | 1179 | ret = data->cb(obj->adev, &err_data, &entry); |
c030f2e4 | 1180 | /* ue will trigger an interrupt, and in that case |
1181 | * we need do a reset to recovery the whole system. | |
1182 | * But leave IP do that recovery, here we just dispatch | |
1183 | * the error. | |
1184 | */ | |
bd2280da | 1185 | if (ret == AMDGPU_RAS_SUCCESS) { |
51437623 TZ |
1186 | /* these counts could be left as 0 if |
1187 | * some blocks do not count error number | |
1188 | */ | |
cf04dfd0 | 1189 | obj->err_data.ue_count += err_data.ue_count; |
51437623 | 1190 | obj->err_data.ce_count += err_data.ce_count; |
c030f2e4 | 1191 | } |
c030f2e4 | 1192 | } |
1193 | } | |
1194 | } | |
1195 | ||
1196 | static void amdgpu_ras_interrupt_process_handler(struct work_struct *work) | |
1197 | { | |
1198 | struct ras_ih_data *data = | |
1199 | container_of(work, struct ras_ih_data, ih_work); | |
1200 | struct ras_manager *obj = | |
1201 | container_of(data, struct ras_manager, ih_data); | |
1202 | ||
1203 | amdgpu_ras_interrupt_handler(obj); | |
1204 | } | |
1205 | ||
1206 | int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev, | |
1207 | struct ras_dispatch_if *info) | |
1208 | { | |
1209 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1210 | struct ras_ih_data *data = &obj->ih_data; | |
1211 | ||
1212 | if (!obj) | |
1213 | return -EINVAL; | |
1214 | ||
1215 | if (data->inuse == 0) | |
1216 | return 0; | |
1217 | ||
1218 | /* Might be overflow... */ | |
1219 | memcpy(&data->ring[data->wptr], info->entry, | |
1220 | data->element_size); | |
1221 | ||
1222 | wmb(); | |
1223 | data->wptr = (data->aligned_element_size + | |
1224 | data->wptr) % data->ring_size; | |
1225 | ||
1226 | schedule_work(&data->ih_work); | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
1231 | int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev, | |
1232 | struct ras_ih_if *info) | |
1233 | { | |
1234 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1235 | struct ras_ih_data *data; | |
1236 | ||
1237 | if (!obj) | |
1238 | return -EINVAL; | |
1239 | ||
1240 | data = &obj->ih_data; | |
1241 | if (data->inuse == 0) | |
1242 | return 0; | |
1243 | ||
1244 | cancel_work_sync(&data->ih_work); | |
1245 | ||
1246 | kfree(data->ring); | |
1247 | memset(data, 0, sizeof(*data)); | |
1248 | put_obj(obj); | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev, | |
1254 | struct ras_ih_if *info) | |
1255 | { | |
1256 | struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head); | |
1257 | struct ras_ih_data *data; | |
1258 | ||
1259 | if (!obj) { | |
1260 | /* in case we registe the IH before enable ras feature */ | |
1261 | obj = amdgpu_ras_create_obj(adev, &info->head); | |
1262 | if (!obj) | |
1263 | return -EINVAL; | |
1264 | } else | |
1265 | get_obj(obj); | |
1266 | ||
1267 | data = &obj->ih_data; | |
1268 | /* add the callback.etc */ | |
1269 | *data = (struct ras_ih_data) { | |
1270 | .inuse = 0, | |
1271 | .cb = info->cb, | |
1272 | .element_size = sizeof(struct amdgpu_iv_entry), | |
1273 | .rptr = 0, | |
1274 | .wptr = 0, | |
1275 | }; | |
1276 | ||
1277 | INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler); | |
1278 | ||
1279 | data->aligned_element_size = ALIGN(data->element_size, 8); | |
1280 | /* the ring can store 64 iv entries. */ | |
1281 | data->ring_size = 64 * data->aligned_element_size; | |
1282 | data->ring = kmalloc(data->ring_size, GFP_KERNEL); | |
1283 | if (!data->ring) { | |
1284 | put_obj(obj); | |
1285 | return -ENOMEM; | |
1286 | } | |
1287 | ||
1288 | /* IH is ready */ | |
1289 | data->inuse = 1; | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev) | |
1295 | { | |
1296 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1297 | struct ras_manager *obj, *tmp; | |
1298 | ||
1299 | list_for_each_entry_safe(obj, tmp, &con->head, node) { | |
1300 | struct ras_ih_if info = { | |
1301 | .head = obj->head, | |
1302 | }; | |
1303 | amdgpu_ras_interrupt_remove_handler(adev, &info); | |
1304 | } | |
1305 | ||
1306 | return 0; | |
1307 | } | |
1308 | /* ih end */ | |
1309 | ||
313c8fd3 GC |
1310 | /* traversal all IPs except NBIO to query error counter */ |
1311 | static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) | |
1312 | { | |
1313 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1314 | struct ras_manager *obj; | |
1315 | ||
1316 | if (!con) | |
1317 | return; | |
1318 | ||
1319 | list_for_each_entry(obj, &con->head, node) { | |
1320 | struct ras_query_if info = { | |
1321 | .head = obj->head, | |
1322 | }; | |
1323 | ||
1324 | /* | |
1325 | * PCIE_BIF IP has one different isr by ras controller | |
1326 | * interrupt, the specific ras counter query will be | |
1327 | * done in that isr. So skip such block from common | |
1328 | * sync flood interrupt isr calling. | |
1329 | */ | |
1330 | if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF) | |
1331 | continue; | |
1332 | ||
1333 | amdgpu_ras_error_query(adev, &info); | |
1334 | } | |
1335 | } | |
1336 | ||
c030f2e4 | 1337 | /* recovery begin */ |
466b1793 | 1338 | |
1339 | /* return 0 on success. | |
1340 | * caller need free bps. | |
1341 | */ | |
1342 | static int amdgpu_ras_badpages_read(struct amdgpu_device *adev, | |
1343 | struct ras_badpage **bps, unsigned int *count) | |
1344 | { | |
1345 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1346 | struct ras_err_handler_data *data; | |
1347 | int i = 0; | |
1348 | int ret = 0; | |
1349 | ||
1350 | if (!con || !con->eh_data || !bps || !count) | |
1351 | return -EINVAL; | |
1352 | ||
1353 | mutex_lock(&con->recovery_lock); | |
1354 | data = con->eh_data; | |
1355 | if (!data || data->count == 0) { | |
1356 | *bps = NULL; | |
46cf2fec | 1357 | ret = -EINVAL; |
466b1793 | 1358 | goto out; |
1359 | } | |
1360 | ||
1361 | *bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL); | |
1362 | if (!*bps) { | |
1363 | ret = -ENOMEM; | |
1364 | goto out; | |
1365 | } | |
1366 | ||
1367 | for (; i < data->count; i++) { | |
1368 | (*bps)[i] = (struct ras_badpage){ | |
9dc23a63 | 1369 | .bp = data->bps[i].retired_page, |
466b1793 | 1370 | .size = AMDGPU_GPU_PAGE_SIZE, |
52dd95f2 | 1371 | .flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED, |
466b1793 | 1372 | }; |
1373 | ||
1374 | if (data->last_reserved <= i) | |
52dd95f2 | 1375 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING; |
9dc23a63 | 1376 | else if (data->bps_bo[i] == NULL) |
52dd95f2 | 1377 | (*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT; |
466b1793 | 1378 | } |
1379 | ||
1380 | *count = data->count; | |
1381 | out: | |
1382 | mutex_unlock(&con->recovery_lock); | |
1383 | return ret; | |
1384 | } | |
1385 | ||
c030f2e4 | 1386 | static void amdgpu_ras_do_recovery(struct work_struct *work) |
1387 | { | |
1388 | struct amdgpu_ras *ras = | |
1389 | container_of(work, struct amdgpu_ras, recovery_work); | |
1390 | ||
313c8fd3 GC |
1391 | /* |
1392 | * Query and print non zero error counter per IP block for | |
1393 | * awareness before recovering GPU. | |
1394 | */ | |
1395 | amdgpu_ras_log_on_err_counter(ras->adev); | |
1396 | ||
93af20f7 HZ |
1397 | if (amdgpu_device_should_recover_gpu(ras->adev)) |
1398 | amdgpu_device_gpu_recover(ras->adev, 0); | |
c030f2e4 | 1399 | atomic_set(&ras->in_recovery, 0); |
1400 | } | |
1401 | ||
c030f2e4 | 1402 | /* alloc/realloc bps array */ |
1403 | static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev, | |
1404 | struct ras_err_handler_data *data, int pages) | |
1405 | { | |
1406 | unsigned int old_space = data->count + data->space_left; | |
1407 | unsigned int new_space = old_space + pages; | |
9dc23a63 TZ |
1408 | unsigned int align_space = ALIGN(new_space, 512); |
1409 | void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL); | |
1410 | struct amdgpu_bo **bps_bo = | |
1411 | kmalloc(align_space * sizeof(*data->bps_bo), GFP_KERNEL); | |
1412 | ||
1413 | if (!bps || !bps_bo) { | |
1414 | kfree(bps); | |
1415 | kfree(bps_bo); | |
c030f2e4 | 1416 | return -ENOMEM; |
9dc23a63 | 1417 | } |
c030f2e4 | 1418 | |
1419 | if (data->bps) { | |
9dc23a63 | 1420 | memcpy(bps, data->bps, |
c030f2e4 | 1421 | data->count * sizeof(*data->bps)); |
1422 | kfree(data->bps); | |
1423 | } | |
9dc23a63 TZ |
1424 | if (data->bps_bo) { |
1425 | memcpy(bps_bo, data->bps_bo, | |
1426 | data->count * sizeof(*data->bps_bo)); | |
1427 | kfree(data->bps_bo); | |
1428 | } | |
c030f2e4 | 1429 | |
9dc23a63 TZ |
1430 | data->bps = bps; |
1431 | data->bps_bo = bps_bo; | |
c030f2e4 | 1432 | data->space_left += align_space - old_space; |
1433 | return 0; | |
1434 | } | |
1435 | ||
1436 | /* it deal with vram only. */ | |
1437 | int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev, | |
9dc23a63 | 1438 | struct eeprom_table_record *bps, int pages) |
c030f2e4 | 1439 | { |
1440 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1441 | struct ras_err_handler_data *data; |
c030f2e4 | 1442 | int ret = 0; |
1443 | ||
73aa8e1a | 1444 | if (!con || !con->eh_data || !bps || pages <= 0) |
c030f2e4 | 1445 | return 0; |
1446 | ||
1447 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1448 | data = con->eh_data; |
c030f2e4 | 1449 | if (!data) |
1450 | goto out; | |
1451 | ||
1452 | if (data->space_left <= pages) | |
1453 | if (amdgpu_ras_realloc_eh_data_space(adev, data, pages)) { | |
1454 | ret = -ENOMEM; | |
1455 | goto out; | |
1456 | } | |
1457 | ||
9dc23a63 TZ |
1458 | memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); |
1459 | data->count += pages; | |
c030f2e4 | 1460 | data->space_left -= pages; |
9dc23a63 | 1461 | |
c030f2e4 | 1462 | out: |
1463 | mutex_unlock(&con->recovery_lock); | |
1464 | ||
1465 | return ret; | |
1466 | } | |
1467 | ||
78ad00c9 TZ |
1468 | /* |
1469 | * write error record array to eeprom, the function should be | |
1470 | * protected by recovery_lock | |
1471 | */ | |
1472 | static int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev) | |
1473 | { | |
1474 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1475 | struct ras_err_handler_data *data; | |
8a3e801f | 1476 | struct amdgpu_ras_eeprom_control *control; |
78ad00c9 TZ |
1477 | int save_count; |
1478 | ||
1479 | if (!con || !con->eh_data) | |
1480 | return 0; | |
1481 | ||
8a3e801f | 1482 | control = &con->eeprom_control; |
78ad00c9 TZ |
1483 | data = con->eh_data; |
1484 | save_count = data->count - control->num_recs; | |
1485 | /* only new entries are saved */ | |
1486 | if (save_count > 0) | |
0771b0bf | 1487 | if (amdgpu_ras_eeprom_process_recods(control, |
78ad00c9 TZ |
1488 | &data->bps[control->num_recs], |
1489 | true, | |
1490 | save_count)) { | |
1491 | DRM_ERROR("Failed to save EEPROM table data!"); | |
1492 | return -EIO; | |
1493 | } | |
1494 | ||
1495 | return 0; | |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * read error record array in eeprom and reserve enough space for | |
1500 | * storing new bad pages | |
1501 | */ | |
1502 | static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev) | |
1503 | { | |
1504 | struct amdgpu_ras_eeprom_control *control = | |
1505 | &adev->psp.ras.ras->eeprom_control; | |
1506 | struct eeprom_table_record *bps = NULL; | |
1507 | int ret = 0; | |
1508 | ||
1509 | /* no bad page record, skip eeprom access */ | |
1510 | if (!control->num_recs) | |
1511 | return ret; | |
1512 | ||
1513 | bps = kcalloc(control->num_recs, sizeof(*bps), GFP_KERNEL); | |
1514 | if (!bps) | |
1515 | return -ENOMEM; | |
1516 | ||
1517 | if (amdgpu_ras_eeprom_process_recods(control, bps, false, | |
1518 | control->num_recs)) { | |
1519 | DRM_ERROR("Failed to load EEPROM table records!"); | |
1520 | ret = -EIO; | |
1521 | goto out; | |
1522 | } | |
1523 | ||
1524 | ret = amdgpu_ras_add_bad_pages(adev, bps, control->num_recs); | |
1525 | ||
1526 | out: | |
1527 | kfree(bps); | |
1528 | return ret; | |
1529 | } | |
1530 | ||
6e4be987 TZ |
1531 | /* |
1532 | * check if an address belongs to bad page | |
1533 | * | |
1534 | * Note: this check is only for umc block | |
1535 | */ | |
1536 | static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, | |
1537 | uint64_t addr) | |
1538 | { | |
1539 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1540 | struct ras_err_handler_data *data; | |
1541 | int i; | |
1542 | bool ret = false; | |
1543 | ||
1544 | if (!con || !con->eh_data) | |
1545 | return ret; | |
1546 | ||
1547 | mutex_lock(&con->recovery_lock); | |
1548 | data = con->eh_data; | |
1549 | if (!data) | |
1550 | goto out; | |
1551 | ||
1552 | addr >>= AMDGPU_GPU_PAGE_SHIFT; | |
1553 | for (i = 0; i < data->count; i++) | |
1554 | if (addr == data->bps[i].retired_page) { | |
1555 | ret = true; | |
1556 | goto out; | |
1557 | } | |
1558 | ||
1559 | out: | |
1560 | mutex_unlock(&con->recovery_lock); | |
1561 | return ret; | |
1562 | } | |
1563 | ||
c030f2e4 | 1564 | /* called in gpu recovery/init */ |
1565 | int amdgpu_ras_reserve_bad_pages(struct amdgpu_device *adev) | |
1566 | { | |
1567 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1568 | struct ras_err_handler_data *data; |
c030f2e4 | 1569 | uint64_t bp; |
de7b45ba | 1570 | struct amdgpu_bo *bo = NULL; |
78ad00c9 | 1571 | int i, ret = 0; |
c030f2e4 | 1572 | |
73aa8e1a | 1573 | if (!con || !con->eh_data) |
c030f2e4 | 1574 | return 0; |
1575 | ||
1576 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1577 | data = con->eh_data; |
1578 | if (!data) | |
1579 | goto out; | |
c030f2e4 | 1580 | /* reserve vram at driver post stage. */ |
1581 | for (i = data->last_reserved; i < data->count; i++) { | |
9dc23a63 | 1582 | bp = data->bps[i].retired_page; |
c030f2e4 | 1583 | |
ae115c81 TZ |
1584 | /* There are two cases of reserve error should be ignored: |
1585 | * 1) a ras bad page has been allocated (used by someone); | |
1586 | * 2) a ras bad page has been reserved (duplicate error injection | |
1587 | * for one page); | |
1588 | */ | |
a142ba88 AD |
1589 | if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, |
1590 | AMDGPU_GPU_PAGE_SIZE, | |
de7b45ba CK |
1591 | AMDGPU_GEM_DOMAIN_VRAM, |
1592 | &bo, NULL)) | |
ae115c81 | 1593 | DRM_WARN("RAS WARN: reserve vram for retired page %llx fail\n", bp); |
c030f2e4 | 1594 | |
9dc23a63 | 1595 | data->bps_bo[i] = bo; |
c030f2e4 | 1596 | data->last_reserved = i + 1; |
de7b45ba | 1597 | bo = NULL; |
c030f2e4 | 1598 | } |
78ad00c9 TZ |
1599 | |
1600 | /* continue to save bad pages to eeprom even reesrve_vram fails */ | |
1601 | ret = amdgpu_ras_save_bad_pages(adev); | |
73aa8e1a | 1602 | out: |
c030f2e4 | 1603 | mutex_unlock(&con->recovery_lock); |
78ad00c9 | 1604 | return ret; |
c030f2e4 | 1605 | } |
1606 | ||
1607 | /* called when driver unload */ | |
1608 | static int amdgpu_ras_release_bad_pages(struct amdgpu_device *adev) | |
1609 | { | |
1610 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
73aa8e1a | 1611 | struct ras_err_handler_data *data; |
c030f2e4 | 1612 | struct amdgpu_bo *bo; |
1613 | int i; | |
1614 | ||
73aa8e1a | 1615 | if (!con || !con->eh_data) |
c030f2e4 | 1616 | return 0; |
1617 | ||
1618 | mutex_lock(&con->recovery_lock); | |
73aa8e1a | 1619 | data = con->eh_data; |
1620 | if (!data) | |
1621 | goto out; | |
1622 | ||
c030f2e4 | 1623 | for (i = data->last_reserved - 1; i >= 0; i--) { |
9dc23a63 | 1624 | bo = data->bps_bo[i]; |
c030f2e4 | 1625 | |
de7b45ba | 1626 | amdgpu_bo_free_kernel(&bo, NULL, NULL); |
c030f2e4 | 1627 | |
9dc23a63 | 1628 | data->bps_bo[i] = bo; |
c030f2e4 | 1629 | data->last_reserved = i; |
1630 | } | |
73aa8e1a | 1631 | out: |
c030f2e4 | 1632 | mutex_unlock(&con->recovery_lock); |
1633 | return 0; | |
1634 | } | |
1635 | ||
1a6fc071 | 1636 | int amdgpu_ras_recovery_init(struct amdgpu_device *adev) |
c030f2e4 | 1637 | { |
1638 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4d1337d2 | 1639 | struct ras_err_handler_data **data; |
78ad00c9 | 1640 | int ret; |
c030f2e4 | 1641 | |
4d1337d2 AG |
1642 | if (con) |
1643 | data = &con->eh_data; | |
1644 | else | |
1645 | return 0; | |
1646 | ||
1a6fc071 TZ |
1647 | *data = kmalloc(sizeof(**data), GFP_KERNEL | __GFP_ZERO); |
1648 | if (!*data) { | |
1649 | ret = -ENOMEM; | |
1650 | goto out; | |
1651 | } | |
c030f2e4 | 1652 | |
1653 | mutex_init(&con->recovery_lock); | |
1654 | INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery); | |
1655 | atomic_set(&con->in_recovery, 0); | |
1656 | con->adev = adev; | |
1657 | ||
0771b0bf | 1658 | ret = amdgpu_ras_eeprom_init(&con->eeprom_control); |
78ad00c9 | 1659 | if (ret) |
1a6fc071 | 1660 | goto free; |
78ad00c9 | 1661 | |
0771b0bf | 1662 | if (con->eeprom_control.num_recs) { |
78ad00c9 TZ |
1663 | ret = amdgpu_ras_load_bad_pages(adev); |
1664 | if (ret) | |
1a6fc071 | 1665 | goto free; |
78ad00c9 TZ |
1666 | ret = amdgpu_ras_reserve_bad_pages(adev); |
1667 | if (ret) | |
1a6fc071 | 1668 | goto release; |
78ad00c9 | 1669 | } |
c030f2e4 | 1670 | |
1671 | return 0; | |
1a6fc071 TZ |
1672 | |
1673 | release: | |
1674 | amdgpu_ras_release_bad_pages(adev); | |
1675 | free: | |
1a6fc071 TZ |
1676 | kfree((*data)->bps); |
1677 | kfree((*data)->bps_bo); | |
1678 | kfree(*data); | |
1995b3a3 | 1679 | con->eh_data = NULL; |
1a6fc071 TZ |
1680 | out: |
1681 | DRM_WARN("Failed to initialize ras recovery!\n"); | |
1682 | ||
1683 | return ret; | |
c030f2e4 | 1684 | } |
1685 | ||
1686 | static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |
1687 | { | |
1688 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1689 | struct ras_err_handler_data *data = con->eh_data; | |
1690 | ||
1a6fc071 TZ |
1691 | /* recovery_init failed to init it, fini is useless */ |
1692 | if (!data) | |
1693 | return 0; | |
1694 | ||
c030f2e4 | 1695 | cancel_work_sync(&con->recovery_work); |
c030f2e4 | 1696 | amdgpu_ras_release_bad_pages(adev); |
1697 | ||
1698 | mutex_lock(&con->recovery_lock); | |
1699 | con->eh_data = NULL; | |
1700 | kfree(data->bps); | |
1a6fc071 | 1701 | kfree(data->bps_bo); |
c030f2e4 | 1702 | kfree(data); |
1703 | mutex_unlock(&con->recovery_lock); | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | /* recovery end */ | |
1708 | ||
a564808e | 1709 | /* return 0 if ras will reset gpu and repost.*/ |
1710 | int amdgpu_ras_request_reset_on_boot(struct amdgpu_device *adev, | |
1711 | unsigned int block) | |
1712 | { | |
1713 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1714 | ||
1715 | if (!ras) | |
1716 | return -EINVAL; | |
1717 | ||
1718 | ras->flags |= AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1719 | return 0; | |
1720 | } | |
1721 | ||
5caf466a | 1722 | /* |
1723 | * check hardware's ras ability which will be saved in hw_supported. | |
1724 | * if hardware does not support ras, we can skip some ras initializtion and | |
1725 | * forbid some ras operations from IP. | |
1726 | * if software itself, say boot parameter, limit the ras ability. We still | |
1727 | * need allow IP do some limited operations, like disable. In such case, | |
1728 | * we have to initialize ras as normal. but need check if operation is | |
1729 | * allowed or not in each function. | |
1730 | */ | |
1731 | static void amdgpu_ras_check_supported(struct amdgpu_device *adev, | |
1732 | uint32_t *hw_supported, uint32_t *supported) | |
c030f2e4 | 1733 | { |
5caf466a | 1734 | *hw_supported = 0; |
1735 | *supported = 0; | |
c030f2e4 | 1736 | |
5caf466a | 1737 | if (amdgpu_sriov_vf(adev) || |
baaeb610 HZ |
1738 | (adev->asic_type != CHIP_VEGA20 && |
1739 | adev->asic_type != CHIP_ARCTURUS)) | |
5caf466a | 1740 | return; |
b404ae82 | 1741 | |
5d0f903f | 1742 | if (adev->is_atom_fw && |
1743 | (amdgpu_atomfirmware_mem_ecc_supported(adev) || | |
1744 | amdgpu_atomfirmware_sram_ecc_supported(adev))) | |
5caf466a | 1745 | *hw_supported = AMDGPU_RAS_BLOCK_MASK; |
b404ae82 | 1746 | |
5caf466a | 1747 | *supported = amdgpu_ras_enable == 0 ? |
1748 | 0 : *hw_supported & amdgpu_ras_mask; | |
c030f2e4 | 1749 | } |
1750 | ||
1751 | int amdgpu_ras_init(struct amdgpu_device *adev) | |
1752 | { | |
1753 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
4e644fff | 1754 | int r; |
c030f2e4 | 1755 | |
b404ae82 | 1756 | if (con) |
c030f2e4 | 1757 | return 0; |
1758 | ||
1759 | con = kmalloc(sizeof(struct amdgpu_ras) + | |
1760 | sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNT, | |
1761 | GFP_KERNEL|__GFP_ZERO); | |
1762 | if (!con) | |
1763 | return -ENOMEM; | |
1764 | ||
1765 | con->objs = (struct ras_manager *)(con + 1); | |
1766 | ||
1767 | amdgpu_ras_set_context(adev, con); | |
1768 | ||
5caf466a | 1769 | amdgpu_ras_check_supported(adev, &con->hw_supported, |
1770 | &con->supported); | |
fb2a3607 HZ |
1771 | if (!con->hw_supported) { |
1772 | amdgpu_ras_set_context(adev, NULL); | |
1773 | kfree(con); | |
1774 | return 0; | |
1775 | } | |
1776 | ||
c030f2e4 | 1777 | con->features = 0; |
1778 | INIT_LIST_HEAD(&con->head); | |
108c6a63 | 1779 | /* Might need get this flag from vbios. */ |
1780 | con->flags = RAS_DEFAULT_FLAGS; | |
c030f2e4 | 1781 | |
4e644fff HZ |
1782 | if (adev->nbio.funcs->init_ras_controller_interrupt) { |
1783 | r = adev->nbio.funcs->init_ras_controller_interrupt(adev); | |
1784 | if (r) | |
1785 | return r; | |
1786 | } | |
1787 | ||
1788 | if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) { | |
1789 | r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev); | |
1790 | if (r) | |
1791 | return r; | |
1792 | } | |
1793 | ||
c030f2e4 | 1794 | amdgpu_ras_mask &= AMDGPU_RAS_BLOCK_MASK; |
1795 | ||
c030f2e4 | 1796 | if (amdgpu_ras_fs_init(adev)) |
1797 | goto fs_out; | |
1798 | ||
5d0f903f | 1799 | DRM_INFO("RAS INFO: ras initialized successfully, " |
1800 | "hardware ability[%x] ras_mask[%x]\n", | |
1801 | con->hw_supported, con->supported); | |
c030f2e4 | 1802 | return 0; |
1803 | fs_out: | |
c030f2e4 | 1804 | amdgpu_ras_set_context(adev, NULL); |
1805 | kfree(con); | |
1806 | ||
1807 | return -EINVAL; | |
1808 | } | |
1809 | ||
b293e891 HZ |
1810 | /* helper function to handle common stuff in ip late init phase */ |
1811 | int amdgpu_ras_late_init(struct amdgpu_device *adev, | |
1812 | struct ras_common_if *ras_block, | |
1813 | struct ras_fs_if *fs_info, | |
1814 | struct ras_ih_if *ih_info) | |
1815 | { | |
1816 | int r; | |
1817 | ||
1818 | /* disable RAS feature per IP block if it is not supported */ | |
1819 | if (!amdgpu_ras_is_supported(adev, ras_block->block)) { | |
1820 | amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); | |
1821 | return 0; | |
1822 | } | |
1823 | ||
1824 | r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1); | |
1825 | if (r) { | |
1826 | if (r == -EAGAIN) { | |
1827 | /* request gpu reset. will run again */ | |
1828 | amdgpu_ras_request_reset_on_boot(adev, | |
1829 | ras_block->block); | |
1830 | return 0; | |
1831 | } else if (adev->in_suspend || adev->in_gpu_reset) { | |
1832 | /* in resume phase, if fail to enable ras, | |
1833 | * clean up all ras fs nodes, and disable ras */ | |
1834 | goto cleanup; | |
1835 | } else | |
1836 | return r; | |
1837 | } | |
1838 | ||
1839 | /* in resume phase, no need to create ras fs node */ | |
1840 | if (adev->in_suspend || adev->in_gpu_reset) | |
1841 | return 0; | |
1842 | ||
1843 | if (ih_info->cb) { | |
1844 | r = amdgpu_ras_interrupt_add_handler(adev, ih_info); | |
1845 | if (r) | |
1846 | goto interrupt; | |
1847 | } | |
1848 | ||
1849 | amdgpu_ras_debugfs_create(adev, fs_info); | |
1850 | ||
1851 | r = amdgpu_ras_sysfs_create(adev, fs_info); | |
1852 | if (r) | |
1853 | goto sysfs; | |
1854 | ||
1855 | return 0; | |
1856 | cleanup: | |
1857 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
1858 | sysfs: | |
1859 | amdgpu_ras_debugfs_remove(adev, ras_block); | |
1860 | if (ih_info->cb) | |
1861 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1862 | interrupt: | |
1863 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1864 | return r; | |
1865 | } | |
1866 | ||
1867 | /* helper function to remove ras fs node and interrupt handler */ | |
1868 | void amdgpu_ras_late_fini(struct amdgpu_device *adev, | |
1869 | struct ras_common_if *ras_block, | |
1870 | struct ras_ih_if *ih_info) | |
1871 | { | |
1872 | if (!ras_block || !ih_info) | |
1873 | return; | |
1874 | ||
1875 | amdgpu_ras_sysfs_remove(adev, ras_block); | |
1876 | amdgpu_ras_debugfs_remove(adev, ras_block); | |
1877 | if (ih_info->cb) | |
1878 | amdgpu_ras_interrupt_remove_handler(adev, ih_info); | |
1879 | amdgpu_ras_feature_enable(adev, ras_block, 0); | |
1880 | } | |
1881 | ||
a564808e | 1882 | /* do some init work after IP late init as dependence. |
511fdbc3 | 1883 | * and it runs in resume/gpu reset/booting up cases. |
a564808e | 1884 | */ |
511fdbc3 | 1885 | void amdgpu_ras_resume(struct amdgpu_device *adev) |
108c6a63 | 1886 | { |
1887 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1888 | struct ras_manager *obj, *tmp; | |
1889 | ||
1890 | if (!con) | |
1891 | return; | |
1892 | ||
108c6a63 | 1893 | if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS) { |
191051a1 | 1894 | /* Set up all other IPs which are not implemented. There is a |
1895 | * tricky thing that IP's actual ras error type should be | |
1896 | * MULTI_UNCORRECTABLE, but as driver does not handle it, so | |
1897 | * ERROR_NONE make sense anyway. | |
1898 | */ | |
1899 | amdgpu_ras_enable_all_features(adev, 1); | |
1900 | ||
1901 | /* We enable ras on all hw_supported block, but as boot | |
1902 | * parameter might disable some of them and one or more IP has | |
1903 | * not implemented yet. So we disable them on behalf. | |
1904 | */ | |
108c6a63 | 1905 | list_for_each_entry_safe(obj, tmp, &con->head, node) { |
1906 | if (!amdgpu_ras_is_supported(adev, obj->head.block)) { | |
1907 | amdgpu_ras_feature_enable(adev, &obj->head, 0); | |
1908 | /* there should be no any reference. */ | |
1909 | WARN_ON(alive_obj(obj)); | |
1910 | } | |
191051a1 | 1911 | } |
108c6a63 | 1912 | } |
a564808e | 1913 | |
1914 | if (con->flags & AMDGPU_RAS_FLAG_INIT_NEED_RESET) { | |
1915 | con->flags &= ~AMDGPU_RAS_FLAG_INIT_NEED_RESET; | |
1916 | /* setup ras obj state as disabled. | |
1917 | * for init_by_vbios case. | |
1918 | * if we want to enable ras, just enable it in a normal way. | |
1919 | * If we want do disable it, need setup ras obj as enabled, | |
1920 | * then issue another TA disable cmd. | |
1921 | * See feature_enable_on_boot | |
1922 | */ | |
1923 | amdgpu_ras_disable_all_features(adev, 1); | |
61934624 | 1924 | amdgpu_ras_reset_gpu(adev); |
a564808e | 1925 | } |
108c6a63 | 1926 | } |
1927 | ||
511fdbc3 | 1928 | void amdgpu_ras_suspend(struct amdgpu_device *adev) |
1929 | { | |
1930 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1931 | ||
1932 | if (!con) | |
1933 | return; | |
1934 | ||
1935 | amdgpu_ras_disable_all_features(adev, 0); | |
1936 | /* Make sure all ras objects are disabled. */ | |
1937 | if (con->features) | |
1938 | amdgpu_ras_disable_all_features(adev, 1); | |
1939 | } | |
1940 | ||
c030f2e4 | 1941 | /* do some fini work before IP fini as dependence */ |
1942 | int amdgpu_ras_pre_fini(struct amdgpu_device *adev) | |
1943 | { | |
1944 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1945 | ||
1946 | if (!con) | |
1947 | return 0; | |
1948 | ||
1949 | /* Need disable ras on all IPs here before ip [hw/sw]fini */ | |
1950 | amdgpu_ras_disable_all_features(adev, 0); | |
1951 | amdgpu_ras_recovery_fini(adev); | |
1952 | return 0; | |
1953 | } | |
1954 | ||
1955 | int amdgpu_ras_fini(struct amdgpu_device *adev) | |
1956 | { | |
1957 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | |
1958 | ||
1959 | if (!con) | |
1960 | return 0; | |
1961 | ||
1962 | amdgpu_ras_fs_fini(adev); | |
1963 | amdgpu_ras_interrupt_remove_all(adev); | |
1964 | ||
1965 | WARN(con->features, "Feature mask is not cleared"); | |
1966 | ||
1967 | if (con->features) | |
1968 | amdgpu_ras_disable_all_features(adev, 1); | |
1969 | ||
1970 | amdgpu_ras_set_context(adev, NULL); | |
1971 | kfree(con); | |
1972 | ||
1973 | return 0; | |
1974 | } | |
7c6e68c7 AG |
1975 | |
1976 | void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev) | |
1977 | { | |
ed606f8a AG |
1978 | uint32_t hw_supported, supported; |
1979 | ||
1980 | amdgpu_ras_check_supported(adev, &hw_supported, &supported); | |
1981 | if (!hw_supported) | |
1982 | return; | |
1983 | ||
7c6e68c7 | 1984 | if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1) == 0) { |
d5ea093e AG |
1985 | DRM_WARN("RAS event of type ERREVENT_ATHUB_INTERRUPT detected!\n"); |
1986 | ||
61934624 | 1987 | amdgpu_ras_reset_gpu(adev); |
7c6e68c7 AG |
1988 | } |
1989 | } |