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drm/amdgpu: drop psp v13 query_boot_status implementation
[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_psp.c
CommitLineData
0e5ca0d1
HR		 1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Author: Huang Rui
23 *
24 */
25
26#include <linux/firmware.h>
f89f8c6b 27#include <drm/drm_drv.h>
fdf2f6c5 28
0e5ca0d1
HR		 29#include "amdgpu.h"
30#include "amdgpu_psp.h"
31#include "amdgpu_ucode.h"
44357a1b 32#include "amdgpu_xgmi.h"
0e5ca0d1
HR		 33#include "soc15_common.h"
34#include "psp_v3_1.h"
c1798b54 35#include "psp_v10_0.h"
654f761c 36#include "psp_v11_0.h"
3188fd07 37#include "psp_v11_0_8.h"
6a7a0bdb 38#include "psp_v12_0.h"
ee821083 39#include "psp_v13_0.h"
7e8a3ca9 40#include "psp_v13_0_4.h"
0e5ca0d1 41
bff77e86 42#include "amdgpu_ras.h"
ecaafb7b 43#include "amdgpu_securedisplay.h"
c6a11133 44#include "amdgpu_atomfirmware.h"
bff77e86 45
8424f2cc
LG		 46#define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
47
40e611bd 48static int psp_load_smu_fw(struct psp_context *psp);
25c94b33
CL		 49static int psp_rap_terminate(struct psp_context *psp);
50static int psp_securedisplay_terminate(struct psp_context *psp);
40e611bd 51
aec3bb3a
AD		 52static int psp_ring_init(struct psp_context *psp,
53 enum psp_ring_type ring_type)
54{
55 int ret = 0;
56 struct psp_ring *ring;
57 struct amdgpu_device *adev = psp->adev;
58
59 ring = &psp->km_ring;
60
61 ring->ring_type = ring_type;
62
63 /* allocate 4k Page of Local Frame Buffer memory for ring */
64 ring->ring_size = 0x1000;
65 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
58ab2c08
CK		 66 AMDGPU_GEM_DOMAIN_VRAM |
67 AMDGPU_GEM_DOMAIN_GTT,
aec3bb3a
AD		 68 &adev->firmware.rbuf,
69 &ring->ring_mem_mc_addr,
70 (void **)&ring->ring_mem);
71 if (ret) {
72 ring->ring_size = 0;
73 return ret;
74 }
75
76 return 0;
77}
78
995da6cc
EQ		 79/*
80 * Due to DF Cstate management centralized to PMFW, the firmware
81 * loading sequence will be updated as below:
82 * - Load KDB
83 * - Load SYS_DRV
84 * - Load tOS
85 * - Load PMFW
86 * - Setup TMR
87 * - Load other non-psp fw
88 * - Load ASD
89 * - Load XGMI/RAS/HDCP/DTM TA if any
90 *
91 * This new sequence is required for
b335f289 92 * - Arcturus and onwards
995da6cc
EQ		 93 */
94static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
95{
96 struct amdgpu_device *adev = psp->adev;
97
82d05736
AD		 98 if (amdgpu_sriov_vf(adev)) {
99 psp->pmfw_centralized_cstate_management = false;
995da6cc 100 return;
82d05736 101 }
995da6cc 102
4e8303cf 103 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
48737ac4 104 case IP_VERSION(11, 0, 0):
82d05736 105 case IP_VERSION(11, 0, 4):
48737ac4 106 case IP_VERSION(11, 0, 5):
82d05736
AD		 107 case IP_VERSION(11, 0, 7):
108 case IP_VERSION(11, 0, 9):
109 case IP_VERSION(11, 0, 11):
110 case IP_VERSION(11, 0, 12):
111 case IP_VERSION(11, 0, 13):
911a7504 112 case IP_VERSION(13, 0, 0):
82d05736 113 case IP_VERSION(13, 0, 2):
438a937d 114 case IP_VERSION(13, 0, 7):
995da6cc 115 psp->pmfw_centralized_cstate_management = true;
82d05736
AD		 116 break;
117 default:
118 psp->pmfw_centralized_cstate_management = false;
119 break;
120 }
995da6cc
EQ		 121}
122
2d39c7ae
ML		 123static int psp_init_sriov_microcode(struct psp_context *psp)
124{
125 struct amdgpu_device *adev = psp->adev;
126 char ucode_prefix[30];
127 int ret = 0;
128
129 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
130
4e8303cf 131 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
2d39c7ae 132 case IP_VERSION(9, 0, 0):
2d39c7ae 133 case IP_VERSION(11, 0, 7):
62a27480 134 case IP_VERSION(11, 0, 9):
2d39c7ae
ML		 135 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
136 ret = psp_init_cap_microcode(psp, ucode_prefix);
137 break;
138 case IP_VERSION(13, 0, 2):
139 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
140 ret = psp_init_cap_microcode(psp, ucode_prefix);
141 ret &= psp_init_ta_microcode(psp, ucode_prefix);
142 break;
143 case IP_VERSION(13, 0, 0):
144 adev->virt.autoload_ucode_id = 0;
145 break;
63630c9e
GW		 146 case IP_VERSION(13, 0, 6):
147 ret = psp_init_cap_microcode(psp, ucode_prefix);
e24b2fda 148 ret &= psp_init_ta_microcode(psp, ucode_prefix);
63630c9e 149 break;
2d39c7ae
ML		 150 case IP_VERSION(13, 0, 10):
151 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
3cd658de 152 ret = psp_init_cap_microcode(psp, ucode_prefix);
2d39c7ae
ML		 153 break;
154 default:
155 return -EINVAL;
156 }
157 return ret;
158}
159
0e5ca0d1
HR		 160static int psp_early_init(void *handle)
161{
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
9d6fea57 163 struct psp_context *psp = &adev->psp;
0e5ca0d1 164
4e8303cf 165 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
82d05736 166 case IP_VERSION(9, 0, 0):
e7f9ccb4 167 psp_v3_1_set_psp_funcs(psp);
1d1f41cf 168 psp->autoload_supported = false;
0e5ca0d1 169 break;
82d05736
AD		 170 case IP_VERSION(10, 0, 0):
171 case IP_VERSION(10, 0, 1):
e7f9ccb4 172 psp_v10_0_set_psp_funcs(psp);
1d1f41cf 173 psp->autoload_supported = false;
c1798b54 174 break;
82d05736
AD		 175 case IP_VERSION(11, 0, 2):
176 case IP_VERSION(11, 0, 4):
1d1f41cf
HZ		 177 psp_v11_0_set_psp_funcs(psp);
178 psp->autoload_supported = false;
179 break;
82d05736 180 case IP_VERSION(11, 0, 0):
e7347f1c
ML		 181 case IP_VERSION(11, 0, 7):
182 adev->psp.sup_pd_fw_up = !amdgpu_sriov_vf(adev);
183 fallthrough;
82d05736
AD		 184 case IP_VERSION(11, 0, 5):
185 case IP_VERSION(11, 0, 9):
82d05736
AD		 186 case IP_VERSION(11, 0, 11):
187 case IP_VERSION(11, 5, 0):
188 case IP_VERSION(11, 0, 12):
189 case IP_VERSION(11, 0, 13):
654f761c 190 psp_v11_0_set_psp_funcs(psp);
1d1f41cf 191 psp->autoload_supported = true;
654f761c 192 break;
82d05736
AD		 193 case IP_VERSION(11, 0, 3):
194 case IP_VERSION(12, 0, 1):
6a7a0bdb
AL		 195 psp_v12_0_set_psp_funcs(psp);
196 break;
82d05736 197 case IP_VERSION(13, 0, 2):
55f86c2b 198 case IP_VERSION(13, 0, 6):
ee821083
HZ		 199 psp_v13_0_set_psp_funcs(psp);
200 break;
82d05736
AD		 201 case IP_VERSION(13, 0, 1):
202 case IP_VERSION(13, 0, 3):
d7fd297c 203 case IP_VERSION(13, 0, 5):
f99a7eb2 204 case IP_VERSION(13, 0, 8):
2c83e3fd 205 case IP_VERSION(13, 0, 11):
14b2760f 206 case IP_VERSION(14, 0, 0):
903bb18b
AL		 207 psp_v13_0_set_psp_funcs(psp);
208 psp->autoload_supported = true;
209 break;
82d05736 210 case IP_VERSION(11, 0, 8):
dfcc3e8c 211 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
3188fd07
LY		 212 psp_v11_0_8_set_psp_funcs(psp);
213 psp->autoload_supported = false;
214 }
215 break;
911a7504 216 case IP_VERSION(13, 0, 0):
438a937d 217 case IP_VERSION(13, 0, 7):
521289d2 218 case IP_VERSION(13, 0, 10):
911a7504
LG		 219 psp_v13_0_set_psp_funcs(psp);
220 psp->autoload_supported = true;
e7347f1c 221 adev->psp.sup_ifwi_up = !amdgpu_sriov_vf(adev);
911a7504 222 break;
7e8a3ca9
XD		 223 case IP_VERSION(13, 0, 4):
224 psp_v13_0_4_set_psp_funcs(psp);
225 psp->autoload_supported = true;
226 break;
0e5ca0d1
HR		 227 default:
228 return -EINVAL;
229 }
230
231 psp->adev = adev;
232
995da6cc
EQ		 233 psp_check_pmfw_centralized_cstate_management(psp);
234
2d39c7ae
ML		 235 if (amdgpu_sriov_vf(adev))
236 return psp_init_sriov_microcode(psp);
237 else
238 return psp_init_microcode(psp);
9d6fea57
AD		 239}
240
e2c34219
AW		 241void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
242{
243 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
244 &mem_ctx->shared_buf);
96e1a88f 245 mem_ctx->shared_bo = NULL;
e2c34219
AW		 246}
247
da40bf8f
AD		 248static void psp_free_shared_bufs(struct psp_context *psp)
249{
250 void *tmr_buf;
251 void **pptr;
252
253 /* free TMR memory buffer */
254 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
255 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
96e1a88f 256 psp->tmr_bo = NULL;
da40bf8f
AD		 257
258 /* free xgmi shared memory */
259 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
260
261 /* free ras shared memory */
262 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
263
264 /* free hdcp shared memory */
265 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
266
267 /* free dtm shared memory */
268 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
269
270 /* free rap shared memory */
271 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
272
273 /* free securedisplay shared memory */
274 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
275
276
277}
278
963cee55
LG		 279static void psp_memory_training_fini(struct psp_context *psp)
280{
281 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
282
283 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
284 kfree(ctx->sys_cache);
285 ctx->sys_cache = NULL;
286}
287
288static int psp_memory_training_init(struct psp_context *psp)
289{
290 int ret;
291 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
292
293 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
ac3ff8a9 294 dev_dbg(psp->adev->dev, "memory training is not supported!\n");
963cee55
LG		 295 return 0;
296 }
297
298 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
299 if (ctx->sys_cache == NULL) {
ac3ff8a9 300 dev_err(psp->adev->dev, "alloc mem_train_ctx.sys_cache failed!\n");
963cee55
LG		 301 ret = -ENOMEM;
302 goto Err_out;
303 }
304
ac3ff8a9
HZ		 305 dev_dbg(psp->adev->dev,
306 "train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
307 ctx->train_data_size,
308 ctx->p2c_train_data_offset,
309 ctx->c2p_train_data_offset);
963cee55
LG		 310 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
311 return 0;
312
313Err_out:
314 psp_memory_training_fini(psp);
315 return ret;
316}
317
3d689ae4
HZ		 318/*
319 * Helper funciton to query psp runtime database entry
320 *
321 * @adev: amdgpu_device pointer
322 * @entry_type: the type of psp runtime database entry
323 * @db_entry: runtime database entry pointer
324 *
325 * Return false if runtime database doesn't exit or entry is invalid
326 * or true if the specific database entry is found, and copy to @db_entry
327 */
328static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
329 enum psp_runtime_entry_type entry_type,
330 void *db_entry)
331{
332 uint64_t db_header_pos, db_dir_pos;
333 struct psp_runtime_data_header db_header = {0};
334 struct psp_runtime_data_directory db_dir = {0};
335 bool ret = false;
336 int i;
337
4e8303cf 338 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6))
cbd442ce
LL		 339 return false;
340
3d689ae4
HZ		 341 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
342 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
343
344 /* read runtime db header from vram */
345 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
346 sizeof(struct psp_runtime_data_header), false);
347
348 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
349 /* runtime db doesn't exist, exit */
96b810d8 350 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
3d689ae4
HZ		 351 return false;
352 }
353
354 /* read runtime database entry from vram */
355 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
356 sizeof(struct psp_runtime_data_directory), false);
357
358 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
359 /* invalid db entry count, exit */
360 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
361 return false;
362 }
363
364 /* look up for requested entry type */
365 for (i = 0; i < db_dir.entry_count && !ret; i++) {
366 if (db_dir.entry_list[i].entry_type == entry_type) {
367 switch (entry_type) {
368 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
369 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
370 /* invalid db entry size */
7f318f4e 371 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
3d689ae4
HZ		 372 return false;
373 }
374 /* read runtime database entry */
375 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
376 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
377 ret = true;
378 break;
7f318f4e
LG		 379 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
380 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
381 /* invalid db entry size */
382 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
383 return false;
384 }
385 /* read runtime database entry */
386 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
387 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
388 ret = true;
389 break;
3d689ae4
HZ		 390 default:
391 ret = false;
392 break;
393 }
394 }
395 }
396
397 return ret;
398}
399
9d6fea57
AD		 400static int psp_sw_init(void *handle)
401{
402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
403 struct psp_context *psp = &adev->psp;
404 int ret;
8e6e054d 405 struct psp_runtime_boot_cfg_entry boot_cfg_entry;
3a07101b 406 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
7f318f4e 407 struct psp_runtime_scpm_entry scpm_entry;
9d6fea57 408
4fb93071
CL		 409 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
410 if (!psp->cmd) {
ac3ff8a9 411 dev_err(adev->dev, "Failed to allocate memory to command buffer!\n");
4fb93071
CL		 412 ret = -ENOMEM;
413 }
414
6f172ae5
JK		 415 adev->psp.xgmi_context.supports_extended_data =
416 !adev->gmc.xgmi.connected_to_cpu &&
4e8303cf 417 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2);
6f172ae5 418
7f318f4e
LG		 419 memset(&scpm_entry, 0, sizeof(scpm_entry));
420 if ((psp_get_runtime_db_entry(adev,
421 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
422 &scpm_entry)) &&
f14c8c3e 423 (scpm_entry.scpm_status != SCPM_DISABLE)) {
7f318f4e
LG		 424 adev->scpm_enabled = true;
425 adev->scpm_status = scpm_entry.scpm_status;
426 } else {
427 adev->scpm_enabled = false;
428 adev->scpm_status = SCPM_DISABLE;
429 }
430
431 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
432
8e6e054d
HZ		 433 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
434 if (psp_get_runtime_db_entry(adev,
435 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
3a07101b 436 &boot_cfg_entry)) {
8e6e054d 437 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
3a07101b
HZ		 438 if ((psp->boot_cfg_bitmask) &
439 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
440 /* If psp runtime database exists, then
441 * only enable two stage memory training
442 * when TWO_STAGE_DRAM_TRAINING bit is set
2d5c0415
PS		 443 * in runtime database
444 */
3a07101b
HZ		 445 mem_training_ctx->enable_mem_training = true;
446 }
8e6e054d 447
3a07101b 448 } else {
2d5c0415
PS		 449 /* If psp runtime database doesn't exist or is
450 * invalid, force enable two stage memory training
451 */
3a07101b 452 mem_training_ctx->enable_mem_training = true;
0586a059 453 }
3a07101b
HZ		 454
455 if (mem_training_ctx->enable_mem_training) {
456 ret = psp_memory_training_init(psp);
457 if (ret) {
ac3ff8a9 458 dev_err(adev->dev, "Failed to initialize memory training!\n");
3a07101b
HZ		 459 return ret;
460 }
461
462 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
463 if (ret) {
ac3ff8a9 464 dev_err(adev->dev, "Failed to process memory training!\n");
3a07101b
HZ		 465 return ret;
466 }
0586a059
TY		 467 }
468
b95b5391 469 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
d20e1aec 470 (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ?
b95b5391
AD		 471 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
472 &psp->fw_pri_bo,
473 &psp->fw_pri_mc_addr,
474 &psp->fw_pri_buf);
475 if (ret)
476 return ret;
477
478 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
228ce176
RB		 479 AMDGPU_GEM_DOMAIN_VRAM |
480 AMDGPU_GEM_DOMAIN_GTT,
b95b5391
AD		 481 &psp->fence_buf_bo,
482 &psp->fence_buf_mc_addr,
483 &psp->fence_buf);
484 if (ret)
485 goto failed1;
486
487 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
228ce176
RB		 488 AMDGPU_GEM_DOMAIN_VRAM |
489 AMDGPU_GEM_DOMAIN_GTT,
b95b5391
AD		 490 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
491 (void **)&psp->cmd_buf_mem);
492 if (ret)
493 goto failed2;
494
0e5ca0d1 495 return 0;
b95b5391
AD		 496
497failed2:
b95b5391
AD		 498 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
499 &psp->fence_buf_mc_addr, &psp->fence_buf);
6b4cf4a3
ML		 500failed1:
501 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
502 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
b95b5391 503 return ret;
0e5ca0d1
HR		 504}
505
506static int psp_sw_fini(void *handle)
507{
c833d8aa 508 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4fb93071
CL		 509 struct psp_context *psp = &adev->psp;
510 struct psp_gfx_cmd_resp *cmd = psp->cmd;
c833d8aa 511
4fb93071 512 psp_memory_training_fini(psp);
5a2a19b7 513
07dbfc6b
ML		 514 amdgpu_ucode_release(&psp->sos_fw);
515 amdgpu_ucode_release(&psp->asd_fw);
516 amdgpu_ucode_release(&psp->ta_fw);
517 amdgpu_ucode_release(&psp->cap_fw);
518 amdgpu_ucode_release(&psp->toc_fw);
5a2a19b7 519
4fb93071
CL		 520 kfree(cmd);
521 cmd = NULL;
522
01382501
LY		 523 psp_free_shared_bufs(psp);
524
83d29a5f
YC		 525 if (psp->km_ring.ring_mem)
526 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
527 &psp->km_ring.ring_mem_mc_addr,
528 (void **)&psp->km_ring.ring_mem);
529
b95b5391
AD		 530 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
531 &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
532 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
533 &psp->fence_buf_mc_addr, &psp->fence_buf);
534 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
535 (void **)&psp->cmd_buf_mem);
536
0e5ca0d1
HR		 537 return 0;
538}
539
540int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
541 uint32_t reg_val, uint32_t mask, bool check_changed)
542{
543 uint32_t val;
544 int i;
545 struct amdgpu_device *adev = psp->adev;
546
7afefb81 547 if (psp->adev->no_hw_access)
bf36b52e
AG		 548 return 0;
549
0e5ca0d1 550 for (i = 0; i < adev->usec_timeout; i++) {
2890decf 551 val = RREG32(reg_index);
0e5ca0d1
HR		 552 if (check_changed) {
553 if (val != reg_val)
554 return 0;
555 } else {
556 if ((val & mask) == reg_val)
557 return 0;
558 }
559 udelay(1);
560 }
561
562 return -ETIME;
563}
564
d4a4ff1c
LG		 565int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
566 uint32_t reg_val, uint32_t mask, uint32_t msec_timeout)
567{
568 uint32_t val;
569 int i;
570 struct amdgpu_device *adev = psp->adev;
571
572 if (psp->adev->no_hw_access)
573 return 0;
574
575 for (i = 0; i < msec_timeout; i++) {
576 val = RREG32(reg_index);
577 if ((val & mask) == reg_val)
578 return 0;
579 msleep(1);
580 }
581
582 return -ETIME;
583}
584
dc739d18
LY		 585static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
586{
587 switch (cmd_id) {
588 case GFX_CMD_ID_LOAD_TA:
589 return "LOAD_TA";
590 case GFX_CMD_ID_UNLOAD_TA:
591 return "UNLOAD_TA";
592 case GFX_CMD_ID_INVOKE_CMD:
593 return "INVOKE_CMD";
594 case GFX_CMD_ID_LOAD_ASD:
595 return "LOAD_ASD";
596 case GFX_CMD_ID_SETUP_TMR:
597 return "SETUP_TMR";
598 case GFX_CMD_ID_LOAD_IP_FW:
599 return "LOAD_IP_FW";
600 case GFX_CMD_ID_DESTROY_TMR:
601 return "DESTROY_TMR";
602 case GFX_CMD_ID_SAVE_RESTORE:
603 return "SAVE_RESTORE_IP_FW";
604 case GFX_CMD_ID_SETUP_VMR:
605 return "SETUP_VMR";
606 case GFX_CMD_ID_DESTROY_VMR:
607 return "DESTROY_VMR";
608 case GFX_CMD_ID_PROG_REG:
609 return "PROG_REG";
610 case GFX_CMD_ID_GET_FW_ATTESTATION:
611 return "GET_FW_ATTESTATION";
612 case GFX_CMD_ID_LOAD_TOC:
613 return "ID_LOAD_TOC";
614 case GFX_CMD_ID_AUTOLOAD_RLC:
615 return "AUTOLOAD_RLC";
616 case GFX_CMD_ID_BOOT_CFG:
617 return "BOOT_CFG";
618 default:
619 return "UNKNOWN CMD";
620 }
621}
622
0e5ca0d1
HR		 623static int
624psp_cmd_submit_buf(struct psp_context *psp,
625 struct amdgpu_firmware_info *ucode,
0b25cbf9 626 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
0e5ca0d1
HR		 627{
628 int ret;
a2c5dd9e 629 int index;
57995aa8 630 int timeout = 20000;
c2c6f816 631 bool ras_intr = false;
d73cd701 632 bool skip_unsupport = false;
0e5ca0d1 633
7afefb81 634 if (psp->adev->no_hw_access)
bf36b52e
AG		 635 return 0;
636
a1952da7 637 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
0e5ca0d1 638
a1952da7 639 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
0e5ca0d1 640
0b25cbf9 641 index = atomic_inc_return(&psp->fence_value);
5bdd0b72 642 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
0b25cbf9
HZ		 643 if (ret) {
644 atomic_dec(&psp->fence_value);
f89f8c6b 645 goto exit;
0b25cbf9 646 }
0e5ca0d1 647
810085dd 648 amdgpu_device_invalidate_hdp(psp->adev, NULL);
ea114213 649 while (*((unsigned int *)psp->fence_buf) != index) {
650 if (--timeout == 0)
7a3d7bf6 651 break;
bff77e86
LM		 652 /*
653 * Shouldn't wait for timeout when err_event_athub occurs,
654 * because gpu reset thread triggered and lock resource should
655 * be released for psp resume sequence.
656 */
c2c6f816
JC		 657 ras_intr = amdgpu_ras_intr_triggered();
658 if (ras_intr)
bff77e86 659 break;
57995aa8 660 usleep_range(10, 100);
810085dd 661 amdgpu_device_invalidate_hdp(psp->adev, NULL);
ea114213 662 }
0e5ca0d1 663
3bda8acd
ED		 664 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
665 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
666 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
d73cd701 667
f14c8c3e 668 memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
19ae3330 669
466bcb75
AL		 670 /* In some cases, psp response status is not 0 even there is no
671 * problem while the command is submitted. Some version of PSP FW
672 * doesn't write 0 to that field.
673 * So here we would like to only print a warning instead of an error
674 * during psp initialization to avoid breaking hw_init and it doesn't
675 * return -EINVAL.
676 */
d73cd701 677 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
76223c54 678 if (ucode)
ac3ff8a9
HZ		 679 dev_warn(psp->adev->dev,
680 "failed to load ucode %s(0x%X) ",
681 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
682 dev_warn(psp->adev->dev,
683 "psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
50c6dede 684 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
e6e193c0 685 psp->cmd_buf_mem->resp.status);
4bef1abe
AW		 686 /* If any firmware (including CAP) load fails under SRIOV, it should
687 * return failure to stop the VF from initializing.
688 * Also return failure in case of timeout
c4381d0e 689 */
4bef1abe 690 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
f89f8c6b
AG		 691 ret = -EINVAL;
692 goto exit;
32eaeae0 693 }
28a16027
HR		 694 }
695
435198f3
JZ		 696 if (ucode) {
697 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
698 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
699 }
700
f89f8c6b 701exit:
0e5ca0d1
HR		 702 return ret;
703}
704
4b296527
JC		 705static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
706{
707 struct psp_gfx_cmd_resp *cmd = psp->cmd;
708
709 mutex_lock(&psp->mutex);
710
711 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
712
713 return cmd;
714}
715
6c18ecef 716static void release_psp_cmd_buf(struct psp_context *psp)
4b296527
JC		 717{
718 mutex_unlock(&psp->mutex);
719}
720
5ec996df
XY		 721static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
722 struct psp_gfx_cmd_resp *cmd,
36c08237 723 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
0e5ca0d1 724{
36c08237 725 struct amdgpu_device *adev = psp->adev;
5b03127d
LL		 726 uint32_t size = 0;
727 uint64_t tmr_pa = 0;
728
729 if (tmr_bo) {
730 size = amdgpu_bo_size(tmr_bo);
731 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
732 }
36c08237 733
a2676149 734 if (amdgpu_sriov_vf(psp->adev))
5ec996df
XY		 735 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
736 else
737 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
f03defe0
AD		 738 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
739 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
0e5ca0d1 740 cmd->cmd.cmd_setup_tmr.buf_size = size;
36c08237
OZ		 741 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
742 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
743 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
0e5ca0d1
HR		 744}
745
7ea49e76
HZ		 746static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
747 uint64_t pri_buf_mc, uint32_t size)
748{
749 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
750 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
751 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
752 cmd->cmd.cmd_load_toc.toc_size = size;
753}
754
755/* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
756static int psp_load_toc(struct psp_context *psp,
757 uint32_t *tmr_size)
758{
759 int ret;
4b296527 760 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
7ea49e76 761
7ea49e76 762 /* Copy toc to psp firmware private buffer */
222e0a71 763 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
7ea49e76 764
222e0a71 765 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
7ea49e76
HZ		 766
767 ret = psp_cmd_submit_buf(psp, NULL, cmd,
768 psp->fence_buf_mc_addr);
769 if (!ret)
770 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
4fb93071 771
4b296527
JC		 772 release_psp_cmd_buf(psp);
773
7ea49e76
HZ		 774 return ret;
775}
776
5b03127d
LL		 777static bool psp_boottime_tmr(struct psp_context *psp)
778{
4e8303cf 779 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
5b03127d
LL		 780 case IP_VERSION(13, 0, 6):
781 return true;
782 default:
783 return false;
784 }
785}
786
0e5ca0d1
HR		 787/* Set up Trusted Memory Region */
788static int psp_tmr_init(struct psp_context *psp)
789{
96e1a88f 790 int ret = 0;
7ea49e76 791 int tmr_size;
12842d02
TY		 792 void *tmr_buf;
793 void **pptr;
0e5ca0d1
HR		 794
795 /*
795c1b8d 796 * According to HW engineer, they prefer the TMR address be "naturally
797 * aligned" , e.g. the start address be an integer divide of TMR size.
0e5ca0d1
HR		 798 *
799 * Note: this memory need be reserved till the driver
800 * uninitializes.
801 */
47bfa5f6 802 tmr_size = PSP_TMR_SIZE(psp->adev);
7ea49e76
HZ		 803
804 /* For ASICs support RLC autoload, psp will parse the toc
2d5c0415
PS		 805 * and calculate the total size of TMR needed
806 */
1b657824 807 if (!amdgpu_sriov_vf(psp->adev) &&
222e0a71
CL		 808 psp->toc.start_addr &&
809 psp->toc.size_bytes &&
7ea49e76
HZ		 810 psp->fw_pri_buf) {
811 ret = psp_load_toc(psp, &tmr_size);
812 if (ret) {
ac3ff8a9 813 dev_err(psp->adev->dev, "Failed to load toc\n");
7ea49e76
HZ		 814 return ret;
815 }
816 }
817
96e1a88f
AD		 818 if (!psp->tmr_bo) {
819 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
58ab2c08
CK		 820 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
821 PSP_TMR_ALIGNMENT,
822 AMDGPU_HAS_VRAM(psp->adev) ?
823 AMDGPU_GEM_DOMAIN_VRAM :
824 AMDGPU_GEM_DOMAIN_GTT,
825 &psp->tmr_bo, &psp->tmr_mc_addr,
826 pptr);
96e1a88f 827 }
6f2b1fcc
HR		 828
829 return ret;
830}
831
f61772cd
LC		 832static bool psp_skip_tmr(struct psp_context *psp)
833{
4e8303cf 834 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
82d05736
AD		 835 case IP_VERSION(11, 0, 9):
836 case IP_VERSION(11, 0, 7):
837 case IP_VERSION(13, 0, 2):
acbe7610 838 case IP_VERSION(13, 0, 6):
f8bd7321 839 case IP_VERSION(13, 0, 10):
f61772cd
LC		 840 return true;
841 default:
842 return false;
843 }
844}
845
6f2b1fcc
HR		 846static int psp_tmr_load(struct psp_context *psp)
847{
848 int ret;
4b296527 849 struct psp_gfx_cmd_resp *cmd;
6f2b1fcc 850
f61772cd
LC		 851 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
852 * Already set up by host driver.
853 */
854 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
855 return 0;
856
4b296527
JC		 857 cmd = acquire_psp_cmd_buf(psp);
858
36c08237 859 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
5b03127d 860 if (psp->tmr_bo)
ac3ff8a9 861 dev_info(psp->adev->dev, "reserve 0x%lx from 0x%llx for PSP TMR\n",
5b03127d 862 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
0e5ca0d1
HR		 863
864 ret = psp_cmd_submit_buf(psp, NULL, cmd,
0b25cbf9 865 psp->fence_buf_mc_addr);
0e5ca0d1 866
4b296527
JC		 867 release_psp_cmd_buf(psp);
868
0e5ca0d1
HR		 869 return ret;
870}
871
90937420 872static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
f14c8c3e 873 struct psp_gfx_cmd_resp *cmd)
90937420
HR		 874{
875 if (amdgpu_sriov_vf(psp->adev))
876 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
877 else
878 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
879}
880
881static int psp_tmr_unload(struct psp_context *psp)
882{
883 int ret;
f5a5b081
TL		 884 struct psp_gfx_cmd_resp *cmd;
885
886 /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
887 * as TMR is not loaded at all
888 */
889 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
890 return 0;
891
892 cmd = acquire_psp_cmd_buf(psp);
90937420
HR		 893
894 psp_prep_tmr_unload_cmd_buf(psp, cmd);
abcb2ace 895 dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
90937420
HR		 896
897 ret = psp_cmd_submit_buf(psp, NULL, cmd,
898 psp->fence_buf_mc_addr);
899
4b296527
JC		 900 release_psp_cmd_buf(psp);
901
90937420
HR		 902 return ret;
903}
904
905static int psp_tmr_terminate(struct psp_context *psp)
906{
da40bf8f 907 return psp_tmr_unload(psp);
90937420
HR		 908}
909
19ae3330
JC		 910int psp_get_fw_attestation_records_addr(struct psp_context *psp,
911 uint64_t *output_ptr)
912{
913 int ret;
4b296527 914 struct psp_gfx_cmd_resp *cmd;
19ae3330
JC		 915
916 if (!output_ptr)
917 return -EINVAL;
918
919 if (amdgpu_sriov_vf(psp->adev))
920 return 0;
921
4b296527
JC		 922 cmd = acquire_psp_cmd_buf(psp);
923
19ae3330
JC		 924 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
925
926 ret = psp_cmd_submit_buf(psp, NULL, cmd,
927 psp->fence_buf_mc_addr);
928
929 if (!ret) {
930 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
931 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
932 }
933
4b296527
JC		 934 release_psp_cmd_buf(psp);
935
19ae3330
JC		 936 return ret;
937}
938
c6642234
HZ		 939static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
940{
941 struct psp_context *psp = &adev->psp;
4b296527 942 struct psp_gfx_cmd_resp *cmd;
c6642234
HZ		 943 int ret;
944
945 if (amdgpu_sriov_vf(adev))
946 return 0;
947
4b296527 948 cmd = acquire_psp_cmd_buf(psp);
c6642234
HZ		 949
950 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
951 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
952
953 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
954 if (!ret) {
955 *boot_cfg =
956 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
957 }
958
4b296527
JC		 959 release_psp_cmd_buf(psp);
960
c6642234
HZ		 961 return ret;
962}
963
55188d64 964static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
cad7b751 965{
4b296527 966 int ret;
cad7b751 967 struct psp_context *psp = &adev->psp;
4b296527 968 struct psp_gfx_cmd_resp *cmd;
cad7b751 969
c6a11133 970 if (amdgpu_sriov_vf(adev))
cad7b751
JC		 971 return 0;
972
4b296527 973 cmd = acquire_psp_cmd_buf(psp);
cad7b751
JC		 974
975 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
976 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
55188d64
HZ		 977 cmd->cmd.boot_cfg.boot_config = boot_cfg;
978 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
cad7b751 979
4b296527
JC		 980 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
981
982 release_psp_cmd_buf(psp);
983
984 return ret;
cad7b751
JC		 985}
986
0d2c1855
JC		 987static int psp_rl_load(struct amdgpu_device *adev)
988{
4b296527 989 int ret;
0d2c1855 990 struct psp_context *psp = &adev->psp;
4b296527 991 struct psp_gfx_cmd_resp *cmd;
4fb93071 992
222e0a71 993 if (!is_psp_fw_valid(psp->rl))
0d2c1855
JC		 994 return 0;
995
4b296527
JC		 996 cmd = acquire_psp_cmd_buf(psp);
997
0d2c1855 998 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
222e0a71 999 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
0d2c1855 1000
0d2c1855
JC		 1001 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
1002 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
1003 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
222e0a71 1004 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
0d2c1855
JC		 1005 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
1006
4b296527
JC		 1007 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1008
1009 release_psp_cmd_buf(psp);
1010
1011 return ret;
0d2c1855
JC		 1012}
1013
ba08e9cb
LL		 1014int psp_spatial_partition(struct psp_context *psp, int mode)
1015{
1016 struct psp_gfx_cmd_resp *cmd;
1017 int ret;
1018
1019 if (amdgpu_sriov_vf(psp->adev))
1020 return 0;
1021
1022 cmd = acquire_psp_cmd_buf(psp);
1023
1024 cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1025 cmd->cmd.cmd_spatial_part.mode = mode;
1026
9f77af01 1027 dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
ba08e9cb
LL		 1028 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1029
1030 release_psp_cmd_buf(psp);
1031
1032 return ret;
1033}
1034
3f83f17b 1035static int psp_asd_initialize(struct psp_context *psp)
0e5ca0d1
HR		 1036{
1037 int ret;
0e5ca0d1 1038
943cafb8
XY		 1039 /* If PSP version doesn't match ASD version, asd loading will be failed.
1040 * add workaround to bypass it for sriov now.
1041 * TODO: add version check to make it common
1042 */
de3a1e33 1043 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
943cafb8
XY		 1044 return 0;
1045
3f83f17b
CL		 1046 psp->asd_context.mem_context.shared_mc_addr = 0;
1047 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1048 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD;
4b296527 1049
f03d97b0 1050 ret = psp_ta_load(psp, &psp->asd_context);
3f83f17b
CL		 1051 if (!ret)
1052 psp->asd_context.initialized = true;
4b296527 1053
0e5ca0d1
HR		 1054 return ret;
1055}
1056
1f455f25
JC		 1057static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1058 uint32_t session_id)
71e5f0cb
HZ		 1059{
1060 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1f455f25 1061 cmd->cmd.cmd_unload_ta.session_id = session_id;
71e5f0cb
HZ		 1062}
1063
fe96e563 1064int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
25c94b33
CL		 1065{
1066 int ret;
1067 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1068
17c6805a 1069 psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
25c94b33
CL		 1070
1071 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1072
bf7d7772
CL		 1073 context->resp_status = cmd->resp.status;
1074
25c94b33
CL		 1075 release_psp_cmd_buf(psp);
1076
1077 return ret;
1078}
1079
25c94b33 1080static int psp_asd_terminate(struct psp_context *psp)
71e5f0cb
HZ		 1081{
1082 int ret;
71e5f0cb
HZ		 1083
1084 if (amdgpu_sriov_vf(psp->adev))
1085 return 0;
1086
3f83f17b 1087 if (!psp->asd_context.initialized)
71e5f0cb
HZ		 1088 return 0;
1089
f03d97b0 1090 ret = psp_ta_unload(psp, &psp->asd_context);
71e5f0cb 1091 if (!ret)
3f83f17b 1092 psp->asd_context.initialized = false;
71e5f0cb 1093
71e5f0cb
HZ		 1094 return ret;
1095}
1096
c5d19419
TH		 1097static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1098 uint32_t id, uint32_t value)
1099{
1100 cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1101 cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1102 cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1103}
1104
1105int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1106 uint32_t value)
1107{
4b296527 1108 struct psp_gfx_cmd_resp *cmd;
c5d19419
TH		 1109 int ret = 0;
1110
1111 if (reg >= PSP_REG_LAST)
1112 return -EINVAL;
1113
4b296527
JC		 1114 cmd = acquire_psp_cmd_buf(psp);
1115
c5d19419
TH		 1116 psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1117 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
2b9ced5a 1118 if (ret)
ac3ff8a9 1119 dev_err(psp->adev->dev, "PSP failed to program reg id %d\n", reg);
c5d19419 1120
4b296527
JC		 1121 release_psp_cmd_buf(psp);
1122
c5d19419
TH		 1123 return ret;
1124}
1125
1f455f25
JC		 1126static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1127 uint64_t ta_bin_mc,
de3a1e33 1128 struct ta_context *context)
97c8d171 1129{
3f83f17b 1130 cmd->cmd_id = context->ta_load_type;
f14c8c3e 1131 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc);
f3729f7b 1132 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc);
de3a1e33 1133 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes;
1f455f25 1134
de3a1e33
CL		 1135 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1136 lower_32_bits(context->mem_context.shared_mc_addr);
1137 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1138 upper_32_bits(context->mem_context.shared_mc_addr);
1139 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
97c8d171
HZ		 1140}
1141
fe96e563 1142int psp_ta_init_shared_buf(struct psp_context *psp,
ac1509d1 1143 struct ta_mem_context *mem_ctx)
97c8d171 1144{
97c8d171 1145 /*
2d5c0415
PS		 1146 * Allocate 16k memory aligned to 4k from Frame Buffer (local
1147 * physical) for ta to host memory
1148 */
a5e7ffa1 1149 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
58ab2c08
CK		 1150 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1151 AMDGPU_GEM_DOMAIN_GTT,
30acef3c
CL		 1152 &mem_ctx->shared_bo,
1153 &mem_ctx->shared_mc_addr,
1154 &mem_ctx->shared_buf);
97c8d171
HZ		 1155}
1156
34e48cae
JC		 1157static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1158 uint32_t ta_cmd_id,
1159 uint32_t session_id)
1160{
f3729f7b
DV		 1161 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD;
1162 cmd->cmd.cmd_invoke_cmd.session_id = session_id;
1163 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id;
34e48cae
JC		 1164}
1165
fe96e563 1166int psp_ta_invoke(struct psp_context *psp,
34e48cae 1167 uint32_t ta_cmd_id,
77ec28ea 1168 struct ta_context *context)
34e48cae
JC		 1169{
1170 int ret;
4b296527 1171 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
34e48cae 1172
77ec28ea 1173 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
34e48cae
JC		 1174
1175 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1176 psp->fence_buf_mc_addr);
1177
fe96e563
CL		 1178 context->resp_status = cmd->resp.status;
1179
4b296527
JC		 1180 release_psp_cmd_buf(psp);
1181
34e48cae
JC		 1182 return ret;
1183}
1184
fe96e563 1185int psp_ta_load(struct psp_context *psp, struct ta_context *context)
97c8d171
HZ		 1186{
1187 int ret;
4b296527 1188 struct psp_gfx_cmd_resp *cmd;
97c8d171 1189
4b296527
JC		 1190 cmd = acquire_psp_cmd_buf(psp);
1191
de3a1e33
CL		 1192 psp_copy_fw(psp, context->bin_desc.start_addr,
1193 context->bin_desc.size_bytes);
97c8d171 1194
3f83f17b 1195 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
97c8d171
HZ		 1196
1197 ret = psp_cmd_submit_buf(psp, NULL, cmd,
1198 psp->fence_buf_mc_addr);
1199
fe96e563
CL		 1200 context->resp_status = cmd->resp.status;
1201
f14c8c3e 1202 if (!ret)
ac1509d1 1203 context->session_id = cmd->resp.session_id;
97c8d171 1204
4b296527
JC		 1205 release_psp_cmd_buf(psp);
1206
97c8d171
HZ		 1207 return ret;
1208}
1209
ca6e1e59
HZ		 1210int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1211{
77ec28ea 1212 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
ca6e1e59
HZ		 1213}
1214
0b9d3760 1215int psp_xgmi_terminate(struct psp_context *psp)
3e2e2ab5
HZ		 1216{
1217 int ret;
25c94b33
CL		 1218 struct amdgpu_device *adev = psp->adev;
1219
1220 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
4e8303cf
LL		 1221 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
1222 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 2) &&
82d05736 1223 adev->gmc.xgmi.connected_to_cpu))
25c94b33 1224 return 0;
3e2e2ab5 1225
ce97f37b 1226 if (!psp->xgmi_context.context.initialized)
3e2e2ab5
HZ		 1227 return 0;
1228
f03d97b0 1229 ret = psp_ta_unload(psp, &psp->xgmi_context.context);
3e2e2ab5 1230
ce97f37b 1231 psp->xgmi_context.context.initialized = false;
3e2e2ab5 1232
fb4f4f42 1233 return ret;
3e2e2ab5
HZ		 1234}
1235
44357a1b 1236int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
3e2e2ab5
HZ		 1237{
1238 struct ta_xgmi_shared_memory *xgmi_cmd;
1239 int ret;
1240
6457205c 1241 if (!psp->ta_fw ||
de3a1e33
CL		 1242 !psp->xgmi_context.context.bin_desc.size_bytes ||
1243 !psp->xgmi_context.context.bin_desc.start_addr)
1d69511e
AD		 1244 return -ENOENT;
1245
44357a1b
JK		 1246 if (!load_ta)
1247 goto invoke;
1248
ac1509d1 1249 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
3f83f17b 1250 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 1251
a5457087 1252 if (!psp->xgmi_context.context.mem_context.shared_buf) {
f03d97b0 1253 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
3e2e2ab5
HZ		 1254 if (ret)
1255 return ret;
1256 }
1257
1258 /* Load XGMI TA */
f03d97b0 1259 ret = psp_ta_load(psp, &psp->xgmi_context.context);
ac1509d1
CL		 1260 if (!ret)
1261 psp->xgmi_context.context.initialized = true;
1262 else
3e2e2ab5
HZ		 1263 return ret;
1264
44357a1b 1265invoke:
3e2e2ab5 1266 /* Initialize XGMI session */
ce97f37b 1267 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
3e2e2ab5 1268 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
44357a1b 1269 xgmi_cmd->flag_extend_link_record = set_extended_data;
3e2e2ab5
HZ		 1270 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1271
1272 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
723fac64
SZ		 1273 /* note down the capbility flag for XGMI TA */
1274 psp->xgmi_context.xgmi_ta_caps = xgmi_cmd->caps_flag;
3e2e2ab5
HZ		 1275
1276 return ret;
1277}
1278
35ccba4e
HZ		 1279int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1280{
1281 struct ta_xgmi_shared_memory *xgmi_cmd;
1282 int ret;
1283
ce97f37b 1284 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
35ccba4e
HZ		 1285 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1286
1287 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1288
1289 /* Invoke xgmi ta to get hive id */
1290 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1291 if (ret)
1292 return ret;
1293
1294 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1295
1296 return 0;
1297}
1298
1299int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1300{
1301 struct ta_xgmi_shared_memory *xgmi_cmd;
1302 int ret;
1303
ce97f37b 1304 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
35ccba4e
HZ		 1305 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1306
1307 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1308
1309 /* Invoke xgmi ta to get the node id */
1310 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1311 if (ret)
1312 return ret;
1313
1314 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1315
1316 return 0;
1317}
1318
331e7818
JK		 1319static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1320{
4e8303cf
LL		 1321 return (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1322 IP_VERSION(13, 0, 2) &&
07bc768a 1323 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
4e8303cf
LL		 1324 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >=
1325 IP_VERSION(13, 0, 6);
331e7818
JK		 1326}
1327
44357a1b
JK		 1328/*
1329 * Chips that support extended topology information require the driver to
1330 * reflect topology information in the opposite direction. This is
1331 * because the TA has already exceeded its link record limit and if the
1332 * TA holds bi-directional information, the driver would have to do
1333 * multiple fetches instead of just two.
1334 */
1335static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1336 struct psp_xgmi_node_info node_info)
1337{
1338 struct amdgpu_device *mirror_adev;
1339 struct amdgpu_hive_info *hive;
1340 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1341 uint64_t dst_node_id = node_info.node_id;
1342 uint8_t dst_num_hops = node_info.num_hops;
1343 uint8_t dst_num_links = node_info.num_links;
1344
1345 hive = amdgpu_get_xgmi_hive(psp->adev);
1346 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1347 struct psp_xgmi_topology_info *mirror_top_info;
1348 int j;
1349
1350 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1351 continue;
1352
1353 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1354 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1355 if (mirror_top_info->nodes[j].node_id != src_node_id)
1356 continue;
1357
1358 mirror_top_info->nodes[j].num_hops = dst_num_hops;
1359 /*
1360 * prevent 0 num_links value re-reflection since reflection
1361 * criteria is based on num_hops (direct or indirect).
1362 *
1363 */
1364 if (dst_num_links)
1365 mirror_top_info->nodes[j].num_links = dst_num_links;
1366
1367 break;
1368 }
1369
1370 break;
1371 }
1ff186ff
JK		 1372
1373 amdgpu_put_xgmi_hive(hive);
44357a1b
JK		 1374}
1375
35ccba4e
HZ		 1376int psp_xgmi_get_topology_info(struct psp_context *psp,
1377 int number_devices,
44357a1b
JK		 1378 struct psp_xgmi_topology_info *topology,
1379 bool get_extended_data)
35ccba4e
HZ		 1380{
1381 struct ta_xgmi_shared_memory *xgmi_cmd;
1382 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1383 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1384 int i;
1385 int ret;
1386
1387 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1388 return -EINVAL;
1389
ce97f37b 1390 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
35ccba4e 1391 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
44357a1b 1392 xgmi_cmd->flag_extend_link_record = get_extended_data;
35ccba4e
HZ		 1393
1394 /* Fill in the shared memory with topology information as input */
1395 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
626121fc 1396 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_TOPOLOGY_INFO;
35ccba4e
HZ		 1397 topology_info_input->num_nodes = number_devices;
1398
1399 for (i = 0; i < topology_info_input->num_nodes; i++) {
1400 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1401 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1402 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1403 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1404 }
1405
1406 /* Invoke xgmi ta to get the topology information */
626121fc 1407 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_TOPOLOGY_INFO);
35ccba4e
HZ		 1408 if (ret)
1409 return ret;
1410
1411 /* Read the output topology information from the shared memory */
1412 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1413 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1414 for (i = 0; i < topology->num_nodes; i++) {
44357a1b
JK		 1415 /* extended data will either be 0 or equal to non-extended data */
1416 if (topology_info_output->nodes[i].num_hops)
1417 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1418
1419 /* non-extended data gets everything here so no need to update */
1420 if (!get_extended_data) {
1421 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1422 topology->nodes[i].is_sharing_enabled =
1423 topology_info_output->nodes[i].is_sharing_enabled;
1424 topology->nodes[i].sdma_engine =
1425 topology_info_output->nodes[i].sdma_engine;
1426 }
1427
35ccba4e
HZ		 1428 }
1429
331e7818
JK		 1430 /* Invoke xgmi ta again to get the link information */
1431 if (psp_xgmi_peer_link_info_supported(psp)) {
626121fc 1432 struct ta_xgmi_cmd_get_peer_link_info *link_info_output;
723fac64 1433 struct ta_xgmi_cmd_get_extend_peer_link_info *link_extend_info_output;
07bc768a 1434 bool requires_reflection =
4e8303cf
LL		 1435 (psp->xgmi_context.supports_extended_data &&
1436 get_extended_data) ||
1437 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) ==
1438 IP_VERSION(13, 0, 6);
4e95669e
VC		 1439 bool ta_port_num_support = amdgpu_sriov_vf(psp->adev) ? 0 :
1440 psp->xgmi_context.xgmi_ta_caps & EXTEND_PEER_LINK_INFO_CMD_FLAG;
331e7818 1441
e8a5ded3
SZ		 1442 /* popluate the shared output buffer rather than the cmd input buffer
1443 * with node_ids as the input for GET_PEER_LINKS command execution.
723fac64
SZ		 1444 * This is required for GET_PEER_LINKS per xgmi ta implementation.
1445 * The same requirement for GET_EXTEND_PEER_LINKS command.
e8a5ded3 1446 */
723fac64
SZ		 1447 if (ta_port_num_support) {
1448 link_extend_info_output = &xgmi_cmd->xgmi_out_message.get_extend_link_info;
1449
1450 for (i = 0; i < topology->num_nodes; i++)
1451 link_extend_info_output->nodes[i].node_id = topology->nodes[i].node_id;
1452
1453 link_extend_info_output->num_nodes = topology->num_nodes;
1454 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_EXTEND_PEER_LINKS;
1455 } else {
1456 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1457
1458 for (i = 0; i < topology->num_nodes; i++)
1459 link_info_output->nodes[i].node_id = topology->nodes[i].node_id;
331e7818 1460
723fac64
SZ		 1461 link_info_output->num_nodes = topology->num_nodes;
1462 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1463 }
331e7818 1464
723fac64 1465 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
331e7818
JK		 1466 if (ret)
1467 return ret;
1468
44357a1b 1469 for (i = 0; i < topology->num_nodes; i++) {
723fac64
SZ		 1470 uint8_t node_num_links = ta_port_num_support ?
1471 link_extend_info_output->nodes[i].num_links : link_info_output->nodes[i].num_links;
44357a1b 1472 /* accumulate num_links on extended data */
723fac64
SZ		 1473 if (get_extended_data) {
1474 topology->nodes[i].num_links = topology->nodes[i].num_links + node_num_links;
1475 } else {
1476 topology->nodes[i].num_links = (requires_reflection && topology->nodes[i].num_links) ?
1477 topology->nodes[i].num_links : node_num_links;
1478 }
9ddea8c9
SZ		 1479 /* popluate the connected port num info if supported and available */
1480 if (ta_port_num_support && topology->nodes[i].num_links) {
1481 memcpy(topology->nodes[i].port_num, link_extend_info_output->nodes[i].port_num,
1482 sizeof(struct xgmi_connected_port_num) * TA_XGMI__MAX_PORT_NUM);
1483 }
44357a1b
JK		 1484
1485 /* reflect the topology information for bi-directionality */
07bc768a 1486 if (requires_reflection && topology->nodes[i].num_hops)
44357a1b
JK		 1487 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1488 }
331e7818
JK		 1489 }
1490
35ccba4e
HZ		 1491 return 0;
1492}
1493
1494int psp_xgmi_set_topology_info(struct psp_context *psp,
1495 int number_devices,
1496 struct psp_xgmi_topology_info *topology)
1497{
1498 struct ta_xgmi_shared_memory *xgmi_cmd;
1499 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1500 int i;
1501
1502 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1503 return -EINVAL;
1504
ce97f37b 1505 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
35ccba4e
HZ		 1506 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1507
1508 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1509 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1510 topology_info_input->num_nodes = number_devices;
1511
1512 for (i = 0; i < topology_info_input->num_nodes; i++) {
1513 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1514 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1515 topology_info_input->nodes[i].is_sharing_enabled = 1;
1516 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1517 }
1518
1519 /* Invoke xgmi ta to set topology information */
1520 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1521}
1522
5e5d3154 1523// ras begin
1b5254e8
TZ		 1524static void psp_ras_ta_check_status(struct psp_context *psp)
1525{
1526 struct ta_ras_shared_memory *ras_cmd =
1527 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1528
1529 switch (ras_cmd->ras_status) {
1530 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1531 dev_warn(psp->adev->dev,
ac3ff8a9 1532 "RAS WARNING: cmd failed due to unsupported ip\n");
1b5254e8 1533 break;
42f88ab7
TZ		 1534 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1535 dev_warn(psp->adev->dev,
ac3ff8a9 1536 "RAS WARNING: cmd failed due to unsupported error injection\n");
42f88ab7 1537 break;
1b5254e8
TZ		 1538 case TA_RAS_STATUS__SUCCESS:
1539 break;
79c04621
SY		 1540 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1541 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1542 dev_warn(psp->adev->dev,
ac3ff8a9 1543 "RAS WARNING: Inject error to critical region is not allowed\n");
79c04621 1544 break;
1b5254e8
TZ		 1545 default:
1546 dev_warn(psp->adev->dev,
ac3ff8a9 1547 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1b5254e8
TZ		 1548 break;
1549 }
1550}
1551
5e5d3154 1552int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1553{
43965797
JC		 1554 struct ta_ras_shared_memory *ras_cmd;
1555 int ret;
1556
ce97f37b 1557 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
43965797 1558
5e5d3154 1559 /*
1560 * TODO: bypass the loading in sriov for now
1561 */
1562 if (amdgpu_sriov_vf(psp->adev))
1563 return 0;
1564
77ec28ea 1565 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
43965797 1566
624e8c87
JC		 1567 if (amdgpu_ras_intr_triggered())
1568 return ret;
1569
f14c8c3e 1570 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
ac3ff8a9 1571 dev_warn(psp->adev->dev, "RAS: Unsupported Interface\n");
43965797
JC		 1572 return -EINVAL;
1573 }
1574
43965797
JC		 1575 if (!ret) {
1576 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1577 dev_warn(psp->adev->dev, "ECC switch disabled\n");
1578
1579 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
f14c8c3e 1580 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
43965797
JC		 1581 dev_warn(psp->adev->dev,
1582 "RAS internal register access blocked\n");
73490d26 1583
1b5254e8 1584 psp_ras_ta_check_status(psp);
43965797
JC		 1585 }
1586
1587 return ret;
5e5d3154 1588}
1589
1590int psp_ras_enable_features(struct psp_context *psp,
1591 union ta_ras_cmd_input *info, bool enable)
1592{
1593 struct ta_ras_shared_memory *ras_cmd;
1594 int ret;
1595
ce97f37b 1596 if (!psp->ras_context.context.initialized)
5e5d3154 1597 return -EINVAL;
1598
ce97f37b 1599 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
5e5d3154 1600 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1601
1602 if (enable)
1603 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1604 else
1605 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1606
1607 ras_cmd->ras_in_message = *info;
1608
1609 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1610 if (ret)
1611 return -EINVAL;
1612
334f81d1 1613 return 0;
5e5d3154 1614}
1615
fe96e563 1616int psp_ras_terminate(struct psp_context *psp)
5e5d3154 1617{
1618 int ret;
1619
edc2176d
JZ		 1620 /*
1621 * TODO: bypass the terminate in sriov for now
1622 */
1623 if (amdgpu_sriov_vf(psp->adev))
1624 return 0;
1625
ce97f37b 1626 if (!psp->ras_context.context.initialized)
5e5d3154 1627 return 0;
1628
f03d97b0 1629 ret = psp_ta_unload(psp, &psp->ras_context.context);
5e5d3154 1630
ce97f37b 1631 psp->ras_context.context.initialized = false;
5e5d3154 1632
fb4f4f42 1633 return ret;
5e5d3154 1634}
1635
896b7add 1636int psp_ras_initialize(struct psp_context *psp)
5e5d3154 1637{
1638 int ret;
6246a416
HZ		 1639 uint32_t boot_cfg = 0xFF;
1640 struct amdgpu_device *adev = psp->adev;
ac1509d1 1641 struct ta_ras_shared_memory *ras_cmd;
5e5d3154 1642
edc2176d
JZ		 1643 /*
1644 * TODO: bypass the initialize in sriov for now
1645 */
6246a416 1646 if (amdgpu_sriov_vf(adev))
edc2176d
JZ		 1647 return 0;
1648
de3a1e33
CL		 1649 if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1650 !adev->psp.ras_context.context.bin_desc.start_addr) {
6246a416 1651 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
51bd3638
HZ		 1652 return 0;
1653 }
1654
6246a416
HZ		 1655 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1656 /* query GECC enablement status from boot config
1657 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1658 */
1659 ret = psp_boot_config_get(adev, &boot_cfg);
1660 if (ret)
1661 dev_warn(adev->dev, "PSP get boot config failed\n");
1662
1663 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1664 if (!boot_cfg) {
1665 dev_info(adev->dev, "GECC is disabled\n");
1666 } else {
1667 /* disable GECC in next boot cycle if ras is
1668 * disabled by module parameter amdgpu_ras_enable
1669 * and/or amdgpu_ras_mask, or boot_config_get call
1670 * is failed
1671 */
1672 ret = psp_boot_config_set(adev, 0);
1673 if (ret)
1674 dev_warn(adev->dev, "PSP set boot config failed\n");
1675 else
f14c8c3e 1676 dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
6246a416
HZ		 1677 }
1678 } else {
f14c8c3e 1679 if (boot_cfg == 1) {
6246a416
HZ		 1680 dev_info(adev->dev, "GECC is enabled\n");
1681 } else {
1682 /* enable GECC in next boot cycle if it is disabled
1683 * in boot config, or force enable GECC if failed to
1684 * get boot configuration
1685 */
1686 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1687 if (ret)
1688 dev_warn(adev->dev, "PSP set boot config failed\n");
1689 else
1690 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1691 }
1692 }
1693 }
1694
ac1509d1 1695 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
3f83f17b 1696 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 1697
bf7d7772 1698 if (!psp->ras_context.context.mem_context.shared_buf) {
f03d97b0 1699 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
5e5d3154 1700 if (ret)
1701 return ret;
1702 }
1703
ac1509d1
CL		 1704 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1705 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1706
e4348849 1707 if (amdgpu_ras_is_poison_mode_supported(adev))
ac1509d1 1708 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
38298ce6 1709 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
ac1509d1 1710 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
61a7c162
SY		 1711 ras_cmd->ras_in_message.init_flags.xcc_mask =
1712 adev->gfx.xcc_mask;
6fac3964 1713 ras_cmd->ras_in_message.init_flags.channel_dis_num = hweight32(adev->gmc.m_half_use) * 2;
ac1509d1 1714
f03d97b0 1715 ret = psp_ta_load(psp, &psp->ras_context.context);
5e5d3154 1716
ac1509d1
CL		 1717 if (!ret && !ras_cmd->ras_status)
1718 psp->ras_context.context.initialized = true;
1719 else {
1720 if (ras_cmd->ras_status)
ac3ff8a9 1721 dev_warn(adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
3e931368
TZ		 1722
1723 /* fail to load RAS TA */
1724 psp->ras_context.context.initialized = false;
ac1509d1
CL		 1725 }
1726
1727 return ret;
5e5d3154 1728}
001a0a95
HZ		 1729
1730int psp_ras_trigger_error(struct psp_context *psp,
2c22ed0b 1731 struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
001a0a95
HZ		 1732{
1733 struct ta_ras_shared_memory *ras_cmd;
2c22ed0b 1734 struct amdgpu_device *adev = psp->adev;
001a0a95 1735 int ret;
2c22ed0b 1736 uint32_t dev_mask;
001a0a95 1737
ce97f37b 1738 if (!psp->ras_context.context.initialized)
001a0a95
HZ		 1739 return -EINVAL;
1740
2c22ed0b
TZ		 1741 switch (info->block_id) {
1742 case TA_RAS_BLOCK__GFX:
1743 dev_mask = GET_MASK(GC, instance_mask);
1744 break;
1745 case TA_RAS_BLOCK__SDMA:
1746 dev_mask = GET_MASK(SDMA0, instance_mask);
1747 break;
3898c8fc
SY		 1748 case TA_RAS_BLOCK__VCN:
1749 case TA_RAS_BLOCK__JPEG:
1750 dev_mask = GET_MASK(VCN, instance_mask);
1751 break;
2c22ed0b
TZ		 1752 default:
1753 dev_mask = instance_mask;
1754 break;
1755 }
1756
1757 /* reuse sub_block_index for backward compatibility */
1758 dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1759 dev_mask &= AMDGPU_RAS_INST_MASK;
1760 info->sub_block_index |= dev_mask;
1761
ce97f37b 1762 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
001a0a95
HZ		 1763 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1764
1765 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1766 ras_cmd->ras_in_message.trigger_error = *info;
1767
1768 ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1769 if (ret)
1770 return -EINVAL;
1771
1772 /* If err_event_athub occurs error inject was successful, however
2d5c0415
PS		 1773 * return status from TA is no long reliable
1774 */
001a0a95
HZ		 1775 if (amdgpu_ras_intr_triggered())
1776 return 0;
1777
79c04621
SY		 1778 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1779 return -EACCES;
1780 else if (ras_cmd->ras_status)
334f81d1 1781 return -EINVAL;
334f81d1
JC		 1782
1783 return 0;
001a0a95 1784}
5e5d3154 1785// ras end
1786
ed19a9a2 1787// HDCP start
ed19a9a2
BL		 1788static int psp_hdcp_initialize(struct psp_context *psp)
1789{
1790 int ret;
1791
edc2176d
JZ		 1792 /*
1793 * TODO: bypass the initialize in sriov for now
1794 */
1795 if (amdgpu_sriov_vf(psp->adev))
1796 return 0;
1797
de3a1e33
CL		 1798 if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1799 !psp->hdcp_context.context.bin_desc.start_addr) {
a45a9e5e 1800 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
51bd3638
HZ		 1801 return 0;
1802 }
1803
ac1509d1 1804 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
3f83f17b 1805 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 1806
61d2a9be 1807 if (!psp->hdcp_context.context.mem_context.shared_buf) {
f03d97b0 1808 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
ed19a9a2
BL		 1809 if (ret)
1810 return ret;
1811 }
1812
f03d97b0 1813 ret = psp_ta_load(psp, &psp->hdcp_context.context);
ac1509d1
CL		 1814 if (!ret) {
1815 psp->hdcp_context.context.initialized = true;
1816 mutex_init(&psp->hdcp_context.mutex);
1817 }
ed19a9a2 1818
ac1509d1 1819 return ret;
ed19a9a2 1820}
ed19a9a2 1821
ed19a9a2
BL		 1822int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1823{
ed19a9a2
BL		 1824 /*
1825 * TODO: bypass the loading in sriov for now
1826 */
1827 if (amdgpu_sriov_vf(psp->adev))
1828 return 0;
1829
77ec28ea 1830 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
ed19a9a2
BL		 1831}
1832
1833static int psp_hdcp_terminate(struct psp_context *psp)
1834{
1835 int ret;
1836
edc2176d
JZ		 1837 /*
1838 * TODO: bypass the terminate in sriov for now
1839 */
1840 if (amdgpu_sriov_vf(psp->adev))
1841 return 0;
1842
da40bf8f
AD		 1843 if (!psp->hdcp_context.context.initialized)
1844 return 0;
ed19a9a2 1845
f03d97b0 1846 ret = psp_ta_unload(psp, &psp->hdcp_context.context);
ed19a9a2 1847
ce97f37b 1848 psp->hdcp_context.context.initialized = false;
ed19a9a2 1849
fb4f4f42 1850 return ret;
ed19a9a2
BL		 1851}
1852// HDCP end
1853
143f2305 1854// DTM start
143f2305
BL		 1855static int psp_dtm_initialize(struct psp_context *psp)
1856{
1857 int ret;
1858
edc2176d
JZ		 1859 /*
1860 * TODO: bypass the initialize in sriov for now
1861 */
1862 if (amdgpu_sriov_vf(psp->adev))
1863 return 0;
1864
de3a1e33
CL		 1865 if (!psp->dtm_context.context.bin_desc.size_bytes ||
1866 !psp->dtm_context.context.bin_desc.start_addr) {
a45a9e5e 1867 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
51bd3638
HZ		 1868 return 0;
1869 }
1870
ac1509d1 1871 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
3f83f17b 1872 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 1873
61d2a9be 1874 if (!psp->dtm_context.context.mem_context.shared_buf) {
f03d97b0 1875 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
143f2305
BL		 1876 if (ret)
1877 return ret;
1878 }
1879
f03d97b0 1880 ret = psp_ta_load(psp, &psp->dtm_context.context);
ac1509d1
CL		 1881 if (!ret) {
1882 psp->dtm_context.context.initialized = true;
1883 mutex_init(&psp->dtm_context.mutex);
1884 }
143f2305 1885
ac1509d1 1886 return ret;
143f2305
BL		 1887}
1888
143f2305
BL		 1889int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1890{
143f2305
BL		 1891 /*
1892 * TODO: bypass the loading in sriov for now
1893 */
1894 if (amdgpu_sriov_vf(psp->adev))
1895 return 0;
1896
77ec28ea 1897 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
143f2305
BL		 1898}
1899
1900static int psp_dtm_terminate(struct psp_context *psp)
1901{
1902 int ret;
1903
edc2176d
JZ		 1904 /*
1905 * TODO: bypass the terminate in sriov for now
1906 */
1907 if (amdgpu_sriov_vf(psp->adev))
1908 return 0;
1909
da40bf8f
AD		 1910 if (!psp->dtm_context.context.initialized)
1911 return 0;
143f2305 1912
f03d97b0 1913 ret = psp_ta_unload(psp, &psp->dtm_context.context);
143f2305 1914
ce97f37b 1915 psp->dtm_context.context.initialized = false;
143f2305 1916
fb4f4f42 1917 return ret;
143f2305
BL		 1918}
1919// DTM end
1920
8602692b 1921// RAP start
8602692b
WS		 1922static int psp_rap_initialize(struct psp_context *psp)
1923{
1924 int ret;
2fb3c5d0 1925 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
8602692b
WS		 1926
1927 /*
1928 * TODO: bypass the initialize in sriov for now
1929 */
1930 if (amdgpu_sriov_vf(psp->adev))
1931 return 0;
1932
de3a1e33
CL		 1933 if (!psp->rap_context.context.bin_desc.size_bytes ||
1934 !psp->rap_context.context.bin_desc.start_addr) {
8602692b
WS		 1935 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1936 return 0;
1937 }
1938
ac1509d1 1939 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
3f83f17b 1940 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 1941
61d2a9be 1942 if (!psp->rap_context.context.mem_context.shared_buf) {
f03d97b0 1943 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
8602692b
WS		 1944 if (ret)
1945 return ret;
1946 }
1947
f03d97b0 1948 ret = psp_ta_load(psp, &psp->rap_context.context);
ac1509d1
CL		 1949 if (!ret) {
1950 psp->rap_context.context.initialized = true;
1951 mutex_init(&psp->rap_context.mutex);
1952 } else
8602692b
WS		 1953 return ret;
1954
2fb3c5d0
KW		 1955 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1956 if (ret || status != TA_RAP_STATUS__SUCCESS) {
25c94b33 1957 psp_rap_terminate(psp);
da40bf8f
AD		 1958 /* free rap shared memory */
1959 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
8602692b 1960
2fb3c5d0
KW		 1961 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1962 ret, status);
1963
1964 return ret;
8602692b
WS		 1965 }
1966
1967 return 0;
1968}
1969
1970static int psp_rap_terminate(struct psp_context *psp)
1971{
1972 int ret;
1973
ce97f37b 1974 if (!psp->rap_context.context.initialized)
8602692b
WS		 1975 return 0;
1976
f03d97b0 1977 ret = psp_ta_unload(psp, &psp->rap_context.context);
8602692b 1978
ce97f37b 1979 psp->rap_context.context.initialized = false;
8602692b 1980
8602692b
WS		 1981 return ret;
1982}
1983
2fb3c5d0 1984int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
8602692b
WS		 1985{
1986 struct ta_rap_shared_memory *rap_cmd;
2fb3c5d0 1987 int ret = 0;
8602692b 1988
ce97f37b 1989 if (!psp->rap_context.context.initialized)
2fb3c5d0 1990 return 0;
8602692b
WS		 1991
1992 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1993 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1994 return -EINVAL;
1995
1996 mutex_lock(&psp->rap_context.mutex);
1997
1998 rap_cmd = (struct ta_rap_shared_memory *)
ce97f37b 1999 psp->rap_context.context.mem_context.shared_buf;
8602692b
WS		 2000 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
2001
2002 rap_cmd->cmd_id = ta_cmd_id;
2003 rap_cmd->validation_method_id = METHOD_A;
2004
77ec28ea 2005 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
2fb3c5d0
KW		 2006 if (ret)
2007 goto out_unlock;
2008
2009 if (status)
2010 *status = rap_cmd->rap_status;
8602692b 2011
2fb3c5d0 2012out_unlock:
8602692b
WS		 2013 mutex_unlock(&psp->rap_context.mutex);
2014
2fb3c5d0 2015 return ret;
8602692b
WS		 2016}
2017// RAP end
2018
ecaafb7b 2019/* securedisplay start */
ecaafb7b
JS		 2020static int psp_securedisplay_initialize(struct psp_context *psp)
2021{
2022 int ret;
f6e856e7 2023 struct ta_securedisplay_cmd *securedisplay_cmd;
ecaafb7b
JS		 2024
2025 /*
2026 * TODO: bypass the initialize in sriov for now
2027 */
2028 if (amdgpu_sriov_vf(psp->adev))
2029 return 0;
2030
de3a1e33
CL		 2031 if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
2032 !psp->securedisplay_context.context.bin_desc.start_addr) {
ecaafb7b
JS		 2033 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
2034 return 0;
2035 }
2036
ac1509d1
CL		 2037 psp->securedisplay_context.context.mem_context.shared_mem_size =
2038 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
3f83f17b 2039 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
ac1509d1 2040
ce97f37b 2041 if (!psp->securedisplay_context.context.initialized) {
f03d97b0
AD		 2042 ret = psp_ta_init_shared_buf(psp,
2043 &psp->securedisplay_context.context.mem_context);
ecaafb7b
JS		 2044 if (ret)
2045 return ret;
2046 }
2047
f03d97b0 2048 ret = psp_ta_load(psp, &psp->securedisplay_context.context);
ac1509d1
CL		 2049 if (!ret) {
2050 psp->securedisplay_context.context.initialized = true;
2051 mutex_init(&psp->securedisplay_context.mutex);
2052 } else
ecaafb7b
JS		 2053 return ret;
2054
7117007e
AL		 2055 mutex_lock(&psp->securedisplay_context.mutex);
2056
ecaafb7b
JS		 2057 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2058 TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2059
2060 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
7117007e
AL		 2061
2062 mutex_unlock(&psp->securedisplay_context.mutex);
2063
ecaafb7b 2064 if (ret) {
25c94b33 2065 psp_securedisplay_terminate(psp);
da40bf8f
AD		 2066 /* free securedisplay shared memory */
2067 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
ecaafb7b
JS		 2068 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2069 return -EINVAL;
2070 }
2071
2072 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2073 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2074 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2075 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
5c6d52ff
ML		 2076 /* don't try again */
2077 psp->securedisplay_context.context.bin_desc.size_bytes = 0;
ecaafb7b
JS		 2078 }
2079
2080 return 0;
2081}
2082
2083static int psp_securedisplay_terminate(struct psp_context *psp)
2084{
2085 int ret;
2086
2087 /*
2088 * TODO:bypass the terminate in sriov for now
2089 */
2090 if (amdgpu_sriov_vf(psp->adev))
2091 return 0;
2092
ce97f37b 2093 if (!psp->securedisplay_context.context.initialized)
ecaafb7b
JS		 2094 return 0;
2095
f03d97b0 2096 ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
ecaafb7b 2097
ce97f37b 2098 psp->securedisplay_context.context.initialized = false;
ecaafb7b 2099
ecaafb7b
JS		 2100 return ret;
2101}
2102
2103int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2104{
2105 int ret;
2106
ce97f37b 2107 if (!psp->securedisplay_context.context.initialized)
ecaafb7b
JS		 2108 return -EINVAL;
2109
2110 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2111 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2112 return -EINVAL;
2113
77ec28ea 2114 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
ecaafb7b 2115
ecaafb7b
JS		 2116 return ret;
2117}
2118/* SECUREDISPLAY end */
2119
15c5c5f5
LL		 2120int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev)
2121{
2122 struct psp_context *psp = &adev->psp;
2123 int ret = 0;
2124
2125 if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL)
2126 ret = psp->funcs->wait_for_bootloader(psp);
2127
2128 return ret;
2129}
2130
be70bbda 2131static int psp_hw_start(struct psp_context *psp)
0e5ca0d1 2132{
55981bd2 2133 struct amdgpu_device *adev = psp->adev;
0e5ca0d1 2134 int ret;
0e5ca0d1 2135
82c4ebfa 2136 if (!amdgpu_sriov_vf(adev)) {
222e0a71 2137 if ((is_psp_fw_valid(psp->kdb)) &&
42989359
HZ		 2138 (psp->funcs->bootloader_load_kdb != NULL)) {
2139 ret = psp_bootloader_load_kdb(psp);
2140 if (ret) {
ac3ff8a9 2141 dev_err(adev->dev, "PSP load kdb failed!\n");
70509057
LG		 2142 return ret;
2143 }
2144 }
2145
222e0a71
CL		 2146 if ((is_psp_fw_valid(psp->spl)) &&
2147 (psp->funcs->bootloader_load_spl != NULL)) {
70509057
LG		 2148 ret = psp_bootloader_load_spl(psp);
2149 if (ret) {
ac3ff8a9 2150 dev_err(adev->dev, "PSP load spl failed!\n");
42989359
HZ		 2151 return ret;
2152 }
2153 }
2154
222e0a71
CL		 2155 if ((is_psp_fw_valid(psp->sys)) &&
2156 (psp->funcs->bootloader_load_sysdrv != NULL)) {
2157 ret = psp_bootloader_load_sysdrv(psp);
2158 if (ret) {
ac3ff8a9 2159 dev_err(adev->dev, "PSP load sys drv failed!\n");
6ff34fd6
JC		 2160 return ret;
2161 }
2162 }
2163
2164 if ((is_psp_fw_valid(psp->soc_drv)) &&
2165 (psp->funcs->bootloader_load_soc_drv != NULL)) {
2166 ret = psp_bootloader_load_soc_drv(psp);
2167 if (ret) {
ac3ff8a9 2168 dev_err(adev->dev, "PSP load soc drv failed!\n");
6ff34fd6
JC		 2169 return ret;
2170 }
2171 }
2172
2173 if ((is_psp_fw_valid(psp->intf_drv)) &&
2174 (psp->funcs->bootloader_load_intf_drv != NULL)) {
2175 ret = psp_bootloader_load_intf_drv(psp);
2176 if (ret) {
ac3ff8a9 2177 dev_err(adev->dev, "PSP load intf drv failed!\n");
6ff34fd6
JC		 2178 return ret;
2179 }
2180 }
2181
2182 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2183 (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2184 ret = psp_bootloader_load_dbg_drv(psp);
2185 if (ret) {
ac3ff8a9 2186 dev_err(adev->dev, "PSP load dbg drv failed!\n");
222e0a71
CL		 2187 return ret;
2188 }
7a3d7bf6 2189 }
0e5ca0d1 2190
c3db1b90
JC		 2191 if ((is_psp_fw_valid(psp->ras_drv)) &&
2192 (psp->funcs->bootloader_load_ras_drv != NULL)) {
2193 ret = psp_bootloader_load_ras_drv(psp);
2194 if (ret) {
ac3ff8a9 2195 dev_err(adev->dev, "PSP load ras_drv failed!\n");
c3db1b90
JC		 2196 return ret;
2197 }
2198 }
2199
222e0a71
CL		 2200 if ((is_psp_fw_valid(psp->sos)) &&
2201 (psp->funcs->bootloader_load_sos != NULL)) {
2202 ret = psp_bootloader_load_sos(psp);
2203 if (ret) {
ac3ff8a9 2204 dev_err(adev->dev, "PSP load sos failed!\n");
222e0a71
CL		 2205 return ret;
2206 }
7a3d7bf6 2207 }
55981bd2 2208 }
0e5ca0d1 2209
be70bbda 2210 ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
7a3d7bf6 2211 if (ret) {
ac3ff8a9 2212 dev_err(adev->dev, "PSP create ring failed!\n");
be70bbda 2213 return ret;
7a3d7bf6 2214 }
0e5ca0d1 2215
85dfc1d6
JC		 2216 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2217 goto skip_pin_bo;
2218
5b03127d
LL		 2219 if (!psp_boottime_tmr(psp)) {
2220 ret = psp_tmr_init(psp);
2221 if (ret) {
ac3ff8a9 2222 dev_err(adev->dev, "PSP tmr init failed!\n");
5b03127d
LL		 2223 return ret;
2224 }
fba08a77
HZ		 2225 }
2226
85dfc1d6 2227skip_pin_bo:
995da6cc 2228 /*
40e611bd 2229 * For ASICs with DF Cstate management centralized
995da6cc
EQ		 2230 * to PMFW, TMR setup should be performed after PMFW
2231 * loaded and before other non-psp firmware loaded.
2232 */
40e611bd
JC		 2233 if (psp->pmfw_centralized_cstate_management) {
2234 ret = psp_load_smu_fw(psp);
2235 if (ret)
995da6cc 2236 return ret;
40e611bd
JC		 2237 }
2238
2239 ret = psp_tmr_load(psp);
2240 if (ret) {
ac3ff8a9 2241 dev_err(adev->dev, "PSP load tmr failed!\n");
40e611bd 2242 return ret;
7a3d7bf6 2243 }
0e5ca0d1 2244
be70bbda
HR		 2245 return 0;
2246}
2247
be4630d9
HZ		 2248static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2249 enum psp_gfx_fw_type *type)
2250{
2251 switch (ucode->ucode_id) {
c4381d0e
BZ		 2252 case AMDGPU_UCODE_ID_CAP:
2253 *type = GFX_FW_TYPE_CAP;
2254 break;
be4630d9
HZ		 2255 case AMDGPU_UCODE_ID_SDMA0:
2256 *type = GFX_FW_TYPE_SDMA0;
2257 break;
2258 case AMDGPU_UCODE_ID_SDMA1:
2259 *type = GFX_FW_TYPE_SDMA1;
2260 break;
b86f8d8b
JC		 2261 case AMDGPU_UCODE_ID_SDMA2:
2262 *type = GFX_FW_TYPE_SDMA2;
2263 break;
2264 case AMDGPU_UCODE_ID_SDMA3:
2265 *type = GFX_FW_TYPE_SDMA3;
2266 break;
2267 case AMDGPU_UCODE_ID_SDMA4:
2268 *type = GFX_FW_TYPE_SDMA4;
2269 break;
2270 case AMDGPU_UCODE_ID_SDMA5:
2271 *type = GFX_FW_TYPE_SDMA5;
2272 break;
2273 case AMDGPU_UCODE_ID_SDMA6:
2274 *type = GFX_FW_TYPE_SDMA6;
2275 break;
2276 case AMDGPU_UCODE_ID_SDMA7:
2277 *type = GFX_FW_TYPE_SDMA7;
2278 break;
93fd978b
JX		 2279 case AMDGPU_UCODE_ID_CP_MES:
2280 *type = GFX_FW_TYPE_CP_MES;
2281 break;
2282 case AMDGPU_UCODE_ID_CP_MES_DATA:
2283 *type = GFX_FW_TYPE_MES_STACK;
2284 break;
c1248e11
LG		 2285 case AMDGPU_UCODE_ID_CP_MES1:
2286 *type = GFX_FW_TYPE_CP_MES_KIQ;
2287 break;
2288 case AMDGPU_UCODE_ID_CP_MES1_DATA:
2289 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2290 break;
be4630d9
HZ		 2291 case AMDGPU_UCODE_ID_CP_CE:
2292 *type = GFX_FW_TYPE_CP_CE;
2293 break;
2294 case AMDGPU_UCODE_ID_CP_PFP:
2295 *type = GFX_FW_TYPE_CP_PFP;
2296 break;
2297 case AMDGPU_UCODE_ID_CP_ME:
2298 *type = GFX_FW_TYPE_CP_ME;
2299 break;
2300 case AMDGPU_UCODE_ID_CP_MEC1:
2301 *type = GFX_FW_TYPE_CP_MEC;
2302 break;
2303 case AMDGPU_UCODE_ID_CP_MEC1_JT:
2304 *type = GFX_FW_TYPE_CP_MEC_ME1;
2305 break;
2306 case AMDGPU_UCODE_ID_CP_MEC2:
2307 *type = GFX_FW_TYPE_CP_MEC;
2308 break;
2309 case AMDGPU_UCODE_ID_CP_MEC2_JT:
2310 *type = GFX_FW_TYPE_CP_MEC_ME2;
2311 break;
a0fe38b4
LG		 2312 case AMDGPU_UCODE_ID_RLC_P:
2313 *type = GFX_FW_TYPE_RLC_P;
2314 break;
8e41a56a
LG		 2315 case AMDGPU_UCODE_ID_RLC_V:
2316 *type = GFX_FW_TYPE_RLC_V;
2317 break;
be4630d9
HZ		 2318 case AMDGPU_UCODE_ID_RLC_G:
2319 *type = GFX_FW_TYPE_RLC_G;
2320 break;
2321 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2322 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2323 break;
2324 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2325 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2326 break;
2327 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2328 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2329 break;
5bab858e
LG		 2330 case AMDGPU_UCODE_ID_RLC_IRAM:
2331 *type = GFX_FW_TYPE_RLC_IRAM;
2332 break;
2333 case AMDGPU_UCODE_ID_RLC_DRAM:
2334 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2335 break;
2207efdd
CG		 2336 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2337 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2338 break;
2339 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2340 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2341 break;
2342 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2343 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2344 break;
2345 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2346 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2347 break;
2348 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2349 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2350 break;
be4630d9
HZ		 2351 case AMDGPU_UCODE_ID_SMC:
2352 *type = GFX_FW_TYPE_SMU;
2353 break;
b37c41f2
EQ		 2354 case AMDGPU_UCODE_ID_PPTABLE:
2355 *type = GFX_FW_TYPE_PPTABLE;
2356 break;
be4630d9
HZ		 2357 case AMDGPU_UCODE_ID_UVD:
2358 *type = GFX_FW_TYPE_UVD;
2359 break;
2360 case AMDGPU_UCODE_ID_UVD1:
2361 *type = GFX_FW_TYPE_UVD1;
2362 break;
2363 case AMDGPU_UCODE_ID_VCE:
2364 *type = GFX_FW_TYPE_VCE;
2365 break;
2366 case AMDGPU_UCODE_ID_VCN:
2367 *type = GFX_FW_TYPE_VCN;
2368 break;
d83c7a07
JJ		 2369 case AMDGPU_UCODE_ID_VCN1:
2370 *type = GFX_FW_TYPE_VCN1;
2371 break;
be4630d9
HZ		 2372 case AMDGPU_UCODE_ID_DMCU_ERAM:
2373 *type = GFX_FW_TYPE_DMCU_ERAM;
2374 break;
2375 case AMDGPU_UCODE_ID_DMCU_INTV:
2376 *type = GFX_FW_TYPE_DMCU_ISR;
2377 break;
c76ff09b
JX		 2378 case AMDGPU_UCODE_ID_VCN0_RAM:
2379 *type = GFX_FW_TYPE_VCN0_RAM;
2380 break;
2381 case AMDGPU_UCODE_ID_VCN1_RAM:
2382 *type = GFX_FW_TYPE_VCN1_RAM;
2383 break;
2bd2a27f
NK		 2384 case AMDGPU_UCODE_ID_DMCUB:
2385 *type = GFX_FW_TYPE_DMUB;
2386 break;
6777c8cf
LG		 2387 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2388 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2389 break;
2390 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2391 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2392 break;
a32fa029
LG		 2393 case AMDGPU_UCODE_ID_IMU_I:
2394 *type = GFX_FW_TYPE_IMU_I;
2395 break;
2396 case AMDGPU_UCODE_ID_IMU_D:
2397 *type = GFX_FW_TYPE_IMU_D;
2398 break;
be3a3409
LG		 2399 case AMDGPU_UCODE_ID_CP_RS64_PFP:
2400 *type = GFX_FW_TYPE_RS64_PFP;
2401 break;
2402 case AMDGPU_UCODE_ID_CP_RS64_ME:
2403 *type = GFX_FW_TYPE_RS64_ME;
2404 break;
2405 case AMDGPU_UCODE_ID_CP_RS64_MEC:
2406 *type = GFX_FW_TYPE_RS64_MEC;
2407 break;
2408 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2409 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2410 break;
2411 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2412 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2413 break;
2414 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2415 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2416 break;
2417 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2418 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2419 break;
2420 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2421 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2422 break;
2423 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2424 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2425 break;
2426 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2427 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2428 break;
2429 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2430 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2431 break;
964a36d7
LY		 2432 case AMDGPU_UCODE_ID_VPE_CTX:
2433 *type = GFX_FW_TYPE_VPEC_FW1;
2434 break;
2435 case AMDGPU_UCODE_ID_VPE_CTL:
2436 *type = GFX_FW_TYPE_VPEC_FW2;
2437 break;
f9ecae9a
LY		 2438 case AMDGPU_UCODE_ID_VPE:
2439 *type = GFX_FW_TYPE_VPE;
2440 break;
4f949033
LY		 2441 case AMDGPU_UCODE_ID_UMSCH_MM_UCODE:
2442 *type = GFX_FW_TYPE_UMSCH_UCODE;
2443 break;
2444 case AMDGPU_UCODE_ID_UMSCH_MM_DATA:
2445 *type = GFX_FW_TYPE_UMSCH_DATA;
2446 break;
2447 case AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER:
2448 *type = GFX_FW_TYPE_UMSCH_CMD_BUFFER;
2449 break;
79daf692
LL		 2450 case AMDGPU_UCODE_ID_P2S_TABLE:
2451 *type = GFX_FW_TYPE_P2S_TABLE;
2452 break;
be4630d9
HZ		 2453 case AMDGPU_UCODE_ID_MAXIMUM:
2454 default:
2455 return -EINVAL;
2456 }
2457
2458 return 0;
2459}
2460
c5fb9126
XY		 2461static void psp_print_fw_hdr(struct psp_context *psp,
2462 struct amdgpu_firmware_info *ucode)
2463{
2464 struct amdgpu_device *adev = psp->adev;
bfa603aa 2465 struct common_firmware_header *hdr;
c5fb9126
XY		 2466
2467 switch (ucode->ucode_id) {
2468 case AMDGPU_UCODE_ID_SDMA0:
2469 case AMDGPU_UCODE_ID_SDMA1:
2470 case AMDGPU_UCODE_ID_SDMA2:
2471 case AMDGPU_UCODE_ID_SDMA3:
2472 case AMDGPU_UCODE_ID_SDMA4:
2473 case AMDGPU_UCODE_ID_SDMA5:
2474 case AMDGPU_UCODE_ID_SDMA6:
2475 case AMDGPU_UCODE_ID_SDMA7:
bfa603aa
XY		 2476 hdr = (struct common_firmware_header *)
2477 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2478 amdgpu_ucode_print_sdma_hdr(hdr);
c5fb9126
XY		 2479 break;
2480 case AMDGPU_UCODE_ID_CP_CE:
bfa603aa
XY		 2481 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2482 amdgpu_ucode_print_gfx_hdr(hdr);
c5fb9126
XY		 2483 break;
2484 case AMDGPU_UCODE_ID_CP_PFP:
bfa603aa
XY		 2485 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2486 amdgpu_ucode_print_gfx_hdr(hdr);
c5fb9126
XY		 2487 break;
2488 case AMDGPU_UCODE_ID_CP_ME:
bfa603aa
XY		 2489 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2490 amdgpu_ucode_print_gfx_hdr(hdr);
c5fb9126
XY		 2491 break;
2492 case AMDGPU_UCODE_ID_CP_MEC1:
bfa603aa
XY		 2493 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2494 amdgpu_ucode_print_gfx_hdr(hdr);
c5fb9126
XY		 2495 break;
2496 case AMDGPU_UCODE_ID_RLC_G:
bfa603aa
XY		 2497 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2498 amdgpu_ucode_print_rlc_hdr(hdr);
c5fb9126
XY		 2499 break;
2500 case AMDGPU_UCODE_ID_SMC:
bfa603aa
XY		 2501 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2502 amdgpu_ucode_print_smc_hdr(hdr);
c5fb9126
XY		 2503 break;
2504 default:
2505 break;
2506 }
2507}
2508
ac3ff8a9
HZ		 2509static int psp_prep_load_ip_fw_cmd_buf(struct psp_context *psp,
2510 struct amdgpu_firmware_info *ucode,
be4630d9
HZ		 2511 struct psp_gfx_cmd_resp *cmd)
2512{
2513 int ret;
2514 uint64_t fw_mem_mc_addr = ucode->mc_addr;
2515
be4630d9
HZ		 2516 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2517 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2518 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2519 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2520
2521 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2522 if (ret)
ac3ff8a9 2523 dev_err(psp->adev->dev, "Unknown firmware type\n");
be4630d9
HZ		 2524
2525 return ret;
2526}
2527
45b51acb
LY		 2528int psp_execute_ip_fw_load(struct psp_context *psp,
2529 struct amdgpu_firmware_info *ucode)
13169562
HR		 2530{
2531 int ret = 0;
4b296527 2532 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
13169562 2533
ac3ff8a9 2534 ret = psp_prep_load_ip_fw_cmd_buf(psp, ucode, cmd);
4b296527
JC		 2535 if (!ret) {
2536 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2537 psp->fence_buf_mc_addr);
2538 }
13169562 2539
4b296527 2540 release_psp_cmd_buf(psp);
13169562
HR		 2541
2542 return ret;
2543}
2544
79daf692
LL		 2545static int psp_load_p2s_table(struct psp_context *psp)
2546{
2547 int ret;
2548 struct amdgpu_device *adev = psp->adev;
2549 struct amdgpu_firmware_info *ucode =
2550 &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
2551
2552 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2553 return 0;
2554
f20f3b0d
LL		 2555 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
2556 uint32_t supp_vers = adev->flags & AMD_IS_APU ? 0x0036013D :
2557 0x0036003C;
2558 if (psp->sos.fw_version < supp_vers)
2559 return 0;
2560 }
2561
79daf692
LL		 2562 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2563 return 0;
2564
2565 ret = psp_execute_ip_fw_load(psp, ucode);
2566
2567 return ret;
2568}
2569
40e611bd
JC		 2570static int psp_load_smu_fw(struct psp_context *psp)
2571{
2572 int ret;
c4c5ae67 2573 struct amdgpu_device *adev = psp->adev;
40e611bd 2574 struct amdgpu_firmware_info *ucode =
7f70443f 2575 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
6457205c 2576 struct amdgpu_ras *ras = psp->ras_context.ras;
40e611bd 2577
f746556a
GC		 2578 /*
2579 * Skip SMU FW reloading in case of using BACO for runpm only,
2580 * as SMU is always alive.
2581 */
2582 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2583 return 0;
2584
40e611bd
JC		 2585 if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2586 return 0;
2587
4e8303cf
LL		 2588 if ((amdgpu_in_reset(adev) && ras && adev->ras_enabled &&
2589 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 4) ||
2590 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(11, 0, 2)))) {
7f70443f 2591 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
f14c8c3e 2592 if (ret)
ac3ff8a9 2593 dev_err(adev->dev, "Failed to set MP1 state prepare for reload\n");
7f70443f
JC		 2594 }
2595
45b51acb 2596 ret = psp_execute_ip_fw_load(psp, ucode);
40e611bd
JC		 2597
2598 if (ret)
ac3ff8a9 2599 dev_err(adev->dev, "PSP load smu failed!\n");
40e611bd
JC		 2600
2601 return ret;
2602}
2603
2604static bool fw_load_skip_check(struct psp_context *psp,
2605 struct amdgpu_firmware_info *ucode)
2606{
68fb37bc 2607 if (!ucode->fw || !ucode->ucode_size)
40e611bd
JC		 2608 return true;
2609
79daf692
LL		 2610 if (ucode->ucode_id == AMDGPU_UCODE_ID_P2S_TABLE)
2611 return true;
2612
40e611bd
JC		 2613 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2614 (psp_smu_reload_quirk(psp) ||
2615 psp->autoload_supported ||
2616 psp->pmfw_centralized_cstate_management))
2617 return true;
2618
2619 if (amdgpu_sriov_vf(psp->adev) &&
d9d86d08 2620 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
40e611bd
JC		 2621 return true;
2622
2623 if (psp->autoload_supported &&
2624 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2625 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2626 /* skip mec JT when autoload is enabled */
2627 return true;
2628
2629 return false;
2630}
2631
a2052839
LL		 2632int psp_load_fw_list(struct psp_context *psp,
2633 struct amdgpu_firmware_info **ucode_list, int ucode_count)
2634{
2635 int ret = 0, i;
2636 struct amdgpu_firmware_info *ucode;
2637
2638 for (i = 0; i < ucode_count; ++i) {
2639 ucode = ucode_list[i];
2640 psp_print_fw_hdr(psp, ucode);
45b51acb 2641 ret = psp_execute_ip_fw_load(psp, ucode);
a2052839
LL		 2642 if (ret)
2643 return ret;
2644 }
2645 return ret;
2646}
2647
cd5955f4 2648static int psp_load_non_psp_fw(struct psp_context *psp)
be70bbda
HR		 2649{
2650 int i, ret;
0e5ca0d1 2651 struct amdgpu_firmware_info *ucode;
c4c5ae67 2652 struct amdgpu_device *adev = psp->adev;
0e5ca0d1 2653
40e611bd
JC		 2654 if (psp->autoload_supported &&
2655 !psp->pmfw_centralized_cstate_management) {
2656 ret = psp_load_smu_fw(psp);
13169562
HR		 2657 if (ret)
2658 return ret;
2659 }
2660
79daf692
LL		 2661 /* Load P2S table first if it's available */
2662 psp_load_p2s_table(psp);
2663
0e5ca0d1
HR		 2664 for (i = 0; i < adev->firmware.max_ucodes; i++) {
2665 ucode = &adev->firmware.ucode[i];
0e5ca0d1
HR		 2666
2667 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
40e611bd
JC		 2668 !fw_load_skip_check(psp, ucode)) {
2669 ret = psp_load_smu_fw(psp);
2670 if (ret)
2671 return ret;
e993ca4f 2672 continue;
40e611bd 2673 }
b86f8d8b 2674
40e611bd 2675 if (fw_load_skip_check(psp, ucode))
119eb6db 2676 continue;
0e5ca0d1 2677
738c822c 2678 if (psp->autoload_supported &&
4e8303cf
LL		 2679 (amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2680 IP_VERSION(11, 0, 7) ||
2681 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2682 IP_VERSION(11, 0, 11) ||
2683 amdgpu_ip_version(adev, MP0_HWIP, 0) ==
2684 IP_VERSION(11, 0, 12)) &&
738c822c
LG		 2685 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2686 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2687 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2688 /* PSP only receive one SDMA fw for sienna_cichlid,
2d5c0415
PS		 2689 * as all four sdma fw are same
2690 */
738c822c
LG		 2691 continue;
2692
c5fb9126
XY		 2693 psp_print_fw_hdr(psp, ucode);
2694
45b51acb 2695 ret = psp_execute_ip_fw_load(psp, ucode);
0e5ca0d1 2696 if (ret)
be70bbda 2697 return ret;
0e5ca0d1 2698
1a5b4cca 2699 /* Start rlc autoload after psp recieved all the gfx firmware */
6de40f02 2700 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
f8bd7321 2701 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
999a69e2 2702 ret = psp_rlc_autoload_start(psp);
1a5b4cca 2703 if (ret) {
ac3ff8a9 2704 dev_err(adev->dev, "Failed to start rlc autoload\n");
1a5b4cca
HZ		 2705 return ret;
2706 }
2707 }
0e5ca0d1
HR		 2708 }
2709
be70bbda
HR		 2710 return 0;
2711}
2712
2713static int psp_load_fw(struct amdgpu_device *adev)
2714{
2715 int ret;
0e5ca0d1
HR		 2716 struct psp_context *psp = &adev->psp;
2717
53b3f8f4 2718 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
b95b5391
AD		 2719 /* should not destroy ring, only stop */
2720 psp_ring_stop(psp, PSP_RING_TYPE__KM);
e1944deb 2721 } else {
b95b5391 2722 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
0e5ca0d1 2723
b95b5391
AD		 2724 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2725 if (ret) {
ac3ff8a9 2726 dev_err(adev->dev, "PSP ring init failed!\n");
b95b5391
AD		 2727 goto failed;
2728 }
7a3d7bf6 2729 }
0e5ca0d1 2730
be70bbda 2731 ret = psp_hw_start(psp);
0e5ca0d1 2732 if (ret)
37945a3a 2733 goto failed;
0e5ca0d1 2734
cd5955f4 2735 ret = psp_load_non_psp_fw(psp);
be70bbda 2736 if (ret)
e2c34219 2737 goto failed1;
0e5ca0d1 2738
3f83f17b 2739 ret = psp_asd_initialize(psp);
7091b60c 2740 if (ret) {
ac3ff8a9 2741 dev_err(adev->dev, "PSP load asd failed!\n");
e2c34219 2742 goto failed1;
7091b60c
HZ		 2743 }
2744
0d2c1855
JC		 2745 ret = psp_rl_load(adev);
2746 if (ret) {
ac3ff8a9 2747 dev_err(adev->dev, "PSP load RL failed!\n");
e2c34219 2748 goto failed1;
0d2c1855
JC		 2749 }
2750
dd26e018
ZL		 2751 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2752 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2753 ret = psp_xgmi_initialize(psp, false, true);
2754 /* Warning the XGMI seesion initialize failure
2d5c0415
PS		 2755 * Instead of stop driver initialization
2756 */
dd26e018
ZL		 2757 if (ret)
2758 dev_err(psp->adev->dev,
2759 "XGMI: Failed to initialize XGMI session\n");
2760 }
2761 }
2762
6457205c 2763 if (psp->ta_fw) {
7091b60c
HZ		 2764 ret = psp_ras_initialize(psp);
2765 if (ret)
2766 dev_err(psp->adev->dev,
ac3ff8a9 2767 "RAS: Failed to initialize RAS\n");
7091b60c
HZ		 2768
2769 ret = psp_hdcp_initialize(psp);
2770 if (ret)
2771 dev_err(psp->adev->dev,
2772 "HDCP: Failed to initialize HDCP\n");
2773
2774 ret = psp_dtm_initialize(psp);
2775 if (ret)
2776 dev_err(psp->adev->dev,
2777 "DTM: Failed to initialize DTM\n");
8602692b
WS		 2778
2779 ret = psp_rap_initialize(psp);
2780 if (ret)
2781 dev_err(psp->adev->dev,
2782 "RAP: Failed to initialize RAP\n");
ecaafb7b
JS		 2783
2784 ret = psp_securedisplay_initialize(psp);
2785 if (ret)
2786 dev_err(psp->adev->dev,
2787 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
7091b60c
HZ		 2788 }
2789
0e5ca0d1
HR		 2790 return 0;
2791
e2c34219
AW		 2792failed1:
2793 psp_free_shared_bufs(psp);
0e5ca0d1 2794failed:
37945a3a
EQ		 2795 /*
2796 * all cleanup jobs (xgmi terminate, ras terminate,
2797 * ring destroy, cmd/fence/fw buffers destory,
2798 * psp->cmd destory) are delayed to psp_hw_fini
2799 */
e2c34219 2800 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
0e5ca0d1
HR		 2801 return ret;
2802}
2803
2804static int psp_hw_init(void *handle)
2805{
2806 int ret;
2807 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2808
0e5ca0d1 2809 mutex_lock(&adev->firmware.mutex);
6e13bdf6
RZ		 2810 /*
2811 * This sequence is just used on hw_init only once, no need on
2812 * resume.
2813 */
2814 ret = amdgpu_ucode_init_bo(adev);
2815 if (ret)
2816 goto failed;
0e5ca0d1
HR		 2817
2818 ret = psp_load_fw(adev);
2819 if (ret) {
ac3ff8a9 2820 dev_err(adev->dev, "PSP firmware loading failed\n");
0e5ca0d1
HR		 2821 goto failed;
2822 }
2823
2824 mutex_unlock(&adev->firmware.mutex);
03597b47 2825 return 0;
0e5ca0d1
HR		 2826
2827failed:
2828 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2829 mutex_unlock(&adev->firmware.mutex);
2830 return -EINVAL;
2831}
2832
2833static int psp_hw_fini(void *handle)
2834{
2835 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2836 struct psp_context *psp = &adev->psp;
2837
6457205c 2838 if (psp->ta_fw) {
54eb4ed6 2839 psp_ras_terminate(psp);
ecaafb7b 2840 psp_securedisplay_terminate(psp);
8602692b 2841 psp_rap_terminate(psp);
143f2305 2842 psp_dtm_terminate(psp);
ed19a9a2 2843 psp_hdcp_terminate(psp);
d8adafc7
YC		 2844
2845 if (adev->gmc.xgmi.num_physical_nodes > 1)
2846 psp_xgmi_terminate(psp);
ed19a9a2 2847 }
5e5d3154 2848
25c94b33 2849 psp_asd_terminate(psp);
90937420 2850 psp_tmr_terminate(psp);
da40bf8f 2851
e3c5e982 2852 psp_ring_destroy(psp, PSP_RING_TYPE__KM);
0e5ca0d1 2853
0e5ca0d1
HR		 2854 return 0;
2855}
2856
2857static int psp_suspend(void *handle)
2858{
da40bf8f 2859 int ret = 0;
bcd6eab8
EQ		 2860 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2861 struct psp_context *psp = &adev->psp;
2862
3e2e2ab5 2863 if (adev->gmc.xgmi.num_physical_nodes > 1 &&
ce97f37b 2864 psp->xgmi_context.context.initialized) {
3e2e2ab5
HZ		 2865 ret = psp_xgmi_terminate(psp);
2866 if (ret) {
ac3ff8a9 2867 dev_err(adev->dev, "Failed to terminate xgmi ta\n");
da40bf8f 2868 goto out;
3e2e2ab5
HZ		 2869 }
2870 }
2871
6457205c 2872 if (psp->ta_fw) {
54eb4ed6 2873 ret = psp_ras_terminate(psp);
2874 if (ret) {
ac3ff8a9 2875 dev_err(adev->dev, "Failed to terminate ras ta\n");
da40bf8f 2876 goto out;
54eb4ed6 2877 }
ed19a9a2
BL		 2878 ret = psp_hdcp_terminate(psp);
2879 if (ret) {
ac3ff8a9 2880 dev_err(adev->dev, "Failed to terminate hdcp ta\n");
da40bf8f 2881 goto out;
ed19a9a2 2882 }
143f2305
BL		 2883 ret = psp_dtm_terminate(psp);
2884 if (ret) {
ac3ff8a9 2885 dev_err(adev->dev, "Failed to terminate dtm ta\n");
da40bf8f 2886 goto out;
143f2305 2887 }
8602692b
WS		 2888 ret = psp_rap_terminate(psp);
2889 if (ret) {
ac3ff8a9 2890 dev_err(adev->dev, "Failed to terminate rap ta\n");
da40bf8f 2891 goto out;
8602692b 2892 }
ecaafb7b
JS		 2893 ret = psp_securedisplay_terminate(psp);
2894 if (ret) {
ac3ff8a9 2895 dev_err(adev->dev, "Failed to terminate securedisplay ta\n");
da40bf8f 2896 goto out;
ecaafb7b 2897 }
5e5d3154 2898 }
2899
25c94b33 2900 ret = psp_asd_terminate(psp);
429f3d24 2901 if (ret) {
ac3ff8a9 2902 dev_err(adev->dev, "Failed to terminate asd\n");
da40bf8f 2903 goto out;
429f3d24
HR		 2904 }
2905
90937420
HR		 2906 ret = psp_tmr_terminate(psp);
2907 if (ret) {
ac3ff8a9 2908 dev_err(adev->dev, "Failed to terminate tmr\n");
da40bf8f 2909 goto out;
90937420
HR		 2910 }
2911
bcd6eab8 2912 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
f14c8c3e 2913 if (ret)
ac3ff8a9 2914 dev_err(adev->dev, "PSP ring stop failed\n");
bcd6eab8 2915
da40bf8f 2916out:
da40bf8f 2917 return ret;
0e5ca0d1
HR		 2918}
2919
2920static int psp_resume(void *handle)
2921{
2922 int ret;
2923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
93ea9b9f 2924 struct psp_context *psp = &adev->psp;
0e5ca0d1 2925
ac3ff8a9 2926 dev_info(adev->dev, "PSP is resuming...\n");
93ea9b9f 2927
3a07101b
HZ		 2928 if (psp->mem_train_ctx.enable_mem_training) {
2929 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2930 if (ret) {
ac3ff8a9 2931 dev_err(adev->dev, "Failed to process memory training!\n");
3a07101b
HZ		 2932 return ret;
2933 }
0586a059
TY		 2934 }
2935
0e5ca0d1
HR		 2936 mutex_lock(&adev->firmware.mutex);
2937
93ea9b9f 2938 ret = psp_hw_start(psp);
0e5ca0d1 2939 if (ret)
93ea9b9f
HR		 2940 goto failed;
2941
cd5955f4 2942 ret = psp_load_non_psp_fw(psp);
93ea9b9f
HR		 2943 if (ret)
2944 goto failed;
0e5ca0d1 2945
3f83f17b 2946 ret = psp_asd_initialize(psp);
0d6f39bb 2947 if (ret) {
ac3ff8a9 2948 dev_err(adev->dev, "PSP load asd failed!\n");
0d6f39bb
HZ		 2949 goto failed;
2950 }
2951
c72942c1
TZ		 2952 ret = psp_rl_load(adev);
2953 if (ret) {
2954 dev_err(adev->dev, "PSP load RL failed!\n");
2955 goto failed;
2956 }
2957
0d6f39bb 2958 if (adev->gmc.xgmi.num_physical_nodes > 1) {
44357a1b 2959 ret = psp_xgmi_initialize(psp, false, true);
0d6f39bb
HZ		 2960 /* Warning the XGMI seesion initialize failure
2961 * Instead of stop driver initialization
2962 */
2963 if (ret)
2964 dev_err(psp->adev->dev,
2965 "XGMI: Failed to initialize XGMI session\n");
2966 }
2967
6457205c 2968 if (psp->ta_fw) {
0d6f39bb
HZ		 2969 ret = psp_ras_initialize(psp);
2970 if (ret)
2971 dev_err(psp->adev->dev,
ac3ff8a9 2972 "RAS: Failed to initialize RAS\n");
0d6f39bb
HZ		 2973
2974 ret = psp_hdcp_initialize(psp);
2975 if (ret)
2976 dev_err(psp->adev->dev,
2977 "HDCP: Failed to initialize HDCP\n");
2978
2979 ret = psp_dtm_initialize(psp);
2980 if (ret)
2981 dev_err(psp->adev->dev,
2982 "DTM: Failed to initialize DTM\n");
8602692b
WS		 2983
2984 ret = psp_rap_initialize(psp);
2985 if (ret)
2986 dev_err(psp->adev->dev,
2987 "RAP: Failed to initialize RAP\n");
ecaafb7b
JS		 2988
2989 ret = psp_securedisplay_initialize(psp);
2990 if (ret)
2991 dev_err(psp->adev->dev,
2992 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
0d6f39bb
HZ		 2993 }
2994
0e5ca0d1
HR		 2995 mutex_unlock(&adev->firmware.mutex);
2996
93ea9b9f
HR		 2997 return 0;
2998
2999failed:
ac3ff8a9 3000 dev_err(adev->dev, "PSP resume failed\n");
93ea9b9f 3001 mutex_unlock(&adev->firmware.mutex);
0e5ca0d1
HR		 3002 return ret;
3003}
3004
f75a9a5d 3005int psp_gpu_reset(struct amdgpu_device *adev)
98512bb8 3006{
32eaeae0
AD		 3007 int ret;
3008
2d4f9020
HR		 3009 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
3010 return 0;
3011
32eaeae0
AD		 3012 mutex_lock(&adev->psp.mutex);
3013 ret = psp_mode1_reset(&adev->psp);
3014 mutex_unlock(&adev->psp.mutex);
3015
3016 return ret;
98512bb8
KW		 3017}
3018
1a5b4cca
HZ		 3019int psp_rlc_autoload_start(struct psp_context *psp)
3020{
3021 int ret;
4b296527 3022 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1a5b4cca
HZ		 3023
3024 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
3025
3026 ret = psp_cmd_submit_buf(psp, NULL, cmd,
3027 psp->fence_buf_mc_addr);
4fb93071 3028
4b296527
JC		 3029 release_psp_cmd_buf(psp);
3030
1a5b4cca
HZ		 3031 return ret;
3032}
3033
cc65176e
HZ		 3034int psp_ring_cmd_submit(struct psp_context *psp,
3035 uint64_t cmd_buf_mc_addr,
3036 uint64_t fence_mc_addr,
3037 int index)
3038{
3039 unsigned int psp_write_ptr_reg = 0;
2e77541b 3040 struct psp_gfx_rb_frame *write_frame;
cc65176e
HZ		 3041 struct psp_ring *ring = &psp->km_ring;
3042 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
3043 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
3044 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
3045 struct amdgpu_device *adev = psp->adev;
3046 uint32_t ring_size_dw = ring->ring_size / 4;
3047 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
3048
3049 /* KM (GPCOM) prepare write pointer */
3050 psp_write_ptr_reg = psp_ring_get_wptr(psp);
3051
3052 /* Update KM RB frame pointer to new frame */
3053 /* write_frame ptr increments by size of rb_frame in bytes */
3054 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
3055 if ((psp_write_ptr_reg % ring_size_dw) == 0)
3056 write_frame = ring_buffer_start;
3057 else
3058 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
3059 /* Check invalid write_frame ptr address */
3060 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
ac3ff8a9
HZ		 3061 dev_err(adev->dev,
3062 "ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
3063 ring_buffer_start, ring_buffer_end, write_frame);
3064 dev_err(adev->dev,
3065 "write_frame is pointing to address out of bounds\n");
cc65176e
HZ		 3066 return -EINVAL;
3067 }
3068
3069 /* Initialize KM RB frame */
3070 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
3071
3072 /* Update KM RB frame */
3073 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
3074 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
3075 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
3076 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
3077 write_frame->fence_value = index;
810085dd 3078 amdgpu_device_flush_hdp(adev, NULL);
cc65176e
HZ		 3079
3080 /* Update the write Pointer in DWORDs */
3081 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
3082 psp_ring_set_wptr(psp, psp_write_ptr_reg);
3083 return 0;
3084}
3085
2d39c7ae 3086int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
dc7195f6
HZ		 3087{
3088 struct amdgpu_device *adev = psp->adev;
0a305e34 3089 char fw_name[PSP_FW_NAME_LEN];
dc7195f6
HZ		 3090 const struct psp_firmware_header_v1_0 *asd_hdr;
3091 int err = 0;
3092
dc7195f6 3093 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
07dbfc6b 3094 err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
dc7195f6
HZ		 3095 if (err)
3096 goto out;
3097
3098 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
de3a1e33
CL		 3099 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
3100 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
3101 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
3102 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
dc7195f6
HZ		 3103 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
3104 return 0;
3105out:
07dbfc6b 3106 amdgpu_ucode_release(&adev->psp.asd_fw);
dc7195f6
HZ		 3107 return err;
3108}
3109
2d39c7ae 3110int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
5120cb54
HR		 3111{
3112 struct amdgpu_device *adev = psp->adev;
30ebc16a 3113 char fw_name[PSP_FW_NAME_LEN];
5120cb54
HR		 3114 const struct psp_firmware_header_v1_0 *toc_hdr;
3115 int err = 0;
3116
5120cb54 3117 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
07dbfc6b 3118 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
5120cb54
HR		 3119 if (err)
3120 goto out;
3121
3122 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
222e0a71
CL		 3123 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3124 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3125 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3126 adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
5120cb54
HR		 3127 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3128 return 0;
3129out:
07dbfc6b 3130 amdgpu_ucode_release(&adev->psp.toc_fw);
5120cb54
HR		 3131 return err;
3132}
3133
f8e487ce
JC		 3134static int parse_sos_bin_descriptor(struct psp_context *psp,
3135 const struct psp_fw_bin_desc *desc,
3136 const struct psp_firmware_header_v2_0 *sos_hdr)
3137{
3138 uint8_t *ucode_start_addr = NULL;
3139
3140 if (!psp || !desc || !sos_hdr)
3141 return -EINVAL;
3142
3143 ucode_start_addr = (uint8_t *)sos_hdr +
3144 le32_to_cpu(desc->offset_bytes) +
3145 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3146
3147 switch (desc->fw_type) {
3148 case PSP_FW_TYPE_PSP_SOS:
3149 psp->sos.fw_version = le32_to_cpu(desc->fw_version);
3150 psp->sos.feature_version = le32_to_cpu(desc->fw_version);
3151 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes);
f14c8c3e 3152 psp->sos.start_addr = ucode_start_addr;
f8e487ce
JC		 3153 break;
3154 case PSP_FW_TYPE_PSP_SYS_DRV:
3155 psp->sys.fw_version = le32_to_cpu(desc->fw_version);
3156 psp->sys.feature_version = le32_to_cpu(desc->fw_version);
3157 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes);
3158 psp->sys.start_addr = ucode_start_addr;
3159 break;
3160 case PSP_FW_TYPE_PSP_KDB:
3161 psp->kdb.fw_version = le32_to_cpu(desc->fw_version);
3162 psp->kdb.feature_version = le32_to_cpu(desc->fw_version);
3163 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes);
3164 psp->kdb.start_addr = ucode_start_addr;
3165 break;
3166 case PSP_FW_TYPE_PSP_TOC:
3167 psp->toc.fw_version = le32_to_cpu(desc->fw_version);
3168 psp->toc.feature_version = le32_to_cpu(desc->fw_version);
3169 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes);
3170 psp->toc.start_addr = ucode_start_addr;
3171 break;
3172 case PSP_FW_TYPE_PSP_SPL:
3173 psp->spl.fw_version = le32_to_cpu(desc->fw_version);
3174 psp->spl.feature_version = le32_to_cpu(desc->fw_version);
3175 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes);
3176 psp->spl.start_addr = ucode_start_addr;
3177 break;
3178 case PSP_FW_TYPE_PSP_RL:
3179 psp->rl.fw_version = le32_to_cpu(desc->fw_version);
3180 psp->rl.feature_version = le32_to_cpu(desc->fw_version);
3181 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes);
3182 psp->rl.start_addr = ucode_start_addr;
3183 break;
6ff34fd6
JC		 3184 case PSP_FW_TYPE_PSP_SOC_DRV:
3185 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version);
3186 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version);
3187 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3188 psp->soc_drv.start_addr = ucode_start_addr;
3189 break;
3190 case PSP_FW_TYPE_PSP_INTF_DRV:
3191 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version);
3192 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version);
3193 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3194 psp->intf_drv.start_addr = ucode_start_addr;
3195 break;
3196 case PSP_FW_TYPE_PSP_DBG_DRV:
3197 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version);
3198 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version);
3199 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3200 psp->dbg_drv.start_addr = ucode_start_addr;
3201 break;
c3db1b90
JC		 3202 case PSP_FW_TYPE_PSP_RAS_DRV:
3203 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version);
3204 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version);
3205 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes);
3206 psp->ras_drv.start_addr = ucode_start_addr;
3207 break;
f8e487ce
JC		 3208 default:
3209 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3210 break;
3211 }
3212
3213 return 0;
3214}
3215
2a9a151f
JC		 3216static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3217{
3218 const struct psp_firmware_header_v1_0 *sos_hdr;
3219 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
ed4454c3 3220 uint8_t *ucode_array_start_addr;
2a9a151f
JC		 3221
3222 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
ed4454c3
HZ		 3223 ucode_array_start_addr = (uint8_t *)sos_hdr +
3224 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2a9a151f 3225
82d05736 3226 if (adev->gmc.xgmi.connected_to_cpu ||
4e8303cf 3227 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2))) {
222e0a71
CL		 3228 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3229 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
2a9a151f 3230
222e0a71
CL		 3231 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3232 adev->psp.sys.start_addr = ucode_array_start_addr;
2a9a151f 3233
222e0a71
CL		 3234 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3235 adev->psp.sos.start_addr = ucode_array_start_addr +
2a9a151f
JC		 3236 le32_to_cpu(sos_hdr->sos.offset_bytes);
3237 } else {
3238 /* Load alternate PSP SOS FW */
3239 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3240
222e0a71
CL		 3241 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3242 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
2a9a151f 3243
222e0a71
CL		 3244 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3245 adev->psp.sys.start_addr = ucode_array_start_addr +
2a9a151f
JC		 3246 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3247
222e0a71
CL		 3248 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3249 adev->psp.sos.start_addr = ucode_array_start_addr +
2a9a151f
JC		 3250 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3251 }
3252
222e0a71 3253 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
2a9a151f
JC		 3254 dev_warn(adev->dev, "PSP SOS FW not available");
3255 return -EINVAL;
3256 }
3257
3258 return 0;
3259}
3260
2d39c7ae 3261int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
1c301f44
HZ		 3262{
3263 struct amdgpu_device *adev = psp->adev;
0a305e34 3264 char fw_name[PSP_FW_NAME_LEN];
1c301f44
HZ		 3265 const struct psp_firmware_header_v1_0 *sos_hdr;
3266 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3267 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
43a188e0 3268 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
f8e487ce 3269 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
1c301f44 3270 int err = 0;
ed4454c3 3271 uint8_t *ucode_array_start_addr;
f8e487ce 3272 int fw_index = 0;
1c301f44 3273
1c301f44 3274 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
07dbfc6b 3275 err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
1c301f44
HZ		 3276 if (err)
3277 goto out;
3278
3279 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
ed4454c3
HZ		 3280 ucode_array_start_addr = (uint8_t *)sos_hdr +
3281 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
1c301f44
HZ		 3282 amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3283
3284 switch (sos_hdr->header.header_version_major) {
3285 case 1:
2a9a151f
JC		 3286 err = psp_init_sos_base_fw(adev);
3287 if (err)
3288 goto out;
3289
1c301f44
HZ		 3290 if (sos_hdr->header.header_version_minor == 1) {
3291 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
222e0a71
CL		 3292 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3293 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
79a0f441 3294 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
222e0a71
CL		 3295 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3296 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
79a0f441 3297 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
1c301f44
HZ		 3298 }
3299 if (sos_hdr->header.header_version_minor == 2) {
3300 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
222e0a71
CL		 3301 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3302 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
79a0f441 3303 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
1c301f44 3304 }
43a188e0
LG		 3305 if (sos_hdr->header.header_version_minor == 3) {
3306 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
222e0a71
CL		 3307 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3308 adev->psp.toc.start_addr = ucode_array_start_addr +
79a0f441 3309 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
222e0a71
CL		 3310 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3311 adev->psp.kdb.start_addr = ucode_array_start_addr +
79a0f441 3312 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
222e0a71
CL		 3313 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3314 adev->psp.spl.start_addr = ucode_array_start_addr +
79a0f441 3315 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
222e0a71
CL		 3316 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3317 adev->psp.rl.start_addr = ucode_array_start_addr +
79a0f441 3318 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
43a188e0 3319 }
1c301f44 3320 break;
f8e487ce
JC		 3321 case 2:
3322 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3323
3324 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3325 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3326 err = -EINVAL;
3327 goto out;
3328 }
3329
3330 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3331 err = parse_sos_bin_descriptor(psp,
3332 &sos_hdr_v2_0->psp_fw_bin[fw_index],
3333 sos_hdr_v2_0);
3334 if (err)
3335 goto out;
3336 }
3337 break;
1c301f44
HZ		 3338 default:
3339 dev_err(adev->dev,
3340 "unsupported psp sos firmware\n");
3341 err = -EINVAL;
3342 goto out;
3343 }
3344
3345 return 0;
3346out:
07dbfc6b 3347 amdgpu_ucode_release(&adev->psp.sos_fw);
1c301f44
HZ		 3348
3349 return err;
3350}
3351
c18dd61a 3352static int parse_ta_bin_descriptor(struct psp_context *psp,
f8e487ce 3353 const struct psp_fw_bin_desc *desc,
c18dd61a 3354 const struct ta_firmware_header_v2_0 *ta_hdr)
dcf9864d
JC		 3355{
3356 uint8_t *ucode_start_addr = NULL;
3357
3358 if (!psp || !desc || !ta_hdr)
3359 return -EINVAL;
3360
a3302729
JC		 3361 ucode_start_addr = (uint8_t *)ta_hdr +
3362 le32_to_cpu(desc->offset_bytes) +
3363 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
dcf9864d
JC		 3364
3365 switch (desc->fw_type) {
3366 case TA_FW_TYPE_PSP_ASD:
de3a1e33
CL		 3367 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
3368 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version);
3369 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3370 psp->asd_context.bin_desc.start_addr = ucode_start_addr;
dcf9864d
JC		 3371 break;
3372 case TA_FW_TYPE_PSP_XGMI:
4320e6f8 3373 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
de3a1e33
CL		 3374 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3375 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr;
dcf9864d
JC		 3376 break;
3377 case TA_FW_TYPE_PSP_RAS:
4320e6f8 3378 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
de3a1e33
CL		 3379 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3380 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr;
dcf9864d
JC		 3381 break;
3382 case TA_FW_TYPE_PSP_HDCP:
4320e6f8 3383 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
de3a1e33
CL		 3384 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3385 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr;
dcf9864d
JC		 3386 break;
3387 case TA_FW_TYPE_PSP_DTM:
4320e6f8 3388 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
de3a1e33
CL		 3389 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3390 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr;
dcf9864d 3391 break;
8602692b 3392 case TA_FW_TYPE_PSP_RAP:
4320e6f8 3393 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version);
de3a1e33
CL		 3394 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes);
3395 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr;
8602692b 3396 break;
ecaafb7b 3397 case TA_FW_TYPE_PSP_SECUREDISPLAY:
4320e6f8 3398 psp->securedisplay_context.context.bin_desc.fw_version =
de3a1e33
CL		 3399 le32_to_cpu(desc->fw_version);
3400 psp->securedisplay_context.context.bin_desc.size_bytes =
3401 le32_to_cpu(desc->size_bytes);
3402 psp->securedisplay_context.context.bin_desc.start_addr =
3403 ucode_start_addr;
ecaafb7b 3404 break;
dcf9864d
JC		 3405 default:
3406 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3407 break;
3408 }
3409
3410 return 0;
3411}
3412
994a9744 3413static int parse_ta_v1_microcode(struct psp_context *psp)
dcf9864d 3414{
994a9744 3415 const struct ta_firmware_header_v1_0 *ta_hdr;
dcf9864d 3416 struct amdgpu_device *adev = psp->adev;
dcf9864d 3417
994a9744
ML		 3418 ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3419
3420 if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
dcf9864d 3421 return -EINVAL;
dcf9864d 3422
994a9744
ML		 3423 adev->psp.xgmi_context.context.bin_desc.fw_version =
3424 le32_to_cpu(ta_hdr->xgmi.fw_version);
3425 adev->psp.xgmi_context.context.bin_desc.size_bytes =
3426 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3427 adev->psp.xgmi_context.context.bin_desc.start_addr =
3428 (uint8_t *)ta_hdr +
3429 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3430
3431 adev->psp.ras_context.context.bin_desc.fw_version =
3432 le32_to_cpu(ta_hdr->ras.fw_version);
3433 adev->psp.ras_context.context.bin_desc.size_bytes =
3434 le32_to_cpu(ta_hdr->ras.size_bytes);
3435 adev->psp.ras_context.context.bin_desc.start_addr =
3436 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3437 le32_to_cpu(ta_hdr->ras.offset_bytes);
3438
3439 adev->psp.hdcp_context.context.bin_desc.fw_version =
3440 le32_to_cpu(ta_hdr->hdcp.fw_version);
3441 adev->psp.hdcp_context.context.bin_desc.size_bytes =
3442 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3443 adev->psp.hdcp_context.context.bin_desc.start_addr =
3444 (uint8_t *)ta_hdr +
3445 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3446
3447 adev->psp.dtm_context.context.bin_desc.fw_version =
3448 le32_to_cpu(ta_hdr->dtm.fw_version);
3449 adev->psp.dtm_context.context.bin_desc.size_bytes =
3450 le32_to_cpu(ta_hdr->dtm.size_bytes);
3451 adev->psp.dtm_context.context.bin_desc.start_addr =
3452 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3453 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3454
3455 adev->psp.securedisplay_context.context.bin_desc.fw_version =
3456 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3457 adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3458 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3459 adev->psp.securedisplay_context.context.bin_desc.start_addr =
3460 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3461 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3462
3463 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
dcf9864d 3464
994a9744
ML		 3465 return 0;
3466}
3467
3468static int parse_ta_v2_microcode(struct psp_context *psp)
3469{
3470 const struct ta_firmware_header_v2_0 *ta_hdr;
3471 struct amdgpu_device *adev = psp->adev;
3472 int err = 0;
3473 int ta_index = 0;
dcf9864d
JC		 3474
3475 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3476
994a9744
ML		 3477 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3478 return -EINVAL;
dcf9864d 3479
f8e487ce 3480 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
dcf9864d 3481 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
994a9744 3482 return -EINVAL;
dcf9864d
JC		 3483 }
3484
3485 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3486 err = parse_ta_bin_descriptor(psp,
3487 &ta_hdr->ta_fw_bin[ta_index],
3488 ta_hdr);
3489 if (err)
994a9744 3490 return err;
dcf9864d
JC		 3491 }
3492
3493 return 0;
994a9744
ML		 3494}
3495
3496int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3497{
3498 const struct common_firmware_header *hdr;
3499 struct amdgpu_device *adev = psp->adev;
3500 char fw_name[PSP_FW_NAME_LEN];
3501 int err;
3502
3503 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
07dbfc6b 3504 err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
994a9744
ML		 3505 if (err)
3506 return err;
3507
3508 hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3509 switch (le16_to_cpu(hdr->header_version_major)) {
3510 case 1:
3511 err = parse_ta_v1_microcode(psp);
3512 break;
3513 case 2:
3514 err = parse_ta_v2_microcode(psp);
3515 break;
3516 default:
3517 dev_err(adev->dev, "unsupported TA header version\n");
3518 err = -EINVAL;
3519 }
3520
07dbfc6b
ML		 3521 if (err)
3522 amdgpu_ucode_release(&adev->psp.ta_fw);
994a9744 3523
dcf9864d
JC		 3524 return err;
3525}
3526
2d39c7ae 3527int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
c4381d0e
BZ		 3528{
3529 struct amdgpu_device *adev = psp->adev;
3530 char fw_name[PSP_FW_NAME_LEN];
3531 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3532 struct amdgpu_firmware_info *info = NULL;
3533 int err = 0;
3534
c4381d0e
BZ		 3535 if (!amdgpu_sriov_vf(adev)) {
3536 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3537 return -EINVAL;
3538 }
3539
3540 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
07dbfc6b 3541 err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
c4381d0e 3542 if (err) {
07dbfc6b
ML		 3543 if (err == -ENODEV) {
3544 dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3545 err = 0;
3546 goto out;
3547 }
c4381d0e 3548 dev_err(adev->dev, "fail to initialize cap microcode\n");
c4381d0e
BZ		 3549 }
3550
3551 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3552 info->ucode_id = AMDGPU_UCODE_ID_CAP;
3553 info->fw = adev->psp.cap_fw;
3554 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3555 adev->psp.cap_fw->data;
3556 adev->firmware.fw_size += ALIGN(
3557 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3558 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3559 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3560 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3561
3562 return 0;
3563
3564out:
07dbfc6b 3565 amdgpu_ucode_release(&adev->psp.cap_fw);
c4381d0e
BZ		 3566 return err;
3567}
3568
0e5ca0d1
HR		 3569static int psp_set_clockgating_state(void *handle,
3570 enum amd_clockgating_state state)
3571{
3572 return 0;
3573}
3574
3575static int psp_set_powergating_state(void *handle,
3576 enum amd_powergating_state state)
3577{
3578 return 0;
3579}
3580
57430471
AG		 3581static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3582 struct device_attribute *attr,
3583 char *buf)
3584{
3585 struct drm_device *ddev = dev_get_drvdata(dev);
1348969a 3586 struct amdgpu_device *adev = drm_to_adev(ddev);
57430471
AG		 3587 uint32_t fw_ver;
3588 int ret;
3589
90f88cdd 3590 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
ac3ff8a9 3591 dev_info(adev->dev, "PSP block is not ready yet\n.");
90f88cdd
AG		 3592 return -EBUSY;
3593 }
3594
57430471
AG		 3595 mutex_lock(&adev->psp.mutex);
3596 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3597 mutex_unlock(&adev->psp.mutex);
3598
3599 if (ret) {
ac3ff8a9 3600 dev_err(adev->dev, "Failed to read USBC PD FW, err = %d\n", ret);
57430471
AG		 3601 return ret;
3602 }
3603
36000c7a 3604 return sysfs_emit(buf, "%x\n", fw_ver);
57430471
AG		 3605}
3606
3607static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3608 struct device_attribute *attr,
3609 const char *buf,
3610 size_t count)
3611{
3612 struct drm_device *ddev = dev_get_drvdata(dev);
1348969a 3613 struct amdgpu_device *adev = drm_to_adev(ddev);
f89f8c6b 3614 int ret, idx;
57430471
AG		 3615 char fw_name[100];
3616 const struct firmware *usbc_pd_fw;
25a3e8ac
AG		 3617 struct amdgpu_bo *fw_buf_bo = NULL;
3618 uint64_t fw_pri_mc_addr;
3619 void *fw_pri_cpu_addr;
57430471 3620
90f88cdd 3621 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
ac3ff8a9 3622 dev_err(adev->dev, "PSP block is not ready yet.");
90f88cdd
AG		 3623 return -EBUSY;
3624 }
57430471 3625
f89f8c6b
AG		 3626 if (!drm_dev_enter(ddev, &idx))
3627 return -ENODEV;
3628
57430471
AG		 3629 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3630 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3631 if (ret)
3632 goto fail;
3633
25a3e8ac
AG		 3634 /* LFB address which is aligned to 1MB boundary per PSP request */
3635 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
58ab2c08
CK		 3636 AMDGPU_GEM_DOMAIN_VRAM |
3637 AMDGPU_GEM_DOMAIN_GTT,
3638 &fw_buf_bo, &fw_pri_mc_addr,
3639 &fw_pri_cpu_addr);
57430471
AG		 3640 if (ret)
3641 goto rel_buf;
3642
25a3e8ac 3643 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
57430471
AG		 3644
3645 mutex_lock(&adev->psp.mutex);
25a3e8ac 3646 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
57430471
AG		 3647 mutex_unlock(&adev->psp.mutex);
3648
25a3e8ac
AG		 3649 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3650
57430471 3651rel_buf:
57430471 3652 release_firmware(usbc_pd_fw);
57430471
AG		 3653fail:
3654 if (ret) {
ac3ff8a9 3655 dev_err(adev->dev, "Failed to load USBC PD FW, err = %d", ret);
f89f8c6b 3656 count = ret;
57430471
AG		 3657 }
3658
f89f8c6b 3659 drm_dev_exit(idx);
57430471
AG		 3660 return count;
3661}
3662
f89f8c6b
AG		 3663void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3664{
3665 int idx;
3666
c58a863b 3667 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
f89f8c6b
AG		 3668 return;
3669
3670 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3671 memcpy(psp->fw_pri_buf, start_addr, bin_size);
3672
3673 drm_dev_exit(idx);
3674}
3675
649663af
ML		 3676/**
3677 * DOC: usbc_pd_fw
3678 * Reading from this file will retrieve the USB-C PD firmware version. Writing to
3679 * this file will trigger the update process.
3680 */
f14c8c3e 3681static DEVICE_ATTR(usbc_pd_fw, 0644,
57430471
AG		 3682 psp_usbc_pd_fw_sysfs_read,
3683 psp_usbc_pd_fw_sysfs_write);
3684
222e0a71
CL		 3685int is_psp_fw_valid(struct psp_bin_desc bin)
3686{
3687 return bin.size_bytes;
3688}
57430471 3689
8424f2cc
LG		 3690static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3691 struct bin_attribute *bin_attr,
3692 char *buffer, loff_t pos, size_t count)
3693{
3694 struct device *dev = kobj_to_dev(kobj);
3695 struct drm_device *ddev = dev_get_drvdata(dev);
3696 struct amdgpu_device *adev = drm_to_adev(ddev);
3697
dfc53681
LG		 3698 adev->psp.vbflash_done = false;
3699
8424f2cc
LG		 3700 /* Safeguard against memory drain */
3701 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
ac3ff8a9 3702 dev_err(adev->dev, "File size cannot exceed %u\n", AMD_VBIOS_FILE_MAX_SIZE_B);
8424f2cc
LG		 3703 kvfree(adev->psp.vbflash_tmp_buf);
3704 adev->psp.vbflash_tmp_buf = NULL;
3705 adev->psp.vbflash_image_size = 0;
3706 return -ENOMEM;
3707 }
3708
3709 /* TODO Just allocate max for now and optimize to realloc later if needed */
3710 if (!adev->psp.vbflash_tmp_buf) {
3711 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3712 if (!adev->psp.vbflash_tmp_buf)
3713 return -ENOMEM;
3714 }
3715
3716 mutex_lock(&adev->psp.mutex);
3717 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3718 adev->psp.vbflash_image_size += count;
3719 mutex_unlock(&adev->psp.mutex);
3720
ac3ff8a9 3721 dev_dbg(adev->dev, "IFWI staged for update\n");
8424f2cc
LG		 3722
3723 return count;
3724}
3725
3726static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3727 struct bin_attribute *bin_attr, char *buffer,
3728 loff_t pos, size_t count)
3729{
3730 struct device *dev = kobj_to_dev(kobj);
3731 struct drm_device *ddev = dev_get_drvdata(dev);
3732 struct amdgpu_device *adev = drm_to_adev(ddev);
3733 struct amdgpu_bo *fw_buf_bo = NULL;
3734 uint64_t fw_pri_mc_addr;
3735 void *fw_pri_cpu_addr;
3736 int ret;
3737
3537d6a4
ML		 3738 if (adev->psp.vbflash_image_size == 0)
3739 return -EINVAL;
3740
ac3ff8a9 3741 dev_dbg(adev->dev, "PSP IFWI flash process initiated\n");
8424f2cc
LG		 3742
3743 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3744 AMDGPU_GPU_PAGE_SIZE,
3745 AMDGPU_GEM_DOMAIN_VRAM,
3746 &fw_buf_bo,
3747 &fw_pri_mc_addr,
3748 &fw_pri_cpu_addr);
3749 if (ret)
3750 goto rel_buf;
3751
3752 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3753
3754 mutex_lock(&adev->psp.mutex);
3755 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3756 mutex_unlock(&adev->psp.mutex);
3757
3758 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3759
3760rel_buf:
3761 kvfree(adev->psp.vbflash_tmp_buf);
3762 adev->psp.vbflash_tmp_buf = NULL;
3763 adev->psp.vbflash_image_size = 0;
3764
3765 if (ret) {
ac3ff8a9 3766 dev_err(adev->dev, "Failed to load IFWI, err = %d\n", ret);
8424f2cc
LG		 3767 return ret;
3768 }
3769
ac3ff8a9 3770 dev_dbg(adev->dev, "PSP IFWI flash process done\n");
8424f2cc
LG		 3771 return 0;
3772}
3773
649663af
ML		 3774/**
3775 * DOC: psp_vbflash
3776 * Writing to this file will stage an IFWI for update. Reading from this file
3777 * will trigger the update process.
3778 */
521289d2
ML		 3779static struct bin_attribute psp_vbflash_bin_attr = {
3780 .attr = {.name = "psp_vbflash", .mode = 0660},
3781 .size = 0,
3782 .write = amdgpu_psp_vbflash_write,
3783 .read = amdgpu_psp_vbflash_read,
3784};
3785
649663af
ML		 3786/**
3787 * DOC: psp_vbflash_status
3788 * The status of the flash process.
3789 * 0: IFWI flash not complete.
3790 * 1: IFWI flash complete.
3791 */
dfc53681
LG		 3792static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3793 struct device_attribute *attr,
3794 char *buf)
3795{
3796 struct drm_device *ddev = dev_get_drvdata(dev);
3797 struct amdgpu_device *adev = drm_to_adev(ddev);
3798 uint32_t vbflash_status;
3799
3800 vbflash_status = psp_vbflash_status(&adev->psp);
3801 if (!adev->psp.vbflash_done)
3802 vbflash_status = 0;
3803 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3804 vbflash_status = 1;
3805
3806 return sysfs_emit(buf, "0x%x\n", vbflash_status);
3807}
521289d2 3808static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
dfc53681 3809
e7347f1c
ML		 3810static struct bin_attribute *bin_flash_attrs[] = {
3811 &psp_vbflash_bin_attr,
3812 NULL
3813};
3814
521289d2
ML		 3815static struct attribute *flash_attrs[] = {
3816 &dev_attr_psp_vbflash_status.attr,
98d19a6c 3817 &dev_attr_usbc_pd_fw.attr,
521289d2 3818 NULL
8424f2cc
LG		 3819};
3820
521289d2 3821static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribute *attr, int idx)
8424f2cc 3822{
521289d2
ML		 3823 struct device *dev = kobj_to_dev(kobj);
3824 struct drm_device *ddev = dev_get_drvdata(dev);
3825 struct amdgpu_device *adev = drm_to_adev(ddev);
8424f2cc 3826
e7347f1c
ML		 3827 if (attr == &dev_attr_usbc_pd_fw.attr)
3828 return adev->psp.sup_pd_fw_up ? 0660 : 0;
8424f2cc 3829
e7347f1c
ML		 3830 return adev->psp.sup_ifwi_up ? 0440 : 0;
3831}
3832
3833static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj,
3834 struct bin_attribute *attr,
3835 int idx)
3836{
3837 struct device *dev = kobj_to_dev(kobj);
3838 struct drm_device *ddev = dev_get_drvdata(dev);
3839 struct amdgpu_device *adev = drm_to_adev(ddev);
3840
3841 return adev->psp.sup_ifwi_up ? 0660 : 0;
8424f2cc
LG		 3842}
3843
521289d2
ML		 3844const struct attribute_group amdgpu_flash_attr_group = {
3845 .attrs = flash_attrs,
e7347f1c
ML		 3846 .bin_attrs = bin_flash_attrs,
3847 .is_bin_visible = amdgpu_bin_flash_attr_is_visible,
521289d2
ML		 3848 .is_visible = amdgpu_flash_attr_is_visible,
3849};
3850
0e5ca0d1
HR		 3851const struct amd_ip_funcs psp_ip_funcs = {
3852 .name = "psp",
3853 .early_init = psp_early_init,
90f88cdd 3854 .late_init = NULL,
0e5ca0d1
HR		 3855 .sw_init = psp_sw_init,
3856 .sw_fini = psp_sw_fini,
3857 .hw_init = psp_hw_init,
3858 .hw_fini = psp_hw_fini,
3859 .suspend = psp_suspend,
3860 .resume = psp_resume,
3861 .is_idle = NULL,
f75a9a5d 3862 .check_soft_reset = NULL,
0e5ca0d1 3863 .wait_for_idle = NULL,
f75a9a5d 3864 .soft_reset = NULL,
0e5ca0d1
HR		 3865 .set_clockgating_state = psp_set_clockgating_state,
3866 .set_powergating_state = psp_set_powergating_state,
3867};
3868
f14c8c3e 3869const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
0e5ca0d1
HR		 3870 .type = AMD_IP_BLOCK_TYPE_PSP,
3871 .major = 3,
3872 .minor = 1,
3873 .rev = 0,
3874 .funcs = &psp_ip_funcs,
3875};
dfbd6438 3876
f14c8c3e 3877const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
dfbd6438
HR		 3878 .type = AMD_IP_BLOCK_TYPE_PSP,
3879 .major = 10,
3880 .minor = 0,
3881 .rev = 0,
3882 .funcs = &psp_ip_funcs,
3883};
654f761c 3884
f14c8c3e 3885const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
654f761c
FX		 3886 .type = AMD_IP_BLOCK_TYPE_PSP,
3887 .major = 11,
3888 .minor = 0,
3889 .rev = 0,
3890 .funcs = &psp_ip_funcs,
3891};
6a7a0bdb 3892
1c7916af
LY		 3893const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3894 .type = AMD_IP_BLOCK_TYPE_PSP,
3895 .major = 11,
3896 .minor = 0,
3897 .rev = 8,
3898 .funcs = &psp_ip_funcs,
3899};
3900
f14c8c3e 3901const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
6a7a0bdb
AL		 3902 .type = AMD_IP_BLOCK_TYPE_PSP,
3903 .major = 12,
3904 .minor = 0,
3905 .rev = 0,
3906 .funcs = &psp_ip_funcs,
3907};
9fbd96a1
HZ		 3908
3909const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3910 .type = AMD_IP_BLOCK_TYPE_PSP,
3911 .major = 13,
3912 .minor = 0,
3913 .rev = 0,
3914 .funcs = &psp_ip_funcs,
3915};
7e8a3ca9
XD		 3916
3917const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3918 .type = AMD_IP_BLOCK_TYPE_PSP,
3919 .major = 13,
3920 .minor = 0,
3921 .rev = 4,
3922 .funcs = &psp_ip_funcs,
3923};
Linux 6.x block layer and io_uring tree(s)