[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_nbio.h

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef __AMDGPU_NBIO_H__
#define __AMDGPU_NBIO_H__

/*
 * amdgpu nbio functions
 */
struct nbio_hdp_flush_reg {
	u32 ref_and_mask_cp0;
	u32 ref_and_mask_cp1;
	u32 ref_and_mask_cp2;
	u32 ref_and_mask_cp3;
	u32 ref_and_mask_cp4;
	u32 ref_and_mask_cp5;
	u32 ref_and_mask_cp6;
	u32 ref_and_mask_cp7;
	u32 ref_and_mask_cp8;
	u32 ref_and_mask_cp9;
	u32 ref_and_mask_sdma0;
	u32 ref_and_mask_sdma1;
	u32 ref_and_mask_sdma2;
	u32 ref_and_mask_sdma3;
	u32 ref_and_mask_sdma4;
	u32 ref_and_mask_sdma5;
	u32 ref_and_mask_sdma6;
	u32 ref_and_mask_sdma7;
};

struct amdgpu_nbio_ras {
	struct amdgpu_ras_block_object ras_block;
	void (*handle_ras_controller_intr_no_bifring)(struct amdgpu_device *adev);
	void (*handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device *adev);
	int (*init_ras_controller_interrupt)(struct amdgpu_device *adev);
	int (*init_ras_err_event_athub_interrupt)(struct amdgpu_device *adev);
};

struct amdgpu_nbio_funcs {
	const struct nbio_hdp_flush_reg *hdp_flush_reg;
	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);
	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);
	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
	u32 (*get_pcie_port_index_offset)(struct amdgpu_device *adev);
	u32 (*get_pcie_port_data_offset)(struct amdgpu_device *adev);
	u32 (*get_rev_id)(struct amdgpu_device *adev);
	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
	u32 (*get_memsize)(struct amdgpu_device *adev);
	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
			bool use_doorbell, int doorbell_index, int doorbell_size);
	void (*vcn_doorbell_range)(struct amdgpu_device *adev, bool use_doorbell,
				   int doorbell_index, int instance);
	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,
					 bool enable);
	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,
						  bool enable);
	void (*ih_doorbell_range)(struct amdgpu_device *adev,
				  bool use_doorbell, int doorbell_index);
	void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
					  bool enable);
	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
						 bool enable);
	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
						bool enable);
	void (*get_clockgating_state)(struct amdgpu_device *adev,
				      u32 *flags);
	void (*ih_control)(struct amdgpu_device *adev);
	void (*init_registers)(struct amdgpu_device *adev);
	void (*remap_hdp_registers)(struct amdgpu_device *adev);
	void (*enable_aspm)(struct amdgpu_device *adev,
			    bool enable);
	void (*program_aspm)(struct amdgpu_device *adev);
	void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
	void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev);
	void (*clear_doorbell_interrupt)(struct amdgpu_device *adev);
};

struct amdgpu_nbio {
	const struct nbio_hdp_flush_reg *hdp_flush_reg;
	struct amdgpu_irq_src ras_controller_irq;
	struct amdgpu_irq_src ras_err_event_athub_irq;
	struct ras_common_if *ras_if;
	const struct amdgpu_nbio_funcs *funcs;
	struct amdgpu_nbio_ras  *ras;
};

int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
#endif
Commit	Line	Data
078ef4e9 HZ	1	/*
	2	* Copyright 2019 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#ifndef __AMDGPU_NBIO_H__
	24	#define __AMDGPU_NBIO_H__
	25
	26	/*
	27	* amdgpu nbio functions
	28	*/
	29	struct nbio_hdp_flush_reg {
	30	u32 ref_and_mask_cp0;
	31	u32 ref_and_mask_cp1;
	32	u32 ref_and_mask_cp2;
	33	u32 ref_and_mask_cp3;
	34	u32 ref_and_mask_cp4;
	35	u32 ref_and_mask_cp5;
	36	u32 ref_and_mask_cp6;
	37	u32 ref_and_mask_cp7;
	38	u32 ref_and_mask_cp8;
	39	u32 ref_and_mask_cp9;
	40	u32 ref_and_mask_sdma0;
	41	u32 ref_and_mask_sdma1;
	42	u32 ref_and_mask_sdma2;
	43	u32 ref_and_mask_sdma3;
	44	u32 ref_and_mask_sdma4;
	45	u32 ref_and_mask_sdma5;
	46	u32 ref_and_mask_sdma6;
	47	u32 ref_and_mask_sdma7;
	48	};
	49
2e54fe5d	50	struct amdgpu_nbio_ras {
2e54fe5d	51	struct amdgpu_ras_block_object ras_block;
6e36f231 HZ	52	void (handle_ras_controller_intr_no_bifring)(struct amdgpu_device adev);
	53	void (handle_ras_err_event_athub_intr_no_bifring)(struct amdgpu_device adev);
	54	int (init_ras_controller_interrupt)(struct amdgpu_device adev);
	55	int (init_ras_err_event_athub_interrupt)(struct amdgpu_device adev);
6e36f231 HZ	56	};
6e36f231 HZ	57
078ef4e9 HZ	58	struct amdgpu_nbio_funcs {
	59	const struct nbio_hdp_flush_reg *hdp_flush_reg;
	60	u32 (get_hdp_flush_req_offset)(struct amdgpu_device adev);
	61	u32 (get_hdp_flush_done_offset)(struct amdgpu_device adev);
	62	u32 (get_pcie_index_offset)(struct amdgpu_device adev);
	63	u32 (get_pcie_data_offset)(struct amdgpu_device adev);
5de54343 HR	64	u32 (get_pcie_port_index_offset)(struct amdgpu_device adev);
5de54343 HR	65	u32 (get_pcie_port_data_offset)(struct amdgpu_device adev);
078ef4e9 HZ	66	u32 (get_rev_id)(struct amdgpu_device adev);
078ef4e9 HZ	67	void (mc_access_enable)(struct amdgpu_device adev, bool enable);
078ef4e9 HZ	68	u32 (get_memsize)(struct amdgpu_device adev);
	69	void (sdma_doorbell_range)(struct amdgpu_device adev, int instance,
	70	bool use_doorbell, int doorbell_index, int doorbell_size);
	71	void (vcn_doorbell_range)(struct amdgpu_device adev, bool use_doorbell,
	72	int doorbell_index, int instance);
	73	void (enable_doorbell_aperture)(struct amdgpu_device adev,
	74	bool enable);
	75	void (enable_doorbell_selfring_aperture)(struct amdgpu_device adev,
	76	bool enable);
	77	void (ih_doorbell_range)(struct amdgpu_device adev,
	78	bool use_doorbell, int doorbell_index);
956f6705 LM	79	void (enable_doorbell_interrupt)(struct amdgpu_device adev,
956f6705 LM	80	bool enable);
078ef4e9 HZ	81	void (update_medium_grain_clock_gating)(struct amdgpu_device adev,
	82	bool enable);
	83	void (update_medium_grain_light_sleep)(struct amdgpu_device adev,
	84	bool enable);
	85	void (get_clockgating_state)(struct amdgpu_device adev,
	86	u32 *flags);
	87	void (ih_control)(struct amdgpu_device adev);
	88	void (init_registers)(struct amdgpu_device adev);
078ef4e9	89	void (remap_hdp_registers)(struct amdgpu_device adev);
f1213b15 EQ	90	void (enable_aspm)(struct amdgpu_device adev,
f1213b15 EQ	91	bool enable);
e1edaeaf	92	void (program_aspm)(struct amdgpu_device adev);
5a5da8ae	93	void (apply_lc_spc_mode_wa)(struct amdgpu_device adev);
adcf949e	94	void (apply_l1_link_width_reconfig_wa)(struct amdgpu_device adev);
1bece222	95	void (clear_doorbell_interrupt)(struct amdgpu_device adev);
078ef4e9 HZ	96	};
	97
	98	struct amdgpu_nbio {
	99	const struct nbio_hdp_flush_reg *hdp_flush_reg;
4e644fff HZ	100	struct amdgpu_irq_src ras_controller_irq;
4e644fff HZ	101	struct amdgpu_irq_src ras_err_event_athub_irq;
9ad1dc29	102	struct ras_common_if *ras_if;
078ef4e9	103	const struct amdgpu_nbio_funcs *funcs;
2e54fe5d	104	struct amdgpu_nbio_ras *ras;
078ef4e9 HZ	105	};
078ef4e9 HZ	106
4e9b1fa5	107	int amdgpu_nbio_ras_late_init(struct amdgpu_device adev, struct ras_common_if ras_block);
de9bbd52	108	void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
078ef4e9	109	#endif