Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
fdf2f6c5 | 28 | |
d38ceaf9 AD |
29 | #include "amdgpu.h" |
30 | #include <drm/amdgpu_drm.h> | |
72c8c97b | 31 | #include <drm/drm_drv.h> |
45b64fd9 | 32 | #include <drm/drm_fb_helper.h> |
d38ceaf9 AD |
33 | #include "amdgpu_uvd.h" |
34 | #include "amdgpu_vce.h" | |
32d8c662 | 35 | #include "atom.h" |
d38ceaf9 AD |
36 | |
37 | #include <linux/vga_switcheroo.h> | |
38 | #include <linux/slab.h> | |
fdf2f6c5 SR |
39 | #include <linux/uaccess.h> |
40 | #include <linux/pci.h> | |
d38ceaf9 | 41 | #include <linux/pm_runtime.h> |
130e0371 | 42 | #include "amdgpu_amdkfd.h" |
2cddc50e | 43 | #include "amdgpu_gem.h" |
5df58525 | 44 | #include "amdgpu_display.h" |
5cb77114 | 45 | #include "amdgpu_ras.h" |
e3e84b0a | 46 | #include "amd_pcie.h" |
d38ceaf9 | 47 | |
fdafb359 | 48 | void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) |
62d73fbc EQ |
49 | { |
50 | struct amdgpu_gpu_instance *gpu_instance; | |
51 | int i; | |
52 | ||
53 | mutex_lock(&mgpu_info.mutex); | |
54 | ||
55 | for (i = 0; i < mgpu_info.num_gpu; i++) { | |
56 | gpu_instance = &(mgpu_info.gpu_ins[i]); | |
57 | if (gpu_instance->adev == adev) { | |
58 | mgpu_info.gpu_ins[i] = | |
59 | mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; | |
60 | mgpu_info.num_gpu--; | |
61 | if (adev->flags & AMD_IS_APU) | |
62 | mgpu_info.num_apu--; | |
63 | else | |
64 | mgpu_info.num_dgpu--; | |
65 | break; | |
66 | } | |
67 | } | |
68 | ||
69 | mutex_unlock(&mgpu_info.mutex); | |
70 | } | |
71 | ||
d38ceaf9 AD |
72 | /** |
73 | * amdgpu_driver_unload_kms - Main unload function for KMS. | |
74 | * | |
75 | * @dev: drm dev pointer | |
76 | * | |
77 | * This is the main unload function for KMS (all asics). | |
78 | * Returns 0 on success. | |
79 | */ | |
11b3c20b | 80 | void amdgpu_driver_unload_kms(struct drm_device *dev) |
d38ceaf9 | 81 | { |
1348969a | 82 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
83 | |
84 | if (adev == NULL) | |
11b3c20b | 85 | return; |
d38ceaf9 | 86 | |
62d73fbc EQ |
87 | amdgpu_unregister_gpu_instance(adev); |
88 | ||
d38ceaf9 | 89 | if (adev->rmmio == NULL) |
8aba21b7 | 90 | return; |
d38ceaf9 | 91 | |
3fa8f89d S |
92 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) |
93 | DRM_WARN("smart shift update failed\n"); | |
94 | ||
d38ceaf9 | 95 | amdgpu_acpi_fini(adev); |
72c8c97b | 96 | amdgpu_device_fini_hw(adev); |
d38ceaf9 AD |
97 | } |
98 | ||
fdafb359 | 99 | void amdgpu_register_gpu_instance(struct amdgpu_device *adev) |
62d73fbc EQ |
100 | { |
101 | struct amdgpu_gpu_instance *gpu_instance; | |
102 | ||
103 | mutex_lock(&mgpu_info.mutex); | |
104 | ||
105 | if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { | |
106 | DRM_ERROR("Cannot register more gpu instance\n"); | |
107 | mutex_unlock(&mgpu_info.mutex); | |
108 | return; | |
109 | } | |
110 | ||
111 | gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); | |
112 | gpu_instance->adev = adev; | |
113 | gpu_instance->mgpu_fan_enabled = 0; | |
114 | ||
115 | mgpu_info.num_gpu++; | |
116 | if (adev->flags & AMD_IS_APU) | |
117 | mgpu_info.num_apu++; | |
118 | else | |
119 | mgpu_info.num_dgpu++; | |
120 | ||
121 | mutex_unlock(&mgpu_info.mutex); | |
122 | } | |
123 | ||
d38ceaf9 AD |
124 | /** |
125 | * amdgpu_driver_load_kms - Main load function for KMS. | |
126 | * | |
8aba21b7 | 127 | * @adev: pointer to struct amdgpu_device |
d38ceaf9 AD |
128 | * @flags: device flags |
129 | * | |
130 | * This is the main load function for KMS (all asics). | |
131 | * Returns 0 on success, error on failure. | |
132 | */ | |
8aba21b7 | 133 | int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) |
d38ceaf9 | 134 | { |
8aba21b7 | 135 | struct drm_device *dev; |
1daee8b4 | 136 | int r, acpi_status; |
d38ceaf9 | 137 | |
8aba21b7 | 138 | dev = adev_to_drm(adev); |
d38ceaf9 | 139 | |
d38ceaf9 AD |
140 | /* amdgpu_device_init should report only fatal error |
141 | * like memory allocation failure or iomapping failure, | |
142 | * or memory manager initialization failure, it must | |
143 | * properly initialize the GPU MC controller and permit | |
144 | * VRAM allocation | |
145 | */ | |
8aba21b7 | 146 | r = amdgpu_device_init(adev, flags); |
1daee8b4 | 147 | if (r) { |
8f66090b | 148 | dev_err(dev->dev, "Fatal error during GPU init\n"); |
d38ceaf9 AD |
149 | goto out; |
150 | } | |
151 | ||
9c913f38 | 152 | adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; |
b98c6299 | 153 | if (amdgpu_device_supports_px(dev) && |
9c913f38 | 154 | (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ |
50fe04d4 | 155 | adev->pm.rpm_mode = AMDGPU_RUNPM_PX; |
d00a88ab | 156 | dev_info(adev->dev, "Using ATPX for runtime pm\n"); |
157e8306 | 157 | } else if (amdgpu_device_supports_boco(dev) && |
9c913f38 | 158 | (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ |
50fe04d4 | 159 | adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; |
d00a88ab | 160 | dev_info(adev->dev, "Using BOCO for runtime pm\n"); |
b38c6968 AD |
161 | } else if (amdgpu_device_supports_baco(dev) && |
162 | (amdgpu_runtime_pm != 0)) { | |
163 | switch (adev->asic_type) { | |
b38c6968 AD |
164 | case CHIP_VEGA20: |
165 | case CHIP_ARCTURUS: | |
9c913f38 | 166 | /* enable BACO as runpm mode if runpm=1 */ |
b38c6968 | 167 | if (amdgpu_runtime_pm > 0) |
9c913f38 | 168 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; |
b38c6968 | 169 | break; |
cd527780 | 170 | case CHIP_VEGA10: |
9c913f38 | 171 | /* enable BACO as runpm mode if noretry=0 */ |
9b498efa | 172 | if (!adev->gmc.noretry) |
9c913f38 | 173 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; |
cd527780 | 174 | break; |
b38c6968 | 175 | default: |
9c913f38 GC |
176 | /* enable BACO as runpm mode on CI+ */ |
177 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; | |
b38c6968 AD |
178 | break; |
179 | } | |
d1acd68b | 180 | |
9c913f38 | 181 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) |
d00a88ab | 182 | dev_info(adev->dev, "Using BACO for runtime pm\n"); |
b38c6968 | 183 | } |
72f058b7 | 184 | |
d38ceaf9 AD |
185 | /* Call ACPI methods: require modeset init |
186 | * but failure is not fatal | |
187 | */ | |
ad36d71b AP |
188 | |
189 | acpi_status = amdgpu_acpi_init(adev); | |
190 | if (acpi_status) | |
8f66090b | 191 | dev_dbg(dev->dev, "Error during ACPI methods call\n"); |
d38ceaf9 | 192 | |
3fa8f89d S |
193 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) |
194 | DRM_WARN("smart shift update failed\n"); | |
195 | ||
d38ceaf9 | 196 | out: |
d0d66b8c | 197 | if (r) |
d38ceaf9 | 198 | amdgpu_driver_unload_kms(dev); |
d38ceaf9 AD |
199 | |
200 | return r; | |
201 | } | |
202 | ||
000cab9a HR |
203 | static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, |
204 | struct drm_amdgpu_query_fw *query_fw, | |
205 | struct amdgpu_device *adev) | |
206 | { | |
207 | switch (query_fw->fw_type) { | |
208 | case AMDGPU_INFO_FW_VCE: | |
209 | fw_info->ver = adev->vce.fw_version; | |
210 | fw_info->feature = adev->vce.fb_version; | |
211 | break; | |
212 | case AMDGPU_INFO_FW_UVD: | |
213 | fw_info->ver = adev->uvd.fw_version; | |
214 | fw_info->feature = 0; | |
215 | break; | |
3ac952b1 AD |
216 | case AMDGPU_INFO_FW_VCN: |
217 | fw_info->ver = adev->vcn.fw_version; | |
218 | fw_info->feature = 0; | |
219 | break; | |
000cab9a | 220 | case AMDGPU_INFO_FW_GMC: |
770d13b1 | 221 | fw_info->ver = adev->gmc.fw_version; |
000cab9a HR |
222 | fw_info->feature = 0; |
223 | break; | |
224 | case AMDGPU_INFO_FW_GFX_ME: | |
225 | fw_info->ver = adev->gfx.me_fw_version; | |
226 | fw_info->feature = adev->gfx.me_feature_version; | |
227 | break; | |
228 | case AMDGPU_INFO_FW_GFX_PFP: | |
229 | fw_info->ver = adev->gfx.pfp_fw_version; | |
230 | fw_info->feature = adev->gfx.pfp_feature_version; | |
231 | break; | |
232 | case AMDGPU_INFO_FW_GFX_CE: | |
233 | fw_info->ver = adev->gfx.ce_fw_version; | |
234 | fw_info->feature = adev->gfx.ce_feature_version; | |
235 | break; | |
236 | case AMDGPU_INFO_FW_GFX_RLC: | |
237 | fw_info->ver = adev->gfx.rlc_fw_version; | |
238 | fw_info->feature = adev->gfx.rlc_feature_version; | |
239 | break; | |
621a6318 HR |
240 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: |
241 | fw_info->ver = adev->gfx.rlc_srlc_fw_version; | |
242 | fw_info->feature = adev->gfx.rlc_srlc_feature_version; | |
243 | break; | |
244 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: | |
245 | fw_info->ver = adev->gfx.rlc_srlg_fw_version; | |
246 | fw_info->feature = adev->gfx.rlc_srlg_feature_version; | |
247 | break; | |
248 | case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: | |
249 | fw_info->ver = adev->gfx.rlc_srls_fw_version; | |
250 | fw_info->feature = adev->gfx.rlc_srls_feature_version; | |
251 | break; | |
670c6edf HZ |
252 | case AMDGPU_INFO_FW_GFX_RLCP: |
253 | fw_info->ver = adev->gfx.rlcp_ucode_version; | |
254 | fw_info->feature = adev->gfx.rlcp_ucode_feature_version; | |
255 | break; | |
256 | case AMDGPU_INFO_FW_GFX_RLCV: | |
257 | fw_info->ver = adev->gfx.rlcv_ucode_version; | |
258 | fw_info->feature = adev->gfx.rlcv_ucode_feature_version; | |
259 | break; | |
000cab9a HR |
260 | case AMDGPU_INFO_FW_GFX_MEC: |
261 | if (query_fw->index == 0) { | |
262 | fw_info->ver = adev->gfx.mec_fw_version; | |
263 | fw_info->feature = adev->gfx.mec_feature_version; | |
264 | } else if (query_fw->index == 1) { | |
265 | fw_info->ver = adev->gfx.mec2_fw_version; | |
266 | fw_info->feature = adev->gfx.mec2_feature_version; | |
267 | } else | |
268 | return -EINVAL; | |
269 | break; | |
270 | case AMDGPU_INFO_FW_SMC: | |
271 | fw_info->ver = adev->pm.fw_version; | |
272 | fw_info->feature = 0; | |
273 | break; | |
9b9ca62d | 274 | case AMDGPU_INFO_FW_TA: |
f399d4de | 275 | switch (query_fw->index) { |
4d5ae731 | 276 | case TA_FW_TYPE_PSP_XGMI: |
4320e6f8 | 277 | fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; |
de3a1e33 CL |
278 | fw_info->feature = adev->psp.xgmi_context.context |
279 | .bin_desc.feature_version; | |
f399d4de | 280 | break; |
4d5ae731 | 281 | case TA_FW_TYPE_PSP_RAS: |
4320e6f8 | 282 | fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; |
de3a1e33 CL |
283 | fw_info->feature = adev->psp.ras_context.context |
284 | .bin_desc.feature_version; | |
f399d4de | 285 | break; |
4d5ae731 | 286 | case TA_FW_TYPE_PSP_HDCP: |
4320e6f8 | 287 | fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; |
de3a1e33 CL |
288 | fw_info->feature = adev->psp.hdcp_context.context |
289 | .bin_desc.feature_version; | |
f399d4de | 290 | break; |
4d5ae731 | 291 | case TA_FW_TYPE_PSP_DTM: |
4320e6f8 | 292 | fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; |
de3a1e33 CL |
293 | fw_info->feature = adev->psp.dtm_context.context |
294 | .bin_desc.feature_version; | |
f399d4de | 295 | break; |
4d5ae731 | 296 | case TA_FW_TYPE_PSP_RAP: |
4320e6f8 | 297 | fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; |
de3a1e33 CL |
298 | fw_info->feature = adev->psp.rap_context.context |
299 | .bin_desc.feature_version; | |
4890d4e9 | 300 | break; |
e7bdf00e | 301 | case TA_FW_TYPE_PSP_SECUREDISPLAY: |
4320e6f8 | 302 | fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; |
de3a1e33 CL |
303 | fw_info->feature = |
304 | adev->psp.securedisplay_context.context.bin_desc | |
305 | .feature_version; | |
e7bdf00e | 306 | break; |
f399d4de C |
307 | default: |
308 | return -EINVAL; | |
9b9ca62d | 309 | } |
310 | break; | |
000cab9a HR |
311 | case AMDGPU_INFO_FW_SDMA: |
312 | if (query_fw->index >= adev->sdma.num_instances) | |
313 | return -EINVAL; | |
314 | fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; | |
315 | fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; | |
316 | break; | |
6a7ed07e | 317 | case AMDGPU_INFO_FW_SOS: |
222e0a71 CL |
318 | fw_info->ver = adev->psp.sos.fw_version; |
319 | fw_info->feature = adev->psp.sos.feature_version; | |
6a7ed07e HR |
320 | break; |
321 | case AMDGPU_INFO_FW_ASD: | |
de3a1e33 CL |
322 | fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; |
323 | fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; | |
6a7ed07e | 324 | break; |
4d11b4b2 DF |
325 | case AMDGPU_INFO_FW_DMCU: |
326 | fw_info->ver = adev->dm.dmcu_fw_version; | |
327 | fw_info->feature = 0; | |
328 | break; | |
976e51a7 NK |
329 | case AMDGPU_INFO_FW_DMCUB: |
330 | fw_info->ver = adev->dm.dmcub_fw_version; | |
331 | fw_info->feature = 0; | |
332 | break; | |
5120cb54 | 333 | case AMDGPU_INFO_FW_TOC: |
222e0a71 CL |
334 | fw_info->ver = adev->psp.toc.fw_version; |
335 | fw_info->feature = adev->psp.toc.feature_version; | |
5120cb54 | 336 | break; |
c4381d0e BZ |
337 | case AMDGPU_INFO_FW_CAP: |
338 | fw_info->ver = adev->psp.cap_fw_version; | |
339 | fw_info->feature = adev->psp.cap_feature_version; | |
340 | break; | |
10faf078 | 341 | case AMDGPU_INFO_FW_MES_KIQ: |
1d522b51 GS |
342 | fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; |
343 | fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) | |
344 | >> AMDGPU_MES_FEAT_VERSION_SHIFT; | |
10faf078 YZ |
345 | break; |
346 | case AMDGPU_INFO_FW_MES: | |
1d522b51 GS |
347 | fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; |
348 | fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) | |
349 | >> AMDGPU_MES_FEAT_VERSION_SHIFT; | |
10faf078 | 350 | break; |
b7236296 DF |
351 | case AMDGPU_INFO_FW_IMU: |
352 | fw_info->ver = adev->gfx.imu_fw_version; | |
353 | fw_info->feature = 0; | |
354 | break; | |
5f6e9cdc LY |
355 | case AMDGPU_INFO_FW_VPE: |
356 | fw_info->ver = adev->vpe.fw_version; | |
357 | fw_info->feature = adev->vpe.feature_version; | |
358 | break; | |
000cab9a HR |
359 | default: |
360 | return -EINVAL; | |
361 | } | |
362 | return 0; | |
363 | } | |
364 | ||
a245daf3 CK |
365 | static int amdgpu_hw_ip_info(struct amdgpu_device *adev, |
366 | struct drm_amdgpu_info *info, | |
367 | struct drm_amdgpu_info_hw_ip *result) | |
368 | { | |
369 | uint32_t ib_start_alignment = 0; | |
370 | uint32_t ib_size_alignment = 0; | |
371 | enum amd_ip_block_type type; | |
1b1f2fec | 372 | unsigned int num_rings = 0; |
a245daf3 CK |
373 | unsigned int i, j; |
374 | ||
375 | if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) | |
376 | return -EINVAL; | |
377 | ||
378 | switch (info->query_hw_ip.type) { | |
379 | case AMDGPU_HW_IP_GFX: | |
380 | type = AMD_IP_BLOCK_TYPE_GFX; | |
381 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) | |
c66ed765 | 382 | if (adev->gfx.gfx_ring[i].sched.ready) |
1b1f2fec | 383 | ++num_rings; |
a245daf3 CK |
384 | ib_start_alignment = 32; |
385 | ib_size_alignment = 32; | |
386 | break; | |
387 | case AMDGPU_HW_IP_COMPUTE: | |
388 | type = AMD_IP_BLOCK_TYPE_GFX; | |
389 | for (i = 0; i < adev->gfx.num_compute_rings; i++) | |
c66ed765 | 390 | if (adev->gfx.compute_ring[i].sched.ready) |
1b1f2fec | 391 | ++num_rings; |
a245daf3 CK |
392 | ib_start_alignment = 32; |
393 | ib_size_alignment = 32; | |
394 | break; | |
395 | case AMDGPU_HW_IP_DMA: | |
396 | type = AMD_IP_BLOCK_TYPE_SDMA; | |
397 | for (i = 0; i < adev->sdma.num_instances; i++) | |
c66ed765 | 398 | if (adev->sdma.instance[i].ring.sched.ready) |
1b1f2fec | 399 | ++num_rings; |
a245daf3 CK |
400 | ib_start_alignment = 256; |
401 | ib_size_alignment = 4; | |
402 | break; | |
403 | case AMDGPU_HW_IP_UVD: | |
404 | type = AMD_IP_BLOCK_TYPE_UVD; | |
405 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) { | |
406 | if (adev->uvd.harvest_config & (1 << i)) | |
407 | continue; | |
1b1f2fec | 408 | |
c66ed765 | 409 | if (adev->uvd.inst[i].ring.sched.ready) |
1b1f2fec | 410 | ++num_rings; |
a245daf3 CK |
411 | } |
412 | ib_start_alignment = 64; | |
413 | ib_size_alignment = 64; | |
414 | break; | |
415 | case AMDGPU_HW_IP_VCE: | |
416 | type = AMD_IP_BLOCK_TYPE_VCE; | |
417 | for (i = 0; i < adev->vce.num_rings; i++) | |
c66ed765 | 418 | if (adev->vce.ring[i].sched.ready) |
1b1f2fec | 419 | ++num_rings; |
a245daf3 CK |
420 | ib_start_alignment = 4; |
421 | ib_size_alignment = 1; | |
422 | break; | |
423 | case AMDGPU_HW_IP_UVD_ENC: | |
424 | type = AMD_IP_BLOCK_TYPE_UVD; | |
425 | for (i = 0; i < adev->uvd.num_uvd_inst; i++) { | |
426 | if (adev->uvd.harvest_config & (1 << i)) | |
427 | continue; | |
1b1f2fec | 428 | |
a245daf3 | 429 | for (j = 0; j < adev->uvd.num_enc_rings; j++) |
c66ed765 | 430 | if (adev->uvd.inst[i].ring_enc[j].sched.ready) |
1b1f2fec | 431 | ++num_rings; |
a245daf3 CK |
432 | } |
433 | ib_start_alignment = 64; | |
434 | ib_size_alignment = 64; | |
435 | break; | |
436 | case AMDGPU_HW_IP_VCN_DEC: | |
437 | type = AMD_IP_BLOCK_TYPE_VCN; | |
fa739f4b | 438 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
56ee5122 | 439 | if (adev->vcn.harvest_config & (1 << i)) |
cd1fd7b3 JZ |
440 | continue; |
441 | ||
fa739f4b JZ |
442 | if (adev->vcn.inst[i].ring_dec.sched.ready) |
443 | ++num_rings; | |
444 | } | |
a245daf3 CK |
445 | ib_start_alignment = 16; |
446 | ib_size_alignment = 16; | |
447 | break; | |
448 | case AMDGPU_HW_IP_VCN_ENC: | |
449 | type = AMD_IP_BLOCK_TYPE_VCN; | |
fa739f4b | 450 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
56ee5122 | 451 | if (adev->vcn.harvest_config & (1 << i)) |
cd1fd7b3 JZ |
452 | continue; |
453 | ||
fa739f4b JZ |
454 | for (j = 0; j < adev->vcn.num_enc_rings; j++) |
455 | if (adev->vcn.inst[i].ring_enc[j].sched.ready) | |
456 | ++num_rings; | |
457 | } | |
a245daf3 CK |
458 | ib_start_alignment = 64; |
459 | ib_size_alignment = 1; | |
460 | break; | |
461 | case AMDGPU_HW_IP_VCN_JPEG: | |
52f2e779 LL |
462 | type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? |
463 | AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; | |
464 | ||
0388aee7 LL |
465 | for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { |
466 | if (adev->jpeg.harvest_config & (1 << i)) | |
cd1fd7b3 JZ |
467 | continue; |
468 | ||
bc224553 JZ |
469 | for (j = 0; j < adev->jpeg.num_jpeg_rings; j++) |
470 | if (adev->jpeg.inst[i].ring_dec[j].sched.ready) | |
471 | ++num_rings; | |
fa739f4b | 472 | } |
a245daf3 CK |
473 | ib_start_alignment = 16; |
474 | ib_size_alignment = 16; | |
475 | break; | |
523c1280 LY |
476 | case AMDGPU_HW_IP_VPE: |
477 | type = AMD_IP_BLOCK_TYPE_VPE; | |
478 | if (adev->vpe.ring.sched.ready) | |
479 | ++num_rings; | |
480 | ib_start_alignment = 256; | |
481 | ib_size_alignment = 4; | |
482 | break; | |
a245daf3 CK |
483 | default: |
484 | return -EINVAL; | |
485 | } | |
486 | ||
487 | for (i = 0; i < adev->num_ip_blocks; i++) | |
488 | if (adev->ip_blocks[i].version->type == type && | |
489 | adev->ip_blocks[i].status.valid) | |
490 | break; | |
491 | ||
492 | if (i == adev->num_ip_blocks) | |
493 | return 0; | |
494 | ||
1b1f2fec CK |
495 | num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], |
496 | num_rings); | |
497 | ||
a245daf3 CK |
498 | result->hw_ip_version_major = adev->ip_blocks[i].version->major; |
499 | result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; | |
af14e7c2 AD |
500 | |
501 | if (adev->asic_type >= CHIP_VEGA10) { | |
502 | switch (type) { | |
503 | case AMD_IP_BLOCK_TYPE_GFX: | |
4e8303cf LL |
504 | result->ip_discovery_version = |
505 | amdgpu_ip_version(adev, GC_HWIP, 0); | |
af14e7c2 AD |
506 | break; |
507 | case AMD_IP_BLOCK_TYPE_SDMA: | |
4e8303cf LL |
508 | result->ip_discovery_version = |
509 | amdgpu_ip_version(adev, SDMA0_HWIP, 0); | |
af14e7c2 AD |
510 | break; |
511 | case AMD_IP_BLOCK_TYPE_UVD: | |
512 | case AMD_IP_BLOCK_TYPE_VCN: | |
513 | case AMD_IP_BLOCK_TYPE_JPEG: | |
4e8303cf LL |
514 | result->ip_discovery_version = |
515 | amdgpu_ip_version(adev, UVD_HWIP, 0); | |
af14e7c2 AD |
516 | break; |
517 | case AMD_IP_BLOCK_TYPE_VCE: | |
4e8303cf LL |
518 | result->ip_discovery_version = |
519 | amdgpu_ip_version(adev, VCE_HWIP, 0); | |
af14e7c2 AD |
520 | break; |
521 | default: | |
522 | result->ip_discovery_version = 0; | |
523 | break; | |
524 | } | |
525 | } else { | |
526 | result->ip_discovery_version = 0; | |
527 | } | |
a245daf3 | 528 | result->capabilities_flags = 0; |
1b1f2fec | 529 | result->available_rings = (1 << num_rings) - 1; |
a245daf3 CK |
530 | result->ib_start_alignment = ib_start_alignment; |
531 | result->ib_size_alignment = ib_size_alignment; | |
532 | return 0; | |
533 | } | |
534 | ||
d38ceaf9 AD |
535 | /* |
536 | * Userspace get information ioctl | |
537 | */ | |
538 | /** | |
539 | * amdgpu_info_ioctl - answer a device specific request. | |
540 | * | |
8970b698 | 541 | * @dev: drm device pointer |
d38ceaf9 AD |
542 | * @data: request object |
543 | * @filp: drm filp | |
544 | * | |
545 | * This function is used to pass device specific parameters to the userspace | |
546 | * drivers. Examples include: pci device id, pipeline parms, tiling params, | |
547 | * etc. (all asics). | |
548 | * Returns 0 on success, -EINVAL on failure. | |
549 | */ | |
5088d657 | 550 | int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) |
d38ceaf9 | 551 | { |
1348969a | 552 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
553 | struct drm_amdgpu_info *info = data; |
554 | struct amdgpu_mode_info *minfo = &adev->mode_info; | |
ec2c467e | 555 | void __user *out = (void __user *)(uintptr_t)info->return_pointer; |
d38ceaf9 AD |
556 | uint32_t size = info->return_size; |
557 | struct drm_crtc *crtc; | |
558 | uint32_t ui32 = 0; | |
559 | uint64_t ui64 = 0; | |
a245daf3 | 560 | int i, found; |
5ebbac4b | 561 | int ui32_size = sizeof(ui32); |
d38ceaf9 AD |
562 | |
563 | if (!info->return_size || !info->return_pointer) | |
564 | return -EINVAL; | |
565 | ||
566 | switch (info->query) { | |
567 | case AMDGPU_INFO_ACCEL_WORKING: | |
568 | ui32 = adev->accel_working; | |
569 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
570 | case AMDGPU_INFO_CRTC_FROM_ID: | |
571 | for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { | |
572 | crtc = (struct drm_crtc *)minfo->crtcs[i]; | |
573 | if (crtc && crtc->base.id == info->mode_crtc.id) { | |
574 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); | |
a0cc8e15 | 575 | |
d38ceaf9 AD |
576 | ui32 = amdgpu_crtc->crtc_id; |
577 | found = 1; | |
578 | break; | |
579 | } | |
580 | } | |
581 | if (!found) { | |
582 | DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); | |
583 | return -EINVAL; | |
584 | } | |
585 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
586 | case AMDGPU_INFO_HW_IP_INFO: { | |
587 | struct drm_amdgpu_info_hw_ip ip = {}; | |
a245daf3 | 588 | int ret; |
d38ceaf9 | 589 | |
a245daf3 CK |
590 | ret = amdgpu_hw_ip_info(adev, info, &ip); |
591 | if (ret) | |
592 | return ret; | |
d38ceaf9 | 593 | |
a0cc8e15 | 594 | ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip))); |
a245daf3 | 595 | return ret ? -EFAULT : 0; |
d38ceaf9 AD |
596 | } |
597 | case AMDGPU_INFO_HW_IP_COUNT: { | |
5fc3aeeb | 598 | enum amd_ip_block_type type; |
d38ceaf9 AD |
599 | uint32_t count = 0; |
600 | ||
601 | switch (info->query_hw_ip.type) { | |
602 | case AMDGPU_HW_IP_GFX: | |
5fc3aeeb | 603 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
604 | break; |
605 | case AMDGPU_HW_IP_COMPUTE: | |
5fc3aeeb | 606 | type = AMD_IP_BLOCK_TYPE_GFX; |
d38ceaf9 AD |
607 | break; |
608 | case AMDGPU_HW_IP_DMA: | |
5fc3aeeb | 609 | type = AMD_IP_BLOCK_TYPE_SDMA; |
d38ceaf9 AD |
610 | break; |
611 | case AMDGPU_HW_IP_UVD: | |
5fc3aeeb | 612 | type = AMD_IP_BLOCK_TYPE_UVD; |
d38ceaf9 AD |
613 | break; |
614 | case AMDGPU_HW_IP_VCE: | |
5fc3aeeb | 615 | type = AMD_IP_BLOCK_TYPE_VCE; |
d38ceaf9 | 616 | break; |
63defd3f LL |
617 | case AMDGPU_HW_IP_UVD_ENC: |
618 | type = AMD_IP_BLOCK_TYPE_UVD; | |
619 | break; | |
bdc799e5 | 620 | case AMDGPU_HW_IP_VCN_DEC: |
cefbc598 | 621 | case AMDGPU_HW_IP_VCN_ENC: |
bdc799e5 LL |
622 | type = AMD_IP_BLOCK_TYPE_VCN; |
623 | break; | |
52f2e779 LL |
624 | case AMDGPU_HW_IP_VCN_JPEG: |
625 | type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? | |
626 | AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; | |
627 | break; | |
d38ceaf9 AD |
628 | default: |
629 | return -EINVAL; | |
630 | } | |
631 | ||
632 | for (i = 0; i < adev->num_ip_blocks; i++) | |
a1255107 AD |
633 | if (adev->ip_blocks[i].version->type == type && |
634 | adev->ip_blocks[i].status.valid && | |
d38ceaf9 AD |
635 | count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) |
636 | count++; | |
637 | ||
638 | return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; | |
639 | } | |
640 | case AMDGPU_INFO_TIMESTAMP: | |
b95e31fd | 641 | ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); |
d38ceaf9 AD |
642 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
643 | case AMDGPU_INFO_FW_VERSION: { | |
644 | struct drm_amdgpu_info_firmware fw_info; | |
000cab9a | 645 | int ret; |
d38ceaf9 AD |
646 | |
647 | /* We only support one instance of each IP block right now. */ | |
648 | if (info->query_fw.ip_instance != 0) | |
649 | return -EINVAL; | |
650 | ||
000cab9a HR |
651 | ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); |
652 | if (ret) | |
653 | return ret; | |
654 | ||
d38ceaf9 AD |
655 | return copy_to_user(out, &fw_info, |
656 | min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; | |
657 | } | |
658 | case AMDGPU_INFO_NUM_BYTES_MOVED: | |
659 | ui64 = atomic64_read(&adev->num_bytes_moved); | |
660 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
83a59b63 MO |
661 | case AMDGPU_INFO_NUM_EVICTIONS: |
662 | ui64 = atomic64_read(&adev->num_evictions); | |
663 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
68e2c5ff MO |
664 | case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: |
665 | ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); | |
666 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; | |
d38ceaf9 | 667 | case AMDGPU_INFO_VRAM_USAGE: |
7db47b83 | 668 | ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); |
d38ceaf9 AD |
669 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
670 | case AMDGPU_INFO_VIS_VRAM_USAGE: | |
ec6aae97 | 671 | ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); |
d38ceaf9 AD |
672 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
673 | case AMDGPU_INFO_GTT_USAGE: | |
dfa714b8 | 674 | ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); |
d38ceaf9 AD |
675 | return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; |
676 | case AMDGPU_INFO_GDS_CONFIG: { | |
677 | struct drm_amdgpu_info_gds gds_info; | |
678 | ||
c92b90cc | 679 | memset(&gds_info, 0, sizeof(gds_info)); |
dca29491 CK |
680 | gds_info.compute_partition_size = adev->gds.gds_size; |
681 | gds_info.gds_total_size = adev->gds.gds_size; | |
682 | gds_info.gws_per_compute_partition = adev->gds.gws_size; | |
683 | gds_info.oa_per_compute_partition = adev->gds.oa_size; | |
d38ceaf9 AD |
684 | return copy_to_user(out, &gds_info, |
685 | min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; | |
686 | } | |
687 | case AMDGPU_INFO_VRAM_GTT: { | |
688 | struct drm_amdgpu_info_vram_gtt vram_gtt; | |
689 | ||
a5ccfe5c | 690 | vram_gtt.vram_size = adev->gmc.real_vram_size - |
9d1b3c78 CK |
691 | atomic64_read(&adev->vram_pin_size) - |
692 | AMDGPU_VM_RESERVED_VRAM; | |
693 | vram_gtt.vram_cpu_accessible_size = | |
694 | min(adev->gmc.visible_vram_size - | |
695 | atomic64_read(&adev->visible_pin_size), | |
696 | vram_gtt.vram_size); | |
6c28aed6 | 697 | vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; |
a5ccfe5c | 698 | vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); |
d38ceaf9 AD |
699 | return copy_to_user(out, &vram_gtt, |
700 | min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; | |
701 | } | |
e0adf6c8 JZ |
702 | case AMDGPU_INFO_MEMORY: { |
703 | struct drm_amdgpu_memory_info mem; | |
9de59bc2 | 704 | struct ttm_resource_manager *gtt_man = |
dfa714b8 | 705 | &adev->mman.gtt_mgr.manager; |
7db47b83 CK |
706 | struct ttm_resource_manager *vram_man = |
707 | &adev->mman.vram_mgr.manager; | |
dfa714b8 | 708 | |
e0adf6c8 | 709 | memset(&mem, 0, sizeof(mem)); |
770d13b1 | 710 | mem.vram.total_heap_size = adev->gmc.real_vram_size; |
a5ccfe5c | 711 | mem.vram.usable_heap_size = adev->gmc.real_vram_size - |
9d1b3c78 CK |
712 | atomic64_read(&adev->vram_pin_size) - |
713 | AMDGPU_VM_RESERVED_VRAM; | |
3c848bb3 | 714 | mem.vram.heap_usage = |
7db47b83 | 715 | ttm_resource_manager_usage(vram_man); |
e0adf6c8 JZ |
716 | mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; |
717 | ||
718 | mem.cpu_accessible_vram.total_heap_size = | |
770d13b1 | 719 | adev->gmc.visible_vram_size; |
9d1b3c78 CK |
720 | mem.cpu_accessible_vram.usable_heap_size = |
721 | min(adev->gmc.visible_vram_size - | |
722 | atomic64_read(&adev->visible_pin_size), | |
723 | mem.vram.usable_heap_size); | |
e0adf6c8 | 724 | mem.cpu_accessible_vram.heap_usage = |
ec6aae97 | 725 | amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); |
e0adf6c8 JZ |
726 | mem.cpu_accessible_vram.max_allocation = |
727 | mem.cpu_accessible_vram.usable_heap_size * 3 / 4; | |
728 | ||
6c28aed6 | 729 | mem.gtt.total_heap_size = gtt_man->size; |
a5ccfe5c MD |
730 | mem.gtt.usable_heap_size = mem.gtt.total_heap_size - |
731 | atomic64_read(&adev->gart_pin_size); | |
dfa714b8 | 732 | mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); |
e0adf6c8 JZ |
733 | mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; |
734 | ||
735 | return copy_to_user(out, &mem, | |
736 | min((size_t)size, sizeof(mem))) | |
cfa32556 JZ |
737 | ? -EFAULT : 0; |
738 | } | |
d38ceaf9 | 739 | case AMDGPU_INFO_READ_MMR_REG: { |
a0cc8e15 | 740 | unsigned int n, alloc_size; |
d38ceaf9 | 741 | uint32_t *regs; |
a0cc8e15 | 742 | unsigned int se_num = (info->read_mmr_reg.instance >> |
d38ceaf9 AD |
743 | AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & |
744 | AMDGPU_INFO_MMR_SE_INDEX_MASK; | |
a0cc8e15 | 745 | unsigned int sh_num = (info->read_mmr_reg.instance >> |
d38ceaf9 AD |
746 | AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & |
747 | AMDGPU_INFO_MMR_SH_INDEX_MASK; | |
748 | ||
749 | /* set full masks if the userspace set all bits | |
a0cc8e15 SS |
750 | * in the bitfields |
751 | */ | |
d38ceaf9 AD |
752 | if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) |
753 | se_num = 0xffffffff; | |
b5b97cab AD |
754 | else if (se_num >= AMDGPU_GFX_MAX_SE) |
755 | return -EINVAL; | |
d38ceaf9 AD |
756 | if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) |
757 | sh_num = 0xffffffff; | |
b5b97cab AD |
758 | else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) |
759 | return -EINVAL; | |
d38ceaf9 | 760 | |
73d8e6c7 T |
761 | if (info->read_mmr_reg.count > 128) |
762 | return -EINVAL; | |
763 | ||
0d2edd37 | 764 | regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); |
d38ceaf9 AD |
765 | if (!regs) |
766 | return -ENOMEM; | |
0d2edd37 | 767 | alloc_size = info->read_mmr_reg.count * sizeof(*regs); |
d38ceaf9 | 768 | |
ca9317b9 AD |
769 | amdgpu_gfx_off_ctrl(adev, false); |
770 | for (i = 0; i < info->read_mmr_reg.count; i++) { | |
d38ceaf9 AD |
771 | if (amdgpu_asic_read_register(adev, se_num, sh_num, |
772 | info->read_mmr_reg.dword_offset + i, | |
773 | ®s[i])) { | |
774 | DRM_DEBUG_KMS("unallowed offset %#x\n", | |
775 | info->read_mmr_reg.dword_offset + i); | |
776 | kfree(regs); | |
ca9317b9 | 777 | amdgpu_gfx_off_ctrl(adev, true); |
d38ceaf9 AD |
778 | return -EFAULT; |
779 | } | |
ca9317b9 AD |
780 | } |
781 | amdgpu_gfx_off_ctrl(adev, true); | |
d38ceaf9 AD |
782 | n = copy_to_user(out, regs, min(size, alloc_size)); |
783 | kfree(regs); | |
784 | return n ? -EFAULT : 0; | |
785 | } | |
786 | case AMDGPU_INFO_DEV_INFO: { | |
a5a52a43 | 787 | struct drm_amdgpu_info_device *dev_info; |
5b565e0e | 788 | uint64_t vm_size; |
e3e84b0a | 789 | uint32_t pcie_gen_mask; |
a5a52a43 LJ |
790 | int ret; |
791 | ||
792 | dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); | |
793 | if (!dev_info) | |
794 | return -ENOMEM; | |
d38ceaf9 | 795 | |
8f66090b | 796 | dev_info->device_id = adev->pdev->device; |
a5a52a43 LJ |
797 | dev_info->chip_rev = adev->rev_id; |
798 | dev_info->external_rev = adev->external_rev_id; | |
8f66090b | 799 | dev_info->pci_rev = adev->pdev->revision; |
a5a52a43 LJ |
800 | dev_info->family = adev->family; |
801 | dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; | |
802 | dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; | |
d38ceaf9 | 803 | /* return all clocks in KHz */ |
a5a52a43 | 804 | dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; |
32bf7106 | 805 | if (adev->pm.dpm_enabled) { |
a5a52a43 LJ |
806 | dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; |
807 | dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; | |
88347fa1 EQ |
808 | dev_info->min_engine_clock = amdgpu_dpm_get_sclk(adev, true) * 10; |
809 | dev_info->min_memory_clock = amdgpu_dpm_get_mclk(adev, true) * 10; | |
32bf7106 | 810 | } else { |
88347fa1 EQ |
811 | dev_info->max_engine_clock = |
812 | dev_info->min_engine_clock = | |
813 | adev->clock.default_sclk * 10; | |
814 | dev_info->max_memory_clock = | |
815 | dev_info->min_memory_clock = | |
816 | adev->clock.default_mclk * 10; | |
32bf7106 | 817 | } |
a5a52a43 LJ |
818 | dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; |
819 | dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * | |
0b10029d | 820 | adev->gfx.config.max_shader_engines; |
a5a52a43 | 821 | dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; |
a5a52a43 | 822 | dev_info->ids_flags = 0; |
2f7d10b3 | 823 | if (adev->flags & AMD_IS_APU) |
a5a52a43 | 824 | dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; |
02ff519e | 825 | if (adev->gfx.mcbp) |
a5a52a43 | 826 | dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; |
16c642ec | 827 | if (amdgpu_is_tmz(adev)) |
a5a52a43 | 828 | dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; |
b299221f MO |
829 | if (adev->gfx.config.ta_cntl2_truncate_coord_mode) |
830 | dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; | |
5b565e0e CK |
831 | |
832 | vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; | |
a3e9a15a | 833 | vm_size -= AMDGPU_VA_RESERVED_SIZE; |
6b034e25 CK |
834 | |
835 | /* Older VCE FW versions are buggy and can handle only 40bits */ | |
09b6f25b CK |
836 | if (adev->vce.fw_version && |
837 | adev->vce.fw_version < AMDGPU_VCE_FW_53_45) | |
6b034e25 CK |
838 | vm_size = min(vm_size, 1ULL << 40); |
839 | ||
a5a52a43 LJ |
840 | dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; |
841 | dev_info->virtual_address_max = | |
ad9a5b78 | 842 | min(vm_size, AMDGPU_GMC_HOLE_START); |
5b565e0e | 843 | |
ad9a5b78 | 844 | if (vm_size > AMDGPU_GMC_HOLE_START) { |
a5a52a43 LJ |
845 | dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; |
846 | dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; | |
5b565e0e | 847 | } |
f4d3da72 | 848 | dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
a5a52a43 | 849 | dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; |
f4d3da72 | 850 | dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); |
a5a52a43 LJ |
851 | dev_info->cu_active_number = adev->gfx.cu_info.number; |
852 | dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; | |
853 | dev_info->ce_ram_size = adev->gfx.ce_ram_size; | |
854 | memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], | |
dbfe85ea | 855 | sizeof(adev->gfx.cu_info.ao_cu_bitmap)); |
a5a52a43 | 856 | memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], |
f705a6f0 | 857 | sizeof(dev_info->cu_bitmap)); |
a5a52a43 LJ |
858 | dev_info->vram_type = adev->gmc.vram_type; |
859 | dev_info->vram_bit_width = adev->gmc.vram_width; | |
860 | dev_info->vce_harvest_config = adev->vce.harvest_config; | |
861 | dev_info->gc_double_offchip_lds_buf = | |
df6e2c4a | 862 | adev->gfx.config.double_offchip_lds_buf; |
a5a52a43 LJ |
863 | dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; |
864 | dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; | |
865 | dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; | |
866 | dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; | |
867 | dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; | |
868 | dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; | |
869 | dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; | |
bce23e00 | 870 | |
be9250fb | 871 | if (adev->family >= AMDGPU_FAMILY_NV) |
a5a52a43 | 872 | dev_info->pa_sc_tile_steering_override = |
be9250fb HZ |
873 | adev->gfx.config.pa_sc_tile_steering_override; |
874 | ||
a5a52a43 | 875 | dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; |
815fb4c9 | 876 | |
e3e84b0a MO |
877 | /* Combine the chip gen mask with the platform (CPU/mobo) mask. */ |
878 | pcie_gen_mask = adev->pm.pcie_gen_mask & (adev->pm.pcie_gen_mask >> 16); | |
879 | dev_info->pcie_gen = fls(pcie_gen_mask); | |
880 | dev_info->pcie_num_lanes = | |
881 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 ? 32 : | |
882 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 ? 16 : | |
883 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 ? 12 : | |
884 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 ? 8 : | |
885 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 ? 4 : | |
886 | adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 ? 2 : 1; | |
887 | ||
b299221f MO |
888 | dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size; |
889 | dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp; | |
890 | dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc; | |
891 | dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc; | |
892 | dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance * | |
893 | adev->gfx.config.gc_gl1c_per_sa; | |
894 | dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu; | |
895 | dev_info->mall_size = adev->gmc.mall_size; | |
896 | ||
1ba91b54 AD |
897 | |
898 | if (adev->gfx.funcs->get_gfx_shadow_info) { | |
899 | struct amdgpu_gfx_shadow_info shadow_info; | |
900 | ||
901 | ret = amdgpu_gfx_get_gfx_shadow_info(adev, &shadow_info); | |
902 | if (!ret) { | |
903 | dev_info->shadow_size = shadow_info.shadow_size; | |
904 | dev_info->shadow_alignment = shadow_info.shadow_alignment; | |
905 | dev_info->csa_size = shadow_info.csa_size; | |
906 | dev_info->csa_alignment = shadow_info.csa_alignment; | |
907 | } | |
908 | } | |
909 | ||
a5a52a43 LJ |
910 | ret = copy_to_user(out, dev_info, |
911 | min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; | |
912 | kfree(dev_info); | |
913 | return ret; | |
d38ceaf9 | 914 | } |
07fecde5 | 915 | case AMDGPU_INFO_VCE_CLOCK_TABLE: { |
a0cc8e15 | 916 | unsigned int i; |
07fecde5 AD |
917 | struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; |
918 | struct amd_vce_state *vce_state; | |
919 | ||
920 | for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { | |
921 | vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); | |
922 | if (vce_state) { | |
923 | vce_clk_table.entries[i].sclk = vce_state->sclk; | |
924 | vce_clk_table.entries[i].mclk = vce_state->mclk; | |
925 | vce_clk_table.entries[i].eclk = vce_state->evclk; | |
926 | vce_clk_table.num_valid_entries++; | |
927 | } | |
928 | } | |
929 | ||
930 | return copy_to_user(out, &vce_clk_table, | |
931 | min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; | |
932 | } | |
40ee5888 EQ |
933 | case AMDGPU_INFO_VBIOS: { |
934 | uint32_t bios_size = adev->bios_size; | |
935 | ||
936 | switch (info->vbios_info.type) { | |
937 | case AMDGPU_INFO_VBIOS_SIZE: | |
938 | return copy_to_user(out, &bios_size, | |
939 | min((size_t)size, sizeof(bios_size))) | |
940 | ? -EFAULT : 0; | |
941 | case AMDGPU_INFO_VBIOS_IMAGE: { | |
942 | uint8_t *bios; | |
943 | uint32_t bios_offset = info->vbios_info.offset; | |
944 | ||
945 | if (bios_offset >= bios_size) | |
946 | return -EINVAL; | |
947 | ||
948 | bios = adev->bios + bios_offset; | |
949 | return copy_to_user(out, bios, | |
950 | min((size_t)size, (size_t)(bios_size - bios_offset))) | |
951 | ? -EFAULT : 0; | |
952 | } | |
29b4c589 JG |
953 | case AMDGPU_INFO_VBIOS_INFO: { |
954 | struct drm_amdgpu_info_vbios vbios_info = {}; | |
955 | struct atom_context *atom_context; | |
956 | ||
957 | atom_context = adev->mode_info.atom_context; | |
86f2ec22 DF |
958 | if (atom_context) { |
959 | memcpy(vbios_info.name, atom_context->name, | |
960 | sizeof(atom_context->name)); | |
961 | memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, | |
962 | sizeof(atom_context->vbios_pn)); | |
963 | vbios_info.version = atom_context->version; | |
964 | memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, | |
965 | sizeof(atom_context->vbios_ver_str)); | |
966 | memcpy(vbios_info.date, atom_context->date, | |
967 | sizeof(atom_context->date)); | |
968 | } | |
29b4c589 JG |
969 | |
970 | return copy_to_user(out, &vbios_info, | |
971 | min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; | |
972 | } | |
40ee5888 EQ |
973 | default: |
974 | DRM_DEBUG_KMS("Invalid request %d\n", | |
975 | info->vbios_info.type); | |
976 | return -EINVAL; | |
977 | } | |
978 | } | |
44879b62 AN |
979 | case AMDGPU_INFO_NUM_HANDLES: { |
980 | struct drm_amdgpu_info_num_handles handle; | |
981 | ||
982 | switch (info->query_hw_ip.type) { | |
983 | case AMDGPU_HW_IP_UVD: | |
984 | /* Starting Polaris, we support unlimited UVD handles */ | |
985 | if (adev->asic_type < CHIP_POLARIS10) { | |
986 | handle.uvd_max_handles = adev->uvd.max_handles; | |
987 | handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); | |
988 | ||
989 | return copy_to_user(out, &handle, | |
990 | min((size_t)size, sizeof(handle))) ? -EFAULT : 0; | |
991 | } else { | |
992 | return -ENODATA; | |
993 | } | |
994 | ||
995 | break; | |
996 | default: | |
997 | return -EINVAL; | |
998 | } | |
999 | } | |
5ebbac4b | 1000 | case AMDGPU_INFO_SENSOR: { |
b13aa109 | 1001 | if (!adev->pm.dpm_enabled) |
5ebbac4b AD |
1002 | return -ENOENT; |
1003 | ||
1004 | switch (info->sensor_info.type) { | |
1005 | case AMDGPU_INFO_SENSOR_GFX_SCLK: | |
1006 | /* get sclk in Mhz */ | |
1007 | if (amdgpu_dpm_read_sensor(adev, | |
1008 | AMDGPU_PP_SENSOR_GFX_SCLK, | |
1009 | (void *)&ui32, &ui32_size)) { | |
1010 | return -EINVAL; | |
1011 | } | |
1012 | ui32 /= 100; | |
1013 | break; | |
1014 | case AMDGPU_INFO_SENSOR_GFX_MCLK: | |
1015 | /* get mclk in Mhz */ | |
1016 | if (amdgpu_dpm_read_sensor(adev, | |
1017 | AMDGPU_PP_SENSOR_GFX_MCLK, | |
1018 | (void *)&ui32, &ui32_size)) { | |
1019 | return -EINVAL; | |
1020 | } | |
1021 | ui32 /= 100; | |
1022 | break; | |
1023 | case AMDGPU_INFO_SENSOR_GPU_TEMP: | |
1024 | /* get temperature in millidegrees C */ | |
1025 | if (amdgpu_dpm_read_sensor(adev, | |
1026 | AMDGPU_PP_SENSOR_GPU_TEMP, | |
1027 | (void *)&ui32, &ui32_size)) { | |
1028 | return -EINVAL; | |
1029 | } | |
1030 | break; | |
1031 | case AMDGPU_INFO_SENSOR_GPU_LOAD: | |
1032 | /* get GPU load */ | |
1033 | if (amdgpu_dpm_read_sensor(adev, | |
1034 | AMDGPU_PP_SENSOR_GPU_LOAD, | |
1035 | (void *)&ui32, &ui32_size)) { | |
1036 | return -EINVAL; | |
1037 | } | |
1038 | break; | |
1039 | case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: | |
1040 | /* get average GPU power */ | |
1041 | if (amdgpu_dpm_read_sensor(adev, | |
9366c2e8 | 1042 | AMDGPU_PP_SENSOR_GPU_AVG_POWER, |
5b79d048 | 1043 | (void *)&ui32, &ui32_size)) { |
5ebbac4b AD |
1044 | return -EINVAL; |
1045 | } | |
5b79d048 | 1046 | ui32 >>= 8; |
5ebbac4b AD |
1047 | break; |
1048 | case AMDGPU_INFO_SENSOR_VDDNB: | |
1049 | /* get VDDNB in millivolts */ | |
1050 | if (amdgpu_dpm_read_sensor(adev, | |
1051 | AMDGPU_PP_SENSOR_VDDNB, | |
1052 | (void *)&ui32, &ui32_size)) { | |
1053 | return -EINVAL; | |
1054 | } | |
1055 | break; | |
1056 | case AMDGPU_INFO_SENSOR_VDDGFX: | |
1057 | /* get VDDGFX in millivolts */ | |
1058 | if (amdgpu_dpm_read_sensor(adev, | |
1059 | AMDGPU_PP_SENSOR_VDDGFX, | |
1060 | (void *)&ui32, &ui32_size)) { | |
1061 | return -EINVAL; | |
1062 | } | |
1063 | break; | |
60bbade2 RZ |
1064 | case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: |
1065 | /* get stable pstate sclk in Mhz */ | |
1066 | if (amdgpu_dpm_read_sensor(adev, | |
1067 | AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, | |
1068 | (void *)&ui32, &ui32_size)) { | |
1069 | return -EINVAL; | |
1070 | } | |
1071 | ui32 /= 100; | |
1072 | break; | |
1073 | case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: | |
1074 | /* get stable pstate mclk in Mhz */ | |
1075 | if (amdgpu_dpm_read_sensor(adev, | |
1076 | AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, | |
1077 | (void *)&ui32, &ui32_size)) { | |
1078 | return -EINVAL; | |
1079 | } | |
1080 | ui32 /= 100; | |
1081 | break; | |
5cfd9784 EQ |
1082 | case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK: |
1083 | /* get peak pstate sclk in Mhz */ | |
1084 | if (amdgpu_dpm_read_sensor(adev, | |
1085 | AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, | |
1086 | (void *)&ui32, &ui32_size)) { | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ui32 /= 100; | |
1090 | break; | |
1091 | case AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK: | |
1092 | /* get peak pstate mclk in Mhz */ | |
1093 | if (amdgpu_dpm_read_sensor(adev, | |
1094 | AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, | |
1095 | (void *)&ui32, &ui32_size)) { | |
1096 | return -EINVAL; | |
1097 | } | |
1098 | ui32 /= 100; | |
1099 | break; | |
5ebbac4b AD |
1100 | default: |
1101 | DRM_DEBUG_KMS("Invalid request %d\n", | |
1102 | info->sensor_info.type); | |
1103 | return -EINVAL; | |
1104 | } | |
1105 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
1106 | } | |
1f7251b7 CK |
1107 | case AMDGPU_INFO_VRAM_LOST_COUNTER: |
1108 | ui32 = atomic_read(&adev->vram_lost_counter); | |
1109 | return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; | |
5cb77114 | 1110 | case AMDGPU_INFO_RAS_ENABLED_FEATURES: { |
1111 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); | |
1febb00e | 1112 | uint64_t ras_mask; |
5cb77114 | 1113 | |
1114 | if (!ras) | |
1115 | return -EINVAL; | |
8ab0d6f0 | 1116 | ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; |
1febb00e | 1117 | |
1118 | return copy_to_user(out, &ras_mask, | |
1119 | min_t(u64, size, sizeof(ras_mask))) ? | |
5cb77114 | 1120 | -EFAULT : 0; |
1121 | } | |
f35e9bdb AD |
1122 | case AMDGPU_INFO_VIDEO_CAPS: { |
1123 | const struct amdgpu_video_codecs *codecs; | |
1124 | struct drm_amdgpu_info_video_caps *caps; | |
1125 | int r; | |
1126 | ||
bc8ba5f2 AD |
1127 | if (!adev->asic_funcs->query_video_codecs) |
1128 | return -EINVAL; | |
1129 | ||
f35e9bdb AD |
1130 | switch (info->video_cap.type) { |
1131 | case AMDGPU_INFO_VIDEO_CAPS_DECODE: | |
1132 | r = amdgpu_asic_query_video_codecs(adev, false, &codecs); | |
1133 | if (r) | |
1134 | return -EINVAL; | |
1135 | break; | |
1136 | case AMDGPU_INFO_VIDEO_CAPS_ENCODE: | |
1137 | r = amdgpu_asic_query_video_codecs(adev, true, &codecs); | |
1138 | if (r) | |
1139 | return -EINVAL; | |
1140 | break; | |
1141 | default: | |
1142 | DRM_DEBUG_KMS("Invalid request %d\n", | |
1143 | info->video_cap.type); | |
1144 | return -EINVAL; | |
1145 | } | |
1146 | ||
1147 | caps = kzalloc(sizeof(*caps), GFP_KERNEL); | |
1148 | if (!caps) | |
1149 | return -ENOMEM; | |
1150 | ||
1151 | for (i = 0; i < codecs->codec_count; i++) { | |
1152 | int idx = codecs->codec_array[i].codec_type; | |
1153 | ||
1154 | switch (idx) { | |
6f786950 AD |
1155 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: |
1156 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: | |
1157 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: | |
1158 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: | |
1159 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: | |
1160 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: | |
1161 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: | |
1162 | case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: | |
f35e9bdb AD |
1163 | caps->codec_info[idx].valid = 1; |
1164 | caps->codec_info[idx].max_width = | |
1165 | codecs->codec_array[i].max_width; | |
1166 | caps->codec_info[idx].max_height = | |
1167 | codecs->codec_array[i].max_height; | |
1168 | caps->codec_info[idx].max_pixels_per_frame = | |
1169 | codecs->codec_array[i].max_pixels_per_frame; | |
1170 | caps->codec_info[idx].max_level = | |
1171 | codecs->codec_array[i].max_level; | |
1172 | break; | |
1173 | default: | |
1174 | break; | |
1175 | } | |
1176 | } | |
1177 | r = copy_to_user(out, caps, | |
1178 | min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; | |
1179 | kfree(caps); | |
1180 | return r; | |
1181 | } | |
4f18b9a6 BN |
1182 | case AMDGPU_INFO_MAX_IBS: { |
1183 | uint32_t max_ibs[AMDGPU_HW_IP_NUM]; | |
1184 | ||
1185 | for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) | |
1186 | max_ibs[i] = amdgpu_ring_max_ibs(i); | |
1187 | ||
1188 | return copy_to_user(out, max_ibs, | |
1189 | min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; | |
1190 | } | |
d38ceaf9 AD |
1191 | default: |
1192 | DRM_DEBUG_KMS("Invalid request %d\n", info->query); | |
1193 | return -EINVAL; | |
1194 | } | |
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | ||
1199 | /* | |
1200 | * Outdated mess for old drm with Xorg being in charge (void function now). | |
1201 | */ | |
1202 | /** | |
8b7530b1 | 1203 | * amdgpu_driver_lastclose_kms - drm callback for last close |
d38ceaf9 AD |
1204 | * |
1205 | * @dev: drm dev pointer | |
1206 | * | |
1694467b | 1207 | * Switch vga_switcheroo state after last close (all asics). |
d38ceaf9 AD |
1208 | */ |
1209 | void amdgpu_driver_lastclose_kms(struct drm_device *dev) | |
1210 | { | |
ab77e02c | 1211 | drm_fb_helper_lastclose(dev); |
d38ceaf9 AD |
1212 | vga_switcheroo_process_delayed_switch(); |
1213 | } | |
1214 | ||
1215 | /** | |
1216 | * amdgpu_driver_open_kms - drm callback for open | |
1217 | * | |
1218 | * @dev: drm dev pointer | |
1219 | * @file_priv: drm file | |
1220 | * | |
1221 | * On device open, init vm on cayman+ (all asics). | |
1222 | * Returns 0 on success, error on failure. | |
1223 | */ | |
1224 | int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |
1225 | { | |
1348969a | 1226 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 | 1227 | struct amdgpu_fpriv *fpriv; |
5c2ff9a6 | 1228 | int r, pasid; |
d38ceaf9 | 1229 | |
2c486cc4 | 1230 | /* Ensure IB tests are run on ring */ |
beff74bc | 1231 | flush_delayed_work(&adev->delayed_init_work); |
2c486cc4 | 1232 | |
7c6e68c7 AG |
1233 | |
1234 | if (amdgpu_ras_intr_triggered()) { | |
1235 | DRM_ERROR("RAS Intr triggered, device disabled!!"); | |
1236 | return -EHWPOISON; | |
1237 | } | |
1238 | ||
d38ceaf9 AD |
1239 | file_priv->driver_priv = NULL; |
1240 | ||
1241 | r = pm_runtime_get_sync(dev->dev); | |
1242 | if (r < 0) | |
9ba8923c | 1243 | goto pm_put; |
d38ceaf9 AD |
1244 | |
1245 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
dc08267a AD |
1246 | if (unlikely(!fpriv)) { |
1247 | r = -ENOMEM; | |
1248 | goto out_suspend; | |
1249 | } | |
d38ceaf9 | 1250 | |
5c2ff9a6 CK |
1251 | pasid = amdgpu_pasid_alloc(16); |
1252 | if (pasid < 0) { | |
1253 | dev_warn(adev->dev, "No more PASIDs available!"); | |
1254 | pasid = 0; | |
dc08267a | 1255 | } |
a35455d0 | 1256 | |
50e63308 | 1257 | r = amdgpu_xcp_open_device(adev, fpriv, file_priv); |
5c2ff9a6 CK |
1258 | if (r) |
1259 | goto error_pasid; | |
d38ceaf9 | 1260 | |
5003ca63 | 1261 | r = amdgpu_vm_init(adev, &fpriv->vm, fpriv->xcp_id); |
934deb64 | 1262 | if (r) |
50e63308 | 1263 | goto error_pasid; |
934deb64 | 1264 | |
88f7f881 ND |
1265 | r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); |
1266 | if (r) | |
1267 | goto error_vm; | |
1268 | ||
b85891bd JZ |
1269 | fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); |
1270 | if (!fpriv->prt_va) { | |
1271 | r = -ENOMEM; | |
5c2ff9a6 | 1272 | goto error_vm; |
b85891bd JZ |
1273 | } |
1274 | ||
02ff519e | 1275 | if (adev->gfx.mcbp) { |
1e256e27 RZ |
1276 | uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; |
1277 | ||
1278 | r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, | |
1279 | &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); | |
5c2ff9a6 CK |
1280 | if (r) |
1281 | goto error_vm; | |
2493664f ML |
1282 | } |
1283 | ||
d38ceaf9 | 1284 | mutex_init(&fpriv->bo_list_lock); |
c4f306e3 | 1285 | idr_init_base(&fpriv->bo_list_handles, 1); |
d38ceaf9 | 1286 | |
69493c03 | 1287 | amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); |
d38ceaf9 AD |
1288 | |
1289 | file_priv->driver_priv = fpriv; | |
5c2ff9a6 CK |
1290 | goto out_suspend; |
1291 | ||
1292 | error_vm: | |
1293 | amdgpu_vm_fini(adev, &fpriv->vm); | |
1294 | ||
1295 | error_pasid: | |
88f7f881 | 1296 | if (pasid) { |
5c2ff9a6 | 1297 | amdgpu_pasid_free(pasid); |
88f7f881 ND |
1298 | amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); |
1299 | } | |
5c2ff9a6 CK |
1300 | |
1301 | kfree(fpriv); | |
d38ceaf9 | 1302 | |
dc08267a | 1303 | out_suspend: |
d38ceaf9 | 1304 | pm_runtime_mark_last_busy(dev->dev); |
9ba8923c | 1305 | pm_put: |
d38ceaf9 | 1306 | pm_runtime_put_autosuspend(dev->dev); |
d38ceaf9 AD |
1307 | |
1308 | return r; | |
1309 | } | |
1310 | ||
1311 | /** | |
1312 | * amdgpu_driver_postclose_kms - drm callback for post close | |
1313 | * | |
1314 | * @dev: drm dev pointer | |
1315 | * @file_priv: drm file | |
1316 | * | |
1317 | * On device post close, tear down vm on cayman+ (all asics). | |
1318 | */ | |
1319 | void amdgpu_driver_postclose_kms(struct drm_device *dev, | |
1320 | struct drm_file *file_priv) | |
1321 | { | |
1348969a | 1322 | struct amdgpu_device *adev = drm_to_adev(dev); |
d38ceaf9 AD |
1323 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
1324 | struct amdgpu_bo_list *list; | |
5c2ff9a6 | 1325 | struct amdgpu_bo *pd; |
c7b6bac9 | 1326 | u32 pasid; |
d38ceaf9 AD |
1327 | int handle; |
1328 | ||
1329 | if (!fpriv) | |
1330 | return; | |
1331 | ||
04e30c9c | 1332 | pm_runtime_get_sync(dev->dev); |
02537d63 | 1333 | |
44876ae2 | 1334 | if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) |
ef80d30b | 1335 | amdgpu_uvd_free_handles(adev, file_priv); |
44876ae2 | 1336 | if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) |
ef80d30b | 1337 | amdgpu_vce_free_handles(adev, file_priv); |
cd437e37 | 1338 | |
5daff15c LY |
1339 | if (fpriv->csa_va) { |
1340 | uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; | |
1341 | ||
1342 | WARN_ON(amdgpu_unmap_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, | |
1343 | fpriv->csa_va, csa_addr)); | |
0f4b3c68 | 1344 | fpriv->csa_va = NULL; |
2493664f ML |
1345 | } |
1346 | ||
5c2ff9a6 | 1347 | pasid = fpriv->vm.pasid; |
391629bd | 1348 | pd = amdgpu_bo_ref(fpriv->vm.root.bo); |
b6fba4ec CK |
1349 | if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { |
1350 | amdgpu_vm_bo_del(adev, fpriv->prt_va); | |
1351 | amdgpu_bo_unreserve(pd); | |
1352 | } | |
5c2ff9a6 | 1353 | |
8ee3a52e | 1354 | amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); |
6ffb6b7f | 1355 | amdgpu_vm_fini(adev, &fpriv->vm); |
8ee3a52e | 1356 | |
5c2ff9a6 | 1357 | if (pasid) |
5a5011a7 | 1358 | amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); |
5c2ff9a6 | 1359 | amdgpu_bo_unref(&pd); |
d38ceaf9 AD |
1360 | |
1361 | idr_for_each_entry(&fpriv->bo_list_handles, list, handle) | |
a0f20845 | 1362 | amdgpu_bo_list_put(list); |
d38ceaf9 AD |
1363 | |
1364 | idr_destroy(&fpriv->bo_list_handles); | |
1365 | mutex_destroy(&fpriv->bo_list_lock); | |
1366 | ||
d38ceaf9 AD |
1367 | kfree(fpriv); |
1368 | file_priv->driver_priv = NULL; | |
d6bda7b4 AD |
1369 | |
1370 | pm_runtime_mark_last_busy(dev->dev); | |
1371 | pm_runtime_put_autosuspend(dev->dev); | |
d38ceaf9 AD |
1372 | } |
1373 | ||
72c8c97b AG |
1374 | |
1375 | void amdgpu_driver_release_kms(struct drm_device *dev) | |
1376 | { | |
1377 | struct amdgpu_device *adev = drm_to_adev(dev); | |
1378 | ||
1379 | amdgpu_device_fini_sw(adev); | |
1380 | pci_set_drvdata(adev->pdev, NULL); | |
1381 | } | |
1382 | ||
d38ceaf9 AD |
1383 | /* |
1384 | * VBlank related functions. | |
1385 | */ | |
1386 | /** | |
1387 | * amdgpu_get_vblank_counter_kms - get frame count | |
1388 | * | |
e3eff4b5 | 1389 | * @crtc: crtc to get the frame count from |
d38ceaf9 AD |
1390 | * |
1391 | * Gets the frame count on the requested crtc (all asics). | |
1392 | * Returns frame count on success, -EINVAL on failure. | |
1393 | */ | |
e3eff4b5 | 1394 | u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) |
d38ceaf9 | 1395 | { |
e3eff4b5 TZ |
1396 | struct drm_device *dev = crtc->dev; |
1397 | unsigned int pipe = crtc->index; | |
1348969a | 1398 | struct amdgpu_device *adev = drm_to_adev(dev); |
8e36f9d3 AD |
1399 | int vpos, hpos, stat; |
1400 | u32 count; | |
d38ceaf9 | 1401 | |
88e72717 TR |
1402 | if (pipe >= adev->mode_info.num_crtc) { |
1403 | DRM_ERROR("Invalid crtc %u\n", pipe); | |
d38ceaf9 AD |
1404 | return -EINVAL; |
1405 | } | |
1406 | ||
8e36f9d3 AD |
1407 | /* The hw increments its frame counter at start of vsync, not at start |
1408 | * of vblank, as is required by DRM core vblank counter handling. | |
1409 | * Cook the hw count here to make it appear to the caller as if it | |
1410 | * incremented at start of vblank. We measure distance to start of | |
1411 | * vblank in vpos. vpos therefore will be >= 0 between start of vblank | |
1412 | * and start of vsync, so vpos >= 0 means to bump the hw frame counter | |
1413 | * result by 1 to give the proper appearance to caller. | |
1414 | */ | |
1415 | if (adev->mode_info.crtcs[pipe]) { | |
1416 | /* Repeat readout if needed to provide stable result if | |
1417 | * we cross start of vsync during the queries. | |
1418 | */ | |
1419 | do { | |
1420 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
aa8e286a SL |
1421 | /* Ask amdgpu_display_get_crtc_scanoutpos to return |
1422 | * vpos as distance to start of vblank, instead of | |
1423 | * regular vertical scanout pos. | |
8e36f9d3 | 1424 | */ |
aa8e286a | 1425 | stat = amdgpu_display_get_crtc_scanoutpos( |
8e36f9d3 AD |
1426 | dev, pipe, GET_DISTANCE_TO_VBLANKSTART, |
1427 | &vpos, &hpos, NULL, NULL, | |
1428 | &adev->mode_info.crtcs[pipe]->base.hwmode); | |
1429 | } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); | |
1430 | ||
1431 | if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != | |
1432 | (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { | |
1433 | DRM_DEBUG_VBL("Query failed! stat %d\n", stat); | |
1434 | } else { | |
1435 | DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", | |
1436 | pipe, vpos); | |
1437 | ||
1438 | /* Bump counter if we are at >= leading edge of vblank, | |
1439 | * but before vsync where vpos would turn negative and | |
1440 | * the hw counter really increments. | |
1441 | */ | |
1442 | if (vpos >= 0) | |
1443 | count++; | |
1444 | } | |
1445 | } else { | |
1446 | /* Fallback to use value as is. */ | |
1447 | count = amdgpu_display_vblank_get_counter(adev, pipe); | |
1448 | DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); | |
1449 | } | |
1450 | ||
1451 | return count; | |
d38ceaf9 AD |
1452 | } |
1453 | ||
1454 | /** | |
1455 | * amdgpu_enable_vblank_kms - enable vblank interrupt | |
1456 | * | |
e3eff4b5 | 1457 | * @crtc: crtc to enable vblank interrupt for |
d38ceaf9 AD |
1458 | * |
1459 | * Enable the interrupt on the requested crtc (all asics). | |
1460 | * Returns 0 on success, -EINVAL on failure. | |
1461 | */ | |
e3eff4b5 | 1462 | int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) |
d38ceaf9 | 1463 | { |
e3eff4b5 TZ |
1464 | struct drm_device *dev = crtc->dev; |
1465 | unsigned int pipe = crtc->index; | |
1348969a | 1466 | struct amdgpu_device *adev = drm_to_adev(dev); |
734dd01d | 1467 | int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
1468 | |
1469 | return amdgpu_irq_get(adev, &adev->crtc_irq, idx); | |
1470 | } | |
1471 | ||
1472 | /** | |
1473 | * amdgpu_disable_vblank_kms - disable vblank interrupt | |
1474 | * | |
e3eff4b5 | 1475 | * @crtc: crtc to disable vblank interrupt for |
d38ceaf9 AD |
1476 | * |
1477 | * Disable the interrupt on the requested crtc (all asics). | |
1478 | */ | |
e3eff4b5 | 1479 | void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) |
d38ceaf9 | 1480 | { |
e3eff4b5 TZ |
1481 | struct drm_device *dev = crtc->dev; |
1482 | unsigned int pipe = crtc->index; | |
1348969a | 1483 | struct amdgpu_device *adev = drm_to_adev(dev); |
734dd01d | 1484 | int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); |
d38ceaf9 AD |
1485 | |
1486 | amdgpu_irq_put(adev, &adev->crtc_irq, idx); | |
1487 | } | |
1488 | ||
50ab2533 HR |
1489 | /* |
1490 | * Debugfs info | |
1491 | */ | |
1492 | #if defined(CONFIG_DEBUG_FS) | |
1493 | ||
98d28ac2 | 1494 | static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) |
50ab2533 | 1495 | { |
109b4d8c | 1496 | struct amdgpu_device *adev = m->private; |
50ab2533 HR |
1497 | struct drm_amdgpu_info_firmware fw_info; |
1498 | struct drm_amdgpu_query_fw query_fw; | |
32d8c662 | 1499 | struct atom_context *ctx = adev->mode_info.atom_context; |
82890466 | 1500 | uint8_t smu_program, smu_major, smu_minor, smu_debug; |
50ab2533 HR |
1501 | int ret, i; |
1502 | ||
4d5ae731 | 1503 | static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { |
5c65a4b8 | 1504 | #define TA_FW_NAME(type)[TA_FW_TYPE_PSP_##type] = #type |
4d5ae731 KW |
1505 | TA_FW_NAME(XGMI), |
1506 | TA_FW_NAME(RAS), | |
1507 | TA_FW_NAME(HDCP), | |
1508 | TA_FW_NAME(DTM), | |
1509 | TA_FW_NAME(RAP), | |
e7bdf00e | 1510 | TA_FW_NAME(SECUREDISPLAY), |
4d5ae731 KW |
1511 | #undef TA_FW_NAME |
1512 | }; | |
1513 | ||
50ab2533 HR |
1514 | /* VCE */ |
1515 | query_fw.fw_type = AMDGPU_INFO_FW_VCE; | |
1516 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1517 | if (ret) | |
1518 | return ret; | |
1519 | seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", | |
1520 | fw_info.feature, fw_info.ver); | |
1521 | ||
1522 | /* UVD */ | |
1523 | query_fw.fw_type = AMDGPU_INFO_FW_UVD; | |
1524 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1525 | if (ret) | |
1526 | return ret; | |
1527 | seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", | |
1528 | fw_info.feature, fw_info.ver); | |
1529 | ||
1530 | /* GMC */ | |
1531 | query_fw.fw_type = AMDGPU_INFO_FW_GMC; | |
1532 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1533 | if (ret) | |
1534 | return ret; | |
1535 | seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", | |
1536 | fw_info.feature, fw_info.ver); | |
1537 | ||
1538 | /* ME */ | |
1539 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; | |
1540 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1541 | if (ret) | |
1542 | return ret; | |
1543 | seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", | |
1544 | fw_info.feature, fw_info.ver); | |
1545 | ||
1546 | /* PFP */ | |
1547 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; | |
1548 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1549 | if (ret) | |
1550 | return ret; | |
1551 | seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", | |
1552 | fw_info.feature, fw_info.ver); | |
1553 | ||
1554 | /* CE */ | |
1555 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; | |
1556 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1557 | if (ret) | |
1558 | return ret; | |
1559 | seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", | |
1560 | fw_info.feature, fw_info.ver); | |
1561 | ||
1562 | /* RLC */ | |
1563 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; | |
1564 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1565 | if (ret) | |
1566 | return ret; | |
1567 | seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", | |
1568 | fw_info.feature, fw_info.ver); | |
1569 | ||
621a6318 HR |
1570 | /* RLC SAVE RESTORE LIST CNTL */ |
1571 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; | |
1572 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1573 | if (ret) | |
1574 | return ret; | |
1575 | seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", | |
1576 | fw_info.feature, fw_info.ver); | |
1577 | ||
1578 | /* RLC SAVE RESTORE LIST GPM MEM */ | |
1579 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; | |
1580 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1581 | if (ret) | |
1582 | return ret; | |
1583 | seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", | |
1584 | fw_info.feature, fw_info.ver); | |
1585 | ||
1586 | /* RLC SAVE RESTORE LIST SRM MEM */ | |
1587 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; | |
1588 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1589 | if (ret) | |
1590 | return ret; | |
1591 | seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", | |
1592 | fw_info.feature, fw_info.ver); | |
1593 | ||
670c6edf HZ |
1594 | /* RLCP */ |
1595 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; | |
1596 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1597 | if (ret) | |
1598 | return ret; | |
1599 | seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", | |
1600 | fw_info.feature, fw_info.ver); | |
1601 | ||
1602 | /* RLCV */ | |
5c65a4b8 | 1603 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; |
670c6edf HZ |
1604 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); |
1605 | if (ret) | |
1606 | return ret; | |
1607 | seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", | |
1608 | fw_info.feature, fw_info.ver); | |
1609 | ||
50ab2533 HR |
1610 | /* MEC */ |
1611 | query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; | |
1612 | query_fw.index = 0; | |
1613 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1614 | if (ret) | |
1615 | return ret; | |
1616 | seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", | |
1617 | fw_info.feature, fw_info.ver); | |
1618 | ||
1619 | /* MEC2 */ | |
d7aca4f0 | 1620 | if (adev->gfx.mec2_fw) { |
50ab2533 HR |
1621 | query_fw.index = 1; |
1622 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1623 | if (ret) | |
1624 | return ret; | |
1625 | seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", | |
1626 | fw_info.feature, fw_info.ver); | |
1627 | } | |
1628 | ||
b7236296 DF |
1629 | /* IMU */ |
1630 | query_fw.fw_type = AMDGPU_INFO_FW_IMU; | |
1631 | query_fw.index = 0; | |
1632 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1633 | if (ret) | |
1634 | return ret; | |
1635 | seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", | |
1636 | fw_info.feature, fw_info.ver); | |
1637 | ||
6a7ed07e HR |
1638 | /* PSP SOS */ |
1639 | query_fw.fw_type = AMDGPU_INFO_FW_SOS; | |
1640 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1641 | if (ret) | |
1642 | return ret; | |
1643 | seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", | |
1644 | fw_info.feature, fw_info.ver); | |
1645 | ||
1646 | ||
1647 | /* PSP ASD */ | |
1648 | query_fw.fw_type = AMDGPU_INFO_FW_ASD; | |
1649 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1650 | if (ret) | |
1651 | return ret; | |
1652 | seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", | |
1653 | fw_info.feature, fw_info.ver); | |
1654 | ||
9b9ca62d | 1655 | query_fw.fw_type = AMDGPU_INFO_FW_TA; |
4d5ae731 | 1656 | for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { |
9b9ca62d | 1657 | query_fw.index = i; |
1658 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1659 | if (ret) | |
1660 | continue; | |
4d5ae731 KW |
1661 | |
1662 | seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", | |
1663 | ta_fw_name[i], fw_info.feature, fw_info.ver); | |
9b9ca62d | 1664 | } |
1665 | ||
50ab2533 HR |
1666 | /* SMC */ |
1667 | query_fw.fw_type = AMDGPU_INFO_FW_SMC; | |
1668 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1669 | if (ret) | |
1670 | return ret; | |
82890466 ML |
1671 | smu_program = (fw_info.ver >> 24) & 0xff; |
1672 | smu_major = (fw_info.ver >> 16) & 0xff; | |
c92f9096 ML |
1673 | smu_minor = (fw_info.ver >> 8) & 0xff; |
1674 | smu_debug = (fw_info.ver >> 0) & 0xff; | |
82890466 ML |
1675 | seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", |
1676 | fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); | |
50ab2533 HR |
1677 | |
1678 | /* SDMA */ | |
1679 | query_fw.fw_type = AMDGPU_INFO_FW_SDMA; | |
1680 | for (i = 0; i < adev->sdma.num_instances; i++) { | |
1681 | query_fw.index = i; | |
1682 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1683 | if (ret) | |
1684 | return ret; | |
1685 | seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", | |
1686 | i, fw_info.feature, fw_info.ver); | |
1687 | } | |
1688 | ||
3ac952b1 AD |
1689 | /* VCN */ |
1690 | query_fw.fw_type = AMDGPU_INFO_FW_VCN; | |
1691 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1692 | if (ret) | |
1693 | return ret; | |
1694 | seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", | |
1695 | fw_info.feature, fw_info.ver); | |
1696 | ||
4d11b4b2 DF |
1697 | /* DMCU */ |
1698 | query_fw.fw_type = AMDGPU_INFO_FW_DMCU; | |
1699 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1700 | if (ret) | |
1701 | return ret; | |
1702 | seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", | |
1703 | fw_info.feature, fw_info.ver); | |
1704 | ||
976e51a7 NK |
1705 | /* DMCUB */ |
1706 | query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; | |
1707 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1708 | if (ret) | |
1709 | return ret; | |
1710 | seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", | |
1711 | fw_info.feature, fw_info.ver); | |
1712 | ||
5120cb54 HR |
1713 | /* TOC */ |
1714 | query_fw.fw_type = AMDGPU_INFO_FW_TOC; | |
1715 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1716 | if (ret) | |
1717 | return ret; | |
1718 | seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", | |
1719 | fw_info.feature, fw_info.ver); | |
32d8c662 | 1720 | |
c4381d0e BZ |
1721 | /* CAP */ |
1722 | if (adev->psp.cap_fw) { | |
1723 | query_fw.fw_type = AMDGPU_INFO_FW_CAP; | |
1724 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1725 | if (ret) | |
1726 | return ret; | |
1727 | seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", | |
1728 | fw_info.feature, fw_info.ver); | |
1729 | } | |
1730 | ||
10faf078 YZ |
1731 | /* MES_KIQ */ |
1732 | query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; | |
1733 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1734 | if (ret) | |
1735 | return ret; | |
1736 | seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", | |
1737 | fw_info.feature, fw_info.ver); | |
1738 | ||
1739 | /* MES */ | |
1740 | query_fw.fw_type = AMDGPU_INFO_FW_MES; | |
1741 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1742 | if (ret) | |
1743 | return ret; | |
1744 | seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", | |
1745 | fw_info.feature, fw_info.ver); | |
1746 | ||
5f6e9cdc LY |
1747 | /* VPE */ |
1748 | query_fw.fw_type = AMDGPU_INFO_FW_VPE; | |
1749 | ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); | |
1750 | if (ret) | |
1751 | return ret; | |
1752 | seq_printf(m, "VPE feature version: %u, firmware version: 0x%08x\n", | |
1753 | fw_info.feature, fw_info.ver); | |
1754 | ||
adf64e21 | 1755 | seq_printf(m, "VBIOS version: %s\n", ctx->vbios_pn); |
32d8c662 | 1756 | |
50ab2533 HR |
1757 | return 0; |
1758 | } | |
1759 | ||
98d28ac2 ND |
1760 | DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); |
1761 | ||
50ab2533 HR |
1762 | #endif |
1763 | ||
98d28ac2 | 1764 | void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) |
50ab2533 HR |
1765 | { |
1766 | #if defined(CONFIG_DEBUG_FS) | |
98d28ac2 ND |
1767 | struct drm_minor *minor = adev_to_drm(adev)->primary; |
1768 | struct dentry *root = minor->debugfs_root; | |
1769 | ||
1770 | debugfs_create_file("amdgpu_firmware_info", 0444, root, | |
1771 | adev, &amdgpu_debugfs_firmware_info_fops); | |
1772 | ||
50ab2533 HR |
1773 | #endif |
1774 | } |