[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_irq.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_IRQ_H__
#define __AMDGPU_IRQ_H__

#include <linux/irqdomain.h>
#include "soc15_ih_clientid.h"
#include "amdgpu_ih.h"

#define AMDGPU_MAX_IRQ_SRC_ID		0x100
#define AMDGPU_MAX_IRQ_CLIENT_ID	0x100

#define AMDGPU_IRQ_CLIENTID_LEGACY	0
#define AMDGPU_IRQ_CLIENTID_MAX		SOC15_IH_CLIENTID_MAX

#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW	4

struct amdgpu_device;

enum amdgpu_interrupt_state {
	AMDGPU_IRQ_STATE_DISABLE,
	AMDGPU_IRQ_STATE_ENABLE,
};

struct amdgpu_iv_entry {
	unsigned client_id;
	unsigned src_id;
	unsigned ring_id;
	unsigned vmid;
	unsigned vmid_src;
	uint64_t timestamp;
	unsigned timestamp_src;
	unsigned pasid;
	unsigned pasid_src;
	unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
	const uint32_t *iv_entry;
};

struct amdgpu_irq_src {
	unsigned				num_types;
	atomic_t				*enabled_types;
	const struct amdgpu_irq_src_funcs	*funcs;
	void *data;
};

struct amdgpu_irq_client {
	struct amdgpu_irq_src **sources;
};

/* provided by interrupt generating IP blocks */
struct amdgpu_irq_src_funcs {
	int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
		   unsigned type, enum amdgpu_interrupt_state state);

	int (*process)(struct amdgpu_device *adev,
		       struct amdgpu_irq_src *source,
		       struct amdgpu_iv_entry *entry);
};

struct amdgpu_irq {
	bool				installed;
	spinlock_t			lock;
	/* interrupt sources */
	struct amdgpu_irq_client	client[AMDGPU_IRQ_CLIENTID_MAX];

	/* status, etc. */
	bool				msi_enabled; /* msi enabled */

	/* interrupt rings */
	struct amdgpu_ih_ring		ih, ih1, ih2;
	const struct amdgpu_ih_funcs    *ih_funcs;
	struct work_struct		ih1_work, ih2_work;
	struct amdgpu_irq_src		self_irq;

	/* gen irq stuff */
	struct irq_domain		*domain; /* GPU irq controller domain */
	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
	uint32_t                        srbm_soft_reset;
};

void amdgpu_irq_disable_all(struct amdgpu_device *adev);
irqreturn_t amdgpu_irq_handler(int irq, void *arg);

int amdgpu_irq_init(struct amdgpu_device *adev);
void amdgpu_irq_fini(struct amdgpu_device *adev);
int amdgpu_irq_add_id(struct amdgpu_device *adev,
		      unsigned client_id, unsigned src_id,
		      struct amdgpu_irq_src *source);
void amdgpu_irq_dispatch(struct amdgpu_device *adev,
			 struct amdgpu_ih_ring *ih);
int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		      unsigned type);
int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		   unsigned type);
int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
		   unsigned type);
bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
			unsigned type);
void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);

int amdgpu_irq_add_domain(struct amdgpu_device *adev);
void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);

#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_IRQ_H__
	25	#define __AMDGPU_IRQ_H__
	26
5f232365	27	#include <linux/irqdomain.h>
1ffdeca6	28	#include "soc15_ih_clientid.h"
d38ceaf9 AD	29	#include "amdgpu_ih.h"
d38ceaf9 AD	30
1ffdeca6	31	#define AMDGPU_MAX_IRQ_SRC_ID 0x100
d766e6a3	32	#define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
d38ceaf9	33
1ffdeca6 CK	34	#define AMDGPU_IRQ_CLIENTID_LEGACY 0
	35	#define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX
	36
	37	#define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4
	38
d38ceaf9	39	struct amdgpu_device;
d38ceaf9 AD	40
	41	enum amdgpu_interrupt_state {
	42	AMDGPU_IRQ_STATE_DISABLE,
	43	AMDGPU_IRQ_STATE_ENABLE,
	44	};
	45
1ffdeca6 CK	46	struct amdgpu_iv_entry {
	47	unsigned client_id;
	48	unsigned src_id;
	49	unsigned ring_id;
	50	unsigned vmid;
	51	unsigned vmid_src;
	52	uint64_t timestamp;
	53	unsigned timestamp_src;
	54	unsigned pasid;
	55	unsigned pasid_src;
	56	unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW];
	57	const uint32_t *iv_entry;
	58	};
	59
d38ceaf9 AD	60	struct amdgpu_irq_src {
	61	unsigned num_types;
	62	atomic_t *enabled_types;
	63	const struct amdgpu_irq_src_funcs *funcs;
0cf3be21	64	void *data;
d38ceaf9 AD	65	};
d38ceaf9 AD	66
d766e6a3 AD	67	struct amdgpu_irq_client {
	68	struct amdgpu_irq_src **sources;
	69	};
	70
d38ceaf9 AD	71	/* provided by interrupt generating IP blocks */
	72	struct amdgpu_irq_src_funcs {
	73	int (set)(struct amdgpu_device adev, struct amdgpu_irq_src *source,
	74	unsigned type, enum amdgpu_interrupt_state state);
	75
	76	int (process)(struct amdgpu_device adev,
	77	struct amdgpu_irq_src *source,
	78	struct amdgpu_iv_entry *entry);
	79	};
	80
	81	struct amdgpu_irq {
	82	bool installed;
	83	spinlock_t lock;
	84	/* interrupt sources */
1ffdeca6	85	struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX];
d38ceaf9 AD	86
	87	/* status, etc. */
	88	bool msi_enabled; /* msi enabled */
	89
ad710812 CK	90	/* interrupt rings */
ad710812 CK	91	struct amdgpu_ih_ring ih, ih1, ih2;
9dd60c4e CK	92	const struct amdgpu_ih_funcs *ih_funcs;
	93	struct work_struct ih1_work, ih2_work;
	94	struct amdgpu_irq_src self_irq;
5f232365 AD	95
	96	/* gen irq stuff */
	97	struct irq_domain domain; / GPU irq controller domain */
	98	unsigned virq[AMDGPU_MAX_IRQ_SRC_ID];
1015a1b1	99	uint32_t srbm_soft_reset;
d38ceaf9 AD	100	};
d38ceaf9 AD	101
9950cda2	102	void amdgpu_irq_disable_all(struct amdgpu_device *adev);
d38ceaf9 AD	103	irqreturn_t amdgpu_irq_handler(int irq, void *arg);
	104
	105	int amdgpu_irq_init(struct amdgpu_device *adev);
	106	void amdgpu_irq_fini(struct amdgpu_device *adev);
d766e6a3 AD	107	int amdgpu_irq_add_id(struct amdgpu_device *adev,
d766e6a3 AD	108	unsigned client_id, unsigned src_id,
d38ceaf9 AD	109	struct amdgpu_irq_src *source);
d38ceaf9 AD	110	void amdgpu_irq_dispatch(struct amdgpu_device *adev,
e2fb6e0a	111	struct amdgpu_ih_ring *ih);
d38ceaf9 AD	112	int amdgpu_irq_update(struct amdgpu_device adev, struct amdgpu_irq_src src,
	113	unsigned type);
	114	int amdgpu_irq_get(struct amdgpu_device adev, struct amdgpu_irq_src src,
	115	unsigned type);
d38ceaf9 AD	116	int amdgpu_irq_put(struct amdgpu_device adev, struct amdgpu_irq_src src,
	117	unsigned type);
	118	bool amdgpu_irq_enabled(struct amdgpu_device adev, struct amdgpu_irq_src src,
	119	unsigned type);
0eaeb070	120	void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev);
d38ceaf9	121
5f232365 AD	122	int amdgpu_irq_add_domain(struct amdgpu_device *adev);
	123	void amdgpu_irq_remove_domain(struct amdgpu_device *adev);
	124	unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id);
	125
d38ceaf9	126	#endif