[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ih.c

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include <drm/drmP.h>
#include "amdgpu.h"
#include "amdgpu_ih.h"
#include "amdgpu_amdkfd.h"

/**
 * amdgpu_ih_ring_alloc - allocate memory for the IH ring
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate a ring buffer for the interrupt controller.
 * Returns 0 for success, errors for failure.
 */
static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
{
	int r;

	/* Allocate ring buffer */
	if (adev->irq.ih.ring_obj == NULL) {
		r = amdgpu_bo_create(adev, adev->irq.ih.ring_size,
				     PAGE_SIZE, true,
				     AMDGPU_GEM_DOMAIN_GTT, 0,
				     NULL, &adev->irq.ih.ring_obj);
		if (r) {
			DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
			return r;
		}
		r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
		if (unlikely(r != 0))
			return r;
		r = amdgpu_bo_pin(adev->irq.ih.ring_obj,
				  AMDGPU_GEM_DOMAIN_GTT,
				  &adev->irq.ih.gpu_addr);
		if (r) {
			amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
			DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r);
			return r;
		}
		r = amdgpu_bo_kmap(adev->irq.ih.ring_obj,
				   (void **)&adev->irq.ih.ring);
		amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
		if (r) {
			DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r);
			return r;
		}
	}
	return 0;
}

/**
 * amdgpu_ih_ring_init - initialize the IH state
 *
 * @adev: amdgpu_device pointer
 *
 * Initializes the IH state and allocates a buffer
 * for the IH ring buffer.
 * Returns 0 for success, errors for failure.
 */
int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
			bool use_bus_addr)
{
	u32 rb_bufsz;
	int r;

	/* Align ring size */
	rb_bufsz = order_base_2(ring_size / 4);
	ring_size = (1 << rb_bufsz) * 4;
	adev->irq.ih.ring_size = ring_size;
	adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
	adev->irq.ih.rptr = 0;
	adev->irq.ih.use_bus_addr = use_bus_addr;

	if (adev->irq.ih.use_bus_addr) {
		if (!adev->irq.ih.ring) {
			/* add 8 bytes for the rptr/wptr shadows and
			 * add them to the end of the ring allocation.
			 */
			adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
			if (adev->irq.ih.ring == NULL)
				return -ENOMEM;
			adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
								  (void *)adev->irq.ih.ring,
								  adev->irq.ih.ring_size,
								  PCI_DMA_BIDIRECTIONAL);
			if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) {
				dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n");
				kfree((void *)adev->irq.ih.ring);
				return -ENOMEM;
			}
			adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
			adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
		}
		return 0;
	} else {
		r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
		if (r) {
			dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
			return r;
		}

		r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
		if (r) {
			amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
			dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
			return r;
		}

		return amdgpu_ih_ring_alloc(adev);
	}
}

/**
 * amdgpu_ih_ring_fini - tear down the IH state
 *
 * @adev: amdgpu_device pointer
 *
 * Tears down the IH state and frees buffer
 * used for the IH ring buffer.
 */
void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
{
	int r;

	if (adev->irq.ih.use_bus_addr) {
		if (adev->irq.ih.ring) {
			/* add 8 bytes for the rptr/wptr shadows and
			 * add them to the end of the ring allocation.
			 */
			pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr,
					 adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL);
			kfree((void *)adev->irq.ih.ring);
			adev->irq.ih.ring = NULL;
		}
	} else {
		if (adev->irq.ih.ring_obj) {
			r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
			if (likely(r == 0)) {
				amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
				amdgpu_bo_unpin(adev->irq.ih.ring_obj);
				amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
			}
			amdgpu_bo_unref(&adev->irq.ih.ring_obj);
			adev->irq.ih.ring = NULL;
			adev->irq.ih.ring_obj = NULL;
		}
		amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
		amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
	}
}

/**
 * amdgpu_ih_process - interrupt handler
 *
 * @adev: amdgpu_device pointer
 *
 * Interrupt hander (VI), walk the IH ring.
 * Returns irq process return code.
 */
int amdgpu_ih_process(struct amdgpu_device *adev)
{
	struct amdgpu_iv_entry entry;
	u32 wptr;

	if (!adev->irq.ih.enabled || adev->shutdown)
		return IRQ_NONE;

	wptr = amdgpu_ih_get_wptr(adev);

restart_ih:
	/* is somebody else already processing irqs? */
	if (atomic_xchg(&adev->irq.ih.lock, 1))
		return IRQ_NONE;

	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);

	/* Order reading of wptr vs. reading of IH ring data */
	rmb();

	while (adev->irq.ih.rptr != wptr) {
		u32 ring_index = adev->irq.ih.rptr >> 2;

		/* Before dispatching irq to IP blocks, send it to amdkfd */
		amdgpu_amdkfd_interrupt(adev,
				(const void *) &adev->irq.ih.ring[ring_index]);

		amdgpu_ih_decode_iv(adev, &entry);
		adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;

		amdgpu_irq_dispatch(adev, &entry);
	}
	amdgpu_ih_set_rptr(adev);
	atomic_set(&adev->irq.ih.lock, 0);

	/* make sure wptr hasn't changed while processing */
	wptr = amdgpu_ih_get_wptr(adev);
	if (wptr != adev->irq.ih.rptr)
		goto restart_ih;

	return IRQ_HANDLED;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#include <drm/drmP.h>
	25	#include "amdgpu.h"
	26	#include "amdgpu_ih.h"
130e0371	27	#include "amdgpu_amdkfd.h"
d38ceaf9 AD	28
	29	/**
	30	* amdgpu_ih_ring_alloc - allocate memory for the IH ring
	31	*
	32	* @adev: amdgpu_device pointer
	33	*
	34	* Allocate a ring buffer for the interrupt controller.
	35	* Returns 0 for success, errors for failure.
	36	*/
	37	static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
	38	{
	39	int r;
	40
	41	/* Allocate ring buffer */
	42	if (adev->irq.ih.ring_obj == NULL) {
	43	r = amdgpu_bo_create(adev, adev->irq.ih.ring_size,
	44	PAGE_SIZE, true,
	45	AMDGPU_GEM_DOMAIN_GTT, 0,
	46	NULL, &adev->irq.ih.ring_obj);
	47	if (r) {
	48	DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
	49	return r;
	50	}
	51	r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
	52	if (unlikely(r != 0))
	53	return r;
	54	r = amdgpu_bo_pin(adev->irq.ih.ring_obj,
	55	AMDGPU_GEM_DOMAIN_GTT,
	56	&adev->irq.ih.gpu_addr);
	57	if (r) {
	58	amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
	59	DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r);
	60	return r;
	61	}
	62	r = amdgpu_bo_kmap(adev->irq.ih.ring_obj,
	63	(void **)&adev->irq.ih.ring);
	64	amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
	65	if (r) {
	66	DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r);
	67	return r;
	68	}
	69	}
	70	return 0;
	71	}
	72
	73	/**
	74	* amdgpu_ih_ring_init - initialize the IH state
	75	*
	76	* @adev: amdgpu_device pointer
	77	*
	78	* Initializes the IH state and allocates a buffer
	79	* for the IH ring buffer.
	80	* Returns 0 for success, errors for failure.
	81	*/
	82	int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
	83	bool use_bus_addr)
	84	{
	85	u32 rb_bufsz;
	86	int r;
	87
	88	/* Align ring size */
	89	rb_bufsz = order_base_2(ring_size / 4);
	90	ring_size = (1 << rb_bufsz) * 4;
	91	adev->irq.ih.ring_size = ring_size;
92	adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
93	adev->irq.ih.rptr = 0;
94	adev->irq.ih.use_bus_addr = use_bus_addr;
95
96	if (adev->irq.ih.use_bus_addr) {
97	if (!adev->irq.ih.ring) {
98	/* add 8 bytes for the rptr/wptr shadows and
99	* add them to the end of the ring allocation.
100	*/
101	adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL);
102	if (adev->irq.ih.ring == NULL)
103	return -ENOMEM;
104	adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev,
105	(void *)adev->irq.ih.ring,
106	adev->irq.ih.ring_size,
107	PCI_DMA_BIDIRECTIONAL);
108	if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) {
109	dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n");
110	kfree((void *)adev->irq.ih.ring);
111	return -ENOMEM;
112	}
113	adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
114	adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
115	}
116	return 0;
117	} else {
118	r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
119	if (r) {
120	dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
121	return r;
122	}
123
124	r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
125	if (r) {
126	amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
127	dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
128	return r;
129	}
130
131	return amdgpu_ih_ring_alloc(adev);
132	}
133	}
134
135	/**
136	* amdgpu_ih_ring_fini - tear down the IH state
137	*
138	* @adev: amdgpu_device pointer
139	*
140	* Tears down the IH state and frees buffer
141	* used for the IH ring buffer.
142	*/
143	void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
144	{
145	int r;
146
147	if (adev->irq.ih.use_bus_addr) {
148	if (adev->irq.ih.ring) {
149	/* add 8 bytes for the rptr/wptr shadows and
150	* add them to the end of the ring allocation.
151	*/
152	pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr,
153	adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL);
154	kfree((void *)adev->irq.ih.ring);
155	adev->irq.ih.ring = NULL;
156	}
157	} else {
158	if (adev->irq.ih.ring_obj) {
159	r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
160	if (likely(r == 0)) {
161	amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
162	amdgpu_bo_unpin(adev->irq.ih.ring_obj);
163	amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
164	}
165	amdgpu_bo_unref(&adev->irq.ih.ring_obj);
166	adev->irq.ih.ring = NULL;
167	adev->irq.ih.ring_obj = NULL;
168	}
169	amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
170	amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
171	}
172	}
173
174	/**
175	* amdgpu_ih_process - interrupt handler
176	*
177	* @adev: amdgpu_device pointer
178	*
179	* Interrupt hander (VI), walk the IH ring.
180	* Returns irq process return code.
181	*/
182	int amdgpu_ih_process(struct amdgpu_device *adev)
183	{
184	struct amdgpu_iv_entry entry;
185	u32 wptr;
186
187	if (!adev->irq.ih.enabled \|\| adev->shutdown)
188	return IRQ_NONE;
189
190	wptr = amdgpu_ih_get_wptr(adev);
191
192	restart_ih:
193	/* is somebody else already processing irqs? */
194	if (atomic_xchg(&adev->irq.ih.lock, 1))
195	return IRQ_NONE;
196
197	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
198
199	/* Order reading of wptr vs. reading of IH ring data */
200	rmb();
201
202	while (adev->irq.ih.rptr != wptr) {
130e0371 OG	203	u32 ring_index = adev->irq.ih.rptr >> 2;
	204
	205	/* Before dispatching irq to IP blocks, send it to amdkfd */
	206	amdgpu_amdkfd_interrupt(adev,
	207	(const void *) &adev->irq.ih.ring[ring_index]);
	208
d38ceaf9 AD	209	amdgpu_ih_decode_iv(adev, &entry);
	210	adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
	211
	212	amdgpu_irq_dispatch(adev, &entry);
	213	}
	214	amdgpu_ih_set_rptr(adev);
	215	atomic_set(&adev->irq.ih.lock, 0);
	216
	217	/* make sure wptr hasn't changed while processing */
	218	wptr = amdgpu_ih_get_wptr(adev);
	219	if (wptr != adev->irq.ih.rptr)
	220	goto restart_ih;
	221
	222	return IRQ_HANDLED;
	223	}