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1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | * Christian König | |
28 | */ | |
29 | #include <linux/seq_file.h> | |
30 | #include <linux/slab.h> | |
31 | #include <drm/drmP.h> | |
32 | #include <drm/amdgpu_drm.h> | |
33 | #include "amdgpu.h" | |
34 | #include "atom.h" | |
35 | ||
36 | /* | |
37 | * IB | |
38 | * IBs (Indirect Buffers) and areas of GPU accessible memory where | |
39 | * commands are stored. You can put a pointer to the IB in the | |
40 | * command ring and the hw will fetch the commands from the IB | |
41 | * and execute them. Generally userspace acceleration drivers | |
42 | * produce command buffers which are send to the kernel and | |
43 | * put in IBs for execution by the requested ring. | |
44 | */ | |
45 | static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); | |
46 | ||
47 | /** | |
48 | * amdgpu_ib_get - request an IB (Indirect Buffer) | |
49 | * | |
50 | * @ring: ring index the IB is associated with | |
51 | * @size: requested IB size | |
52 | * @ib: IB object returned | |
53 | * | |
54 | * Request an IB (all asics). IBs are allocated using the | |
55 | * suballocator. | |
56 | * Returns 0 on success, error on failure. | |
57 | */ | |
58 | int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, | |
59 | unsigned size, struct amdgpu_ib *ib) | |
60 | { | |
61 | struct amdgpu_device *adev = ring->adev; | |
62 | int r; | |
63 | ||
64 | if (size) { | |
65 | r = amdgpu_sa_bo_new(adev, &adev->ring_tmp_bo, | |
66 | &ib->sa_bo, size, 256); | |
67 | if (r) { | |
68 | dev_err(adev->dev, "failed to get a new IB (%d)\n", r); | |
69 | return r; | |
70 | } | |
71 | ||
72 | ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo); | |
73 | ||
74 | if (!vm) | |
75 | ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); | |
76 | else | |
77 | ib->gpu_addr = 0; | |
78 | ||
79 | } else { | |
80 | ib->sa_bo = NULL; | |
81 | ib->ptr = NULL; | |
82 | ib->gpu_addr = 0; | |
83 | } | |
84 | ||
85 | amdgpu_sync_create(&ib->sync); | |
86 | ||
87 | ib->ring = ring; | |
88 | ib->fence = NULL; | |
89 | ib->user = NULL; | |
90 | ib->vm = vm; | |
91 | ib->is_const_ib = false; | |
92 | ib->gds_base = 0; | |
93 | ib->gds_size = 0; | |
94 | ib->gws_base = 0; | |
95 | ib->gws_size = 0; | |
96 | ib->oa_base = 0; | |
97 | ib->oa_size = 0; | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | /** | |
103 | * amdgpu_ib_free - free an IB (Indirect Buffer) | |
104 | * | |
105 | * @adev: amdgpu_device pointer | |
106 | * @ib: IB object to free | |
107 | * | |
108 | * Free an IB (all asics). | |
109 | */ | |
110 | void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) | |
111 | { | |
112 | amdgpu_sync_free(adev, &ib->sync, ib->fence); | |
113 | amdgpu_sa_bo_free(adev, &ib->sa_bo, ib->fence); | |
114 | amdgpu_fence_unref(&ib->fence); | |
115 | } | |
116 | ||
117 | /** | |
118 | * amdgpu_ib_schedule - schedule an IB (Indirect Buffer) on the ring | |
119 | * | |
120 | * @adev: amdgpu_device pointer | |
121 | * @num_ibs: number of IBs to schedule | |
122 | * @ibs: IB objects to schedule | |
123 | * @owner: owner for creating the fences | |
124 | * | |
125 | * Schedule an IB on the associated ring (all asics). | |
126 | * Returns 0 on success, error on failure. | |
127 | * | |
128 | * On SI, there are two parallel engines fed from the primary ring, | |
129 | * the CE (Constant Engine) and the DE (Drawing Engine). Since | |
130 | * resource descriptors have moved to memory, the CE allows you to | |
131 | * prime the caches while the DE is updating register state so that | |
132 | * the resource descriptors will be already in cache when the draw is | |
133 | * processed. To accomplish this, the userspace driver submits two | |
134 | * IBs, one for the CE and one for the DE. If there is a CE IB (called | |
135 | * a CONST_IB), it will be put on the ring prior to the DE IB. Prior | |
136 | * to SI there was just a DE IB. | |
137 | */ | |
138 | int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, | |
139 | struct amdgpu_ib *ibs, void *owner) | |
140 | { | |
141 | struct amdgpu_ring *ring; | |
142 | struct amdgpu_vm *vm = ibs->vm; | |
143 | struct amdgpu_ib *ib = &ibs[0]; | |
144 | unsigned i; | |
145 | int r = 0; | |
146 | bool flush_hdp = true; | |
147 | ||
148 | if (num_ibs == 0) | |
149 | return -EINVAL; | |
150 | ||
151 | ring = ibs->ring; | |
152 | if (!ring->ready) { | |
153 | dev_err(adev->dev, "couldn't schedule ib\n"); | |
154 | return -EINVAL; | |
155 | } | |
156 | ||
157 | r = amdgpu_ring_lock(ring, (256 + AMDGPU_NUM_SYNCS * 8) * num_ibs); | |
158 | if (r) { | |
159 | dev_err(adev->dev, "scheduling IB failed (%d).\n", r); | |
160 | return r; | |
161 | } | |
162 | ||
163 | if (vm) { | |
164 | /* grab a vm id if necessary */ | |
165 | struct amdgpu_fence *vm_id_fence = NULL; | |
166 | vm_id_fence = amdgpu_vm_grab_id(ibs->ring, ibs->vm); | |
167 | amdgpu_sync_fence(&ibs->sync, vm_id_fence); | |
168 | } | |
169 | ||
170 | r = amdgpu_sync_rings(&ibs->sync, ring); | |
171 | if (r) { | |
172 | amdgpu_ring_unlock_undo(ring); | |
173 | dev_err(adev->dev, "failed to sync rings (%d)\n", r); | |
174 | return r; | |
175 | } | |
176 | ||
177 | if (vm) { | |
178 | /* do context switch */ | |
179 | amdgpu_vm_flush(ring, vm, ib->sync.last_vm_update); | |
180 | } | |
181 | ||
182 | if (ring->funcs->emit_gds_switch && ib->vm && ib->gds_needed) | |
183 | amdgpu_ring_emit_gds_switch(ring, ib->vm->ids[ring->idx].id, | |
184 | ib->gds_base, ib->gds_size, | |
185 | ib->gws_base, ib->gws_size, | |
186 | ib->oa_base, ib->oa_size); | |
187 | ||
188 | for (i = 0; i < num_ibs; ++i) { | |
189 | ib = &ibs[i]; | |
190 | ||
191 | if (ib->ring != ring) { | |
192 | amdgpu_ring_unlock_undo(ring); | |
193 | return -EINVAL; | |
194 | } | |
195 | ib->flush_hdp_writefifo = flush_hdp; | |
196 | flush_hdp = false; | |
197 | amdgpu_ring_emit_ib(ring, ib); | |
198 | } | |
199 | ||
200 | r = amdgpu_fence_emit(ring, owner, &ib->fence); | |
201 | if (r) { | |
202 | dev_err(adev->dev, "failed to emit fence (%d)\n", r); | |
203 | amdgpu_ring_unlock_undo(ring); | |
204 | return r; | |
205 | } | |
206 | ||
207 | /* wrap the last IB with fence */ | |
208 | if (ib->user) { | |
209 | uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); | |
210 | addr += ib->user->offset; | |
211 | amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, true); | |
212 | } | |
213 | ||
214 | if (ib->vm) | |
215 | amdgpu_vm_fence(adev, ib->vm, ib->fence); | |
216 | ||
217 | amdgpu_ring_unlock_commit(ring); | |
218 | return 0; | |
219 | } | |
220 | ||
221 | /** | |
222 | * amdgpu_ib_pool_init - Init the IB (Indirect Buffer) pool | |
223 | * | |
224 | * @adev: amdgpu_device pointer | |
225 | * | |
226 | * Initialize the suballocator to manage a pool of memory | |
227 | * for use as IBs (all asics). | |
228 | * Returns 0 on success, error on failure. | |
229 | */ | |
230 | int amdgpu_ib_pool_init(struct amdgpu_device *adev) | |
231 | { | |
232 | int r; | |
233 | ||
234 | if (adev->ib_pool_ready) { | |
235 | return 0; | |
236 | } | |
237 | r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo, | |
238 | AMDGPU_IB_POOL_SIZE*64*1024, | |
239 | AMDGPU_GPU_PAGE_SIZE, | |
240 | AMDGPU_GEM_DOMAIN_GTT); | |
241 | if (r) { | |
242 | return r; | |
243 | } | |
244 | ||
245 | r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo); | |
246 | if (r) { | |
247 | return r; | |
248 | } | |
249 | ||
250 | adev->ib_pool_ready = true; | |
251 | if (amdgpu_debugfs_sa_init(adev)) { | |
252 | dev_err(adev->dev, "failed to register debugfs file for SA\n"); | |
253 | } | |
254 | return 0; | |
255 | } | |
256 | ||
257 | /** | |
258 | * amdgpu_ib_pool_fini - Free the IB (Indirect Buffer) pool | |
259 | * | |
260 | * @adev: amdgpu_device pointer | |
261 | * | |
262 | * Tear down the suballocator managing the pool of memory | |
263 | * for use as IBs (all asics). | |
264 | */ | |
265 | void amdgpu_ib_pool_fini(struct amdgpu_device *adev) | |
266 | { | |
267 | if (adev->ib_pool_ready) { | |
268 | amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo); | |
269 | amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo); | |
270 | adev->ib_pool_ready = false; | |
271 | } | |
272 | } | |
273 | ||
274 | /** | |
275 | * amdgpu_ib_ring_tests - test IBs on the rings | |
276 | * | |
277 | * @adev: amdgpu_device pointer | |
278 | * | |
279 | * Test an IB (Indirect Buffer) on each ring. | |
280 | * If the test fails, disable the ring. | |
281 | * Returns 0 on success, error if the primary GFX ring | |
282 | * IB test fails. | |
283 | */ | |
284 | int amdgpu_ib_ring_tests(struct amdgpu_device *adev) | |
285 | { | |
286 | unsigned i; | |
287 | int r; | |
288 | ||
289 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | |
290 | struct amdgpu_ring *ring = adev->rings[i]; | |
291 | ||
292 | if (!ring || !ring->ready) | |
293 | continue; | |
294 | ||
295 | r = amdgpu_ring_test_ib(ring); | |
296 | if (r) { | |
297 | ring->ready = false; | |
298 | adev->needs_reset = false; | |
299 | ||
300 | if (ring == &adev->gfx.gfx_ring[0]) { | |
301 | /* oh, oh, that's really bad */ | |
302 | DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r); | |
303 | adev->accel_working = false; | |
304 | return r; | |
305 | ||
306 | } else { | |
307 | /* still not good, but we can live with it */ | |
308 | DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r); | |
309 | } | |
310 | } | |
311 | } | |
312 | return 0; | |
313 | } | |
314 | ||
315 | /* | |
316 | * Debugfs info | |
317 | */ | |
318 | #if defined(CONFIG_DEBUG_FS) | |
319 | ||
320 | static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data) | |
321 | { | |
322 | struct drm_info_node *node = (struct drm_info_node *) m->private; | |
323 | struct drm_device *dev = node->minor->dev; | |
324 | struct amdgpu_device *adev = dev->dev_private; | |
325 | ||
326 | amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m); | |
327 | ||
328 | return 0; | |
329 | ||
330 | } | |
331 | ||
332 | static struct drm_info_list amdgpu_debugfs_sa_list[] = { | |
333 | {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL}, | |
334 | }; | |
335 | ||
336 | #endif | |
337 | ||
338 | static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev) | |
339 | { | |
340 | #if defined(CONFIG_DEBUG_FS) | |
341 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1); | |
342 | #else | |
343 | return 0; | |
344 | #endif | |
345 | } |