[linux-2.6-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gfx.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __AMDGPU_GFX_H__
#define __AMDGPU_GFX_H__

/*
 * GFX stuff
 */
#include "clearstate_defs.h"
#include "amdgpu_ring.h"
#include "amdgpu_rlc.h"

/* GFX current status */
#define AMDGPU_GFX_NORMAL_MODE			0x00000000L
#define AMDGPU_GFX_SAFE_MODE			0x00000001L
#define AMDGPU_GFX_PG_DISABLED_MODE		0x00000002L
#define AMDGPU_GFX_CG_DISABLED_MODE		0x00000004L
#define AMDGPU_GFX_LBPW_DISABLED_MODE		0x00000008L

#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES

enum gfx_pipe_priority {
	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
	AMDGPU_GFX_PIPE_PRIO_HIGH,
	AMDGPU_GFX_PIPE_PRIO_MAX
};

/* Argument for PPSMC_MSG_GpuChangeState */
enum gfx_change_state {
	sGpuChangeState_D0Entry = 1,
	sGpuChangeState_D3Entry,
};

#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM  0
#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM  15

struct amdgpu_mec {
	struct amdgpu_bo	*hpd_eop_obj;
	u64			hpd_eop_gpu_addr;
	struct amdgpu_bo	*mec_fw_obj;
	u64			mec_fw_gpu_addr;
	u32 num_mec;
	u32 num_pipe_per_mec;
	u32 num_queue_per_pipe;
	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];

	/* These are the resources for which amdgpu takes ownership */
	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
};

enum amdgpu_unmap_queues_action {
	PREEMPT_QUEUES = 0,
	RESET_QUEUES,
	DISABLE_PROCESS_QUEUES,
	PREEMPT_QUEUES_NO_UNMAP,
};

struct kiq_pm4_funcs {
	/* Support ASIC-specific kiq pm4 packets*/
	void (*kiq_set_resources)(struct amdgpu_ring *kiq_ring,
					uint64_t queue_mask);
	void (*kiq_map_queues)(struct amdgpu_ring *kiq_ring,
					struct amdgpu_ring *ring);
	void (*kiq_unmap_queues)(struct amdgpu_ring *kiq_ring,
				 struct amdgpu_ring *ring,
				 enum amdgpu_unmap_queues_action action,
				 u64 gpu_addr, u64 seq);
	void (*kiq_query_status)(struct amdgpu_ring *kiq_ring,
					struct amdgpu_ring *ring,
					u64 addr,
					u64 seq);
	void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring,
				uint16_t pasid, uint32_t flush_type,
				bool all_hub);
	/* Packet sizes */
	int set_resources_size;
	int map_queues_size;
	int unmap_queues_size;
	int query_status_size;
	int invalidate_tlbs_size;
};

struct amdgpu_kiq {
	u64			eop_gpu_addr;
	struct amdgpu_bo	*eop_obj;
	spinlock_t              ring_lock;
	struct amdgpu_ring	ring;
	struct amdgpu_irq_src	irq;
	const struct kiq_pm4_funcs *pmf;
};

/*
 * GPU scratch registers structures, functions & helpers
 */
struct amdgpu_scratch {
	unsigned		num_reg;
	uint32_t                reg_base;
	uint32_t		free_mask;
};

/*
 * GFX configurations
 */
#define AMDGPU_GFX_MAX_SE 4
#define AMDGPU_GFX_MAX_SH_PER_SE 2

struct amdgpu_rb_config {
	uint32_t rb_backend_disable;
	uint32_t user_rb_backend_disable;
	uint32_t raster_config;
	uint32_t raster_config_1;
};

struct gb_addr_config {
	uint16_t pipe_interleave_size;
	uint8_t num_pipes;
	uint8_t max_compress_frags;
	uint8_t num_banks;
	uint8_t num_se;
	uint8_t num_rb_per_se;
	uint8_t num_pkrs;
};

struct amdgpu_gfx_config {
	unsigned max_shader_engines;
	unsigned max_tile_pipes;
	unsigned max_cu_per_sh;
	unsigned max_sh_per_se;
	unsigned max_backends_per_se;
	unsigned max_texture_channel_caches;
	unsigned max_gprs;
	unsigned max_gs_threads;
	unsigned max_hw_contexts;
	unsigned sc_prim_fifo_size_frontend;
	unsigned sc_prim_fifo_size_backend;
	unsigned sc_hiz_tile_fifo_size;
	unsigned sc_earlyz_tile_fifo_size;

	unsigned num_tile_pipes;
	unsigned backend_enable_mask;
	unsigned mem_max_burst_length_bytes;
	unsigned mem_row_size_in_kb;
	unsigned shader_engine_tile_size;
	unsigned num_gpus;
	unsigned multi_gpu_tile_size;
	unsigned mc_arb_ramcfg;
	unsigned num_banks;
	unsigned num_ranks;
	unsigned gb_addr_config;
	unsigned num_rbs;
	unsigned gs_vgt_table_depth;
	unsigned gs_prim_buffer_depth;

	uint32_t tile_mode_array[32];
	uint32_t macrotile_mode_array[16];

	struct gb_addr_config gb_addr_config_fields;
	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];

	/* gfx configure feature */
	uint32_t double_offchip_lds_buf;
	/* cached value of DB_DEBUG2 */
	uint32_t db_debug2;
	/* gfx10 specific config */
	uint32_t num_sc_per_sh;
	uint32_t num_packer_per_sc;
	uint32_t pa_sc_tile_steering_override;
	uint64_t tcc_disabled_mask;
};

struct amdgpu_cu_info {
	uint32_t simd_per_cu;
	uint32_t max_waves_per_simd;
	uint32_t wave_front_size;
	uint32_t max_scratch_slots_per_cu;
	uint32_t lds_size;

	/* total active CU number */
	uint32_t number;
	uint32_t ao_cu_mask;
	uint32_t ao_cu_bitmap[4][4];
	uint32_t bitmap[4][4];
};

struct amdgpu_gfx_funcs {
	/* get the gpu clock counter */
	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
	void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
			     u32 sh_num, u32 instance);
	void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
			       uint32_t wave, uint32_t *dst, int *no_fields);
	void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
				uint32_t wave, uint32_t thread, uint32_t start,
				uint32_t size, uint32_t *dst);
	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
				uint32_t wave, uint32_t start, uint32_t size,
				uint32_t *dst);
	void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
				 u32 queue, u32 vmid);
	int (*ras_error_inject)(struct amdgpu_device *adev, void *inject_if);
	int (*query_ras_error_count) (struct amdgpu_device *adev, void *ras_error_status);
	void (*reset_ras_error_count) (struct amdgpu_device *adev);
	void (*init_spm_golden)(struct amdgpu_device *adev);
	void (*query_ras_error_status) (struct amdgpu_device *adev);
	void (*update_perfmon_mgcg)(struct amdgpu_device *adev, bool enable);
};

struct sq_work {
	struct work_struct	work;
	unsigned ih_data;
};

struct amdgpu_pfp {
	struct amdgpu_bo		*pfp_fw_obj;
	uint64_t			pfp_fw_gpu_addr;
	uint32_t			*pfp_fw_ptr;
};

struct amdgpu_ce {
	struct amdgpu_bo		*ce_fw_obj;
	uint64_t			ce_fw_gpu_addr;
	uint32_t			*ce_fw_ptr;
};

struct amdgpu_me {
	struct amdgpu_bo		*me_fw_obj;
	uint64_t			me_fw_gpu_addr;
	uint32_t			*me_fw_ptr;
	uint32_t			num_me;
	uint32_t			num_pipe_per_me;
	uint32_t			num_queue_per_pipe;
	void				*mqd_backup[AMDGPU_MAX_GFX_RINGS];

	/* These are the resources for which amdgpu takes ownership */
	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
};

struct amdgpu_gfx {
	struct mutex			gpu_clock_mutex;
	struct amdgpu_gfx_config	config;
	struct amdgpu_rlc		rlc;
	struct amdgpu_pfp		pfp;
	struct amdgpu_ce		ce;
	struct amdgpu_me		me;
	struct amdgpu_mec		mec;
	struct amdgpu_kiq		kiq;
	struct amdgpu_scratch		scratch;
	const struct firmware		*me_fw;	/* ME firmware */
	uint32_t			me_fw_version;
	const struct firmware		*pfp_fw; /* PFP firmware */
	uint32_t			pfp_fw_version;
	const struct firmware		*ce_fw;	/* CE firmware */
	uint32_t			ce_fw_version;
	const struct firmware		*rlc_fw; /* RLC firmware */
	uint32_t			rlc_fw_version;
	const struct firmware		*mec_fw; /* MEC firmware */
	uint32_t			mec_fw_version;
	const struct firmware		*mec2_fw; /* MEC2 firmware */
	uint32_t			mec2_fw_version;
	uint32_t			me_feature_version;
	uint32_t			ce_feature_version;
	uint32_t			pfp_feature_version;
	uint32_t			rlc_feature_version;
	uint32_t			rlc_srlc_fw_version;
	uint32_t			rlc_srlc_feature_version;
	uint32_t			rlc_srlg_fw_version;
	uint32_t			rlc_srlg_feature_version;
	uint32_t			rlc_srls_fw_version;
	uint32_t			rlc_srls_feature_version;
	uint32_t			mec_feature_version;
	uint32_t			mec2_feature_version;
	bool				mec_fw_write_wait;
	bool				me_fw_write_wait;
	bool				cp_fw_write_wait;
	struct amdgpu_ring		gfx_ring[AMDGPU_MAX_GFX_RINGS];
	unsigned			num_gfx_rings;
	struct amdgpu_ring		compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
	unsigned			num_compute_rings;
	struct amdgpu_irq_src		eop_irq;
	struct amdgpu_irq_src		priv_reg_irq;
	struct amdgpu_irq_src		priv_inst_irq;
	struct amdgpu_irq_src		cp_ecc_error_irq;
	struct amdgpu_irq_src		sq_irq;
	struct sq_work			sq_work;

	/* gfx status */
	uint32_t			gfx_current_status;
	/* ce ram size*/
	unsigned			ce_ram_size;
	struct amdgpu_cu_info		cu_info;
	const struct amdgpu_gfx_funcs	*funcs;

	/* reset mask */
	uint32_t                        grbm_soft_reset;
	uint32_t                        srbm_soft_reset;

	/* gfx off */
	bool                            gfx_off_state; /* true: enabled, false: disabled */
	struct mutex                    gfx_off_mutex;
	uint32_t                        gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
	struct delayed_work             gfx_off_delay_work;

	/* pipe reservation */
	struct mutex			pipe_reserve_mutex;
	DECLARE_BITMAP			(pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);

	/*ras */
	struct ras_common_if		*ras_if;
};

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))

/**
 * amdgpu_gfx_create_bitmask - create a bitmask
 *
 * @bit_width: length of the mask
 *
 * create a variable length bit mask.
 * Returns the bitmask.
 */
static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
{
	return (u32)((1ULL << bit_width) - 1);
}

int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);

void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
				 unsigned max_sh);

int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
			     struct amdgpu_ring *ring,
			     struct amdgpu_irq_src *irq);

void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);

void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
			unsigned hpd_size);

int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
			   unsigned mqd_size);
void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);

void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);

int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
				int pipe, int queue);
void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
				 int *mec, int *pipe, int *queue);
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
				     int pipe, int queue);
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
					       int pipe, int queue);
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
			       int pipe, int queue);
void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
				int *me, int *pipe, int *queue);
bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
				    int pipe, int queue);
void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
		void *err_data,
		struct amdgpu_iv_entry *entry);
int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
				  struct amdgpu_irq_src *source,
				  struct amdgpu_iv_entry *entry);
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
#endif
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23
	24	#ifndef __AMDGPU_GFX_H__
	25	#define __AMDGPU_GFX_H__
	26
448fe192 HR	27	/*
	28	* GFX stuff
	29	*/
	30	#include "clearstate_defs.h"
	31	#include "amdgpu_ring.h"
88dfc9a3	32	#include "amdgpu_rlc.h"
d38ceaf9	33
448fe192 HR	34	/* GFX current status */
	35	#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
	36	#define AMDGPU_GFX_SAFE_MODE 0x00000001L
	37	#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
	38	#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
	39	#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
6f8941a2	40
cf02b03f	41	#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES
448fe192 HR	42	#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
448fe192 HR	43
33abcb1f ND	44	enum gfx_pipe_priority {
	45	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,
	46	AMDGPU_GFX_PIPE_PRIO_HIGH,
	47	AMDGPU_GFX_PIPE_PRIO_MAX
	48	};
	49
d90a53d6 PL	50	/* Argument for PPSMC_MSG_GpuChangeState */
	51	enum gfx_change_state {
	52	sGpuChangeState_D0Entry = 1,
	53	sGpuChangeState_D3Entry,
	54	};
	55
33abcb1f ND	56	#define AMDGPU_GFX_QUEUE_PRIORITY_MINIMUM 0
	57	#define AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM 15
	58
448fe192 HR	59	struct amdgpu_mec {
	60	struct amdgpu_bo *hpd_eop_obj;
	61	u64 hpd_eop_gpu_addr;
	62	struct amdgpu_bo *mec_fw_obj;
	63	u64 mec_fw_gpu_addr;
	64	u32 num_mec;
	65	u32 num_pipe_per_mec;
	66	u32 num_queue_per_pipe;
	67	void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
	68
	69	/* These are the resources for which amdgpu takes ownership */
	70	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
	71	};
	72
19191961 JX	73	enum amdgpu_unmap_queues_action {
	74	PREEMPT_QUEUES = 0,
	75	RESET_QUEUES,
	76	DISABLE_PROCESS_QUEUES,
	77	PREEMPT_QUEUES_NO_UNMAP,
	78	};
	79
bc4a6f71 RZ	80	struct kiq_pm4_funcs {
	81	/* Support ASIC-specific kiq pm4 packets*/
	82	void (kiq_set_resources)(struct amdgpu_ring kiq_ring,
	83	uint64_t queue_mask);
	84	void (kiq_map_queues)(struct amdgpu_ring kiq_ring,
	85	struct amdgpu_ring *ring);
	86	void (kiq_unmap_queues)(struct amdgpu_ring kiq_ring,
19191961 JX	87	struct amdgpu_ring *ring,
	88	enum amdgpu_unmap_queues_action action,
	89	u64 gpu_addr, u64 seq);
bc4a6f71 RZ	90	void (kiq_query_status)(struct amdgpu_ring kiq_ring,
	91	struct amdgpu_ring *ring,
	92	u64 addr,
	93	u64 seq);
58e508b6 AS	94	void (kiq_invalidate_tlbs)(struct amdgpu_ring kiq_ring,
	95	uint16_t pasid, uint32_t flush_type,
	96	bool all_hub);
bc4a6f71 RZ	97	/* Packet sizes */
	98	int set_resources_size;
	99	int map_queues_size;
	100	int unmap_queues_size;
	101	int query_status_size;
58e508b6	102	int invalidate_tlbs_size;
bc4a6f71 RZ	103	};
bc4a6f71 RZ	104
448fe192 HR	105	struct amdgpu_kiq {
	106	u64 eop_gpu_addr;
	107	struct amdgpu_bo *eop_obj;
	108	spinlock_t ring_lock;
	109	struct amdgpu_ring ring;
	110	struct amdgpu_irq_src irq;
bc4a6f71	111	const struct kiq_pm4_funcs *pmf;
448fe192 HR	112	};
	113
	114	/*
	115	* GPU scratch registers structures, functions & helpers
	116	*/
	117	struct amdgpu_scratch {
	118	unsigned num_reg;
	119	uint32_t reg_base;
	120	uint32_t free_mask;
	121	};
	122
	123	/*
	124	* GFX configurations
	125	*/
	126	#define AMDGPU_GFX_MAX_SE 4
	127	#define AMDGPU_GFX_MAX_SH_PER_SE 2
	128
	129	struct amdgpu_rb_config {
	130	uint32_t rb_backend_disable;
	131	uint32_t user_rb_backend_disable;
	132	uint32_t raster_config;
	133	uint32_t raster_config_1;
	134	};
	135
	136	struct gb_addr_config {
	137	uint16_t pipe_interleave_size;
	138	uint8_t num_pipes;
	139	uint8_t max_compress_frags;
	140	uint8_t num_banks;
	141	uint8_t num_se;
	142	uint8_t num_rb_per_se;
933c8a93	143	uint8_t num_pkrs;
448fe192 HR	144	};
	145
	146	struct amdgpu_gfx_config {
	147	unsigned max_shader_engines;
	148	unsigned max_tile_pipes;
	149	unsigned max_cu_per_sh;
	150	unsigned max_sh_per_se;
	151	unsigned max_backends_per_se;
	152	unsigned max_texture_channel_caches;
	153	unsigned max_gprs;
	154	unsigned max_gs_threads;
	155	unsigned max_hw_contexts;
	156	unsigned sc_prim_fifo_size_frontend;
	157	unsigned sc_prim_fifo_size_backend;
	158	unsigned sc_hiz_tile_fifo_size;
	159	unsigned sc_earlyz_tile_fifo_size;
	160
	161	unsigned num_tile_pipes;
	162	unsigned backend_enable_mask;
	163	unsigned mem_max_burst_length_bytes;
	164	unsigned mem_row_size_in_kb;
	165	unsigned shader_engine_tile_size;
	166	unsigned num_gpus;
	167	unsigned multi_gpu_tile_size;
	168	unsigned mc_arb_ramcfg;
94b5c215 YZ	169	unsigned num_banks;
94b5c215 YZ	170	unsigned num_ranks;
448fe192 HR	171	unsigned gb_addr_config;
	172	unsigned num_rbs;
	173	unsigned gs_vgt_table_depth;
	174	unsigned gs_prim_buffer_depth;
	175
	176	uint32_t tile_mode_array[32];
	177	uint32_t macrotile_mode_array[16];
	178
	179	struct gb_addr_config gb_addr_config_fields;
	180	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
	181
	182	/* gfx configure feature */
	183	uint32_t double_offchip_lds_buf;
	184	/* cached value of DB_DEBUG2 */
	185	uint32_t db_debug2;
02a9e40a HZ	186	/* gfx10 specific config */
	187	uint32_t num_sc_per_sh;
	188	uint32_t num_packer_per_sc;
3e514732	189	uint32_t pa_sc_tile_steering_override;
cf21e76a	190	uint64_t tcc_disabled_mask;
448fe192 HR	191	};
	192
	193	struct amdgpu_cu_info {
	194	uint32_t simd_per_cu;
	195	uint32_t max_waves_per_simd;
	196	uint32_t wave_front_size;
	197	uint32_t max_scratch_slots_per_cu;
	198	uint32_t lds_size;
	199
	200	/* total active CU number */
	201	uint32_t number;
	202	uint32_t ao_cu_mask;
	203	uint32_t ao_cu_bitmap[4][4];
	204	uint32_t bitmap[4][4];
	205	};
	206
	207	struct amdgpu_gfx_funcs {
	208	/* get the gpu clock counter */
	209	uint64_t (get_gpu_clock_counter)(struct amdgpu_device adev);
	210	void (select_se_sh)(struct amdgpu_device adev, u32 se_num,
	211	u32 sh_num, u32 instance);
	212	void (read_wave_data)(struct amdgpu_device adev, uint32_t simd,
	213	uint32_t wave, uint32_t dst, int no_fields);
	214	void (read_wave_vgprs)(struct amdgpu_device adev, uint32_t simd,
	215	uint32_t wave, uint32_t thread, uint32_t start,
	216	uint32_t size, uint32_t *dst);
	217	void (read_wave_sgprs)(struct amdgpu_device adev, uint32_t simd,
	218	uint32_t wave, uint32_t start, uint32_t size,
	219	uint32_t *dst);
	220	void (select_me_pipe_q)(struct amdgpu_device adev, u32 me, u32 pipe,
0fa4246e	221	u32 queue, u32 vmid);
2c960ea0 DL	222	int (ras_error_inject)(struct amdgpu_device adev, void *inject_if);
2c960ea0 DL	223	int (query_ras_error_count) (struct amdgpu_device adev, void *ras_error_status);
279375c3	224	void (reset_ras_error_count) (struct amdgpu_device adev);
d58fe3cf	225	void (init_spm_golden)(struct amdgpu_device adev);
3f975d0f	226	void (query_ras_error_status) (struct amdgpu_device adev);
3e66275e	227	void (update_perfmon_mgcg)(struct amdgpu_device adev, bool enable);
448fe192 HR	228	};
448fe192 HR	229
448fe192 HR	230	struct sq_work {
	231	struct work_struct work;
	232	unsigned ih_data;
	233	};
	234
068ed934 HZ	235	struct amdgpu_pfp {
	236	struct amdgpu_bo *pfp_fw_obj;
	237	uint64_t pfp_fw_gpu_addr;
	238	uint32_t *pfp_fw_ptr;
	239	};
	240
2a00bb13 HZ	241	struct amdgpu_ce {
	242	struct amdgpu_bo *ce_fw_obj;
	243	uint64_t ce_fw_gpu_addr;
	244	uint32_t *ce_fw_ptr;
	245	};
	246
8825af65 HZ	247	struct amdgpu_me {
	248	struct amdgpu_bo *me_fw_obj;
	249	uint64_t me_fw_gpu_addr;
	250	uint32_t *me_fw_ptr;
cf02b03f HZ	251	uint32_t num_me;
	252	uint32_t num_pipe_per_me;
	253	uint32_t num_queue_per_pipe;
0900a9ef	254	void *mqd_backup[AMDGPU_MAX_GFX_RINGS];
cf02b03f HZ	255
	256	/* These are the resources for which amdgpu takes ownership */
	257	DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
8825af65 HZ	258	};
8825af65 HZ	259
448fe192 HR	260	struct amdgpu_gfx {
	261	struct mutex gpu_clock_mutex;
	262	struct amdgpu_gfx_config config;
	263	struct amdgpu_rlc rlc;
068ed934	264	struct amdgpu_pfp pfp;
2a00bb13	265	struct amdgpu_ce ce;
8825af65	266	struct amdgpu_me me;
448fe192 HR	267	struct amdgpu_mec mec;
	268	struct amdgpu_kiq kiq;
	269	struct amdgpu_scratch scratch;
	270	const struct firmware me_fw; / ME firmware */
	271	uint32_t me_fw_version;
	272	const struct firmware pfp_fw; / PFP firmware */
	273	uint32_t pfp_fw_version;
	274	const struct firmware ce_fw; / CE firmware */
	275	uint32_t ce_fw_version;
	276	const struct firmware rlc_fw; / RLC firmware */
	277	uint32_t rlc_fw_version;
	278	const struct firmware mec_fw; / MEC firmware */
	279	uint32_t mec_fw_version;
	280	const struct firmware mec2_fw; / MEC2 firmware */
	281	uint32_t mec2_fw_version;
	282	uint32_t me_feature_version;
	283	uint32_t ce_feature_version;
	284	uint32_t pfp_feature_version;
	285	uint32_t rlc_feature_version;
	286	uint32_t rlc_srlc_fw_version;
	287	uint32_t rlc_srlc_feature_version;
	288	uint32_t rlc_srlg_fw_version;
	289	uint32_t rlc_srlg_feature_version;
	290	uint32_t rlc_srls_fw_version;
	291	uint32_t rlc_srls_feature_version;
	292	uint32_t mec_feature_version;
	293	uint32_t mec2_feature_version;
39b62541 ED	294	bool mec_fw_write_wait;
39b62541 ED	295	bool me_fw_write_wait;
589b64a7	296	bool cp_fw_write_wait;
448fe192 HR	297	struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
	298	unsigned num_gfx_rings;
	299	struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
	300	unsigned num_compute_rings;
	301	struct amdgpu_irq_src eop_irq;
	302	struct amdgpu_irq_src priv_reg_irq;
	303	struct amdgpu_irq_src priv_inst_irq;
	304	struct amdgpu_irq_src cp_ecc_error_irq;
	305	struct amdgpu_irq_src sq_irq;
	306	struct sq_work sq_work;
	307
	308	/* gfx status */
	309	uint32_t gfx_current_status;
	310	/* ce ram size*/
	311	unsigned ce_ram_size;
	312	struct amdgpu_cu_info cu_info;
	313	const struct amdgpu_gfx_funcs *funcs;
	314
	315	/* reset mask */
	316	uint32_t grbm_soft_reset;
	317	uint32_t srbm_soft_reset;
44779b43	318
448fe192 HR	319	/* gfx off */
	320	bool gfx_off_state; /* true: enabled, false: disabled */
	321	struct mutex gfx_off_mutex;
	322	uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
	323	struct delayed_work gfx_off_delay_work;
	324
	325	/* pipe reservation */
	326	struct mutex pipe_reserve_mutex;
	327	DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
760a1d55 FX	328
	329	/ras /
	330	struct ras_common_if *ras_if;
448fe192 HR	331	};
	332
	333	#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
	334	#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
0fa4246e	335	#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid))
d58fe3cf	336	#define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev))
b9683c21	337
378506a7 AD	338	/**
	339	* amdgpu_gfx_create_bitmask - create a bitmask
	340	*
	341	* @bit_width: length of the mask
	342	*
	343	* create a variable length bit mask.
	344	* Returns the bitmask.
	345	*/
	346	static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
	347	{
	348	return (u32)((1ULL << bit_width) - 1);
	349	}
	350
448fe192 HR	351	int amdgpu_gfx_scratch_get(struct amdgpu_device adev, uint32_t reg);
448fe192 HR	352	void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
2db0cdbe	353
448fe192 HR	354	void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
448fe192 HR	355	unsigned max_sh);
2db0cdbe	356
448fe192 HR	357	int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
	358	struct amdgpu_ring *ring,
	359	struct amdgpu_irq_src *irq);
2db0cdbe	360
9f0256da	361	void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring);
2db0cdbe	362
448fe192 HR	363	void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
	364	int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
	365	unsigned hpd_size);
	366
4fc6a88f HZ	367	int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev,
	368	unsigned mqd_size);
	369	void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev);
ba0c13b7	370	int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev);
849aca9f	371	int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev);
448fe192 HR	372
448fe192 HR	373	void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
e537c994 HZ	374	void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev);
e537c994 HZ	375
7470bfcf HZ	376	int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec,
7470bfcf HZ	377	int pipe, int queue);
5c180eb9	378	void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
7470bfcf	379	int mec, int pipe, int *queue);
448fe192 HR	380	bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
448fe192 HR	381	int pipe, int queue);
33abcb1f	382	bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
3f66bf40	383	int pipe, int queue);
7470bfcf HZ	384	int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me,
	385	int pipe, int queue);
	386	void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
	387	int me, int pipe, int *queue);
	388	bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
	389	int pipe, int queue);
c2d358d7	390	void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
443c7f3c	391	int amdgpu_get_gfx_off_status(struct amdgpu_device adev, uint32_t value);
41190cd7	392	int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
3b7b7647	393	void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
725253ab TZ	394	int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
	395	void *err_data,
	396	struct amdgpu_iv_entry *entry);
	397	int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
	398	struct amdgpu_irq_src *source,
	399	struct amdgpu_iv_entry *entry);
d33a99c4	400	uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg);
d33a99c4	401	void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
a3bab325	402	int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev);
d90a53d6	403	void amdgpu_gfx_state_change_set(struct amdgpu_device *adev, enum gfx_change_state state);
d38ceaf9	404	#endif