Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. | |
3 | * Copyright 2008 Red Hat Inc. | |
4 | * Copyright 2009 Jerome Glisse. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: Dave Airlie | |
25 | * Alex Deucher | |
26 | * Jerome Glisse | |
27 | */ | |
28 | #include <linux/ktime.h> | |
568d7c76 | 29 | #include <linux/pagemap.h> |
d38ceaf9 AD |
30 | #include <drm/drmP.h> |
31 | #include <drm/amdgpu_drm.h> | |
32 | #include "amdgpu.h" | |
bda31a24 | 33 | #include "amdgpu_display.h" |
d38ceaf9 AD |
34 | |
35 | void amdgpu_gem_object_free(struct drm_gem_object *gobj) | |
36 | { | |
37 | struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); | |
38 | ||
39 | if (robj) { | |
9298e52f | 40 | amdgpu_mn_unregister(robj); |
d38ceaf9 AD |
41 | amdgpu_bo_unref(&robj); |
42 | } | |
43 | } | |
44 | ||
45 | int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, | |
e1eb899b | 46 | int alignment, u32 initial_domain, |
eab3de23 | 47 | u64 flags, enum ttm_bo_type type, |
e1eb899b CK |
48 | struct reservation_object *resv, |
49 | struct drm_gem_object **obj) | |
d38ceaf9 | 50 | { |
e1eb899b | 51 | struct amdgpu_bo *bo; |
3216c6b7 | 52 | struct amdgpu_bo_param bp; |
d38ceaf9 AD |
53 | int r; |
54 | ||
3216c6b7 | 55 | memset(&bp, 0, sizeof(bp)); |
d38ceaf9 AD |
56 | *obj = NULL; |
57 | /* At least align on page size */ | |
58 | if (alignment < PAGE_SIZE) { | |
59 | alignment = PAGE_SIZE; | |
60 | } | |
61 | ||
3216c6b7 CZ |
62 | bp.size = size; |
63 | bp.byte_align = alignment; | |
64 | bp.type = type; | |
65 | bp.resv = resv; | |
aa2b2e28 | 66 | bp.preferred_domain = initial_domain; |
08082104 | 67 | retry: |
3216c6b7 CZ |
68 | bp.flags = flags; |
69 | bp.domain = initial_domain; | |
70 | r = amdgpu_bo_create(adev, &bp, &bo); | |
d38ceaf9 | 71 | if (r) { |
08082104 CK |
72 | if (r != -ERESTARTSYS) { |
73 | if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { | |
74 | flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; | |
75 | goto retry; | |
76 | } | |
77 | ||
78 | if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { | |
79 | initial_domain |= AMDGPU_GEM_DOMAIN_GTT; | |
80 | goto retry; | |
81 | } | |
82 | DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n", | |
83 | size, initial_domain, alignment, r); | |
84 | } | |
d38ceaf9 AD |
85 | return r; |
86 | } | |
e1eb899b | 87 | *obj = &bo->gem_base; |
d38ceaf9 | 88 | |
d38ceaf9 AD |
89 | return 0; |
90 | } | |
91 | ||
418aa0c2 | 92 | void amdgpu_gem_force_release(struct amdgpu_device *adev) |
d38ceaf9 | 93 | { |
418aa0c2 CK |
94 | struct drm_device *ddev = adev->ddev; |
95 | struct drm_file *file; | |
d38ceaf9 | 96 | |
1d2ac403 | 97 | mutex_lock(&ddev->filelist_mutex); |
418aa0c2 CK |
98 | |
99 | list_for_each_entry(file, &ddev->filelist, lhead) { | |
100 | struct drm_gem_object *gobj; | |
101 | int handle; | |
102 | ||
103 | WARN_ONCE(1, "Still active user space clients!\n"); | |
104 | spin_lock(&file->table_lock); | |
105 | idr_for_each_entry(&file->object_idr, gobj, handle) { | |
106 | WARN_ONCE(1, "And also active allocations!\n"); | |
f62facc2 | 107 | drm_gem_object_put_unlocked(gobj); |
418aa0c2 CK |
108 | } |
109 | idr_destroy(&file->object_idr); | |
110 | spin_unlock(&file->table_lock); | |
111 | } | |
112 | ||
1d2ac403 | 113 | mutex_unlock(&ddev->filelist_mutex); |
d38ceaf9 AD |
114 | } |
115 | ||
116 | /* | |
117 | * Call from drm_gem_handle_create which appear in both new and open ioctl | |
118 | * case. | |
119 | */ | |
a7d64de6 CK |
120 | int amdgpu_gem_object_open(struct drm_gem_object *obj, |
121 | struct drm_file *file_priv) | |
d38ceaf9 | 122 | { |
765e7fbf | 123 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 124 | struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); |
d38ceaf9 AD |
125 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
126 | struct amdgpu_vm *vm = &fpriv->vm; | |
127 | struct amdgpu_bo_va *bo_va; | |
4f5839c5 | 128 | struct mm_struct *mm; |
d38ceaf9 | 129 | int r; |
4f5839c5 CK |
130 | |
131 | mm = amdgpu_ttm_tt_get_usermm(abo->tbo.ttm); | |
132 | if (mm && mm != current->mm) | |
133 | return -EPERM; | |
134 | ||
e1eb899b CK |
135 | if (abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID && |
136 | abo->tbo.resv != vm->root.base.bo->tbo.resv) | |
137 | return -EPERM; | |
138 | ||
765e7fbf | 139 | r = amdgpu_bo_reserve(abo, false); |
e98c1b0d | 140 | if (r) |
d38ceaf9 | 141 | return r; |
d38ceaf9 | 142 | |
765e7fbf | 143 | bo_va = amdgpu_vm_bo_find(vm, abo); |
d38ceaf9 | 144 | if (!bo_va) { |
765e7fbf | 145 | bo_va = amdgpu_vm_bo_add(adev, vm, abo); |
d38ceaf9 AD |
146 | } else { |
147 | ++bo_va->ref_count; | |
148 | } | |
765e7fbf | 149 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
150 | return 0; |
151 | } | |
152 | ||
153 | void amdgpu_gem_object_close(struct drm_gem_object *obj, | |
154 | struct drm_file *file_priv) | |
155 | { | |
b5a5ec55 | 156 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); |
a7d64de6 | 157 | struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); |
d38ceaf9 AD |
158 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
159 | struct amdgpu_vm *vm = &fpriv->vm; | |
b5a5ec55 CK |
160 | |
161 | struct amdgpu_bo_list_entry vm_pd; | |
e1eb899b | 162 | struct list_head list, duplicates; |
b5a5ec55 CK |
163 | struct ttm_validate_buffer tv; |
164 | struct ww_acquire_ctx ticket; | |
d38ceaf9 AD |
165 | struct amdgpu_bo_va *bo_va; |
166 | int r; | |
b5a5ec55 CK |
167 | |
168 | INIT_LIST_HEAD(&list); | |
e1eb899b | 169 | INIT_LIST_HEAD(&duplicates); |
b5a5ec55 CK |
170 | |
171 | tv.bo = &bo->tbo; | |
172 | tv.shared = true; | |
173 | list_add(&tv.head, &list); | |
174 | ||
175 | amdgpu_vm_get_pd_bo(vm, &list, &vm_pd); | |
176 | ||
e1eb899b | 177 | r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); |
d38ceaf9 AD |
178 | if (r) { |
179 | dev_err(adev->dev, "leaking bo va because " | |
180 | "we fail to reserve bo (%d)\n", r); | |
181 | return; | |
182 | } | |
b5a5ec55 | 183 | bo_va = amdgpu_vm_bo_find(vm, bo); |
5a0f3b5f CK |
184 | if (bo_va && --bo_va->ref_count == 0) { |
185 | amdgpu_vm_bo_rmv(adev, bo_va); | |
186 | ||
3f3333f8 | 187 | if (amdgpu_vm_ready(vm)) { |
5a0f3b5f | 188 | struct dma_fence *fence = NULL; |
23e0563e NH |
189 | |
190 | r = amdgpu_vm_clear_freed(adev, vm, &fence); | |
191 | if (unlikely(r)) { | |
192 | dev_err(adev->dev, "failed to clear page " | |
193 | "tables on GEM object close (%d)\n", r); | |
194 | } | |
195 | ||
196 | if (fence) { | |
197 | amdgpu_bo_fence(bo, fence, true); | |
198 | dma_fence_put(fence); | |
199 | } | |
d38ceaf9 AD |
200 | } |
201 | } | |
b5a5ec55 | 202 | ttm_eu_backoff_reservation(&ticket, &list); |
d38ceaf9 AD |
203 | } |
204 | ||
d38ceaf9 AD |
205 | /* |
206 | * GEM ioctls. | |
207 | */ | |
208 | int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, | |
209 | struct drm_file *filp) | |
210 | { | |
211 | struct amdgpu_device *adev = dev->dev_private; | |
e1eb899b CK |
212 | struct amdgpu_fpriv *fpriv = filp->driver_priv; |
213 | struct amdgpu_vm *vm = &fpriv->vm; | |
d38ceaf9 | 214 | union drm_amdgpu_gem_create *args = data; |
6ac7defb | 215 | uint64_t flags = args->in.domain_flags; |
d38ceaf9 | 216 | uint64_t size = args->in.bo_size; |
e1eb899b | 217 | struct reservation_object *resv = NULL; |
d38ceaf9 AD |
218 | struct drm_gem_object *gobj; |
219 | uint32_t handle; | |
d38ceaf9 AD |
220 | int r; |
221 | ||
834e0f8a | 222 | /* reject invalid gem flags */ |
6ac7defb CK |
223 | if (flags & ~(AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
224 | AMDGPU_GEM_CREATE_NO_CPU_ACCESS | | |
225 | AMDGPU_GEM_CREATE_CPU_GTT_USWC | | |
e1eb899b | 226 | AMDGPU_GEM_CREATE_VRAM_CLEARED | |
177ae09b AR |
227 | AMDGPU_GEM_CREATE_VM_ALWAYS_VALID | |
228 | AMDGPU_GEM_CREATE_EXPLICIT_SYNC)) | |
229 | ||
a022c54e CK |
230 | return -EINVAL; |
231 | ||
834e0f8a | 232 | /* reject invalid gem domains */ |
3f188453 | 233 | if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK) |
a022c54e | 234 | return -EINVAL; |
834e0f8a | 235 | |
d38ceaf9 AD |
236 | /* create a gem object to contain this object in */ |
237 | if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | | |
238 | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { | |
ee5309d5 CZ |
239 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
240 | /* if gds bo is created from user space, it must be | |
241 | * passed to bo list | |
242 | */ | |
243 | DRM_ERROR("GDS bo cannot be per-vm-bo\n"); | |
244 | return -EINVAL; | |
245 | } | |
6ac7defb | 246 | flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; |
d38ceaf9 AD |
247 | if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) |
248 | size = size << AMDGPU_GDS_SHIFT; | |
249 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) | |
250 | size = size << AMDGPU_GWS_SHIFT; | |
251 | else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) | |
252 | size = size << AMDGPU_OA_SHIFT; | |
a022c54e CK |
253 | else |
254 | return -EINVAL; | |
d38ceaf9 AD |
255 | } |
256 | size = roundup(size, PAGE_SIZE); | |
257 | ||
e1eb899b CK |
258 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { |
259 | r = amdgpu_bo_reserve(vm->root.base.bo, false); | |
260 | if (r) | |
261 | return r; | |
262 | ||
263 | resv = vm->root.base.bo->tbo.resv; | |
264 | } | |
265 | ||
d38ceaf9 AD |
266 | r = amdgpu_gem_object_create(adev, size, args->in.alignment, |
267 | (u32)(0xffffffff & args->in.domains), | |
e1eb899b CK |
268 | flags, false, resv, &gobj); |
269 | if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { | |
270 | if (!r) { | |
271 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); | |
272 | ||
273 | abo->parent = amdgpu_bo_ref(vm->root.base.bo); | |
274 | } | |
275 | amdgpu_bo_unreserve(vm->root.base.bo); | |
276 | } | |
d38ceaf9 | 277 | if (r) |
a022c54e | 278 | return r; |
d38ceaf9 AD |
279 | |
280 | r = drm_gem_handle_create(filp, gobj, &handle); | |
281 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 282 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 283 | if (r) |
a022c54e | 284 | return r; |
d38ceaf9 AD |
285 | |
286 | memset(args, 0, sizeof(*args)); | |
287 | args->out.handle = handle; | |
d38ceaf9 | 288 | return 0; |
d38ceaf9 AD |
289 | } |
290 | ||
291 | int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
292 | struct drm_file *filp) | |
293 | { | |
19be5570 | 294 | struct ttm_operation_ctx ctx = { true, false }; |
d38ceaf9 AD |
295 | struct amdgpu_device *adev = dev->dev_private; |
296 | struct drm_amdgpu_gem_userptr *args = data; | |
297 | struct drm_gem_object *gobj; | |
298 | struct amdgpu_bo *bo; | |
299 | uint32_t handle; | |
300 | int r; | |
301 | ||
302 | if (offset_in_page(args->addr | args->size)) | |
303 | return -EINVAL; | |
304 | ||
305 | /* reject unknown flag values */ | |
306 | if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | | |
307 | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | | |
308 | AMDGPU_GEM_USERPTR_REGISTER)) | |
309 | return -EINVAL; | |
310 | ||
358c258a CK |
311 | if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && |
312 | !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) { | |
d38ceaf9 | 313 | |
358c258a | 314 | /* if we want to write to it we must install a MMU notifier */ |
d38ceaf9 AD |
315 | return -EACCES; |
316 | } | |
317 | ||
d38ceaf9 | 318 | /* create a gem object to contain this object in */ |
e1eb899b CK |
319 | r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, |
320 | 0, 0, NULL, &gobj); | |
d38ceaf9 | 321 | if (r) |
a022c54e | 322 | return r; |
d38ceaf9 AD |
323 | |
324 | bo = gem_to_amdgpu_bo(gobj); | |
6d7d9c5a | 325 | bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; |
1ea863fd | 326 | bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; |
d38ceaf9 AD |
327 | r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); |
328 | if (r) | |
329 | goto release_object; | |
330 | ||
331 | if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { | |
332 | r = amdgpu_mn_register(bo, args->addr); | |
333 | if (r) | |
334 | goto release_object; | |
335 | } | |
336 | ||
337 | if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { | |
2f568dbd CK |
338 | r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, |
339 | bo->tbo.ttm->pages); | |
340 | if (r) | |
d5a480b4 | 341 | goto release_object; |
2f568dbd | 342 | |
d38ceaf9 | 343 | r = amdgpu_bo_reserve(bo, true); |
2f568dbd CK |
344 | if (r) |
345 | goto free_pages; | |
d38ceaf9 AD |
346 | |
347 | amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); | |
19be5570 | 348 | r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); |
d38ceaf9 | 349 | amdgpu_bo_unreserve(bo); |
d38ceaf9 | 350 | if (r) |
2f568dbd | 351 | goto free_pages; |
d38ceaf9 AD |
352 | } |
353 | ||
354 | r = drm_gem_handle_create(filp, gobj, &handle); | |
355 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 356 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 357 | if (r) |
a022c54e | 358 | return r; |
d38ceaf9 AD |
359 | |
360 | args->handle = handle; | |
d38ceaf9 AD |
361 | return 0; |
362 | ||
2f568dbd | 363 | free_pages: |
c6f92f9f | 364 | release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); |
2f568dbd | 365 | |
d38ceaf9 | 366 | release_object: |
f62facc2 | 367 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 | 368 | |
d38ceaf9 AD |
369 | return r; |
370 | } | |
371 | ||
372 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | |
373 | struct drm_device *dev, | |
374 | uint32_t handle, uint64_t *offset_p) | |
375 | { | |
376 | struct drm_gem_object *gobj; | |
377 | struct amdgpu_bo *robj; | |
378 | ||
a8ad0bd8 | 379 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
380 | if (gobj == NULL) { |
381 | return -ENOENT; | |
382 | } | |
383 | robj = gem_to_amdgpu_bo(gobj); | |
cc325d19 | 384 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm) || |
271c8125 | 385 | (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { |
f62facc2 | 386 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
387 | return -EPERM; |
388 | } | |
389 | *offset_p = amdgpu_bo_mmap_offset(robj); | |
f62facc2 | 390 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
391 | return 0; |
392 | } | |
393 | ||
394 | int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
395 | struct drm_file *filp) | |
396 | { | |
397 | union drm_amdgpu_gem_mmap *args = data; | |
398 | uint32_t handle = args->in.handle; | |
399 | memset(args, 0, sizeof(*args)); | |
400 | return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); | |
401 | } | |
402 | ||
403 | /** | |
404 | * amdgpu_gem_timeout - calculate jiffies timeout from absolute value | |
405 | * | |
406 | * @timeout_ns: timeout in ns | |
407 | * | |
408 | * Calculate the timeout in jiffies from an absolute timeout in ns. | |
409 | */ | |
410 | unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) | |
411 | { | |
412 | unsigned long timeout_jiffies; | |
413 | ktime_t timeout; | |
414 | ||
415 | /* clamp timeout if it's to large */ | |
416 | if (((int64_t)timeout_ns) < 0) | |
417 | return MAX_SCHEDULE_TIMEOUT; | |
418 | ||
0f117704 | 419 | timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); |
d38ceaf9 AD |
420 | if (ktime_to_ns(timeout) < 0) |
421 | return 0; | |
422 | ||
423 | timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); | |
424 | /* clamp timeout to avoid unsigned-> signed overflow */ | |
425 | if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) | |
426 | return MAX_SCHEDULE_TIMEOUT - 1; | |
427 | ||
428 | return timeout_jiffies; | |
429 | } | |
430 | ||
431 | int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, | |
432 | struct drm_file *filp) | |
433 | { | |
d38ceaf9 AD |
434 | union drm_amdgpu_gem_wait_idle *args = data; |
435 | struct drm_gem_object *gobj; | |
436 | struct amdgpu_bo *robj; | |
437 | uint32_t handle = args->in.handle; | |
438 | unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); | |
439 | int r = 0; | |
440 | long ret; | |
441 | ||
a8ad0bd8 | 442 | gobj = drm_gem_object_lookup(filp, handle); |
d38ceaf9 AD |
443 | if (gobj == NULL) { |
444 | return -ENOENT; | |
445 | } | |
446 | robj = gem_to_amdgpu_bo(gobj); | |
0fea2ed6 CW |
447 | ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, |
448 | timeout); | |
d38ceaf9 AD |
449 | |
450 | /* ret == 0 means not signaled, | |
451 | * ret > 0 means signaled | |
452 | * ret < 0 means interrupted before timeout | |
453 | */ | |
454 | if (ret >= 0) { | |
455 | memset(args, 0, sizeof(*args)); | |
456 | args->out.status = (ret == 0); | |
457 | } else | |
458 | r = ret; | |
459 | ||
f62facc2 | 460 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
461 | return r; |
462 | } | |
463 | ||
464 | int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, | |
465 | struct drm_file *filp) | |
466 | { | |
467 | struct drm_amdgpu_gem_metadata *args = data; | |
468 | struct drm_gem_object *gobj; | |
469 | struct amdgpu_bo *robj; | |
470 | int r = -1; | |
471 | ||
472 | DRM_DEBUG("%d \n", args->handle); | |
a8ad0bd8 | 473 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
474 | if (gobj == NULL) |
475 | return -ENOENT; | |
476 | robj = gem_to_amdgpu_bo(gobj); | |
477 | ||
478 | r = amdgpu_bo_reserve(robj, false); | |
479 | if (unlikely(r != 0)) | |
480 | goto out; | |
481 | ||
482 | if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { | |
483 | amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); | |
484 | r = amdgpu_bo_get_metadata(robj, args->data.data, | |
485 | sizeof(args->data.data), | |
486 | &args->data.data_size_bytes, | |
487 | &args->data.flags); | |
488 | } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { | |
0913eab6 DC |
489 | if (args->data.data_size_bytes > sizeof(args->data.data)) { |
490 | r = -EINVAL; | |
491 | goto unreserve; | |
492 | } | |
d38ceaf9 AD |
493 | r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); |
494 | if (!r) | |
495 | r = amdgpu_bo_set_metadata(robj, args->data.data, | |
496 | args->data.data_size_bytes, | |
497 | args->data.flags); | |
498 | } | |
499 | ||
0913eab6 | 500 | unreserve: |
d38ceaf9 AD |
501 | amdgpu_bo_unreserve(robj); |
502 | out: | |
f62facc2 | 503 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
504 | return r; |
505 | } | |
506 | ||
507 | /** | |
508 | * amdgpu_gem_va_update_vm -update the bo_va in its VM | |
509 | * | |
510 | * @adev: amdgpu_device pointer | |
dc54d3d1 | 511 | * @vm: vm to update |
d38ceaf9 | 512 | * @bo_va: bo_va to update |
dc54d3d1 | 513 | * @operation: map, unmap or clear |
d38ceaf9 | 514 | * |
2ffdaafb | 515 | * Update the bo_va directly after setting its address. Errors are not |
d38ceaf9 AD |
516 | * vital here, so they are not reported back to userspace. |
517 | */ | |
518 | static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, | |
dc54d3d1 | 519 | struct amdgpu_vm *vm, |
f7da30d9 CK |
520 | struct amdgpu_bo_va *bo_va, |
521 | uint32_t operation) | |
d38ceaf9 | 522 | { |
3f3333f8 | 523 | int r; |
d38ceaf9 | 524 | |
3f3333f8 CK |
525 | if (!amdgpu_vm_ready(vm)) |
526 | return; | |
e410b5cb | 527 | |
f3467818 | 528 | r = amdgpu_vm_clear_freed(adev, vm, NULL); |
d38ceaf9 | 529 | if (r) |
2ffdaafb | 530 | goto error; |
194a3364 | 531 | |
80f95c57 | 532 | if (operation == AMDGPU_VA_OP_MAP || |
93bab704 | 533 | operation == AMDGPU_VA_OP_REPLACE) { |
05dcb5c8 | 534 | r = amdgpu_vm_bo_update(adev, bo_va, false); |
93bab704 GS |
535 | if (r) |
536 | goto error; | |
537 | } | |
d38ceaf9 | 538 | |
0abc6878 | 539 | r = amdgpu_vm_update_directories(adev, vm); |
0abc6878 | 540 | |
2ffdaafb | 541 | error: |
68fdd3df | 542 | if (r && r != -ERESTARTSYS) |
d38ceaf9 AD |
543 | DRM_ERROR("Couldn't update BO_VA (%d)\n", r); |
544 | } | |
545 | ||
d38ceaf9 AD |
546 | int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, |
547 | struct drm_file *filp) | |
548 | { | |
b85891bd JZ |
549 | const uint32_t valid_flags = AMDGPU_VM_DELAY_UPDATE | |
550 | AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | | |
66e02bc3 | 551 | AMDGPU_VM_PAGE_EXECUTABLE | AMDGPU_VM_MTYPE_MASK; |
b85891bd JZ |
552 | const uint32_t prt_flags = AMDGPU_VM_DELAY_UPDATE | |
553 | AMDGPU_VM_PAGE_PRT; | |
554 | ||
34b5f6a6 | 555 | struct drm_amdgpu_gem_va *args = data; |
d38ceaf9 AD |
556 | struct drm_gem_object *gobj; |
557 | struct amdgpu_device *adev = dev->dev_private; | |
558 | struct amdgpu_fpriv *fpriv = filp->driver_priv; | |
765e7fbf | 559 | struct amdgpu_bo *abo; |
d38ceaf9 | 560 | struct amdgpu_bo_va *bo_va; |
b88c8796 CK |
561 | struct amdgpu_bo_list_entry vm_pd; |
562 | struct ttm_validate_buffer tv; | |
49b02b18 | 563 | struct ww_acquire_ctx ticket; |
e1eb899b | 564 | struct list_head list, duplicates; |
5463545b | 565 | uint64_t va_flags; |
d38ceaf9 AD |
566 | int r = 0; |
567 | ||
34b5f6a6 | 568 | if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { |
4b7f0848 | 569 | dev_dbg(&dev->pdev->dev, |
ff4cd389 CK |
570 | "va_address 0x%LX is in reserved area 0x%LX\n", |
571 | args->va_address, AMDGPU_VA_RESERVED_SIZE); | |
d38ceaf9 AD |
572 | return -EINVAL; |
573 | } | |
574 | ||
bb7939b2 CK |
575 | if (args->va_address >= AMDGPU_VA_HOLE_START && |
576 | args->va_address < AMDGPU_VA_HOLE_END) { | |
577 | dev_dbg(&dev->pdev->dev, | |
578 | "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n", | |
579 | args->va_address, AMDGPU_VA_HOLE_START, | |
580 | AMDGPU_VA_HOLE_END); | |
581 | return -EINVAL; | |
582 | } | |
583 | ||
584 | args->va_address &= AMDGPU_VA_HOLE_MASK; | |
585 | ||
b85891bd | 586 | if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) { |
4b7f0848 | 587 | dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n", |
b85891bd | 588 | args->flags); |
d38ceaf9 AD |
589 | return -EINVAL; |
590 | } | |
591 | ||
34b5f6a6 | 592 | switch (args->operation) { |
d38ceaf9 AD |
593 | case AMDGPU_VA_OP_MAP: |
594 | case AMDGPU_VA_OP_UNMAP: | |
dc54d3d1 | 595 | case AMDGPU_VA_OP_CLEAR: |
80f95c57 | 596 | case AMDGPU_VA_OP_REPLACE: |
d38ceaf9 AD |
597 | break; |
598 | default: | |
4b7f0848 | 599 | dev_dbg(&dev->pdev->dev, "unsupported operation %d\n", |
34b5f6a6 | 600 | args->operation); |
d38ceaf9 AD |
601 | return -EINVAL; |
602 | } | |
603 | ||
49b02b18 | 604 | INIT_LIST_HEAD(&list); |
e1eb899b | 605 | INIT_LIST_HEAD(&duplicates); |
dc54d3d1 CK |
606 | if ((args->operation != AMDGPU_VA_OP_CLEAR) && |
607 | !(args->flags & AMDGPU_VM_PAGE_PRT)) { | |
b85891bd JZ |
608 | gobj = drm_gem_object_lookup(filp, args->handle); |
609 | if (gobj == NULL) | |
610 | return -ENOENT; | |
611 | abo = gem_to_amdgpu_bo(gobj); | |
612 | tv.bo = &abo->tbo; | |
b1dc9d87 | 613 | tv.shared = !!(abo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID); |
b85891bd JZ |
614 | list_add(&tv.head, &list); |
615 | } else { | |
616 | gobj = NULL; | |
617 | abo = NULL; | |
618 | } | |
49b02b18 | 619 | |
b88c8796 | 620 | amdgpu_vm_get_pd_bo(&fpriv->vm, &list, &vm_pd); |
b5a5ec55 | 621 | |
e1eb899b | 622 | r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); |
b85891bd JZ |
623 | if (r) |
624 | goto error_unref; | |
34b5f6a6 | 625 | |
b85891bd JZ |
626 | if (abo) { |
627 | bo_va = amdgpu_vm_bo_find(&fpriv->vm, abo); | |
628 | if (!bo_va) { | |
629 | r = -ENOENT; | |
630 | goto error_backoff; | |
631 | } | |
dc54d3d1 | 632 | } else if (args->operation != AMDGPU_VA_OP_CLEAR) { |
b85891bd | 633 | bo_va = fpriv->prt_va; |
dc54d3d1 CK |
634 | } else { |
635 | bo_va = NULL; | |
d38ceaf9 AD |
636 | } |
637 | ||
34b5f6a6 | 638 | switch (args->operation) { |
d38ceaf9 | 639 | case AMDGPU_VA_OP_MAP: |
ec681545 | 640 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
663e4577 CK |
641 | args->map_size); |
642 | if (r) | |
643 | goto error_backoff; | |
5463545b | 644 | |
132f34e4 | 645 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
34b5f6a6 CK |
646 | r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, |
647 | args->offset_in_bo, args->map_size, | |
9f7eb536 | 648 | va_flags); |
d38ceaf9 AD |
649 | break; |
650 | case AMDGPU_VA_OP_UNMAP: | |
34b5f6a6 | 651 | r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); |
d38ceaf9 | 652 | break; |
dc54d3d1 CK |
653 | |
654 | case AMDGPU_VA_OP_CLEAR: | |
655 | r = amdgpu_vm_bo_clear_mappings(adev, &fpriv->vm, | |
656 | args->va_address, | |
657 | args->map_size); | |
658 | break; | |
80f95c57 | 659 | case AMDGPU_VA_OP_REPLACE: |
ec681545 | 660 | r = amdgpu_vm_alloc_pts(adev, bo_va->base.vm, args->va_address, |
80f95c57 CK |
661 | args->map_size); |
662 | if (r) | |
663 | goto error_backoff; | |
664 | ||
132f34e4 | 665 | va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); |
80f95c57 CK |
666 | r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, |
667 | args->offset_in_bo, args->map_size, | |
668 | va_flags); | |
669 | break; | |
d38ceaf9 AD |
670 | default: |
671 | break; | |
672 | } | |
b85891bd | 673 | if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !amdgpu_vm_debug) |
59d61be2 | 674 | amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, |
dc54d3d1 | 675 | args->operation); |
b85891bd JZ |
676 | |
677 | error_backoff: | |
2ffdaafb | 678 | ttm_eu_backoff_reservation(&ticket, &list); |
e98c1b0d | 679 | |
b85891bd | 680 | error_unref: |
f62facc2 | 681 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
682 | return r; |
683 | } | |
684 | ||
685 | int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, | |
686 | struct drm_file *filp) | |
687 | { | |
e1eb899b | 688 | struct amdgpu_device *adev = dev->dev_private; |
d38ceaf9 AD |
689 | struct drm_amdgpu_gem_op *args = data; |
690 | struct drm_gem_object *gobj; | |
691 | struct amdgpu_bo *robj; | |
692 | int r; | |
693 | ||
a8ad0bd8 | 694 | gobj = drm_gem_object_lookup(filp, args->handle); |
d38ceaf9 AD |
695 | if (gobj == NULL) { |
696 | return -ENOENT; | |
697 | } | |
698 | robj = gem_to_amdgpu_bo(gobj); | |
699 | ||
700 | r = amdgpu_bo_reserve(robj, false); | |
701 | if (unlikely(r)) | |
702 | goto out; | |
703 | ||
704 | switch (args->op) { | |
705 | case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { | |
706 | struct drm_amdgpu_gem_create_in info; | |
7ecc245a | 707 | void __user *out = u64_to_user_ptr(args->value); |
d38ceaf9 AD |
708 | |
709 | info.bo_size = robj->gem_base.size; | |
710 | info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; | |
6d7d9c5a | 711 | info.domains = robj->preferred_domains; |
d38ceaf9 | 712 | info.domain_flags = robj->flags; |
4c28fb0b | 713 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
714 | if (copy_to_user(out, &info, sizeof(info))) |
715 | r = -EFAULT; | |
716 | break; | |
717 | } | |
d8f65a23 | 718 | case AMDGPU_GEM_OP_SET_PLACEMENT: |
803d89ad CJHR |
719 | if (robj->prime_shared_count && (args->value & AMDGPU_GEM_DOMAIN_VRAM)) { |
720 | r = -EINVAL; | |
721 | amdgpu_bo_unreserve(robj); | |
722 | break; | |
723 | } | |
cc325d19 | 724 | if (amdgpu_ttm_tt_get_usermm(robj->tbo.ttm)) { |
d38ceaf9 | 725 | r = -EPERM; |
4c28fb0b | 726 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
727 | break; |
728 | } | |
6d7d9c5a | 729 | robj->preferred_domains = args->value & (AMDGPU_GEM_DOMAIN_VRAM | |
1ea863fd CK |
730 | AMDGPU_GEM_DOMAIN_GTT | |
731 | AMDGPU_GEM_DOMAIN_CPU); | |
6d7d9c5a | 732 | robj->allowed_domains = robj->preferred_domains; |
1ea863fd CK |
733 | if (robj->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) |
734 | robj->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; | |
735 | ||
e1eb899b CK |
736 | if (robj->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) |
737 | amdgpu_vm_bo_invalidate(adev, robj, true); | |
738 | ||
4c28fb0b | 739 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
740 | break; |
741 | default: | |
4c28fb0b | 742 | amdgpu_bo_unreserve(robj); |
d38ceaf9 AD |
743 | r = -EINVAL; |
744 | } | |
745 | ||
d38ceaf9 | 746 | out: |
f62facc2 | 747 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
748 | return r; |
749 | } | |
750 | ||
751 | int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |
752 | struct drm_device *dev, | |
753 | struct drm_mode_create_dumb *args) | |
754 | { | |
755 | struct amdgpu_device *adev = dev->dev_private; | |
756 | struct drm_gem_object *gobj; | |
757 | uint32_t handle; | |
84b74608 | 758 | u32 domain; |
d38ceaf9 AD |
759 | int r; |
760 | ||
8e911ab7 LP |
761 | args->pitch = amdgpu_align_pitch(adev, args->width, |
762 | DIV_ROUND_UP(args->bpp, 8), 0); | |
54ef0b54 | 763 | args->size = (u64)args->pitch * args->height; |
d38ceaf9 | 764 | args->size = ALIGN(args->size, PAGE_SIZE); |
84b74608 DS |
765 | domain = amdgpu_bo_get_preferred_pin_domain(adev, |
766 | amdgpu_display_supported_domains(adev)); | |
bda31a24 | 767 | r = amdgpu_gem_object_create(adev, args->size, 0, domain, |
857d913d | 768 | AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, |
e1eb899b | 769 | false, NULL, &gobj); |
d38ceaf9 AD |
770 | if (r) |
771 | return -ENOMEM; | |
772 | ||
773 | r = drm_gem_handle_create(file_priv, gobj, &handle); | |
774 | /* drop reference from allocate - handle holds it now */ | |
f62facc2 | 775 | drm_gem_object_put_unlocked(gobj); |
d38ceaf9 AD |
776 | if (r) { |
777 | return r; | |
778 | } | |
779 | args->handle = handle; | |
780 | return 0; | |
781 | } | |
782 | ||
783 | #if defined(CONFIG_DEBUG_FS) | |
6b155d6a CK |
784 | |
785 | #define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag) \ | |
786 | if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ | |
787 | seq_printf((m), " " #flag); \ | |
788 | } | |
789 | ||
7ea23565 CK |
790 | static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data) |
791 | { | |
792 | struct drm_gem_object *gobj = ptr; | |
793 | struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); | |
794 | struct seq_file *m = data; | |
795 | ||
b1f223c0 CK |
796 | struct dma_buf_attachment *attachment; |
797 | struct dma_buf *dma_buf; | |
7ea23565 CK |
798 | unsigned domain; |
799 | const char *placement; | |
800 | unsigned pin_count; | |
801 | ||
802 | domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); | |
803 | switch (domain) { | |
804 | case AMDGPU_GEM_DOMAIN_VRAM: | |
805 | placement = "VRAM"; | |
806 | break; | |
807 | case AMDGPU_GEM_DOMAIN_GTT: | |
808 | placement = " GTT"; | |
809 | break; | |
810 | case AMDGPU_GEM_DOMAIN_CPU: | |
811 | default: | |
812 | placement = " CPU"; | |
813 | break; | |
814 | } | |
b8e0e6e1 CK |
815 | seq_printf(m, "\t0x%08x: %12ld byte %s", |
816 | id, amdgpu_bo_size(bo), placement); | |
817 | ||
6aa7de05 | 818 | pin_count = READ_ONCE(bo->pin_count); |
7ea23565 CK |
819 | if (pin_count) |
820 | seq_printf(m, " pin count %d", pin_count); | |
b1f223c0 CK |
821 | |
822 | dma_buf = READ_ONCE(bo->gem_base.dma_buf); | |
823 | attachment = READ_ONCE(bo->gem_base.import_attach); | |
824 | ||
825 | if (attachment) | |
826 | seq_printf(m, " imported from %p", dma_buf); | |
827 | else if (dma_buf) | |
828 | seq_printf(m, " exported as %p", dma_buf); | |
829 | ||
6b155d6a CK |
830 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); |
831 | amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS); | |
832 | amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC); | |
833 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED); | |
834 | amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW); | |
835 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS); | |
836 | amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID); | |
837 | amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC); | |
838 | ||
7ea23565 CK |
839 | seq_printf(m, "\n"); |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
d38ceaf9 AD |
844 | static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) |
845 | { | |
846 | struct drm_info_node *node = (struct drm_info_node *)m->private; | |
847 | struct drm_device *dev = node->minor->dev; | |
7ea23565 CK |
848 | struct drm_file *file; |
849 | int r; | |
d38ceaf9 | 850 | |
1d2ac403 | 851 | r = mutex_lock_interruptible(&dev->filelist_mutex); |
7ea23565 CK |
852 | if (r) |
853 | return r; | |
854 | ||
855 | list_for_each_entry(file, &dev->filelist, lhead) { | |
856 | struct task_struct *task; | |
857 | ||
858 | /* | |
859 | * Although we have a valid reference on file->pid, that does | |
860 | * not guarantee that the task_struct who called get_pid() is | |
861 | * still alive (e.g. get_pid(current) => fork() => exit()). | |
862 | * Therefore, we need to protect this ->comm access using RCU. | |
863 | */ | |
864 | rcu_read_lock(); | |
865 | task = pid_task(file->pid, PIDTYPE_PID); | |
866 | seq_printf(m, "pid %8d command %s:\n", pid_nr(file->pid), | |
867 | task ? task->comm : "<unknown>"); | |
868 | rcu_read_unlock(); | |
869 | ||
870 | spin_lock(&file->table_lock); | |
871 | idr_for_each(&file->object_idr, amdgpu_debugfs_gem_bo_info, m); | |
872 | spin_unlock(&file->table_lock); | |
d38ceaf9 | 873 | } |
7ea23565 | 874 | |
1d2ac403 | 875 | mutex_unlock(&dev->filelist_mutex); |
d38ceaf9 AD |
876 | return 0; |
877 | } | |
878 | ||
06ab6832 | 879 | static const struct drm_info_list amdgpu_debugfs_gem_list[] = { |
d38ceaf9 AD |
880 | {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, |
881 | }; | |
882 | #endif | |
883 | ||
75758255 | 884 | int amdgpu_debugfs_gem_init(struct amdgpu_device *adev) |
d38ceaf9 AD |
885 | { |
886 | #if defined(CONFIG_DEBUG_FS) | |
887 | return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); | |
888 | #endif | |
889 | return 0; | |
890 | } |