[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"
#include "amdgpu_reset.h"
#include <drm/drm_drv.h>
#include <drm/ttm/ttm_tt.h>

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */

/**
 * amdgpu_gart_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
	struct page *dummy_page = ttm_glob.dummy_read_page;

	if (adev->dummy_page_addr)
		return 0;
	adev->dummy_page_addr = dma_map_page_attrs(&adev->pdev->dev, dummy_page, 0,
							PAGE_SIZE, DMA_BIDIRECTIONAL,
							DMA_ATTR_SKIP_CPU_SYNC);
	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		adev->dummy_page_addr = 0;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
	if (!adev->dummy_page_addr)
		return;
	dma_unmap_page_attrs(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
				DMA_BIDIRECTIONAL,
				DMA_ATTR_SKIP_CPU_SYNC);
	adev->dummy_page_addr = 0;
}

/**
 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate system memory for GART page table for ASICs that don't have
 * dedicated VRAM.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
{
	unsigned int order = get_order(adev->gart.table_size);
	gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
	struct amdgpu_bo *bo = NULL;
	struct sg_table *sg = NULL;
	struct amdgpu_bo_param bp;
	dma_addr_t dma_addr;
	struct page *p;
	unsigned long x;
	int ret;

	if (adev->gart.bo != NULL)
		return 0;

	p = alloc_pages(gfp_flags, order);
	if (!p)
		return -ENOMEM;

	/* assign pages to this device */
	for (x = 0; x < (1UL << order); x++)
		p[x].mapping = adev->mman.bdev.dev_mapping;

	/* If the hardware does not support UTCL2 snooping of the CPU caches
	 * then set_memory_wc() could be used as a workaround to mark the pages
	 * as write combine memory.
	 */
	dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size,
				DMA_BIDIRECTIONAL);
	if (dma_mapping_error(&adev->pdev->dev, dma_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the GART BO page\n");
		__free_pages(p, order);
		p = NULL;
		return -EFAULT;
	}

	dev_info(adev->dev, "%s dma_addr:%pad\n", __func__, &dma_addr);
	/* Create SG table */
	sg = kmalloc(sizeof(*sg), GFP_KERNEL);
	if (!sg) {
		ret = -ENOMEM;
		goto error;
	}
	ret = sg_alloc_table(sg, 1, GFP_KERNEL);
	if (ret)
		goto error;

	sg_dma_address(sg->sgl) = dma_addr;
	sg->sgl->length = adev->gart.table_size;
#ifdef CONFIG_NEED_SG_DMA_LENGTH
	sg->sgl->dma_length = adev->gart.table_size;
#endif
	/* Create SG BO */
	memset(&bp, 0, sizeof(bp));
	bp.size = adev->gart.table_size;
	bp.byte_align = PAGE_SIZE;
	bp.domain = AMDGPU_GEM_DOMAIN_CPU;
	bp.type = ttm_bo_type_sg;
	bp.resv = NULL;
	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
	bp.flags = 0;
	ret = amdgpu_bo_create(adev, &bp, &bo);
	if (ret)
		goto error;

	bo->tbo.sg = sg;
	bo->tbo.ttm->sg = sg;
	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;

	ret = amdgpu_bo_reserve(bo, true);
	if (ret) {
		dev_err(adev->dev, "(%d) failed to reserve bo for GART system bo\n", ret);
		goto error;
	}

	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
	WARN(ret, "Pinning the GART table failed");
	if (ret)
		goto error_resv;

	adev->gart.bo = bo;
	adev->gart.ptr = page_to_virt(p);
	/* Make GART table accessible in VMID0 */
	ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo);
	if (ret)
		amdgpu_gart_table_ram_free(adev);
	amdgpu_bo_unreserve(bo);

	return 0;

error_resv:
	amdgpu_bo_unreserve(bo);
error:
	amdgpu_bo_unref(&bo);
	if (sg) {
		sg_free_table(sg);
		kfree(sg);
	}
	__free_pages(p, order);
	return ret;
}

/**
 * amdgpu_gart_table_ram_free - free gart page table system ram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the system memory used for the GART page tableon ASICs that don't
 * have dedicated VRAM.
 */
void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
{
	unsigned int order = get_order(adev->gart.table_size);
	struct sg_table *sg = adev->gart.bo->tbo.sg;
	struct page *p;
	unsigned long x;
	int ret;

	ret = amdgpu_bo_reserve(adev->gart.bo, false);
	if (!ret) {
		amdgpu_bo_unpin(adev->gart.bo);
		amdgpu_bo_unreserve(adev->gart.bo);
	}
	amdgpu_bo_unref(&adev->gart.bo);
	sg_free_table(sg);
	kfree(sg);
	p = virt_to_page(adev->gart.ptr);
	for (x = 0; x < (1UL << order); x++)
		p[x].mapping = NULL;
	__free_pages(p, order);

	adev->gart.ptr = NULL;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	if (adev->gart.bo != NULL)
		return 0;

	return amdgpu_bo_create_kernel(adev,  adev->gart.table_size, PAGE_SIZE,
				       AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo,
				       NULL, (void *)&adev->gart.ptr);
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr);
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;
	int idx;

	if (!adev->gart.ptr)
		return;

	if (!drm_dev_enter(adev_to_drm(adev), &idx))
		return;

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++) {
		page_base = adev->dummy_page_addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
					       t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	amdgpu_gart_invalidate_tlb(adev);

	drm_dev_exit(idx);
}

/**
 * amdgpu_gart_map - map dma_addresses into GART entries
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 * @dst: CPU address of the gart table
 *
 * Map the dma_addresses into GART entries (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
		    int pages, dma_addr_t *dma_addr, uint64_t flags,
		    void *dst)
{
	uint64_t page_base;
	unsigned i, j, t;
	int idx;

	if (!drm_dev_enter(adev_to_drm(adev), &idx))
		return;

	t = offset / AMDGPU_GPU_PAGE_SIZE;

	for (i = 0; i < pages; i++) {
		page_base = dma_addr[i];
		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	drm_dev_exit(idx);
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, dma_addr_t *dma_addr,
		     uint64_t flags)
{
	if (!adev->gart.ptr)
		return;

	amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr);
}

/**
 * amdgpu_gart_invalidate_tlb - invalidate gart TLB
 *
 * @adev: amdgpu device driver pointer
 *
 * Invalidate gart TLB which can be use as a way to flush gart changes
 *
 */
void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
{
	int i;

	if (!adev->gart.ptr)
		return;

	mb();
	if (down_read_trylock(&adev->reset_domain->sem)) {
		amdgpu_device_flush_hdp(adev, NULL);
		up_read(&adev->reset_domain->sem);
	}
	for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page_addr)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_gart_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
fdf2f6c5 SR	28
	29	#include <linux/pci.h>
	30	#include <linux/vmalloc.h>
	31
d38ceaf9	32	#include <drm/amdgpu_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
d38ceaf9	36	#include "amdgpu.h"
18f2525d	37	#include "amdgpu_reset.h"
b2fe31cf	38	#include <drm/drm_drv.h>
c9a502e9	39	#include <drm/ttm/ttm_tt.h>
d38ceaf9 AD	40
	41	/*
	42	* GART
	43	* The GART (Graphics Aperture Remapping Table) is an aperture
	44	* in the GPU's address space. System pages can be mapped into
	45	* the aperture and look like contiguous pages from the GPU's
	46	* perspective. A page table maps the pages in the aperture
	47	* to the actual backing pages in system memory.
	48	*
	49	* Radeon GPUs support both an internal GART, as described above,
	50	* and AGP. AGP works similarly, but the GART table is configured
	51	* and maintained by the northbridge rather than the driver.
	52	* Radeon hw has a separate AGP aperture that is programmed to
	53	* point to the AGP aperture provided by the northbridge and the
	54	* requests are passed through to the northbridge aperture.
	55	* Both AGP and internal GART can be used at the same time, however
	56	* that is not currently supported by the driver.
	57	*
	58	* This file handles the common internal GART management.
	59	*/
	60
	61	/*
	62	* Common GART table functions.
	63	*/
011d4bbe	64
55e0037a	65	/**
777d9000	66	* amdgpu_gart_dummy_page_init - init dummy page used by the driver
55e0037a AD	67	*
	68	* @adev: amdgpu_device pointer
	69	*
	70	* Allocate the dummy page used by the driver (all asics).
	71	* This dummy page is used by the driver as a filler for gart entries
	72	* when pages are taken out of the GART
	73	* Returns 0 on sucess, -ENOMEM on failure.
	74	*/
	75	static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
	76	{
8af8a109	77	struct page *dummy_page = ttm_glob.dummy_read_page;
92e71b06 CK	78
92e71b06 CK	79	if (adev->dummy_page_addr)
55e0037a	80	return 0;
b7861293 PL	81	adev->dummy_page_addr = dma_map_page_attrs(&adev->pdev->dev, dummy_page, 0,
	82	PAGE_SIZE, DMA_BIDIRECTIONAL,
	83	DMA_ATTR_SKIP_CPU_SYNC);
7dc7b65a	84	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
55e0037a	85	dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
92e71b06	86	adev->dummy_page_addr = 0;
55e0037a AD	87	return -ENOMEM;
	88	}
	89	return 0;
	90	}
	91
	92	/**
777d9000	93	* amdgpu_gart_dummy_page_fini - free dummy page used by the driver
55e0037a AD	94	*
	95	* @adev: amdgpu_device pointer
	96	*
	97	* Frees the dummy page used by the driver (all asics).
	98	*/
d10d0daa	99	void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
55e0037a	100	{
92e71b06	101	if (!adev->dummy_page_addr)
55e0037a	102	return;
b7861293 PL	103	dma_unmap_page_attrs(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
	104	DMA_BIDIRECTIONAL,
	105	DMA_ATTR_SKIP_CPU_SYNC);
92e71b06	106	adev->dummy_page_addr = 0;
55e0037a AD	107	}
55e0037a AD	108
c9a502e9 FK	109	/**
	110	* amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
	111	*
	112	* @adev: amdgpu_device pointer
	113	*
	114	* Allocate system memory for GART page table for ASICs that don't have
	115	* dedicated VRAM.
	116	* Returns 0 for success, error for failure.
	117	*/
	118	int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
	119	{
	120	unsigned int order = get_order(adev->gart.table_size);
	121	gfp_t gfp_flags = GFP_KERNEL \| __GFP_ZERO;
	122	struct amdgpu_bo *bo = NULL;
	123	struct sg_table *sg = NULL;
	124	struct amdgpu_bo_param bp;
	125	dma_addr_t dma_addr;
	126	struct page *p;
e7a8594c	127	unsigned long x;
c9a502e9 FK	128	int ret;
	129
	130	if (adev->gart.bo != NULL)
	131	return 0;
	132
	133	p = alloc_pages(gfp_flags, order);
	134	if (!p)
	135	return -ENOMEM;
	136
e7a8594c TSD	137	/* assign pages to this device */
	138	for (x = 0; x < (1UL << order); x++)
	139	p[x].mapping = adev->mman.bdev.dev_mapping;
	140
c9a502e9 FK	141	/* If the hardware does not support UTCL2 snooping of the CPU caches
	142	* then set_memory_wc() could be used as a workaround to mark the pages
	143	* as write combine memory.
	144	*/
	145	dma_addr = dma_map_page(&adev->pdev->dev, p, 0, adev->gart.table_size,
	146	DMA_BIDIRECTIONAL);
	147	if (dma_mapping_error(&adev->pdev->dev, dma_addr)) {
	148	dev_err(&adev->pdev->dev, "Failed to DMA MAP the GART BO page\n");
	149	__free_pages(p, order);
	150	p = NULL;
	151	return -EFAULT;
	152	}
	153
1f9bb94f	154	dev_info(adev->dev, "%s dma_addr:%pad\n", __func__, &dma_addr);
c9a502e9 FK	155	/* Create SG table */
	156	sg = kmalloc(sizeof(*sg), GFP_KERNEL);
	157	if (!sg) {
	158	ret = -ENOMEM;
	159	goto error;
	160	}
	161	ret = sg_alloc_table(sg, 1, GFP_KERNEL);
	162	if (ret)
	163	goto error;
	164
	165	sg_dma_address(sg->sgl) = dma_addr;
	166	sg->sgl->length = adev->gart.table_size;
	167	#ifdef CONFIG_NEED_SG_DMA_LENGTH
	168	sg->sgl->dma_length = adev->gart.table_size;
	169	#endif
	170	/* Create SG BO */
	171	memset(&bp, 0, sizeof(bp));
	172	bp.size = adev->gart.table_size;
	173	bp.byte_align = PAGE_SIZE;
	174	bp.domain = AMDGPU_GEM_DOMAIN_CPU;
	175	bp.type = ttm_bo_type_sg;
	176	bp.resv = NULL;
	177	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
	178	bp.flags = 0;
	179	ret = amdgpu_bo_create(adev, &bp, &bo);
	180	if (ret)
	181	goto error;
	182
	183	bo->tbo.sg = sg;
	184	bo->tbo.ttm->sg = sg;
	185	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
	186	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
	187
	188	ret = amdgpu_bo_reserve(bo, true);
	189	if (ret) {
	190	dev_err(adev->dev, "(%d) failed to reserve bo for GART system bo\n", ret);
	191	goto error;
	192	}
	193
	194	ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
	195	WARN(ret, "Pinning the GART table failed");
	196	if (ret)
	197	goto error_resv;
	198
	199	adev->gart.bo = bo;
	200	adev->gart.ptr = page_to_virt(p);
	201	/* Make GART table accessible in VMID0 */
	202	ret = amdgpu_ttm_alloc_gart(&adev->gart.bo->tbo);
	203	if (ret)
	204	amdgpu_gart_table_ram_free(adev);
	205	amdgpu_bo_unreserve(bo);
	206
	207	return 0;
	208
	209	error_resv:
	210	amdgpu_bo_unreserve(bo);
	211	error:
	212	amdgpu_bo_unref(&bo);
	213	if (sg) {
	214	sg_free_table(sg);
	215	kfree(sg);
	216	}
	217	__free_pages(p, order);
	218	return ret;
219	}
220
221	/**
222	* amdgpu_gart_table_ram_free - free gart page table system ram
223	*
224	* @adev: amdgpu_device pointer
225	*
226	* Free the system memory used for the GART page tableon ASICs that don't
227	* have dedicated VRAM.
228	*/
229	void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
230	{
231	unsigned int order = get_order(adev->gart.table_size);
232	struct sg_table *sg = adev->gart.bo->tbo.sg;
233	struct page *p;
e7a8594c	234	unsigned long x;
c9a502e9 FK	235	int ret;
	236
	237	ret = amdgpu_bo_reserve(adev->gart.bo, false);
	238	if (!ret) {
	239	amdgpu_bo_unpin(adev->gart.bo);
	240	amdgpu_bo_unreserve(adev->gart.bo);
	241	}
	242	amdgpu_bo_unref(&adev->gart.bo);
	243	sg_free_table(sg);
	244	kfree(sg);
	245	p = virt_to_page(adev->gart.ptr);
e7a8594c TSD	246	for (x = 0; x < (1UL << order); x++)
e7a8594c TSD	247	p[x].mapping = NULL;
c9a502e9 FK	248	__free_pages(p, order);
	249
	250	adev->gart.ptr = NULL;
	251	}
	252
d38ceaf9 AD	253	/**
	254	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
	255	*
	256	* @adev: amdgpu_device pointer
	257	*
	258	* Allocate video memory for GART page table
	259	* (pcie r4xx, r5xx+). These asics require the
	260	* gart table to be in video memory.
	261	* Returns 0 for success, error for failure.
	262	*/
	263	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
	264	{
575e55ee ND	265	if (adev->gart.bo != NULL)
575e55ee ND	266	return 0;
ce1b1b66	267
575e55ee ND	268	return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE,
	269	AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo,
	270	NULL, (void *)&adev->gart.ptr);
d38ceaf9 AD	271	}
	272
	273	/**
	274	* amdgpu_gart_table_vram_free - free gart page table vram
	275	*
	276	* @adev: amdgpu_device pointer
	277	*
	278	* Free the video memory used for the GART page table
	279	* (pcie r4xx, r5xx+). These asics require the gart table to
	280	* be in video memory.
	281	*/
	282	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	283	{
575e55ee	284	amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr);
d38ceaf9 AD	285	}
	286
	287	/*
	288	* Common gart functions.
	289	*/
	290	/**
	291	* amdgpu_gart_unbind - unbind pages from the gart page table
	292	*
	293	* @adev: amdgpu_device pointer
	294	* @offset: offset into the GPU's gart aperture
	295	* @pages: number of pages to unbind
	296	*
	297	* Unbinds the requested pages from the gart page table and
	298	* replaces them with the dummy page (all asics).
738f64cc	299	* Returns 0 for success, -EINVAL for failure.
d38ceaf9	300	*/
1b08dfb8	301	void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	302	int pages)
	303	{
	304	unsigned t;
	305	unsigned p;
	306	int i, j;
	307	u64 page_base;
a0676f60 AD	308	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	309	uint64_t flags = 0;
b2fe31cf	310	int idx;
d38ceaf9	311
f9130b81	312	if (!adev->gart.ptr)
1b08dfb8	313	return;
d38ceaf9	314
c58a863b	315	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1b08dfb8	316	return;
b2fe31cf	317
d38ceaf9	318	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	319	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
d38ceaf9	320	for (i = 0; i < pages; i++, p++) {
92e71b06	321	page_base = adev->dummy_page_addr;
a1d29476 CK	322	if (!adev->gart.ptr)
a1d29476 CK	323	continue;
d38ceaf9	324
463d2fe8	325	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4 CK	326	amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
132f34e4 CK	327	t, page_base, flags);
a1d29476	328	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	329	}
d38ceaf9 AD	330	}
c1f9d82b	331	amdgpu_gart_invalidate_tlb(adev);
3ff98548	332
b2fe31cf	333	drm_dev_exit(idx);
d38ceaf9 AD	334	}
d38ceaf9 AD	335
0c2c421e CK	336	/**
	337	* amdgpu_gart_map - map dma_addresses into GART entries
	338	*
	339	* @adev: amdgpu_device pointer
	340	* @offset: offset into the GPU's gart aperture
	341	* @pages: number of pages to bind
	342	* @dma_addr: DMA addresses of pages
5dcb668d OZ	343	* @flags: page table entry flags
5dcb668d OZ	344	* @dst: CPU address of the gart table
0c2c421e CK	345	*
	346	* Map the dma_addresses into GART entries (all asics).
	347	* Returns 0 for success, -EINVAL for failure.
	348	*/
1b08dfb8	349	void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
0c2c421e CK	350	int pages, dma_addr_t *dma_addr, uint64_t flags,
	351	void *dst)
	352	{
	353	uint64_t page_base;
	354	unsigned i, j, t;
b2fe31cf	355	int idx;
0c2c421e	356
c58a863b	357	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1b08dfb8	358	return;
b2fe31cf	359
0c2c421e CK	360	t = offset / AMDGPU_GPU_PAGE_SIZE;
	361
	362	for (i = 0; i < pages; i++) {
	363	page_base = dma_addr[i];
463d2fe8	364	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4	365	amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
0c2c421e CK	366	page_base += AMDGPU_GPU_PAGE_SIZE;
	367	}
	368	}
b2fe31cf	369	drm_dev_exit(idx);
0c2c421e CK	370	}
0c2c421e CK	371
d38ceaf9 AD	372	/**
	373	* amdgpu_gart_bind - bind pages into the gart page table
	374	*
	375	* @adev: amdgpu_device pointer
	376	* @offset: offset into the GPU's gart aperture
	377	* @pages: number of pages to bind
d38ceaf9	378	* @dma_addr: DMA addresses of pages
e8b74035	379	* @flags: page table entry flags
d38ceaf9 AD	380	*
	381	* Binds the requested pages to the gart page table
	382	* (all asics).
	383	* Returns 0 for success, -EINVAL for failure.
	384	*/
1b08dfb8	385	void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
942ab769	386	int pages, dma_addr_t *dma_addr,
6b777607	387	uint64_t flags)
d38ceaf9	388	{
f9130b81	389	if (!adev->gart.ptr)
1b08dfb8	390	return;
fa2cd036	391
1b08dfb8	392	amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr);
19a1d935 ND	393	}
	394
	395	/**
	396	* amdgpu_gart_invalidate_tlb - invalidate gart TLB
	397	*
	398	* @adev: amdgpu device driver pointer
	399	*
	400	* Invalidate gart TLB which can be use as a way to flush gart changes
	401	*
	402	*/
	403	void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
	404	{
	405	int i;
0c2c421e	406
29ba7b16 AL	407	if (!adev->gart.ptr)
	408	return;
	409
d38ceaf9	410	mb();
18f2525d YL	411	if (down_read_trylock(&adev->reset_domain->sem)) {
	412	amdgpu_device_flush_hdp(adev, NULL);
	413	up_read(&adev->reset_domain->sem);
	414	}
d9426c3d	415	for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
3ff98548	416	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
d38ceaf9 AD	417	}
	418
	419	/**
	420	* amdgpu_gart_init - init the driver info for managing the gart
	421	*
	422	* @adev: amdgpu_device pointer
	423	*
	424	* Allocate the dummy page and init the gart driver info (all asics).
	425	* Returns 0 for success, error for failure.
	426	*/
	427	int amdgpu_gart_init(struct amdgpu_device *adev)
	428	{
43251981	429	int r;
d38ceaf9	430
92e71b06	431	if (adev->dummy_page_addr)
d38ceaf9	432	return 0;
a1d29476	433
d38ceaf9 AD	434	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	435	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	436	DRM_ERROR("Page size is smaller than GPU page size!\n");
	437	return -EINVAL;
	438	}
55e0037a	439	r = amdgpu_gart_dummy_page_init(adev);
d38ceaf9 AD	440	if (r)
	441	return r;
	442	/* Compute table size */
770d13b1 CK	443	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
770d13b1 CK	444	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	445	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
d38ceaf9 AD	446	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	447
d38ceaf9 AD	448	return 0;
d38ceaf9 AD	449	}