[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"
#include <drm/drm_drv.h>

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */

/**
 * amdgpu_gart_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
	struct page *dummy_page = ttm_glob.dummy_read_page;

	if (adev->dummy_page_addr)
		return 0;
	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
					     PAGE_SIZE, DMA_BIDIRECTIONAL);
	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		adev->dummy_page_addr = 0;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
	if (!adev->dummy_page_addr)
		return;
	dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
		       DMA_BIDIRECTIONAL);
	adev->dummy_page_addr = 0;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		struct amdgpu_bo_param bp;

		memset(&bp, 0, sizeof(bp));
		bp.size = adev->gart.table_size;
		bp.byte_align = PAGE_SIZE;
		bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		bp.type = ttm_bo_type_kernel;
		bp.resv = NULL;
		bp.bo_ptr_size = sizeof(struct amdgpu_bo);

		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_table_vram_pin - pin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
{
	int r;

	r = amdgpu_bo_reserve(adev->gart.bo, false);
	if (unlikely(r != 0))
		return r;
	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
	if (r) {
		amdgpu_bo_unreserve(adev->gart.bo);
		return r;
	}
	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
	if (r)
		amdgpu_bo_unpin(adev->gart.bo);
	amdgpu_bo_unreserve(adev->gart.bo);
	return r;
}

/**
 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		return;
	}
	r = amdgpu_bo_reserve(adev->gart.bo, true);
	if (likely(r == 0)) {
		amdgpu_bo_kunmap(adev->gart.bo);
		amdgpu_bo_unpin(adev->gart.bo);
		amdgpu_bo_unreserve(adev->gart.bo);
		adev->gart.ptr = NULL;
	}
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	if (adev->gart.bo == NULL) {
		return;
	}
	amdgpu_bo_unref(&adev->gart.bo);
	adev->gart.ptr = NULL;
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;
	int idx;

	if (!adev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return -EINVAL;
	}

	if (!drm_dev_enter(&adev->ddev, &idx))
		return 0;

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++) {
		page_base = adev->dummy_page_addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
					       t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	mb();
	amdgpu_device_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

	drm_dev_exit(idx);
	return 0;
}

/**
 * amdgpu_gart_map - map dma_addresses into GART entries
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 * @dst: CPU address of the gart table
 *
 * Map the dma_addresses into GART entries (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
		    int pages, dma_addr_t *dma_addr, uint64_t flags,
		    void *dst)
{
	uint64_t page_base;
	unsigned i, j, t;
	int idx;

	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	if (!drm_dev_enter(&adev->ddev, &idx))
		return 0;

	t = offset / AMDGPU_GPU_PAGE_SIZE;

	for (i = 0; i < pages; i++) {
		page_base = dma_addr[i];
		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	drm_dev_exit(idx);
	return 0;
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, dma_addr_t *dma_addr,
		     uint64_t flags)
{
	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	if (!adev->gart.ptr)
		return 0;

	return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
			       adev->gart.ptr);
}

/**
 * amdgpu_gart_invalidate_tlb - invalidate gart TLB
 *
 * @adev: amdgpu device driver pointer
 *
 * Invalidate gart TLB which can be use as a way to flush gart changes
 *
 */
void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
{
	int i;

	mb();
	amdgpu_device_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page_addr)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_gart_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
fdf2f6c5 SR	28
	29	#include <linux/pci.h>
	30	#include <linux/vmalloc.h>
	31
d38ceaf9	32	#include <drm/amdgpu_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
d38ceaf9	36	#include "amdgpu.h"
b2fe31cf	37	#include <drm/drm_drv.h>
d38ceaf9 AD	38
	39	/*
	40	* GART
	41	* The GART (Graphics Aperture Remapping Table) is an aperture
	42	* in the GPU's address space. System pages can be mapped into
	43	* the aperture and look like contiguous pages from the GPU's
	44	* perspective. A page table maps the pages in the aperture
	45	* to the actual backing pages in system memory.
	46	*
	47	* Radeon GPUs support both an internal GART, as described above,
	48	* and AGP. AGP works similarly, but the GART table is configured
	49	* and maintained by the northbridge rather than the driver.
	50	* Radeon hw has a separate AGP aperture that is programmed to
	51	* point to the AGP aperture provided by the northbridge and the
	52	* requests are passed through to the northbridge aperture.
	53	* Both AGP and internal GART can be used at the same time, however
	54	* that is not currently supported by the driver.
	55	*
	56	* This file handles the common internal GART management.
	57	*/
	58
	59	/*
	60	* Common GART table functions.
	61	*/
011d4bbe	62
55e0037a	63	/**
777d9000	64	* amdgpu_gart_dummy_page_init - init dummy page used by the driver
55e0037a AD	65	*
	66	* @adev: amdgpu_device pointer
	67	*
	68	* Allocate the dummy page used by the driver (all asics).
	69	* This dummy page is used by the driver as a filler for gart entries
	70	* when pages are taken out of the GART
	71	* Returns 0 on sucess, -ENOMEM on failure.
	72	*/
	73	static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
	74	{
8af8a109	75	struct page *dummy_page = ttm_glob.dummy_read_page;
92e71b06 CK	76
92e71b06 CK	77	if (adev->dummy_page_addr)
55e0037a	78	return 0;
7dc7b65a	79	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
8a1d1bdb	80	PAGE_SIZE, DMA_BIDIRECTIONAL);
7dc7b65a	81	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
55e0037a	82	dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
92e71b06	83	adev->dummy_page_addr = 0;
55e0037a AD	84	return -ENOMEM;
	85	}
	86	return 0;
	87	}
	88
	89	/**
777d9000	90	* amdgpu_gart_dummy_page_fini - free dummy page used by the driver
55e0037a AD	91	*
	92	* @adev: amdgpu_device pointer
	93	*
	94	* Frees the dummy page used by the driver (all asics).
	95	*/
d10d0daa	96	void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
55e0037a	97	{
92e71b06	98	if (!adev->dummy_page_addr)
55e0037a	99	return;
8a1d1bdb CJ	100	dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
8a1d1bdb CJ	101	DMA_BIDIRECTIONAL);
92e71b06	102	adev->dummy_page_addr = 0;
55e0037a AD	103	}
55e0037a AD	104
d38ceaf9 AD	105	/**
	106	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
	107	*
	108	* @adev: amdgpu_device pointer
	109	*
	110	* Allocate video memory for GART page table
	111	* (pcie r4xx, r5xx+). These asics require the
	112	* gart table to be in video memory.
	113	* Returns 0 for success, error for failure.
	114	*/
	115	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
	116	{
ce1b1b66 ML	117	int r;
ce1b1b66 ML	118
1123b989	119	if (adev->gart.bo == NULL) {
3216c6b7 CZ	120	struct amdgpu_bo_param bp;
	121
	122	memset(&bp, 0, sizeof(bp));
	123	bp.size = adev->gart.table_size;
	124	bp.byte_align = PAGE_SIZE;
	125	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
	126	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
	127	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
	128	bp.type = ttm_bo_type_kernel;
	129	bp.resv = NULL;
9fd5543e ND	130	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
9fd5543e ND	131
1123b989	132	r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
ce1b1b66 ML	133	if (r) {
	134	return r;
	135	}
	136	}
	137	return 0;
	138	}
	139
	140	/**
	141	* amdgpu_gart_table_vram_pin - pin gart page table in vram
	142	*
	143	* @adev: amdgpu_device pointer
	144	*
	145	* Pin the GART page table in vram so it will not be moved
	146	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	147	* gart table to be in video memory.
	148	* Returns 0 for success, error for failure.
	149	*/
	150	int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
	151	{
ce1b1b66 ML	152	int r;
ce1b1b66 ML	153
1123b989	154	r = amdgpu_bo_reserve(adev->gart.bo, false);
ce1b1b66 ML	155	if (unlikely(r != 0))
ce1b1b66 ML	156	return r;
1123b989	157	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
ce1b1b66	158	if (r) {
1123b989	159	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	160	return r;
ce1b1b66 ML	161	}
1123b989	162	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
ce1b1b66	163	if (r)
1123b989 CK	164	amdgpu_bo_unpin(adev->gart.bo);
1123b989 CK	165	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	166	return r;
	167	}
	168
	169	/**
	170	* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
	171	*
	172	* @adev: amdgpu_device pointer
	173	*
	174	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	175	* These asics require the gart table to be in video memory.
	176	*/
	177	void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
	178	{
	179	int r;
	180
1123b989	181	if (adev->gart.bo == NULL) {
ce1b1b66 ML	182	return;
ce1b1b66 ML	183	}
1123b989	184	r = amdgpu_bo_reserve(adev->gart.bo, true);
ce1b1b66	185	if (likely(r == 0)) {
1123b989 CK	186	amdgpu_bo_kunmap(adev->gart.bo);
	187	amdgpu_bo_unpin(adev->gart.bo);
	188	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	189	adev->gart.ptr = NULL;
ce1b1b66 ML	190	}
d38ceaf9 AD	191	}
	192
	193	/**
	194	* amdgpu_gart_table_vram_free - free gart page table vram
	195	*
	196	* @adev: amdgpu_device pointer
	197	*
	198	* Free the video memory used for the GART page table
	199	* (pcie r4xx, r5xx+). These asics require the gart table to
	200	* be in video memory.
	201	*/
	202	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	203	{
1123b989	204	if (adev->gart.bo == NULL) {
ce1b1b66 ML	205	return;
ce1b1b66 ML	206	}
1123b989	207	amdgpu_bo_unref(&adev->gart.bo);
a00aacdf	208	adev->gart.ptr = NULL;
d38ceaf9 AD	209	}
	210
	211	/*
	212	* Common gart functions.
	213	*/
	214	/**
	215	* amdgpu_gart_unbind - unbind pages from the gart page table
	216	*
	217	* @adev: amdgpu_device pointer
	218	* @offset: offset into the GPU's gart aperture
	219	* @pages: number of pages to unbind
	220	*
	221	* Unbinds the requested pages from the gart page table and
	222	* replaces them with the dummy page (all asics).
738f64cc	223	* Returns 0 for success, -EINVAL for failure.
d38ceaf9	224	*/
738f64cc	225	int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	226	int pages)
	227	{
	228	unsigned t;
	229	unsigned p;
	230	int i, j;
	231	u64 page_base;
a0676f60 AD	232	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	233	uint64_t flags = 0;
b2fe31cf	234	int idx;
d38ceaf9 AD	235
	236	if (!adev->gart.ready) {
	237	WARN(1, "trying to unbind memory from uninitialized GART !\n");
738f64cc	238	return -EINVAL;
d38ceaf9 AD	239	}
d38ceaf9 AD	240
b2fe31cf	241	if (!drm_dev_enter(&adev->ddev, &idx))
	242	return 0;
	243
d38ceaf9	244	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	245	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
d38ceaf9	246	for (i = 0; i < pages; i++, p++) {
92e71b06	247	page_base = adev->dummy_page_addr;
a1d29476 CK	248	if (!adev->gart.ptr)
a1d29476 CK	249	continue;
d38ceaf9	250
463d2fe8	251	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4 CK	252	amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
132f34e4 CK	253	t, page_base, flags);
a1d29476	254	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	255	}
	256	}
	257	mb();
810085dd	258	amdgpu_device_flush_hdp(adev, NULL);
3ff98548 OZ	259	for (i = 0; i < adev->num_vmhubs; i++)
	260	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
	261
b2fe31cf	262	drm_dev_exit(idx);
738f64cc	263	return 0;
d38ceaf9 AD	264	}
d38ceaf9 AD	265
0c2c421e CK	266	/**
	267	* amdgpu_gart_map - map dma_addresses into GART entries
	268	*
	269	* @adev: amdgpu_device pointer
	270	* @offset: offset into the GPU's gart aperture
	271	* @pages: number of pages to bind
	272	* @dma_addr: DMA addresses of pages
5dcb668d OZ	273	* @flags: page table entry flags
5dcb668d OZ	274	* @dst: CPU address of the gart table
0c2c421e CK	275	*
	276	* Map the dma_addresses into GART entries (all asics).
	277	* Returns 0 for success, -EINVAL for failure.
	278	*/
	279	int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
	280	int pages, dma_addr_t *dma_addr, uint64_t flags,
	281	void *dst)
	282	{
	283	uint64_t page_base;
	284	unsigned i, j, t;
b2fe31cf	285	int idx;
0c2c421e CK	286
	287	if (!adev->gart.ready) {
	288	WARN(1, "trying to bind memory to uninitialized GART !\n");
	289	return -EINVAL;
	290	}
	291
b2fe31cf	292	if (!drm_dev_enter(&adev->ddev, &idx))
	293	return 0;
	294
0c2c421e CK	295	t = offset / AMDGPU_GPU_PAGE_SIZE;
	296
	297	for (i = 0; i < pages; i++) {
	298	page_base = dma_addr[i];
463d2fe8	299	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4	300	amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
0c2c421e CK	301	page_base += AMDGPU_GPU_PAGE_SIZE;
	302	}
	303	}
b2fe31cf	304	drm_dev_exit(idx);
0c2c421e CK	305	return 0;
	306	}
	307
d38ceaf9 AD	308	/**
	309	* amdgpu_gart_bind - bind pages into the gart page table
	310	*
	311	* @adev: amdgpu_device pointer
	312	* @offset: offset into the GPU's gart aperture
	313	* @pages: number of pages to bind
d38ceaf9	314	* @dma_addr: DMA addresses of pages
e8b74035	315	* @flags: page table entry flags
d38ceaf9 AD	316	*
	317	* Binds the requested pages to the gart page table
	318	* (all asics).
	319	* Returns 0 for success, -EINVAL for failure.
	320	*/
cab0b8d5	321	int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
942ab769	322	int pages, dma_addr_t *dma_addr,
6b777607	323	uint64_t flags)
d38ceaf9	324	{
d38ceaf9 AD	325	if (!adev->gart.ready) {
	326	WARN(1, "trying to bind memory to uninitialized GART !\n");
	327	return -EINVAL;
	328	}
	329
fa2cd036 CK	330	if (!adev->gart.ptr)
	331	return 0;
	332
19a1d935 ND	333	return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
	334	adev->gart.ptr);
	335	}
	336
	337	/**
	338	* amdgpu_gart_invalidate_tlb - invalidate gart TLB
	339	*
	340	* @adev: amdgpu device driver pointer
	341	*
	342	* Invalidate gart TLB which can be use as a way to flush gart changes
	343	*
	344	*/
	345	void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
	346	{
	347	int i;
0c2c421e	348
d38ceaf9	349	mb();
810085dd	350	amdgpu_device_flush_hdp(adev, NULL);
3ff98548 OZ	351	for (i = 0; i < adev->num_vmhubs; i++)
3ff98548 OZ	352	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
d38ceaf9 AD	353	}
	354
	355	/**
	356	* amdgpu_gart_init - init the driver info for managing the gart
	357	*
	358	* @adev: amdgpu_device pointer
	359	*
	360	* Allocate the dummy page and init the gart driver info (all asics).
	361	* Returns 0 for success, error for failure.
	362	*/
	363	int amdgpu_gart_init(struct amdgpu_device *adev)
	364	{
43251981	365	int r;
d38ceaf9	366
92e71b06	367	if (adev->dummy_page_addr)
d38ceaf9	368	return 0;
a1d29476	369
d38ceaf9 AD	370	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	371	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	372	DRM_ERROR("Page size is smaller than GPU page size!\n");
	373	return -EINVAL;
	374	}
55e0037a	375	r = amdgpu_gart_dummy_page_init(adev);
d38ceaf9 AD	376	if (r)
	377	return r;
	378	/* Compute table size */
770d13b1 CK	379	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
770d13b1 CK	380	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	381	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
d38ceaf9 AD	382	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	383
d38ceaf9 AD	384	return 0;
d38ceaf9 AD	385	}