[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */

/**
 * amdgpu_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
	struct page *dummy_page = ttm_bo_glob.dummy_read_page;

	if (adev->dummy_page_addr)
		return 0;
	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
					     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		adev->dummy_page_addr = 0;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
	if (!adev->dummy_page_addr)
		return;
	pci_unmap_page(adev->pdev, adev->dummy_page_addr,
		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	adev->dummy_page_addr = 0;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		struct amdgpu_bo_param bp;

		memset(&bp, 0, sizeof(bp));
		bp.size = adev->gart.table_size;
		bp.byte_align = PAGE_SIZE;
		bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		bp.type = ttm_bo_type_kernel;
		bp.resv = NULL;
		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_table_vram_pin - pin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
{
	int r;

	r = amdgpu_bo_reserve(adev->gart.bo, false);
	if (unlikely(r != 0))
		return r;
	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
	if (r) {
		amdgpu_bo_unreserve(adev->gart.bo);
		return r;
	}
	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
	if (r)
		amdgpu_bo_unpin(adev->gart.bo);
	amdgpu_bo_unreserve(adev->gart.bo);
	return r;
}

/**
 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		return;
	}
	r = amdgpu_bo_reserve(adev->gart.bo, true);
	if (likely(r == 0)) {
		amdgpu_bo_kunmap(adev->gart.bo);
		amdgpu_bo_unpin(adev->gart.bo);
		amdgpu_bo_unreserve(adev->gart.bo);
		adev->gart.ptr = NULL;
	}
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	if (adev->gart.bo == NULL) {
		return;
	}
	amdgpu_bo_unref(&adev->gart.bo);
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;

	if (!adev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return -EINVAL;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++) {
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
		adev->gart.pages[p] = NULL;
#endif
		page_base = adev->dummy_page_addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
					       t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	mb();
	amdgpu_asic_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

	return 0;
}

/**
 * amdgpu_gart_map - map dma_addresses into GART entries
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 * @dst: CPU address of the gart table
 *
 * Map the dma_addresses into GART entries (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
		    int pages, dma_addr_t *dma_addr, uint64_t flags,
		    void *dst)
{
	uint64_t page_base;
	unsigned i, j, t;

	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;

	for (i = 0; i < pages; i++) {
		page_base = dma_addr[i];
		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint64_t flags)
{
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	unsigned t,p;
#endif
	int r, i;

	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++)
		adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
#endif

	if (!adev->gart.ptr)
		return 0;

	r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
		    adev->gart.ptr);
	if (r)
		return r;

	mb();
	amdgpu_asic_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
	return 0;
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page_addr)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_gart_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	/* Allocate pages table */
	adev->gart.pages = vzalloc(array_size(sizeof(void *),
					      adev->gart.num_cpu_pages));
	if (adev->gart.pages == NULL)
		return -ENOMEM;
#endif

	return 0;
}

/**
 * amdgpu_gart_fini - tear down the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Tear down the gart driver info and free the dummy page (all asics).
 */
void amdgpu_gart_fini(struct amdgpu_device *adev)
{
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	vfree(adev->gart.pages);
	adev->gart.pages = NULL;
#endif
	amdgpu_gart_dummy_page_fini(adev);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
fdf2f6c5 SR	28
	29	#include <linux/pci.h>
	30	#include <linux/vmalloc.h>
	31
d38ceaf9	32	#include <drm/amdgpu_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
d38ceaf9 AD	36	#include "amdgpu.h"
	37
	38	/*
	39	* GART
	40	* The GART (Graphics Aperture Remapping Table) is an aperture
	41	* in the GPU's address space. System pages can be mapped into
	42	* the aperture and look like contiguous pages from the GPU's
	43	* perspective. A page table maps the pages in the aperture
	44	* to the actual backing pages in system memory.
	45	*
	46	* Radeon GPUs support both an internal GART, as described above,
	47	* and AGP. AGP works similarly, but the GART table is configured
	48	* and maintained by the northbridge rather than the driver.
	49	* Radeon hw has a separate AGP aperture that is programmed to
	50	* point to the AGP aperture provided by the northbridge and the
	51	* requests are passed through to the northbridge aperture.
	52	* Both AGP and internal GART can be used at the same time, however
	53	* that is not currently supported by the driver.
	54	*
	55	* This file handles the common internal GART management.
	56	*/
	57
	58	/*
	59	* Common GART table functions.
	60	*/
011d4bbe	61
55e0037a AD	62	/**
	63	* amdgpu_dummy_page_init - init dummy page used by the driver
	64	*
	65	* @adev: amdgpu_device pointer
	66	*
	67	* Allocate the dummy page used by the driver (all asics).
	68	* This dummy page is used by the driver as a filler for gart entries
	69	* when pages are taken out of the GART
	70	* Returns 0 on sucess, -ENOMEM on failure.
	71	*/
	72	static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
	73	{
97588b5b	74	struct page *dummy_page = ttm_bo_glob.dummy_read_page;
92e71b06 CK	75
92e71b06 CK	76	if (adev->dummy_page_addr)
55e0037a	77	return 0;
7dc7b65a	78	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
92e71b06	79	PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
7dc7b65a	80	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
55e0037a	81	dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
92e71b06	82	adev->dummy_page_addr = 0;
55e0037a AD	83	return -ENOMEM;
	84	}
	85	return 0;
	86	}
	87
	88	/**
	89	* amdgpu_dummy_page_fini - free dummy page used by the driver
	90	*
	91	* @adev: amdgpu_device pointer
	92	*
	93	* Frees the dummy page used by the driver (all asics).
	94	*/
	95	static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
	96	{
92e71b06	97	if (!adev->dummy_page_addr)
55e0037a	98	return;
92e71b06 CK	99	pci_unmap_page(adev->pdev, adev->dummy_page_addr,
	100	PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	101	adev->dummy_page_addr = 0;
55e0037a AD	102	}
55e0037a AD	103
d38ceaf9 AD	104	/**
	105	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
	106	*
	107	* @adev: amdgpu_device pointer
	108	*
	109	* Allocate video memory for GART page table
	110	* (pcie r4xx, r5xx+). These asics require the
	111	* gart table to be in video memory.
	112	* Returns 0 for success, error for failure.
	113	*/
	114	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
	115	{
ce1b1b66 ML	116	int r;
ce1b1b66 ML	117
1123b989	118	if (adev->gart.bo == NULL) {
3216c6b7 CZ	119	struct amdgpu_bo_param bp;
	120
	121	memset(&bp, 0, sizeof(bp));
	122	bp.size = adev->gart.table_size;
	123	bp.byte_align = PAGE_SIZE;
	124	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
	125	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
	126	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
	127	bp.type = ttm_bo_type_kernel;
	128	bp.resv = NULL;
1123b989	129	r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
ce1b1b66 ML	130	if (r) {
	131	return r;
	132	}
	133	}
	134	return 0;
	135	}
	136
	137	/**
	138	* amdgpu_gart_table_vram_pin - pin gart page table in vram
	139	*
	140	* @adev: amdgpu_device pointer
	141	*
	142	* Pin the GART page table in vram so it will not be moved
	143	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	144	* gart table to be in video memory.
	145	* Returns 0 for success, error for failure.
	146	*/
	147	int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
	148	{
ce1b1b66 ML	149	int r;
ce1b1b66 ML	150
1123b989	151	r = amdgpu_bo_reserve(adev->gart.bo, false);
ce1b1b66 ML	152	if (unlikely(r != 0))
ce1b1b66 ML	153	return r;
1123b989	154	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
ce1b1b66	155	if (r) {
1123b989	156	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	157	return r;
ce1b1b66 ML	158	}
1123b989	159	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
ce1b1b66	160	if (r)
1123b989 CK	161	amdgpu_bo_unpin(adev->gart.bo);
1123b989 CK	162	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	163	return r;
	164	}
	165
	166	/**
	167	* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
	168	*
	169	* @adev: amdgpu_device pointer
	170	*
	171	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	172	* These asics require the gart table to be in video memory.
	173	*/
	174	void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
	175	{
	176	int r;
	177
1123b989	178	if (adev->gart.bo == NULL) {
ce1b1b66 ML	179	return;
ce1b1b66 ML	180	}
1123b989	181	r = amdgpu_bo_reserve(adev->gart.bo, true);
ce1b1b66	182	if (likely(r == 0)) {
1123b989 CK	183	amdgpu_bo_kunmap(adev->gart.bo);
	184	amdgpu_bo_unpin(adev->gart.bo);
	185	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	186	adev->gart.ptr = NULL;
ce1b1b66 ML	187	}
d38ceaf9 AD	188	}
	189
	190	/**
	191	* amdgpu_gart_table_vram_free - free gart page table vram
	192	*
	193	* @adev: amdgpu_device pointer
	194	*
	195	* Free the video memory used for the GART page table
	196	* (pcie r4xx, r5xx+). These asics require the gart table to
	197	* be in video memory.
	198	*/
	199	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	200	{
1123b989	201	if (adev->gart.bo == NULL) {
ce1b1b66 ML	202	return;
ce1b1b66 ML	203	}
1123b989	204	amdgpu_bo_unref(&adev->gart.bo);
d38ceaf9 AD	205	}
	206
	207	/*
	208	* Common gart functions.
	209	*/
	210	/**
	211	* amdgpu_gart_unbind - unbind pages from the gart page table
	212	*
	213	* @adev: amdgpu_device pointer
	214	* @offset: offset into the GPU's gart aperture
	215	* @pages: number of pages to unbind
	216	*
	217	* Unbinds the requested pages from the gart page table and
	218	* replaces them with the dummy page (all asics).
738f64cc	219	* Returns 0 for success, -EINVAL for failure.
d38ceaf9	220	*/
738f64cc	221	int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	222	int pages)
	223	{
	224	unsigned t;
	225	unsigned p;
	226	int i, j;
	227	u64 page_base;
a0676f60 AD	228	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	229	uint64_t flags = 0;
d38ceaf9 AD	230
	231	if (!adev->gart.ready) {
	232	WARN(1, "trying to unbind memory from uninitialized GART !\n");
738f64cc	233	return -EINVAL;
d38ceaf9 AD	234	}
	235
	236	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	237	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
d38ceaf9	238	for (i = 0; i < pages; i++, p++) {
186294f9	239	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
a1d29476 CK	240	adev->gart.pages[p] = NULL;
a1d29476 CK	241	#endif
92e71b06	242	page_base = adev->dummy_page_addr;
a1d29476 CK	243	if (!adev->gart.ptr)
a1d29476 CK	244	continue;
d38ceaf9	245
463d2fe8	246	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4 CK	247	amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
132f34e4 CK	248	t, page_base, flags);
a1d29476	249	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	250	}
	251	}
	252	mb();
69882565	253	amdgpu_asic_flush_hdp(adev, NULL);
3ff98548 OZ	254	for (i = 0; i < adev->num_vmhubs; i++)
	255	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
	256
738f64cc	257	return 0;
d38ceaf9 AD	258	}
d38ceaf9 AD	259
0c2c421e CK	260	/**
	261	* amdgpu_gart_map - map dma_addresses into GART entries
	262	*
	263	* @adev: amdgpu_device pointer
	264	* @offset: offset into the GPU's gart aperture
	265	* @pages: number of pages to bind
	266	* @dma_addr: DMA addresses of pages
5dcb668d OZ	267	* @flags: page table entry flags
5dcb668d OZ	268	* @dst: CPU address of the gart table
0c2c421e CK	269	*
	270	* Map the dma_addresses into GART entries (all asics).
	271	* Returns 0 for success, -EINVAL for failure.
	272	*/
	273	int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
	274	int pages, dma_addr_t *dma_addr, uint64_t flags,
	275	void *dst)
	276	{
	277	uint64_t page_base;
	278	unsigned i, j, t;
	279
	280	if (!adev->gart.ready) {
	281	WARN(1, "trying to bind memory to uninitialized GART !\n");
	282	return -EINVAL;
	283	}
	284
	285	t = offset / AMDGPU_GPU_PAGE_SIZE;
	286
	287	for (i = 0; i < pages; i++) {
	288	page_base = dma_addr[i];
463d2fe8	289	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4	290	amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
0c2c421e CK	291	page_base += AMDGPU_GPU_PAGE_SIZE;
	292	}
	293	}
	294	return 0;
	295	}
	296
d38ceaf9 AD	297	/**
	298	* amdgpu_gart_bind - bind pages into the gart page table
	299	*
	300	* @adev: amdgpu_device pointer
	301	* @offset: offset into the GPU's gart aperture
	302	* @pages: number of pages to bind
	303	* @pagelist: pages to bind
	304	* @dma_addr: DMA addresses of pages
e8b74035	305	* @flags: page table entry flags
d38ceaf9 AD	306	*
	307	* Binds the requested pages to the gart page table
	308	* (all asics).
	309	* Returns 0 for success, -EINVAL for failure.
	310	*/
cab0b8d5	311	int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9	312	int pages, struct page *pagelist, dma_addr_t dma_addr,
6b777607	313	uint64_t flags)
d38ceaf9	314	{
0c2c421e	315	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
b1f5b453	316	unsigned t,p;
0c2c421e	317	#endif
3ff98548	318	int r, i;
d38ceaf9 AD	319
	320	if (!adev->gart.ready) {
	321	WARN(1, "trying to bind memory to uninitialized GART !\n");
	322	return -EINVAL;
	323	}
	324
0c2c421e	325	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9	326	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	327	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
0c2c421e	328	for (i = 0; i < pages; i++, p++)
e89d0d33	329	adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
a1d29476	330	#endif
0c2c421e	331
fa2cd036 CK	332	if (!adev->gart.ptr)
	333	return 0;
	334
	335	r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
	336	adev->gart.ptr);
	337	if (r)
	338	return r;
0c2c421e	339
d38ceaf9	340	mb();
69882565	341	amdgpu_asic_flush_hdp(adev, NULL);
3ff98548 OZ	342	for (i = 0; i < adev->num_vmhubs; i++)
3ff98548 OZ	343	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
d38ceaf9 AD	344	return 0;
	345	}
	346
	347	/**
	348	* amdgpu_gart_init - init the driver info for managing the gart
	349	*
	350	* @adev: amdgpu_device pointer
	351	*
	352	* Allocate the dummy page and init the gart driver info (all asics).
	353	* Returns 0 for success, error for failure.
	354	*/
	355	int amdgpu_gart_init(struct amdgpu_device *adev)
	356	{
43251981	357	int r;
d38ceaf9	358
92e71b06	359	if (adev->dummy_page_addr)
d38ceaf9	360	return 0;
a1d29476	361
d38ceaf9 AD	362	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	363	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	364	DRM_ERROR("Page size is smaller than GPU page size!\n");
	365	return -EINVAL;
	366	}
55e0037a	367	r = amdgpu_gart_dummy_page_init(adev);
d38ceaf9 AD	368	if (r)
	369	return r;
	370	/* Compute table size */
770d13b1 CK	371	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
770d13b1 CK	372	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	373	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
d38ceaf9 AD	374	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	375
186294f9	376	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9	377	/* Allocate pages table */
fad953ce KC	378	adev->gart.pages = vzalloc(array_size(sizeof(void *),
fad953ce KC	379	adev->gart.num_cpu_pages));
f59548c8	380	if (adev->gart.pages == NULL)
d38ceaf9	381	return -ENOMEM;
a1d29476 CK	382	#endif
a1d29476 CK	383
d38ceaf9 AD	384	return 0;
	385	}
	386
	387	/**
	388	* amdgpu_gart_fini - tear down the driver info for managing the gart
	389	*
	390	* @adev: amdgpu_device pointer
	391	*
	392	* Tear down the gart driver info and free the dummy page (all asics).
	393	*/
	394	void amdgpu_gart_fini(struct amdgpu_device *adev)
	395	{
186294f9	396	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9	397	vfree(adev->gart.pages);
d38ceaf9	398	adev->gart.pages = NULL;
a1d29476	399	#endif
55e0037a	400	amdgpu_gart_dummy_page_fini(adev);
d38ceaf9	401	}