[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */

/**
 * amdgpu_gart_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
	struct page *dummy_page = ttm_glob.dummy_read_page;

	if (adev->dummy_page_addr)
		return 0;
	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
					     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		adev->dummy_page_addr = 0;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
	if (!adev->dummy_page_addr)
		return;
	pci_unmap_page(adev->pdev, adev->dummy_page_addr,
		       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	adev->dummy_page_addr = 0;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		struct amdgpu_bo_param bp;

		memset(&bp, 0, sizeof(bp));
		bp.size = adev->gart.table_size;
		bp.byte_align = PAGE_SIZE;
		bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
		bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
		bp.type = ttm_bo_type_kernel;
		bp.resv = NULL;
		bp.bo_ptr_size = sizeof(struct amdgpu_bo);

		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_table_vram_pin - pin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
{
	int r;

	r = amdgpu_bo_reserve(adev->gart.bo, false);
	if (unlikely(r != 0))
		return r;
	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
	if (r) {
		amdgpu_bo_unreserve(adev->gart.bo);
		return r;
	}
	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
	if (r)
		amdgpu_bo_unpin(adev->gart.bo);
	amdgpu_bo_unreserve(adev->gart.bo);
	return r;
}

/**
 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.bo == NULL) {
		return;
	}
	r = amdgpu_bo_reserve(adev->gart.bo, true);
	if (likely(r == 0)) {
		amdgpu_bo_kunmap(adev->gart.bo);
		amdgpu_bo_unpin(adev->gart.bo);
		amdgpu_bo_unreserve(adev->gart.bo);
		adev->gart.ptr = NULL;
	}
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	if (adev->gart.bo == NULL) {
		return;
	}
	amdgpu_bo_unref(&adev->gart.bo);
	adev->gart.ptr = NULL;
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;

	if (!adev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return -EINVAL;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++) {
		page_base = adev->dummy_page_addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
					       t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	mb();
	amdgpu_asic_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

	return 0;
}

/**
 * amdgpu_gart_map - map dma_addresses into GART entries
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 * @dst: CPU address of the gart table
 *
 * Map the dma_addresses into GART entries (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
		    int pages, dma_addr_t *dma_addr, uint64_t flags,
		    void *dst)
{
	uint64_t page_base;
	unsigned i, j, t;

	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;

	for (i = 0; i < pages; i++) {
		page_base = dma_addr[i];
		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint64_t flags)
{
	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	if (!adev->gart.ptr)
		return 0;

	return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
			       adev->gart.ptr);
}

/**
 * amdgpu_gart_invalidate_tlb - invalidate gart TLB
 *
 * @adev: amdgpu device driver pointer
 *
 * Invalidate gart TLB which can be use as a way to flush gart changes
 *
 */
void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
{
	int i;

	mb();
	amdgpu_asic_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page_addr)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_gart_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
fdf2f6c5 SR	28
	29	#include <linux/pci.h>
	30	#include <linux/vmalloc.h>
	31
d38ceaf9	32	#include <drm/amdgpu_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
d38ceaf9 AD	36	#include "amdgpu.h"
	37
	38	/*
	39	* GART
	40	* The GART (Graphics Aperture Remapping Table) is an aperture
	41	* in the GPU's address space. System pages can be mapped into
	42	* the aperture and look like contiguous pages from the GPU's
	43	* perspective. A page table maps the pages in the aperture
	44	* to the actual backing pages in system memory.
	45	*
	46	* Radeon GPUs support both an internal GART, as described above,
	47	* and AGP. AGP works similarly, but the GART table is configured
	48	* and maintained by the northbridge rather than the driver.
	49	* Radeon hw has a separate AGP aperture that is programmed to
	50	* point to the AGP aperture provided by the northbridge and the
	51	* requests are passed through to the northbridge aperture.
	52	* Both AGP and internal GART can be used at the same time, however
	53	* that is not currently supported by the driver.
	54	*
	55	* This file handles the common internal GART management.
	56	*/
	57
	58	/*
	59	* Common GART table functions.
	60	*/
011d4bbe	61
55e0037a	62	/**
777d9000	63	* amdgpu_gart_dummy_page_init - init dummy page used by the driver
55e0037a AD	64	*
	65	* @adev: amdgpu_device pointer
	66	*
	67	* Allocate the dummy page used by the driver (all asics).
	68	* This dummy page is used by the driver as a filler for gart entries
	69	* when pages are taken out of the GART
	70	* Returns 0 on sucess, -ENOMEM on failure.
	71	*/
	72	static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
	73	{
8af8a109	74	struct page *dummy_page = ttm_glob.dummy_read_page;
92e71b06 CK	75
92e71b06 CK	76	if (adev->dummy_page_addr)
55e0037a	77	return 0;
7dc7b65a	78	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
92e71b06	79	PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
7dc7b65a	80	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
55e0037a	81	dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
92e71b06	82	adev->dummy_page_addr = 0;
55e0037a AD	83	return -ENOMEM;
	84	}
	85	return 0;
	86	}
	87
	88	/**
777d9000	89	* amdgpu_gart_dummy_page_fini - free dummy page used by the driver
55e0037a AD	90	*
	91	* @adev: amdgpu_device pointer
	92	*
	93	* Frees the dummy page used by the driver (all asics).
	94	*/
d10d0daa	95	void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
55e0037a	96	{
92e71b06	97	if (!adev->dummy_page_addr)
55e0037a	98	return;
92e71b06 CK	99	pci_unmap_page(adev->pdev, adev->dummy_page_addr,
	100	PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
	101	adev->dummy_page_addr = 0;
55e0037a AD	102	}
55e0037a AD	103
d38ceaf9 AD	104	/**
	105	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
	106	*
	107	* @adev: amdgpu_device pointer
	108	*
	109	* Allocate video memory for GART page table
	110	* (pcie r4xx, r5xx+). These asics require the
	111	* gart table to be in video memory.
	112	* Returns 0 for success, error for failure.
	113	*/
	114	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
	115	{
ce1b1b66 ML	116	int r;
ce1b1b66 ML	117
1123b989	118	if (adev->gart.bo == NULL) {
3216c6b7 CZ	119	struct amdgpu_bo_param bp;
	120
	121	memset(&bp, 0, sizeof(bp));
	122	bp.size = adev->gart.table_size;
	123	bp.byte_align = PAGE_SIZE;
	124	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
	125	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
	126	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
	127	bp.type = ttm_bo_type_kernel;
	128	bp.resv = NULL;
9fd5543e ND	129	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
9fd5543e ND	130
1123b989	131	r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
ce1b1b66 ML	132	if (r) {
	133	return r;
	134	}
	135	}
	136	return 0;
	137	}
	138
	139	/**
	140	* amdgpu_gart_table_vram_pin - pin gart page table in vram
	141	*
	142	* @adev: amdgpu_device pointer
	143	*
	144	* Pin the GART page table in vram so it will not be moved
	145	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	146	* gart table to be in video memory.
	147	* Returns 0 for success, error for failure.
	148	*/
	149	int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
	150	{
ce1b1b66 ML	151	int r;
ce1b1b66 ML	152
1123b989	153	r = amdgpu_bo_reserve(adev->gart.bo, false);
ce1b1b66 ML	154	if (unlikely(r != 0))
ce1b1b66 ML	155	return r;
1123b989	156	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
ce1b1b66	157	if (r) {
1123b989	158	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	159	return r;
ce1b1b66 ML	160	}
1123b989	161	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
ce1b1b66	162	if (r)
1123b989 CK	163	amdgpu_bo_unpin(adev->gart.bo);
1123b989 CK	164	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	165	return r;
	166	}
	167
	168	/**
	169	* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
	170	*
	171	* @adev: amdgpu_device pointer
	172	*
	173	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	174	* These asics require the gart table to be in video memory.
	175	*/
	176	void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
	177	{
	178	int r;
	179
1123b989	180	if (adev->gart.bo == NULL) {
ce1b1b66 ML	181	return;
ce1b1b66 ML	182	}
1123b989	183	r = amdgpu_bo_reserve(adev->gart.bo, true);
ce1b1b66	184	if (likely(r == 0)) {
1123b989 CK	185	amdgpu_bo_kunmap(adev->gart.bo);
	186	amdgpu_bo_unpin(adev->gart.bo);
	187	amdgpu_bo_unreserve(adev->gart.bo);
ce1b1b66 ML	188	adev->gart.ptr = NULL;
ce1b1b66 ML	189	}
d38ceaf9 AD	190	}
	191
	192	/**
	193	* amdgpu_gart_table_vram_free - free gart page table vram
	194	*
	195	* @adev: amdgpu_device pointer
	196	*
	197	* Free the video memory used for the GART page table
	198	* (pcie r4xx, r5xx+). These asics require the gart table to
	199	* be in video memory.
	200	*/
	201	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	202	{
1123b989	203	if (adev->gart.bo == NULL) {
ce1b1b66 ML	204	return;
ce1b1b66 ML	205	}
1123b989	206	amdgpu_bo_unref(&adev->gart.bo);
a00aacdf	207	adev->gart.ptr = NULL;
d38ceaf9 AD	208	}
	209
	210	/*
	211	* Common gart functions.
	212	*/
	213	/**
	214	* amdgpu_gart_unbind - unbind pages from the gart page table
	215	*
	216	* @adev: amdgpu_device pointer
	217	* @offset: offset into the GPU's gart aperture
	218	* @pages: number of pages to unbind
	219	*
	220	* Unbinds the requested pages from the gart page table and
	221	* replaces them with the dummy page (all asics).
738f64cc	222	* Returns 0 for success, -EINVAL for failure.
d38ceaf9	223	*/
738f64cc	224	int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	225	int pages)
	226	{
	227	unsigned t;
	228	unsigned p;
	229	int i, j;
	230	u64 page_base;
a0676f60 AD	231	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	232	uint64_t flags = 0;
d38ceaf9 AD	233
	234	if (!adev->gart.ready) {
	235	WARN(1, "trying to unbind memory from uninitialized GART !\n");
738f64cc	236	return -EINVAL;
d38ceaf9 AD	237	}
	238
	239	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	240	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
d38ceaf9	241	for (i = 0; i < pages; i++, p++) {
92e71b06	242	page_base = adev->dummy_page_addr;
a1d29476 CK	243	if (!adev->gart.ptr)
a1d29476 CK	244	continue;
d38ceaf9	245
463d2fe8	246	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4 CK	247	amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
132f34e4 CK	248	t, page_base, flags);
a1d29476	249	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	250	}
	251	}
	252	mb();
69882565	253	amdgpu_asic_flush_hdp(adev, NULL);
3ff98548 OZ	254	for (i = 0; i < adev->num_vmhubs; i++)
	255	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
	256
738f64cc	257	return 0;
d38ceaf9 AD	258	}
d38ceaf9 AD	259
0c2c421e CK	260	/**
	261	* amdgpu_gart_map - map dma_addresses into GART entries
	262	*
	263	* @adev: amdgpu_device pointer
	264	* @offset: offset into the GPU's gart aperture
	265	* @pages: number of pages to bind
	266	* @dma_addr: DMA addresses of pages
5dcb668d OZ	267	* @flags: page table entry flags
5dcb668d OZ	268	* @dst: CPU address of the gart table
0c2c421e CK	269	*
	270	* Map the dma_addresses into GART entries (all asics).
	271	* Returns 0 for success, -EINVAL for failure.
	272	*/
	273	int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
	274	int pages, dma_addr_t *dma_addr, uint64_t flags,
	275	void *dst)
	276	{
	277	uint64_t page_base;
	278	unsigned i, j, t;
	279
	280	if (!adev->gart.ready) {
	281	WARN(1, "trying to bind memory to uninitialized GART !\n");
	282	return -EINVAL;
	283	}
	284
	285	t = offset / AMDGPU_GPU_PAGE_SIZE;
	286
	287	for (i = 0; i < pages; i++) {
	288	page_base = dma_addr[i];
463d2fe8	289	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4	290	amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
0c2c421e CK	291	page_base += AMDGPU_GPU_PAGE_SIZE;
	292	}
	293	}
	294	return 0;
	295	}
	296
d38ceaf9 AD	297	/**
	298	* amdgpu_gart_bind - bind pages into the gart page table
	299	*
	300	* @adev: amdgpu_device pointer
	301	* @offset: offset into the GPU's gart aperture
	302	* @pages: number of pages to bind
	303	* @pagelist: pages to bind
	304	* @dma_addr: DMA addresses of pages
e8b74035	305	* @flags: page table entry flags
d38ceaf9 AD	306	*
	307	* Binds the requested pages to the gart page table
	308	* (all asics).
	309	* Returns 0 for success, -EINVAL for failure.
	310	*/
cab0b8d5	311	int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9	312	int pages, struct page *pagelist, dma_addr_t dma_addr,
6b777607	313	uint64_t flags)
d38ceaf9	314	{
d38ceaf9 AD	315	if (!adev->gart.ready) {
	316	WARN(1, "trying to bind memory to uninitialized GART !\n");
	317	return -EINVAL;
	318	}
	319
fa2cd036 CK	320	if (!adev->gart.ptr)
	321	return 0;
	322
19a1d935 ND	323	return amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
	324	adev->gart.ptr);
	325	}
	326
	327	/**
	328	* amdgpu_gart_invalidate_tlb - invalidate gart TLB
	329	*
	330	* @adev: amdgpu device driver pointer
	331	*
	332	* Invalidate gart TLB which can be use as a way to flush gart changes
	333	*
	334	*/
	335	void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
	336	{
	337	int i;
0c2c421e	338
d38ceaf9	339	mb();
69882565	340	amdgpu_asic_flush_hdp(adev, NULL);
3ff98548 OZ	341	for (i = 0; i < adev->num_vmhubs; i++)
3ff98548 OZ	342	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
d38ceaf9 AD	343	}
	344
	345	/**
	346	* amdgpu_gart_init - init the driver info for managing the gart
	347	*
	348	* @adev: amdgpu_device pointer
	349	*
	350	* Allocate the dummy page and init the gart driver info (all asics).
	351	* Returns 0 for success, error for failure.
	352	*/
	353	int amdgpu_gart_init(struct amdgpu_device *adev)
	354	{
43251981	355	int r;
d38ceaf9	356
92e71b06	357	if (adev->dummy_page_addr)
d38ceaf9	358	return 0;
a1d29476	359
d38ceaf9 AD	360	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	361	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	362	DRM_ERROR("Page size is smaller than GPU page size!\n");
	363	return -EINVAL;
	364	}
55e0037a	365	r = amdgpu_gart_dummy_page_init(adev);
d38ceaf9 AD	366	if (r)
	367	return r;
	368	/* Compute table size */
770d13b1 CK	369	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
770d13b1 CK	370	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	371	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
d38ceaf9 AD	372	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	373
d38ceaf9 AD	374	return 0;
d38ceaf9 AD	375	}