[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */
/**
 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 * Returns 0 for success, -ENOMEM for failure.
 */
int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
{
	void *ptr;

	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
				   &adev->gart.table_addr);
	if (ptr == NULL) {
		return -ENOMEM;
	}
#ifdef CONFIG_X86
	if (0) {
		set_memory_uc((unsigned long)ptr,
			      adev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	adev->gart.ptr = ptr;
	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
	return 0;
}

/**
 * amdgpu_gart_table_ram_free - free system ram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Free system memory for GART page table
 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
 * gart table to be in system memory.
 */
void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
{
	if (adev->gart.ptr == NULL) {
		return;
	}
#ifdef CONFIG_X86
	if (0) {
		set_memory_wb((unsigned long)adev->gart.ptr,
			      adev->gart.table_size >> PAGE_SHIFT);
	}
#endif
	pci_free_consistent(adev->pdev, adev->gart.table_size,
			    (void *)adev->gart.ptr,
			    adev->gart.table_addr);
	adev->gart.ptr = NULL;
	adev->gart.table_addr = 0;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.robj == NULL) {
		r = amdgpu_bo_create(adev, adev->gart.table_size,
				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
				     AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
				     NULL, NULL, &adev->gart.robj);
		if (r) {
			return r;
		}
	}
	return 0;
}

/**
 * amdgpu_gart_table_vram_pin - pin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Pin the GART page table in vram so it will not be moved
 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
{
	uint64_t gpu_addr;
	int r;

	r = amdgpu_bo_reserve(adev->gart.robj, false);
	if (unlikely(r != 0))
		return r;
	r = amdgpu_bo_pin(adev->gart.robj,
				AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
	if (r) {
		amdgpu_bo_unreserve(adev->gart.robj);
		return r;
	}
	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
	if (r)
		amdgpu_bo_unpin(adev->gart.robj);
	amdgpu_bo_unreserve(adev->gart.robj);
	adev->gart.table_addr = gpu_addr;
	return r;
}

/**
 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
 *
 * @adev: amdgpu_device pointer
 *
 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
 * These asics require the gart table to be in video memory.
 */
void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
{
	int r;

	if (adev->gart.robj == NULL) {
		return;
	}
	r = amdgpu_bo_reserve(adev->gart.robj, true);
	if (likely(r == 0)) {
		amdgpu_bo_kunmap(adev->gart.robj);
		amdgpu_bo_unpin(adev->gart.robj);
		amdgpu_bo_unreserve(adev->gart.robj);
		adev->gart.ptr = NULL;
	}
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	if (adev->gart.robj == NULL) {
		return;
	}
	amdgpu_bo_unref(&adev->gart.robj);
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 */
void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;

	if (!adev->gart.ready) {
		WARN(1, "trying to unbind memory from uninitialized GART !\n");
		return;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
	for (i = 0; i < pages; i++, p++) {
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
		adev->gart.pages[p] = NULL;
#endif
		page_base = adev->dummy_page.addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
			amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
						t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	mb();
	amdgpu_gart_flush_gpu_tlb(adev, 0);
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @pagelist: pages to bind
 * @dma_addr: DMA addresses of pages
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
		     uint64_t flags)
{
	unsigned t;
	unsigned p;
	uint64_t page_base;
	int i, j;

	if (!adev->gart.ready) {
		WARN(1, "trying to bind memory to uninitialized GART !\n");
		return -EINVAL;
	}

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);

	for (i = 0; i < pages; i++, p++) {
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
		adev->gart.pages[p] = pagelist[i];
#endif
		if (adev->gart.ptr) {
			page_base = dma_addr[i];
			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
				page_base += AMDGPU_GPU_PAGE_SIZE;
			}
		}
	}
	mb();
	amdgpu_gart_flush_gpu_tlb(adev, 0);
	return 0;
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page.page)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	/* Allocate pages table */
	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
	if (adev->gart.pages == NULL) {
		amdgpu_gart_fini(adev);
		return -ENOMEM;
	}
#endif

	return 0;
}

/**
 * amdgpu_gart_fini - tear down the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Tear down the gart driver info and free the dummy page (all asics).
 */
void amdgpu_gart_fini(struct amdgpu_device *adev)
{
	if (adev->gart.ready) {
		/* unbind pages */
		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
	}
	adev->gart.ready = false;
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
	vfree(adev->gart.pages);
	adev->gart.pages = NULL;
#endif
	amdgpu_dummy_page_fini(adev);
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
	28	#include <drm/drmP.h>
	29	#include <drm/amdgpu_drm.h>
ed3ba079 LA	30	#ifdef CONFIG_X86
	31	#include <asm/set_memory.h>
	32	#endif
d38ceaf9 AD	33	#include "amdgpu.h"
	34
	35	/*
	36	* GART
	37	* The GART (Graphics Aperture Remapping Table) is an aperture
	38	* in the GPU's address space. System pages can be mapped into
	39	* the aperture and look like contiguous pages from the GPU's
	40	* perspective. A page table maps the pages in the aperture
	41	* to the actual backing pages in system memory.
	42	*
	43	* Radeon GPUs support both an internal GART, as described above,
	44	* and AGP. AGP works similarly, but the GART table is configured
	45	* and maintained by the northbridge rather than the driver.
	46	* Radeon hw has a separate AGP aperture that is programmed to
	47	* point to the AGP aperture provided by the northbridge and the
	48	* requests are passed through to the northbridge aperture.
	49	* Both AGP and internal GART can be used at the same time, however
	50	* that is not currently supported by the driver.
	51	*
	52	* This file handles the common internal GART management.
	53	*/
	54
	55	/*
	56	* Common GART table functions.
	57	*/
	58	/**
	59	* amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
	60	*
	61	* @adev: amdgpu_device pointer
	62	*
	63	* Allocate system memory for GART page table
	64	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	65	* gart table to be in system memory.
	66	* Returns 0 for success, -ENOMEM for failure.
	67	*/
	68	int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
	69	{
	70	void *ptr;
	71
	72	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
	73	&adev->gart.table_addr);
	74	if (ptr == NULL) {
	75	return -ENOMEM;
	76	}
	77	#ifdef CONFIG_X86
	78	if (0) {
	79	set_memory_uc((unsigned long)ptr,
	80	adev->gart.table_size >> PAGE_SHIFT);
	81	}
	82	#endif
	83	adev->gart.ptr = ptr;
	84	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
	85	return 0;
	86	}
	87
	88	/**
	89	* amdgpu_gart_table_ram_free - free system ram for gart page table
	90	*
	91	* @adev: amdgpu_device pointer
	92	*
	93	* Free system memory for GART page table
	94	* (r1xx-r3xx, non-pcie r4xx, rs400). These asics require the
	95	* gart table to be in system memory.
	96	*/
97	void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
98	{
99	if (adev->gart.ptr == NULL) {
100	return;
101	}
102	#ifdef CONFIG_X86
103	if (0) {
104	set_memory_wb((unsigned long)adev->gart.ptr,
105	adev->gart.table_size >> PAGE_SHIFT);
106	}
107	#endif
108	pci_free_consistent(adev->pdev, adev->gart.table_size,
109	(void *)adev->gart.ptr,
110	adev->gart.table_addr);
111	adev->gart.ptr = NULL;
112	adev->gart.table_addr = 0;
113	}
114
115	/**
116	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
117	*
118	* @adev: amdgpu_device pointer
119	*
120	* Allocate video memory for GART page table
121	* (pcie r4xx, r5xx+). These asics require the
122	* gart table to be in video memory.
123	* Returns 0 for success, error for failure.
124	*/
125	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
126	{
127	int r;
128
129	if (adev->gart.robj == NULL) {
130	r = amdgpu_bo_create(adev, adev->gart.table_size,
857d913d	131	PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
03f48dd5 CK	132	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
03f48dd5 CK	133	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
72d7668b	134	NULL, NULL, &adev->gart.robj);
d38ceaf9 AD	135	if (r) {
	136	return r;
	137	}
	138	}
	139	return 0;
	140	}
	141
	142	/**
	143	* amdgpu_gart_table_vram_pin - pin gart page table in vram
	144	*
	145	* @adev: amdgpu_device pointer
	146	*
	147	* Pin the GART page table in vram so it will not be moved
	148	* by the memory manager (pcie r4xx, r5xx+). These asics require the
	149	* gart table to be in video memory.
	150	* Returns 0 for success, error for failure.
	151	*/
	152	int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
	153	{
	154	uint64_t gpu_addr;
	155	int r;
	156
	157	r = amdgpu_bo_reserve(adev->gart.robj, false);
	158	if (unlikely(r != 0))
	159	return r;
	160	r = amdgpu_bo_pin(adev->gart.robj,
	161	AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
	162	if (r) {
	163	amdgpu_bo_unreserve(adev->gart.robj);
	164	return r;
	165	}
	166	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
	167	if (r)
	168	amdgpu_bo_unpin(adev->gart.robj);
	169	amdgpu_bo_unreserve(adev->gart.robj);
	170	adev->gart.table_addr = gpu_addr;
	171	return r;
	172	}
	173
	174	/**
	175	* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
	176	*
	177	* @adev: amdgpu_device pointer
	178	*
	179	* Unpin the GART page table in vram (pcie r4xx, r5xx+).
	180	* These asics require the gart table to be in video memory.
	181	*/
	182	void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
	183	{
	184	int r;
	185
	186	if (adev->gart.robj == NULL) {
	187	return;
	188	}
c81a1a74	189	r = amdgpu_bo_reserve(adev->gart.robj, true);
d38ceaf9 AD	190	if (likely(r == 0)) {
	191	amdgpu_bo_kunmap(adev->gart.robj);
	192	amdgpu_bo_unpin(adev->gart.robj);
	193	amdgpu_bo_unreserve(adev->gart.robj);
	194	adev->gart.ptr = NULL;
	195	}
	196	}
	197
	198	/**
	199	* amdgpu_gart_table_vram_free - free gart page table vram
	200	*
	201	* @adev: amdgpu_device pointer
	202	*
	203	* Free the video memory used for the GART page table
	204	* (pcie r4xx, r5xx+). These asics require the gart table to
	205	* be in video memory.
	206	*/
	207	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	208	{
	209	if (adev->gart.robj == NULL) {
	210	return;
	211	}
	212	amdgpu_bo_unref(&adev->gart.robj);
	213	}
	214
	215	/*
	216	* Common gart functions.
	217	*/
	218	/**
	219	* amdgpu_gart_unbind - unbind pages from the gart page table
	220	*
	221	* @adev: amdgpu_device pointer
	222	* @offset: offset into the GPU's gart aperture
	223	* @pages: number of pages to unbind
	224	*
	225	* Unbinds the requested pages from the gart page table and
	226	* replaces them with the dummy page (all asics).
	227	*/
cab0b8d5	228	void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	229	int pages)
	230	{
	231	unsigned t;
	232	unsigned p;
	233	int i, j;
	234	u64 page_base;
a0676f60 AD	235	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	236	uint64_t flags = 0;
d38ceaf9 AD	237
	238	if (!adev->gart.ready) {
	239	WARN(1, "trying to unbind memory from uninitialized GART !\n");
	240	return;
	241	}
	242
	243	t = offset / AMDGPU_GPU_PAGE_SIZE;
	244	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
	245	for (i = 0; i < pages; i++, p++) {
186294f9	246	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
a1d29476 CK	247	adev->gart.pages[p] = NULL;
	248	#endif
	249	page_base = adev->dummy_page.addr;
	250	if (!adev->gart.ptr)
	251	continue;
d38ceaf9	252
a1d29476 CK	253	for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
	254	amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
	255	t, page_base, flags);
	256	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	257	}
	258	}
	259	mb();
	260	amdgpu_gart_flush_gpu_tlb(adev, 0);
	261	}
	262
	263	/**
	264	* amdgpu_gart_bind - bind pages into the gart page table
	265	*
	266	* @adev: amdgpu_device pointer
	267	* @offset: offset into the GPU's gart aperture
	268	* @pages: number of pages to bind
	269	* @pagelist: pages to bind
	270	* @dma_addr: DMA addresses of pages
	271	*
	272	* Binds the requested pages to the gart page table
	273	* (all asics).
	274	* Returns 0 for success, -EINVAL for failure.
	275	*/
cab0b8d5	276	int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9	277	int pages, struct page *pagelist, dma_addr_t dma_addr,
6b777607	278	uint64_t flags)
d38ceaf9 AD	279	{
	280	unsigned t;
	281	unsigned p;
	282	uint64_t page_base;
	283	int i, j;
	284
	285	if (!adev->gart.ready) {
	286	WARN(1, "trying to bind memory to uninitialized GART !\n");
	287	return -EINVAL;
	288	}
	289
	290	t = offset / AMDGPU_GPU_PAGE_SIZE;
	291	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
	292
	293	for (i = 0; i < pages; i++, p++) {
186294f9	294	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9	295	adev->gart.pages[p] = pagelist[i];
a1d29476	296	#endif
d38ceaf9	297	if (adev->gart.ptr) {
43251981	298	page_base = dma_addr[i];
d38ceaf9 AD	299	for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
	300	amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
	301	page_base += AMDGPU_GPU_PAGE_SIZE;
	302	}
	303	}
	304	}
	305	mb();
	306	amdgpu_gart_flush_gpu_tlb(adev, 0);
	307	return 0;
	308	}
	309
	310	/**
	311	* amdgpu_gart_init - init the driver info for managing the gart
	312	*
	313	* @adev: amdgpu_device pointer
	314	*
	315	* Allocate the dummy page and init the gart driver info (all asics).
	316	* Returns 0 for success, error for failure.
	317	*/
	318	int amdgpu_gart_init(struct amdgpu_device *adev)
	319	{
43251981	320	int r;
d38ceaf9	321
a1d29476	322	if (adev->dummy_page.page)
d38ceaf9	323	return 0;
a1d29476	324
d38ceaf9 AD	325	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	326	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	327	DRM_ERROR("Page size is smaller than GPU page size!\n");
	328	return -EINVAL;
	329	}
	330	r = amdgpu_dummy_page_init(adev);
	331	if (r)
	332	return r;
	333	/* Compute table size */
	334	adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
	335	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
	336	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
	337	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	338
186294f9	339	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9 AD	340	/* Allocate pages table */
	341	adev->gart.pages = vzalloc(sizeof(void ) adev->gart.num_cpu_pages);
	342	if (adev->gart.pages == NULL) {
	343	amdgpu_gart_fini(adev);
	344	return -ENOMEM;
	345	}
a1d29476 CK	346	#endif
a1d29476 CK	347
d38ceaf9 AD	348	return 0;
	349	}
	350
	351	/**
	352	* amdgpu_gart_fini - tear down the driver info for managing the gart
	353	*
	354	* @adev: amdgpu_device pointer
	355	*
	356	* Tear down the gart driver info and free the dummy page (all asics).
	357	*/
	358	void amdgpu_gart_fini(struct amdgpu_device *adev)
	359	{
a1d29476	360	if (adev->gart.ready) {
d38ceaf9 AD	361	/* unbind pages */
	362	amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
	363	}
	364	adev->gart.ready = false;
186294f9	365	#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
d38ceaf9	366	vfree(adev->gart.pages);
d38ceaf9	367	adev->gart.pages = NULL;
a1d29476	368	#endif
d38ceaf9 AD	369	amdgpu_dummy_page_fini(adev);
d38ceaf9 AD	370	}