[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_gart.c

/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */

#include <linux/pci.h>
#include <linux/vmalloc.h>

#include <drm/amdgpu_drm.h>
#ifdef CONFIG_X86
#include <asm/set_memory.h>
#endif
#include "amdgpu.h"
#include <drm/drm_drv.h>

/*
 * GART
 * The GART (Graphics Aperture Remapping Table) is an aperture
 * in the GPU's address space.  System pages can be mapped into
 * the aperture and look like contiguous pages from the GPU's
 * perspective.  A page table maps the pages in the aperture
 * to the actual backing pages in system memory.
 *
 * Radeon GPUs support both an internal GART, as described above,
 * and AGP.  AGP works similarly, but the GART table is configured
 * and maintained by the northbridge rather than the driver.
 * Radeon hw has a separate AGP aperture that is programmed to
 * point to the AGP aperture provided by the northbridge and the
 * requests are passed through to the northbridge aperture.
 * Both AGP and internal GART can be used at the same time, however
 * that is not currently supported by the driver.
 *
 * This file handles the common internal GART management.
 */

/*
 * Common GART table functions.
 */

/**
 * amdgpu_gart_dummy_page_init - init dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page used by the driver (all asics).
 * This dummy page is used by the driver as a filler for gart entries
 * when pages are taken out of the GART
 * Returns 0 on sucess, -ENOMEM on failure.
 */
static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
{
	struct page *dummy_page = ttm_glob.dummy_read_page;

	if (adev->dummy_page_addr)
		return 0;
	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
					     PAGE_SIZE, DMA_BIDIRECTIONAL);
	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
		dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
		adev->dummy_page_addr = 0;
		return -ENOMEM;
	}
	return 0;
}

/**
 * amdgpu_gart_dummy_page_fini - free dummy page used by the driver
 *
 * @adev: amdgpu_device pointer
 *
 * Frees the dummy page used by the driver (all asics).
 */
void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
{
	if (!adev->dummy_page_addr)
		return;
	dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
		       DMA_BIDIRECTIONAL);
	adev->dummy_page_addr = 0;
}

/**
 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate video memory for GART page table
 * (pcie r4xx, r5xx+).  These asics require the
 * gart table to be in video memory.
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
{
	if (adev->gart.bo != NULL)
		return 0;

	return amdgpu_bo_create_kernel(adev,  adev->gart.table_size, PAGE_SIZE,
				       AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo,
				       NULL, (void *)&adev->gart.ptr);
}

/**
 * amdgpu_gart_table_vram_free - free gart page table vram
 *
 * @adev: amdgpu_device pointer
 *
 * Free the video memory used for the GART page table
 * (pcie r4xx, r5xx+).  These asics require the gart table to
 * be in video memory.
 */
void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
{
	amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr);
}

/*
 * Common gart functions.
 */
/**
 * amdgpu_gart_unbind - unbind pages from the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to unbind
 *
 * Unbinds the requested pages from the gart page table and
 * replaces them with the dummy page (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
			int pages)
{
	unsigned t;
	unsigned p;
	int i, j;
	u64 page_base;
	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
	uint64_t flags = 0;
	int idx;

	if (!adev->gart.ptr)
		return;

	if (!drm_dev_enter(adev_to_drm(adev), &idx))
		return;

	t = offset / AMDGPU_GPU_PAGE_SIZE;
	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
	for (i = 0; i < pages; i++, p++) {
		page_base = adev->dummy_page_addr;
		if (!adev->gart.ptr)
			continue;

		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
					       t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	mb();
	amdgpu_device_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

	drm_dev_exit(idx);
}

/**
 * amdgpu_gart_map - map dma_addresses into GART entries
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 * @dst: CPU address of the gart table
 *
 * Map the dma_addresses into GART entries (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
		    int pages, dma_addr_t *dma_addr, uint64_t flags,
		    void *dst)
{
	uint64_t page_base;
	unsigned i, j, t;
	int idx;

	if (!drm_dev_enter(adev_to_drm(adev), &idx))
		return;

	t = offset / AMDGPU_GPU_PAGE_SIZE;

	for (i = 0; i < pages; i++) {
		page_base = dma_addr[i];
		for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
			amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
			page_base += AMDGPU_GPU_PAGE_SIZE;
		}
	}
	drm_dev_exit(idx);
}

/**
 * amdgpu_gart_bind - bind pages into the gart page table
 *
 * @adev: amdgpu_device pointer
 * @offset: offset into the GPU's gart aperture
 * @pages: number of pages to bind
 * @dma_addr: DMA addresses of pages
 * @flags: page table entry flags
 *
 * Binds the requested pages to the gart page table
 * (all asics).
 * Returns 0 for success, -EINVAL for failure.
 */
void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
		     int pages, dma_addr_t *dma_addr,
		     uint64_t flags)
{
	if (!adev->gart.ptr)
		return;

	amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr);
}

/**
 * amdgpu_gart_invalidate_tlb - invalidate gart TLB
 *
 * @adev: amdgpu device driver pointer
 *
 * Invalidate gart TLB which can be use as a way to flush gart changes
 *
 */
void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
{
	int i;

	if (!adev->gart.ptr)
		return;

	mb();
	amdgpu_device_flush_hdp(adev, NULL);
	for (i = 0; i < adev->num_vmhubs; i++)
		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
}

/**
 * amdgpu_gart_init - init the driver info for managing the gart
 *
 * @adev: amdgpu_device pointer
 *
 * Allocate the dummy page and init the gart driver info (all asics).
 * Returns 0 for success, error for failure.
 */
int amdgpu_gart_init(struct amdgpu_device *adev)
{
	int r;

	if (adev->dummy_page_addr)
		return 0;

	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
		DRM_ERROR("Page size is smaller than GPU page size!\n");
		return -EINVAL;
	}
	r = amdgpu_gart_dummy_page_init(adev);
	if (r)
		return r;
	/* Compute table size */
	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);

	return 0;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright 2008 Advanced Micro Devices, Inc.
	3	* Copyright 2008 Red Hat Inc.
	4	* Copyright 2009 Jerome Glisse.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors: Dave Airlie
	25	* Alex Deucher
	26	* Jerome Glisse
	27	*/
fdf2f6c5 SR	28
	29	#include <linux/pci.h>
	30	#include <linux/vmalloc.h>
	31
d38ceaf9	32	#include <drm/amdgpu_drm.h>
ed3ba079 LA	33	#ifdef CONFIG_X86
	34	#include <asm/set_memory.h>
	35	#endif
d38ceaf9	36	#include "amdgpu.h"
b2fe31cf	37	#include <drm/drm_drv.h>
d38ceaf9 AD	38
	39	/*
	40	* GART
	41	* The GART (Graphics Aperture Remapping Table) is an aperture
	42	* in the GPU's address space. System pages can be mapped into
	43	* the aperture and look like contiguous pages from the GPU's
	44	* perspective. A page table maps the pages in the aperture
	45	* to the actual backing pages in system memory.
	46	*
	47	* Radeon GPUs support both an internal GART, as described above,
	48	* and AGP. AGP works similarly, but the GART table is configured
	49	* and maintained by the northbridge rather than the driver.
	50	* Radeon hw has a separate AGP aperture that is programmed to
	51	* point to the AGP aperture provided by the northbridge and the
	52	* requests are passed through to the northbridge aperture.
	53	* Both AGP and internal GART can be used at the same time, however
	54	* that is not currently supported by the driver.
	55	*
	56	* This file handles the common internal GART management.
	57	*/
	58
	59	/*
	60	* Common GART table functions.
	61	*/
011d4bbe	62
55e0037a	63	/**
777d9000	64	* amdgpu_gart_dummy_page_init - init dummy page used by the driver
55e0037a AD	65	*
	66	* @adev: amdgpu_device pointer
	67	*
	68	* Allocate the dummy page used by the driver (all asics).
	69	* This dummy page is used by the driver as a filler for gart entries
	70	* when pages are taken out of the GART
	71	* Returns 0 on sucess, -ENOMEM on failure.
	72	*/
	73	static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
	74	{
8af8a109	75	struct page *dummy_page = ttm_glob.dummy_read_page;
92e71b06 CK	76
92e71b06 CK	77	if (adev->dummy_page_addr)
55e0037a	78	return 0;
7dc7b65a	79	adev->dummy_page_addr = dma_map_page(&adev->pdev->dev, dummy_page, 0,
8a1d1bdb	80	PAGE_SIZE, DMA_BIDIRECTIONAL);
7dc7b65a	81	if (dma_mapping_error(&adev->pdev->dev, adev->dummy_page_addr)) {
55e0037a	82	dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
92e71b06	83	adev->dummy_page_addr = 0;
55e0037a AD	84	return -ENOMEM;
	85	}
	86	return 0;
	87	}
	88
	89	/**
777d9000	90	* amdgpu_gart_dummy_page_fini - free dummy page used by the driver
55e0037a AD	91	*
	92	* @adev: amdgpu_device pointer
	93	*
	94	* Frees the dummy page used by the driver (all asics).
	95	*/
d10d0daa	96	void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
55e0037a	97	{
92e71b06	98	if (!adev->dummy_page_addr)
55e0037a	99	return;
8a1d1bdb CJ	100	dma_unmap_page(&adev->pdev->dev, adev->dummy_page_addr, PAGE_SIZE,
8a1d1bdb CJ	101	DMA_BIDIRECTIONAL);
92e71b06	102	adev->dummy_page_addr = 0;
55e0037a AD	103	}
55e0037a AD	104
d38ceaf9 AD	105	/**
	106	* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
	107	*
	108	* @adev: amdgpu_device pointer
	109	*
	110	* Allocate video memory for GART page table
	111	* (pcie r4xx, r5xx+). These asics require the
	112	* gart table to be in video memory.
	113	* Returns 0 for success, error for failure.
	114	*/
	115	int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
	116	{
575e55ee ND	117	if (adev->gart.bo != NULL)
575e55ee ND	118	return 0;
ce1b1b66	119
575e55ee ND	120	return amdgpu_bo_create_kernel(adev, adev->gart.table_size, PAGE_SIZE,
	121	AMDGPU_GEM_DOMAIN_VRAM, &adev->gart.bo,
	122	NULL, (void *)&adev->gart.ptr);
d38ceaf9 AD	123	}
	124
	125	/**
	126	* amdgpu_gart_table_vram_free - free gart page table vram
	127	*
	128	* @adev: amdgpu_device pointer
	129	*
	130	* Free the video memory used for the GART page table
	131	* (pcie r4xx, r5xx+). These asics require the gart table to
	132	* be in video memory.
	133	*/
	134	void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
	135	{
575e55ee	136	amdgpu_bo_free_kernel(&adev->gart.bo, NULL, (void *)&adev->gart.ptr);
d38ceaf9 AD	137	}
	138
	139	/*
	140	* Common gart functions.
	141	*/
	142	/**
	143	* amdgpu_gart_unbind - unbind pages from the gart page table
	144	*
	145	* @adev: amdgpu_device pointer
	146	* @offset: offset into the GPU's gart aperture
	147	* @pages: number of pages to unbind
	148	*
	149	* Unbinds the requested pages from the gart page table and
	150	* replaces them with the dummy page (all asics).
738f64cc	151	* Returns 0 for success, -EINVAL for failure.
d38ceaf9	152	*/
1b08dfb8	153	void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
d38ceaf9 AD	154	int pages)
	155	{
	156	unsigned t;
	157	unsigned p;
	158	int i, j;
	159	u64 page_base;
a0676f60 AD	160	/* Starting from VEGA10, system bit must be 0 to mean invalid. */
a0676f60 AD	161	uint64_t flags = 0;
b2fe31cf	162	int idx;
d38ceaf9	163
f9130b81	164	if (!adev->gart.ptr)
1b08dfb8	165	return;
d38ceaf9	166
c58a863b	167	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1b08dfb8	168	return;
b2fe31cf	169
d38ceaf9	170	t = offset / AMDGPU_GPU_PAGE_SIZE;
463d2fe8	171	p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
d38ceaf9	172	for (i = 0; i < pages; i++, p++) {
92e71b06	173	page_base = adev->dummy_page_addr;
a1d29476 CK	174	if (!adev->gart.ptr)
a1d29476 CK	175	continue;
d38ceaf9	176
463d2fe8	177	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4 CK	178	amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
132f34e4 CK	179	t, page_base, flags);
a1d29476	180	page_base += AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	181	}
	182	}
	183	mb();
810085dd	184	amdgpu_device_flush_hdp(adev, NULL);
3ff98548 OZ	185	for (i = 0; i < adev->num_vmhubs; i++)
	186	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
	187
b2fe31cf	188	drm_dev_exit(idx);
d38ceaf9 AD	189	}
d38ceaf9 AD	190
0c2c421e CK	191	/**
	192	* amdgpu_gart_map - map dma_addresses into GART entries
	193	*
	194	* @adev: amdgpu_device pointer
	195	* @offset: offset into the GPU's gart aperture
	196	* @pages: number of pages to bind
	197	* @dma_addr: DMA addresses of pages
5dcb668d OZ	198	* @flags: page table entry flags
5dcb668d OZ	199	* @dst: CPU address of the gart table
0c2c421e CK	200	*
	201	* Map the dma_addresses into GART entries (all asics).
	202	* Returns 0 for success, -EINVAL for failure.
	203	*/
1b08dfb8	204	void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
0c2c421e CK	205	int pages, dma_addr_t *dma_addr, uint64_t flags,
	206	void *dst)
	207	{
	208	uint64_t page_base;
	209	unsigned i, j, t;
b2fe31cf	210	int idx;
0c2c421e	211
c58a863b	212	if (!drm_dev_enter(adev_to_drm(adev), &idx))
1b08dfb8	213	return;
b2fe31cf	214
0c2c421e CK	215	t = offset / AMDGPU_GPU_PAGE_SIZE;
	216
	217	for (i = 0; i < pages; i++) {
	218	page_base = dma_addr[i];
463d2fe8	219	for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
132f34e4	220	amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
0c2c421e CK	221	page_base += AMDGPU_GPU_PAGE_SIZE;
	222	}
	223	}
b2fe31cf	224	drm_dev_exit(idx);
0c2c421e CK	225	}
0c2c421e CK	226
d38ceaf9 AD	227	/**
	228	* amdgpu_gart_bind - bind pages into the gart page table
	229	*
	230	* @adev: amdgpu_device pointer
	231	* @offset: offset into the GPU's gart aperture
	232	* @pages: number of pages to bind
d38ceaf9	233	* @dma_addr: DMA addresses of pages
e8b74035	234	* @flags: page table entry flags
d38ceaf9 AD	235	*
	236	* Binds the requested pages to the gart page table
	237	* (all asics).
	238	* Returns 0 for success, -EINVAL for failure.
	239	*/
1b08dfb8	240	void amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
942ab769	241	int pages, dma_addr_t *dma_addr,
6b777607	242	uint64_t flags)
d38ceaf9	243	{
f9130b81	244	if (!adev->gart.ptr)
1b08dfb8	245	return;
fa2cd036	246
1b08dfb8	247	amdgpu_gart_map(adev, offset, pages, dma_addr, flags, adev->gart.ptr);
19a1d935 ND	248	}
	249
	250	/**
	251	* amdgpu_gart_invalidate_tlb - invalidate gart TLB
	252	*
	253	* @adev: amdgpu device driver pointer
	254	*
	255	* Invalidate gart TLB which can be use as a way to flush gart changes
	256	*
	257	*/
	258	void amdgpu_gart_invalidate_tlb(struct amdgpu_device *adev)
	259	{
	260	int i;
0c2c421e	261
29ba7b16 AL	262	if (!adev->gart.ptr)
	263	return;
	264
d38ceaf9	265	mb();
810085dd	266	amdgpu_device_flush_hdp(adev, NULL);
3ff98548 OZ	267	for (i = 0; i < adev->num_vmhubs; i++)
3ff98548 OZ	268	amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);
d38ceaf9 AD	269	}
	270
	271	/**
	272	* amdgpu_gart_init - init the driver info for managing the gart
	273	*
	274	* @adev: amdgpu_device pointer
	275	*
	276	* Allocate the dummy page and init the gart driver info (all asics).
	277	* Returns 0 for success, error for failure.
	278	*/
	279	int amdgpu_gart_init(struct amdgpu_device *adev)
	280	{
43251981	281	int r;
d38ceaf9	282
92e71b06	283	if (adev->dummy_page_addr)
d38ceaf9	284	return 0;
a1d29476	285
d38ceaf9 AD	286	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
	287	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
	288	DRM_ERROR("Page size is smaller than GPU page size!\n");
	289	return -EINVAL;
	290	}
55e0037a	291	r = amdgpu_gart_dummy_page_init(adev);
d38ceaf9 AD	292	if (r)
	293	return r;
	294	/* Compute table size */
770d13b1 CK	295	adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
770d13b1 CK	296	adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
d38ceaf9 AD	297	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
d38ceaf9 AD	298	adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
a1d29476	299
d38ceaf9 AD	300	return 0;
d38ceaf9 AD	301	}