Commit | Line | Data |
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d38ceaf9 AD |
1 | /* |
2 | * Copyright © 2007 David Airlie | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * David Airlie | |
25 | */ | |
fdf2f6c5 | 26 | |
d38ceaf9 | 27 | #include <linux/module.h> |
7c1fa1db | 28 | #include <linux/pm_runtime.h> |
fdf2f6c5 SR |
29 | #include <linux/slab.h> |
30 | #include <linux/vga_switcheroo.h> | |
d38ceaf9 | 31 | |
fdf2f6c5 | 32 | #include <drm/amdgpu_drm.h> |
d38ceaf9 AD |
33 | #include <drm/drm_crtc.h> |
34 | #include <drm/drm_crtc_helper.h> | |
fdf2f6c5 SR |
35 | #include <drm/drm_fb_helper.h> |
36 | #include <drm/drm_fourcc.h> | |
37 | ||
d38ceaf9 | 38 | #include "amdgpu.h" |
fbd76d59 | 39 | #include "cikd.h" |
2cddc50e | 40 | #include "amdgpu_gem.h" |
d38ceaf9 | 41 | |
5d43be0c CK |
42 | #include "amdgpu_display.h" |
43 | ||
d38ceaf9 AD |
44 | /* object hierarchy - |
45 | this contains a helper + a amdgpu fb | |
46 | the helper contains a pointer to amdgpu framebuffer baseclass. | |
47 | */ | |
d38ceaf9 | 48 | |
7c1fa1db AD |
49 | static int |
50 | amdgpufb_open(struct fb_info *info, int user) | |
51 | { | |
bb1c08f9 DV |
52 | struct drm_fb_helper *fb_helper = info->par; |
53 | int ret = pm_runtime_get_sync(fb_helper->dev->dev); | |
7c1fa1db | 54 | if (ret < 0 && ret != -EACCES) { |
bb1c08f9 DV |
55 | pm_runtime_mark_last_busy(fb_helper->dev->dev); |
56 | pm_runtime_put_autosuspend(fb_helper->dev->dev); | |
7c1fa1db AD |
57 | return ret; |
58 | } | |
59 | return 0; | |
60 | } | |
61 | ||
62 | static int | |
63 | amdgpufb_release(struct fb_info *info, int user) | |
64 | { | |
bb1c08f9 | 65 | struct drm_fb_helper *fb_helper = info->par; |
7c1fa1db | 66 | |
bb1c08f9 DV |
67 | pm_runtime_mark_last_busy(fb_helper->dev->dev); |
68 | pm_runtime_put_autosuspend(fb_helper->dev->dev); | |
7c1fa1db AD |
69 | return 0; |
70 | } | |
71 | ||
b6ff753a | 72 | static const struct fb_ops amdgpufb_ops = { |
d38ceaf9 | 73 | .owner = THIS_MODULE, |
ea4ffffe | 74 | DRM_FB_HELPER_DEFAULT_OPS, |
7c1fa1db AD |
75 | .fb_open = amdgpufb_open, |
76 | .fb_release = amdgpufb_release, | |
2dbaf392 AT |
77 | .fb_fillrect = drm_fb_helper_cfb_fillrect, |
78 | .fb_copyarea = drm_fb_helper_cfb_copyarea, | |
79 | .fb_imageblit = drm_fb_helper_cfb_imageblit, | |
d38ceaf9 AD |
80 | }; |
81 | ||
82 | ||
8e911ab7 | 83 | int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) |
d38ceaf9 AD |
84 | { |
85 | int aligned = width; | |
86 | int pitch_mask = 0; | |
87 | ||
8e911ab7 | 88 | switch (cpp) { |
d38ceaf9 AD |
89 | case 1: |
90 | pitch_mask = 255; | |
91 | break; | |
92 | case 2: | |
93 | pitch_mask = 127; | |
94 | break; | |
95 | case 3: | |
96 | case 4: | |
97 | pitch_mask = 63; | |
98 | break; | |
99 | } | |
100 | ||
101 | aligned += pitch_mask; | |
102 | aligned &= ~pitch_mask; | |
8e911ab7 | 103 | return aligned * cpp; |
d38ceaf9 AD |
104 | } |
105 | ||
106 | static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) | |
107 | { | |
765e7fbf | 108 | struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); |
d38ceaf9 AD |
109 | int ret; |
110 | ||
c81a1a74 | 111 | ret = amdgpu_bo_reserve(abo, true); |
d38ceaf9 | 112 | if (likely(ret == 0)) { |
765e7fbf CK |
113 | amdgpu_bo_kunmap(abo); |
114 | amdgpu_bo_unpin(abo); | |
115 | amdgpu_bo_unreserve(abo); | |
d38ceaf9 | 116 | } |
e07ddb0c | 117 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
118 | } |
119 | ||
120 | static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, | |
121 | struct drm_mode_fb_cmd2 *mode_cmd, | |
122 | struct drm_gem_object **gobj_p) | |
123 | { | |
92f08076 | 124 | const struct drm_format_info *info; |
d38ceaf9 AD |
125 | struct amdgpu_device *adev = rfbdev->adev; |
126 | struct drm_gem_object *gobj = NULL; | |
765e7fbf | 127 | struct amdgpu_bo *abo = NULL; |
d38ceaf9 | 128 | bool fb_tiled = false; /* useful for testing */ |
5d43be0c | 129 | u32 tiling_flags = 0, domain; |
d38ceaf9 AD |
130 | int ret; |
131 | int aligned_size, size; | |
132 | int height = mode_cmd->height; | |
8e911ab7 | 133 | u32 cpp; |
f2bd8a0e AG |
134 | u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | |
135 | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | | |
a6aacb2b | 136 | AMDGPU_GEM_CREATE_VRAM_CLEARED; |
d38ceaf9 | 137 | |
4a580877 | 138 | info = drm_get_format_info(adev_to_drm(adev), mode_cmd); |
b0f986b4 | 139 | cpp = info->cpp[0]; |
d38ceaf9 AD |
140 | |
141 | /* need to align pitch with crtc limits */ | |
8e911ab7 LP |
142 | mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, |
143 | fb_tiled); | |
f2bd8a0e | 144 | domain = amdgpu_display_supported_domains(adev, flags); |
d38ceaf9 AD |
145 | height = ALIGN(mode_cmd->height, 8); |
146 | size = mode_cmd->pitches[0] * height; | |
147 | aligned_size = ALIGN(size, PAGE_SIZE); | |
f2bd8a0e | 148 | ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, |
e5e6666d | 149 | ttm_bo_type_device, NULL, &gobj); |
d38ceaf9 | 150 | if (ret) { |
7ca85295 | 151 | pr_err("failed to allocate framebuffer (%d)\n", aligned_size); |
d38ceaf9 AD |
152 | return -ENOMEM; |
153 | } | |
765e7fbf | 154 | abo = gem_to_amdgpu_bo(gobj); |
d38ceaf9 AD |
155 | |
156 | if (fb_tiled) | |
fbd76d59 | 157 | tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); |
d38ceaf9 | 158 | |
765e7fbf | 159 | ret = amdgpu_bo_reserve(abo, false); |
d38ceaf9 AD |
160 | if (unlikely(ret != 0)) |
161 | goto out_unref; | |
162 | ||
163 | if (tiling_flags) { | |
765e7fbf | 164 | ret = amdgpu_bo_set_tiling_flags(abo, |
63ab1c2b | 165 | tiling_flags); |
d38ceaf9 AD |
166 | if (ret) |
167 | dev_err(adev->dev, "FB failed to set tiling flags\n"); | |
168 | } | |
169 | ||
7b7c6c81 | 170 | ret = amdgpu_bo_pin(abo, domain); |
d38ceaf9 | 171 | if (ret) { |
765e7fbf | 172 | amdgpu_bo_unreserve(abo); |
d38ceaf9 AD |
173 | goto out_unref; |
174 | } | |
bb812f1e JZ |
175 | |
176 | ret = amdgpu_ttm_alloc_gart(&abo->tbo); | |
177 | if (ret) { | |
178 | amdgpu_bo_unreserve(abo); | |
179 | dev_err(adev->dev, "%p bind failed\n", abo); | |
180 | goto out_unref; | |
181 | } | |
182 | ||
765e7fbf CK |
183 | ret = amdgpu_bo_kmap(abo, NULL); |
184 | amdgpu_bo_unreserve(abo); | |
d38ceaf9 AD |
185 | if (ret) { |
186 | goto out_unref; | |
187 | } | |
188 | ||
189 | *gobj_p = gobj; | |
190 | return 0; | |
191 | out_unref: | |
192 | amdgpufb_destroy_pinned_object(gobj); | |
193 | *gobj_p = NULL; | |
194 | return ret; | |
195 | } | |
196 | ||
197 | static int amdgpufb_create(struct drm_fb_helper *helper, | |
198 | struct drm_fb_helper_surface_size *sizes) | |
199 | { | |
200 | struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; | |
201 | struct amdgpu_device *adev = rfbdev->adev; | |
202 | struct fb_info *info; | |
203 | struct drm_framebuffer *fb = NULL; | |
204 | struct drm_mode_fb_cmd2 mode_cmd; | |
205 | struct drm_gem_object *gobj = NULL; | |
765e7fbf | 206 | struct amdgpu_bo *abo = NULL; |
d38ceaf9 | 207 | int ret; |
d38ceaf9 | 208 | |
53f4cb8b | 209 | memset(&mode_cmd, 0, sizeof(mode_cmd)); |
d38ceaf9 AD |
210 | mode_cmd.width = sizes->surface_width; |
211 | mode_cmd.height = sizes->surface_height; | |
212 | ||
213 | if (sizes->surface_bpp == 24) | |
214 | sizes->surface_bpp = 32; | |
215 | ||
216 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, | |
217 | sizes->surface_depth); | |
218 | ||
219 | ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); | |
220 | if (ret) { | |
221 | DRM_ERROR("failed to create fbcon object %d\n", ret); | |
222 | return ret; | |
223 | } | |
224 | ||
765e7fbf | 225 | abo = gem_to_amdgpu_bo(gobj); |
d38ceaf9 AD |
226 | |
227 | /* okay we have an object now allocate the framebuffer */ | |
2dbaf392 AT |
228 | info = drm_fb_helper_alloc_fbi(helper); |
229 | if (IS_ERR(info)) { | |
230 | ret = PTR_ERR(info); | |
da7bdda2 | 231 | goto out; |
d38ceaf9 AD |
232 | } |
233 | ||
f258907f MY |
234 | ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, |
235 | &mode_cmd, gobj); | |
d38ceaf9 AD |
236 | if (ret) { |
237 | DRM_ERROR("failed to initialize framebuffer %d\n", ret); | |
da7bdda2 | 238 | goto out; |
d38ceaf9 AD |
239 | } |
240 | ||
241 | fb = &rfbdev->rfb.base; | |
242 | ||
243 | /* setup helper */ | |
244 | rfbdev->helper.fb = fb; | |
d38ceaf9 | 245 | |
d38ceaf9 AD |
246 | info->fbops = &amdgpufb_ops; |
247 | ||
0ca565ab | 248 | info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); |
765e7fbf | 249 | info->fix.smem_len = amdgpu_bo_size(abo); |
f5e1c740 | 250 | info->screen_base = amdgpu_bo_kptr(abo); |
765e7fbf | 251 | info->screen_size = amdgpu_bo_size(abo); |
d38ceaf9 | 252 | |
bb1c08f9 | 253 | drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); |
d38ceaf9 AD |
254 | |
255 | /* setup aperture base/size for vesafb takeover */ | |
4a580877 | 256 | info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; |
770d13b1 | 257 | info->apertures->ranges[0].size = adev->gmc.aper_size; |
d38ceaf9 AD |
258 | |
259 | /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ | |
260 | ||
261 | if (info->screen_base == NULL) { | |
262 | ret = -ENOSPC; | |
da7bdda2 | 263 | goto out; |
d38ceaf9 AD |
264 | } |
265 | ||
266 | DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); | |
770d13b1 | 267 | DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); |
765e7fbf | 268 | DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); |
b00c600e | 269 | DRM_INFO("fb depth is %d\n", fb->format->depth); |
d38ceaf9 AD |
270 | DRM_INFO(" pitch is %d\n", fb->pitches[0]); |
271 | ||
8f66090b | 272 | vga_switcheroo_client_fb_set(adev->pdev, info); |
d38ceaf9 AD |
273 | return 0; |
274 | ||
da7bdda2 | 275 | out: |
765e7fbf | 276 | if (abo) { |
d38ceaf9 AD |
277 | |
278 | } | |
279 | if (fb && ret) { | |
e07ddb0c | 280 | drm_gem_object_put(gobj); |
d38ceaf9 AD |
281 | drm_framebuffer_unregister_private(fb); |
282 | drm_framebuffer_cleanup(fb); | |
283 | kfree(fb); | |
284 | } | |
285 | return ret; | |
286 | } | |
287 | ||
d38ceaf9 AD |
288 | static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) |
289 | { | |
d38ceaf9 AD |
290 | struct amdgpu_framebuffer *rfb = &rfbdev->rfb; |
291 | ||
2dbaf392 | 292 | drm_fb_helper_unregister_fbi(&rfbdev->helper); |
d38ceaf9 | 293 | |
e68d14dd DS |
294 | if (rfb->base.obj[0]) { |
295 | amdgpufb_destroy_pinned_object(rfb->base.obj[0]); | |
296 | rfb->base.obj[0] = NULL; | |
a072c5f8 MD |
297 | drm_framebuffer_unregister_private(&rfb->base); |
298 | drm_framebuffer_cleanup(&rfb->base); | |
d38ceaf9 AD |
299 | } |
300 | drm_fb_helper_fini(&rfbdev->helper); | |
d38ceaf9 AD |
301 | |
302 | return 0; | |
303 | } | |
304 | ||
d38ceaf9 | 305 | static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { |
d38ceaf9 AD |
306 | .fb_probe = amdgpufb_create, |
307 | }; | |
308 | ||
309 | int amdgpu_fbdev_init(struct amdgpu_device *adev) | |
310 | { | |
311 | struct amdgpu_fbdev *rfbdev; | |
312 | int bpp_sel = 32; | |
313 | int ret; | |
314 | ||
315 | /* don't init fbdev on hw without DCE */ | |
316 | if (!adev->mode_info.mode_config_initialized) | |
317 | return 0; | |
318 | ||
f49d45c9 | 319 | /* don't init fbdev if there are no connectors */ |
4a580877 | 320 | if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) |
f49d45c9 AD |
321 | return 0; |
322 | ||
d38ceaf9 | 323 | /* select 8 bpp console on low vram cards */ |
770d13b1 | 324 | if (adev->gmc.real_vram_size <= (32*1024*1024)) |
d38ceaf9 AD |
325 | bpp_sel = 8; |
326 | ||
327 | rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); | |
328 | if (!rfbdev) | |
329 | return -ENOMEM; | |
330 | ||
331 | rfbdev->adev = adev; | |
332 | adev->mode_info.rfbdev = rfbdev; | |
333 | ||
4a580877 LT |
334 | drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, |
335 | &amdgpu_fb_helper_funcs); | |
d38ceaf9 | 336 | |
4a580877 | 337 | ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); |
d38ceaf9 AD |
338 | if (ret) { |
339 | kfree(rfbdev); | |
340 | return ret; | |
341 | } | |
342 | ||
d38ceaf9 | 343 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
93b8ca9b | 344 | if (!amdgpu_device_has_dc_support(adev)) |
4a580877 | 345 | drm_helper_disable_unused_functions(adev_to_drm(adev)); |
d38ceaf9 AD |
346 | |
347 | drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); | |
348 | return 0; | |
349 | } | |
350 | ||
351 | void amdgpu_fbdev_fini(struct amdgpu_device *adev) | |
352 | { | |
353 | if (!adev->mode_info.rfbdev) | |
354 | return; | |
355 | ||
4a580877 | 356 | amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); |
d38ceaf9 AD |
357 | kfree(adev->mode_info.rfbdev); |
358 | adev->mode_info.rfbdev = NULL; | |
359 | } | |
360 | ||
361 | void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) | |
362 | { | |
363 | if (adev->mode_info.rfbdev) | |
ecb8c503 S |
364 | drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, |
365 | state); | |
d38ceaf9 AD |
366 | } |
367 | ||
368 | int amdgpu_fbdev_total_size(struct amdgpu_device *adev) | |
369 | { | |
370 | struct amdgpu_bo *robj; | |
371 | int size = 0; | |
372 | ||
373 | if (!adev->mode_info.rfbdev) | |
374 | return 0; | |
375 | ||
e68d14dd | 376 | robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); |
d38ceaf9 AD |
377 | size += amdgpu_bo_size(robj); |
378 | return size; | |
379 | } | |
380 | ||
381 | bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) | |
382 | { | |
383 | if (!adev->mode_info.rfbdev) | |
384 | return false; | |
e68d14dd | 385 | if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) |
d38ceaf9 AD |
386 | return true; |
387 | return false; | |
388 | } |