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d38ceaf9 AD |
1 | /** |
2 | * \file amdgpu_drv.c | |
3 | * AMD Amdgpu driver | |
4 | * | |
5 | * \author Gareth Hughes <gareth@valinux.com> | |
6 | */ | |
7 | ||
8 | /* | |
9 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
10 | * All Rights Reserved. | |
11 | * | |
12 | * Permission is hereby granted, free of charge, to any person obtaining a | |
13 | * copy of this software and associated documentation files (the "Software"), | |
14 | * to deal in the Software without restriction, including without limitation | |
15 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
16 | * and/or sell copies of the Software, and to permit persons to whom the | |
17 | * Software is furnished to do so, subject to the following conditions: | |
18 | * | |
19 | * The above copyright notice and this permission notice (including the next | |
20 | * paragraph) shall be included in all copies or substantial portions of the | |
21 | * Software. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
24 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
25 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
26 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
27 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
28 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
29 | * OTHER DEALINGS IN THE SOFTWARE. | |
30 | */ | |
31 | ||
32 | #include <drm/drmP.h> | |
33 | #include <drm/amdgpu_drm.h> | |
34 | #include <drm/drm_gem.h> | |
35 | #include "amdgpu_drv.h" | |
36 | ||
37 | #include <drm/drm_pciids.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/pm_runtime.h> | |
41 | #include <linux/vga_switcheroo.h> | |
248a1d6f | 42 | #include <drm/drm_crtc_helper.h> |
d38ceaf9 AD |
43 | |
44 | #include "amdgpu.h" | |
45 | #include "amdgpu_irq.h" | |
46 | ||
130e0371 OG |
47 | #include "amdgpu_amdkfd.h" |
48 | ||
d38ceaf9 AD |
49 | /* |
50 | * KMS wrapper. | |
51 | * - 3.0.0 - initial driver | |
6055f37a | 52 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
f84e63f2 MO |
53 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
54 | * at the end of IBs. | |
d347ce66 | 55 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
83a59b63 | 56 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
8dd31d74 | 57 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
753ad49c | 58 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
9cee3c1f | 59 | * - 3.7.0 - Add support for VCE clock list packet |
b62b5931 | 60 | * - 3.8.0 - Add support raster config init in the kernel |
ef704318 | 61 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
a5b11dac | 62 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
5ebbac4b | 63 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
dfe38bd8 | 64 | * - 3.12.0 - Add query for double offchip LDS buffers |
8eafd505 | 65 | * - 3.13.0 - Add PRT support |
203eb0cb | 66 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
44eb8c1b | 67 | * - 3.15.0 - Export more gpu info for gfx9 |
b98b8dbc | 68 | * - 3.16.0 - Add reserved vmid support |
68e2c5ff | 69 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
dbfe85ea | 70 | * - 3.18.0 - Export gpu always on cu bitmap |
33476319 | 71 | * - 3.19.0 - Add support for UVD MJPEG decode |
fd8bf087 | 72 | * - 3.20.0 - Add support for local BOs |
d38ceaf9 AD |
73 | */ |
74 | #define KMS_DRIVER_MAJOR 3 | |
fd8bf087 | 75 | #define KMS_DRIVER_MINOR 20 |
d38ceaf9 AD |
76 | #define KMS_DRIVER_PATCHLEVEL 0 |
77 | ||
78 | int amdgpu_vram_limit = 0; | |
218b5dcd | 79 | int amdgpu_vis_vram_limit = 0; |
83e74db6 | 80 | int amdgpu_gart_size = -1; /* auto */ |
36d38372 | 81 | int amdgpu_gtt_size = -1; /* auto */ |
95844d20 | 82 | int amdgpu_moverate = -1; /* auto */ |
d38ceaf9 AD |
83 | int amdgpu_benchmarking = 0; |
84 | int amdgpu_testing = 0; | |
85 | int amdgpu_audio = -1; | |
86 | int amdgpu_disp_priority = 0; | |
87 | int amdgpu_hw_i2c = 0; | |
88 | int amdgpu_pcie_gen2 = -1; | |
89 | int amdgpu_msi = -1; | |
a895c222 | 90 | int amdgpu_lockup_timeout = 0; |
d38ceaf9 | 91 | int amdgpu_dpm = -1; |
e635ee07 | 92 | int amdgpu_fw_load_type = -1; |
d38ceaf9 AD |
93 | int amdgpu_aspm = -1; |
94 | int amdgpu_runtime_pm = -1; | |
0b693f0b | 95 | uint amdgpu_ip_block_mask = 0xffffffff; |
d38ceaf9 AD |
96 | int amdgpu_bapm = -1; |
97 | int amdgpu_deep_color = 0; | |
bab4fee7 | 98 | int amdgpu_vm_size = -1; |
d07f14be | 99 | int amdgpu_vm_fragment_size = -1; |
d38ceaf9 | 100 | int amdgpu_vm_block_size = -1; |
d9c13156 | 101 | int amdgpu_vm_fault_stop = 0; |
b495bd3a | 102 | int amdgpu_vm_debug = 0; |
60bfcd31 | 103 | int amdgpu_vram_page_split = 512; |
9a4b7d4c | 104 | int amdgpu_vm_update_mode = -1; |
d38ceaf9 | 105 | int amdgpu_exp_hw_support = 0; |
b70f014d | 106 | int amdgpu_sched_jobs = 32; |
4afcb303 | 107 | int amdgpu_sched_hw_submission = 2; |
3ca67300 RZ |
108 | int amdgpu_no_evict = 0; |
109 | int amdgpu_direct_gma_size = 0; | |
0b693f0b RZ |
110 | uint amdgpu_pcie_gen_cap = 0; |
111 | uint amdgpu_pcie_lane_cap = 0; | |
112 | uint amdgpu_cg_mask = 0xffffffff; | |
113 | uint amdgpu_pg_mask = 0xffffffff; | |
114 | uint amdgpu_sdma_phase_quantum = 32; | |
6f8941a2 | 115 | char *amdgpu_disable_cu = NULL; |
9accf2fd | 116 | char *amdgpu_virtual_display = NULL; |
0b693f0b | 117 | uint amdgpu_pp_feature_mask = 0xffffffff; |
bce23e00 AD |
118 | int amdgpu_ngg = 0; |
119 | int amdgpu_prim_buf_per_se = 0; | |
120 | int amdgpu_pos_buf_per_se = 0; | |
121 | int amdgpu_cntl_sb_buf_per_se = 0; | |
122 | int amdgpu_param_buf_per_se = 0; | |
65781c78 | 123 | int amdgpu_job_hang_limit = 0; |
e8835e0e | 124 | int amdgpu_lbpw = -1; |
d38ceaf9 AD |
125 | |
126 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); | |
127 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
128 | ||
218b5dcd JB |
129 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
130 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); | |
131 | ||
a4da14cc | 132 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
f9321cc4 | 133 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
d38ceaf9 | 134 | |
36d38372 CK |
135 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
136 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); | |
d38ceaf9 | 137 | |
95844d20 MO |
138 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
139 | module_param_named(moverate, amdgpu_moverate, int, 0600); | |
140 | ||
d38ceaf9 AD |
141 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
142 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
143 | ||
144 | MODULE_PARM_DESC(test, "Run tests"); | |
145 | module_param_named(test, amdgpu_testing, int, 0444); | |
146 | ||
147 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); | |
148 | module_param_named(audio, amdgpu_audio, int, 0444); | |
149 | ||
150 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); | |
151 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
152 | ||
153 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); | |
154 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
155 | ||
156 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); | |
157 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
158 | ||
159 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); | |
160 | module_param_named(msi, amdgpu_msi, int, 0444); | |
161 | ||
a895c222 | 162 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); |
d38ceaf9 AD |
163 | module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); |
164 | ||
165 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); | |
166 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
167 | ||
e635ee07 HR |
168 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); |
169 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); | |
d38ceaf9 AD |
170 | |
171 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); | |
172 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
173 | ||
174 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); | |
175 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); | |
176 | ||
d38ceaf9 AD |
177 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
178 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
179 | ||
180 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); | |
181 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
182 | ||
183 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); | |
184 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
185 | ||
ed885b21 | 186 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
d38ceaf9 | 187 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
d07f14be RH |
188 | |
189 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); | |
190 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); | |
d38ceaf9 AD |
191 | |
192 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); | |
193 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
194 | ||
d9c13156 CK |
195 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
196 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
197 | ||
b495bd3a CK |
198 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
199 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
200 | ||
9a4b7d4c HK |
201 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
202 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); | |
203 | ||
ccfee95c | 204 | MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM allocations (default 512, -1 = disable)"); |
6a7f76e7 CK |
205 | module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444); |
206 | ||
d38ceaf9 AD |
207 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
208 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
209 | ||
b70f014d | 210 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
1333f723 JZ |
211 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
212 | ||
4afcb303 JZ |
213 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
214 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
215 | ||
5141e9d2 | 216 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
88826351 | 217 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); |
3a74f6f2 | 218 | |
3ca67300 RZ |
219 | MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); |
220 | module_param_named(no_evict, amdgpu_no_evict, int, 0444); | |
221 | ||
222 | MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); | |
223 | module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); | |
af223dfa | 224 | |
cd474ba0 AD |
225 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
226 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
227 | ||
228 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); | |
229 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
230 | ||
395d1fb9 NH |
231 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
232 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); | |
233 | ||
234 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); | |
235 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); | |
236 | ||
a667386c FK |
237 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
238 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); | |
239 | ||
6f8941a2 NH |
240 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
241 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); | |
242 | ||
0f66356d ED |
243 | MODULE_PARM_DESC(virtual_display, |
244 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); | |
9accf2fd | 245 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
e443059d | 246 | |
bce23e00 AD |
247 | MODULE_PARM_DESC(ngg, "Next Generation Graphics (1 = enable, 0 = disable(default depending on gfx))"); |
248 | module_param_named(ngg, amdgpu_ngg, int, 0444); | |
249 | ||
250 | MODULE_PARM_DESC(prim_buf_per_se, "the size of Primitive Buffer per Shader Engine (default depending on gfx)"); | |
251 | module_param_named(prim_buf_per_se, amdgpu_prim_buf_per_se, int, 0444); | |
252 | ||
253 | MODULE_PARM_DESC(pos_buf_per_se, "the size of Position Buffer per Shader Engine (default depending on gfx)"); | |
254 | module_param_named(pos_buf_per_se, amdgpu_pos_buf_per_se, int, 0444); | |
255 | ||
256 | MODULE_PARM_DESC(cntl_sb_buf_per_se, "the size of Control Sideband per Shader Engine (default depending on gfx)"); | |
257 | module_param_named(cntl_sb_buf_per_se, amdgpu_cntl_sb_buf_per_se, int, 0444); | |
258 | ||
259 | MODULE_PARM_DESC(param_buf_per_se, "the size of Off-Chip Pramater Cache per Shader Engine (default depending on gfx)"); | |
260 | module_param_named(param_buf_per_se, amdgpu_param_buf_per_se, int, 0444); | |
261 | ||
65781c78 ML |
262 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
263 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); | |
264 | ||
e8835e0e HZ |
265 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
266 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); | |
bce23e00 | 267 | |
6dd13096 | 268 | #ifdef CONFIG_DRM_AMDGPU_SI |
53efaf56 MD |
269 | |
270 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
6dd13096 FK |
271 | int amdgpu_si_support = 0; |
272 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
273 | #else |
274 | int amdgpu_si_support = 1; | |
275 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); | |
276 | #endif | |
277 | ||
6dd13096 FK |
278 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
279 | #endif | |
280 | ||
7df28986 | 281 | #ifdef CONFIG_DRM_AMDGPU_CIK |
53efaf56 MD |
282 | |
283 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
2b059658 MD |
284 | int amdgpu_cik_support = 0; |
285 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
286 | #else |
287 | int amdgpu_cik_support = 1; | |
288 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); | |
289 | #endif | |
290 | ||
7df28986 FK |
291 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
292 | #endif | |
293 | ||
bce23e00 | 294 | |
f498d9ed | 295 | static const struct pci_device_id pciidlist[] = { |
78fbb685 KW |
296 | #ifdef CONFIG_DRM_AMDGPU_SI |
297 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
298 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
299 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
300 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
301 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
302 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
303 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
304 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
305 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
306 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
307 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
308 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
309 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
310 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
311 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
312 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
313 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
314 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
315 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
316 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
317 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
318 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
319 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
320 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
321 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
322 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
323 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
324 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
325 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
326 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
327 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
328 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
329 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
330 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
331 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
332 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
333 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
334 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
335 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
336 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
337 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
338 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
339 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
340 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
341 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
342 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
343 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
344 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
345 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
346 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
347 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
348 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
349 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
350 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
351 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
352 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
353 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
354 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
355 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
356 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
357 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
358 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
359 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
360 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
361 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
362 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
363 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
364 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
365 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
366 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
367 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
368 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
369 | #endif | |
89330c39 AD |
370 | #ifdef CONFIG_DRM_AMDGPU_CIK |
371 | /* Kaveri */ | |
2f7d10b3 JZ |
372 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
373 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
374 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
375 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
376 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
377 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
378 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
379 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
380 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
381 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
382 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
383 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
384 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
385 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
386 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
387 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
388 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
389 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
390 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
391 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
392 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
393 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
89330c39 | 394 | /* Bonaire */ |
2f7d10b3 JZ |
395 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
396 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
397 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
398 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
89330c39 AD |
399 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
400 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
401 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
402 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
403 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
404 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
fb4f1737 | 405 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
89330c39 AD |
406 | /* Hawaii */ |
407 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
408 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
409 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
410 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
411 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
412 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
413 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
414 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
415 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
416 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
417 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
418 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
419 | /* Kabini */ | |
2f7d10b3 JZ |
420 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
421 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
422 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
423 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
424 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
425 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
426 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
427 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
428 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
429 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
430 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
431 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
432 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
433 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
434 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
435 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
89330c39 | 436 | /* mullins */ |
2f7d10b3 JZ |
437 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
438 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
439 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
440 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
441 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
442 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
443 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
444 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
445 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
446 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
447 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
448 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
449 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
450 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
451 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
452 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
89330c39 | 453 | #endif |
1256a8b8 | 454 | /* topaz */ |
dba280b2 AD |
455 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
456 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
457 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
458 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
459 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
1256a8b8 AD |
460 | /* tonga */ |
461 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
462 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
463 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 464 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
465 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
466 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 467 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
468 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
469 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
2da78e21 DZ |
470 | /* fiji */ |
471 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
e1d99217 | 472 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
1256a8b8 | 473 | /* carrizo */ |
2f7d10b3 JZ |
474 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
475 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
476 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
477 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
478 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
81b1509a SL |
479 | /* stoney */ |
480 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
2cc0c0b5 FC |
481 | /* Polaris11 */ |
482 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
35621b80 | 483 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 484 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 485 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 | 486 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 487 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 FC |
488 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
489 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
490 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
2cc0c0b5 FC |
491 | /* Polaris10 */ |
492 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1dcf4801 FC |
493 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
494 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
495 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
496 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
7dae6181 | 497 | {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
2cc0c0b5 | 498 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1dcf4801 FC |
499 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
500 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
501 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
502 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
503 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
fc8e9c54 JZ |
504 | /* Polaris12 */ |
505 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
506 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
507 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
508 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
509 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
cf8c73af | 510 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
6e88491c | 511 | {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
fc8e9c54 | 512 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
ca2f1cca JZ |
513 | /* Vega 10 */ |
514 | {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, | |
515 | {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, | |
516 | {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, | |
517 | {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, | |
09062ae1 | 518 | {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, |
ca2f1cca | 519 | {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, |
09062ae1 | 520 | {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, |
ca2f1cca JZ |
521 | {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, |
522 | {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10|AMD_EXP_HW_SUPPORT}, | |
df515052 CZ |
523 | /* Raven */ |
524 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU|AMD_EXP_HW_SUPPORT}, | |
525 | ||
d38ceaf9 AD |
526 | {0, 0, 0} |
527 | }; | |
528 | ||
529 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
530 | ||
531 | static struct drm_driver kms_driver; | |
532 | ||
533 | static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) | |
534 | { | |
535 | struct apertures_struct *ap; | |
536 | bool primary = false; | |
537 | ||
538 | ap = alloc_apertures(1); | |
539 | if (!ap) | |
540 | return -ENOMEM; | |
541 | ||
542 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
543 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
544 | ||
545 | #ifdef CONFIG_X86 | |
546 | primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
547 | #endif | |
44adece5 | 548 | drm_fb_helper_remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); |
d38ceaf9 AD |
549 | kfree(ap); |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
554 | static int amdgpu_pci_probe(struct pci_dev *pdev, | |
555 | const struct pci_device_id *ent) | |
556 | { | |
b58c1131 | 557 | struct drm_device *dev; |
d38ceaf9 AD |
558 | unsigned long flags = ent->driver_data; |
559 | int ret; | |
560 | ||
2f7d10b3 | 561 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
d38ceaf9 AD |
562 | DRM_INFO("This hardware requires experimental hardware support.\n" |
563 | "See modparam exp_hw_support\n"); | |
564 | return -ENODEV; | |
565 | } | |
566 | ||
efb1c658 OG |
567 | /* |
568 | * Initialize amdkfd before starting radeon. If it was not loaded yet, | |
569 | * defer radeon probing | |
570 | */ | |
571 | ret = amdgpu_amdkfd_init(); | |
572 | if (ret == -EPROBE_DEFER) | |
573 | return ret; | |
574 | ||
d38ceaf9 AD |
575 | /* Get rid of things like offb */ |
576 | ret = amdgpu_kick_out_firmware_fb(pdev); | |
577 | if (ret) | |
578 | return ret; | |
579 | ||
b58c1131 AD |
580 | dev = drm_dev_alloc(&kms_driver, &pdev->dev); |
581 | if (IS_ERR(dev)) | |
582 | return PTR_ERR(dev); | |
583 | ||
584 | ret = pci_enable_device(pdev); | |
585 | if (ret) | |
586 | goto err_free; | |
587 | ||
588 | dev->pdev = pdev; | |
589 | ||
590 | pci_set_drvdata(pdev, dev); | |
591 | ||
592 | ret = drm_dev_register(dev, ent->driver_data); | |
593 | if (ret) | |
594 | goto err_pci; | |
595 | ||
596 | return 0; | |
597 | ||
598 | err_pci: | |
599 | pci_disable_device(pdev); | |
600 | err_free: | |
601 | drm_dev_unref(dev); | |
602 | return ret; | |
d38ceaf9 AD |
603 | } |
604 | ||
605 | static void | |
606 | amdgpu_pci_remove(struct pci_dev *pdev) | |
607 | { | |
608 | struct drm_device *dev = pci_get_drvdata(pdev); | |
609 | ||
b58c1131 AD |
610 | drm_dev_unregister(dev); |
611 | drm_dev_unref(dev); | |
fd4495e5 XY |
612 | pci_disable_device(pdev); |
613 | pci_set_drvdata(pdev, NULL); | |
d38ceaf9 AD |
614 | } |
615 | ||
61e11306 AD |
616 | static void |
617 | amdgpu_pci_shutdown(struct pci_dev *pdev) | |
618 | { | |
faefba95 AD |
619 | struct drm_device *dev = pci_get_drvdata(pdev); |
620 | struct amdgpu_device *adev = dev->dev_private; | |
621 | ||
61e11306 | 622 | /* if we are running in a VM, make sure the device |
00ea8cba AD |
623 | * torn down properly on reboot/shutdown. |
624 | * unfortunately we can't detect certain | |
625 | * hypervisors so just do this all the time. | |
61e11306 | 626 | */ |
faefba95 | 627 | amdgpu_suspend(adev); |
61e11306 AD |
628 | } |
629 | ||
d38ceaf9 AD |
630 | static int amdgpu_pmops_suspend(struct device *dev) |
631 | { | |
632 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 633 | |
d38ceaf9 | 634 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 635 | return amdgpu_device_suspend(drm_dev, true, true); |
d38ceaf9 AD |
636 | } |
637 | ||
638 | static int amdgpu_pmops_resume(struct device *dev) | |
639 | { | |
640 | struct pci_dev *pdev = to_pci_dev(dev); | |
641 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
85e154c2 AD |
642 | |
643 | /* GPU comes up enabled by the bios on resume */ | |
644 | if (amdgpu_device_is_px(drm_dev)) { | |
645 | pm_runtime_disable(dev); | |
646 | pm_runtime_set_active(dev); | |
647 | pm_runtime_enable(dev); | |
648 | } | |
649 | ||
810ddc3a | 650 | return amdgpu_device_resume(drm_dev, true, true); |
d38ceaf9 AD |
651 | } |
652 | ||
653 | static int amdgpu_pmops_freeze(struct device *dev) | |
654 | { | |
655 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 656 | |
d38ceaf9 | 657 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 658 | return amdgpu_device_suspend(drm_dev, false, true); |
d38ceaf9 AD |
659 | } |
660 | ||
661 | static int amdgpu_pmops_thaw(struct device *dev) | |
662 | { | |
663 | struct pci_dev *pdev = to_pci_dev(dev); | |
74b0b157 | 664 | |
665 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
666 | return amdgpu_device_resume(drm_dev, false, true); | |
667 | } | |
668 | ||
669 | static int amdgpu_pmops_poweroff(struct device *dev) | |
670 | { | |
671 | struct pci_dev *pdev = to_pci_dev(dev); | |
672 | ||
673 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
674 | return amdgpu_device_suspend(drm_dev, true, true); | |
675 | } | |
676 | ||
677 | static int amdgpu_pmops_restore(struct device *dev) | |
678 | { | |
679 | struct pci_dev *pdev = to_pci_dev(dev); | |
680 | ||
d38ceaf9 | 681 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
810ddc3a | 682 | return amdgpu_device_resume(drm_dev, false, true); |
d38ceaf9 AD |
683 | } |
684 | ||
685 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
686 | { | |
687 | struct pci_dev *pdev = to_pci_dev(dev); | |
688 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
689 | int ret; | |
690 | ||
691 | if (!amdgpu_device_is_px(drm_dev)) { | |
692 | pm_runtime_forbid(dev); | |
693 | return -EBUSY; | |
694 | } | |
695 | ||
696 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
697 | drm_kms_helper_poll_disable(drm_dev); | |
698 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); | |
699 | ||
810ddc3a | 700 | ret = amdgpu_device_suspend(drm_dev, false, false); |
d38ceaf9 AD |
701 | pci_save_state(pdev); |
702 | pci_disable_device(pdev); | |
703 | pci_ignore_hotplug(pdev); | |
11670975 AD |
704 | if (amdgpu_is_atpx_hybrid()) |
705 | pci_set_power_state(pdev, PCI_D3cold); | |
522761cb | 706 | else if (!amdgpu_has_atpx_dgpu_power_cntl()) |
7e32aa61 | 707 | pci_set_power_state(pdev, PCI_D3hot); |
d38ceaf9 AD |
708 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
714 | { | |
715 | struct pci_dev *pdev = to_pci_dev(dev); | |
716 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
717 | int ret; | |
718 | ||
719 | if (!amdgpu_device_is_px(drm_dev)) | |
720 | return -EINVAL; | |
721 | ||
722 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
723 | ||
522761cb AD |
724 | if (amdgpu_is_atpx_hybrid() || |
725 | !amdgpu_has_atpx_dgpu_power_cntl()) | |
726 | pci_set_power_state(pdev, PCI_D0); | |
d38ceaf9 AD |
727 | pci_restore_state(pdev); |
728 | ret = pci_enable_device(pdev); | |
729 | if (ret) | |
730 | return ret; | |
731 | pci_set_master(pdev); | |
732 | ||
810ddc3a | 733 | ret = amdgpu_device_resume(drm_dev, false, false); |
d38ceaf9 AD |
734 | drm_kms_helper_poll_enable(drm_dev); |
735 | vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); | |
736 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
737 | return 0; | |
738 | } | |
739 | ||
740 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
741 | { | |
742 | struct pci_dev *pdev = to_pci_dev(dev); | |
743 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
744 | struct drm_crtc *crtc; | |
745 | ||
746 | if (!amdgpu_device_is_px(drm_dev)) { | |
747 | pm_runtime_forbid(dev); | |
748 | return -EBUSY; | |
749 | } | |
750 | ||
751 | list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { | |
752 | if (crtc->enabled) { | |
753 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
754 | return -EBUSY; | |
755 | } | |
756 | } | |
757 | ||
758 | pm_runtime_mark_last_busy(dev); | |
759 | pm_runtime_autosuspend(dev); | |
760 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ | |
761 | return 1; | |
762 | } | |
763 | ||
764 | long amdgpu_drm_ioctl(struct file *filp, | |
765 | unsigned int cmd, unsigned long arg) | |
766 | { | |
767 | struct drm_file *file_priv = filp->private_data; | |
768 | struct drm_device *dev; | |
769 | long ret; | |
770 | dev = file_priv->minor->dev; | |
771 | ret = pm_runtime_get_sync(dev->dev); | |
772 | if (ret < 0) | |
773 | return ret; | |
774 | ||
775 | ret = drm_ioctl(filp, cmd, arg); | |
776 | ||
777 | pm_runtime_mark_last_busy(dev->dev); | |
778 | pm_runtime_put_autosuspend(dev->dev); | |
779 | return ret; | |
780 | } | |
781 | ||
782 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
783 | .suspend = amdgpu_pmops_suspend, | |
784 | .resume = amdgpu_pmops_resume, | |
785 | .freeze = amdgpu_pmops_freeze, | |
786 | .thaw = amdgpu_pmops_thaw, | |
74b0b157 | 787 | .poweroff = amdgpu_pmops_poweroff, |
788 | .restore = amdgpu_pmops_restore, | |
d38ceaf9 AD |
789 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
790 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
791 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
792 | }; | |
793 | ||
794 | static const struct file_operations amdgpu_driver_kms_fops = { | |
795 | .owner = THIS_MODULE, | |
796 | .open = drm_open, | |
797 | .release = drm_release, | |
798 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
799 | .mmap = amdgpu_mmap, | |
800 | .poll = drm_poll, | |
801 | .read = drm_read, | |
802 | #ifdef CONFIG_COMPAT | |
803 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
804 | #endif | |
805 | }; | |
806 | ||
1bf6ad62 DV |
807 | static bool |
808 | amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, | |
809 | bool in_vblank_irq, int *vpos, int *hpos, | |
810 | ktime_t *stime, ktime_t *etime, | |
811 | const struct drm_display_mode *mode) | |
812 | { | |
813 | return amdgpu_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, | |
814 | stime, etime, mode); | |
815 | } | |
816 | ||
d38ceaf9 AD |
817 | static struct drm_driver kms_driver = { |
818 | .driver_features = | |
819 | DRIVER_USE_AGP | | |
820 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | | |
660e8558 | 821 | DRIVER_PRIME | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, |
d38ceaf9 AD |
822 | .load = amdgpu_driver_load_kms, |
823 | .open = amdgpu_driver_open_kms, | |
d38ceaf9 AD |
824 | .postclose = amdgpu_driver_postclose_kms, |
825 | .lastclose = amdgpu_driver_lastclose_kms, | |
d38ceaf9 AD |
826 | .unload = amdgpu_driver_unload_kms, |
827 | .get_vblank_counter = amdgpu_get_vblank_counter_kms, | |
828 | .enable_vblank = amdgpu_enable_vblank_kms, | |
829 | .disable_vblank = amdgpu_disable_vblank_kms, | |
1bf6ad62 DV |
830 | .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, |
831 | .get_scanout_position = amdgpu_get_crtc_scanout_position, | |
d38ceaf9 AD |
832 | #if defined(CONFIG_DEBUG_FS) |
833 | .debugfs_init = amdgpu_debugfs_init, | |
d38ceaf9 AD |
834 | #endif |
835 | .irq_preinstall = amdgpu_irq_preinstall, | |
836 | .irq_postinstall = amdgpu_irq_postinstall, | |
837 | .irq_uninstall = amdgpu_irq_uninstall, | |
838 | .irq_handler = amdgpu_irq_handler, | |
839 | .ioctls = amdgpu_ioctls_kms, | |
e7294dee | 840 | .gem_free_object_unlocked = amdgpu_gem_object_free, |
d38ceaf9 AD |
841 | .gem_open_object = amdgpu_gem_object_open, |
842 | .gem_close_object = amdgpu_gem_object_close, | |
843 | .dumb_create = amdgpu_mode_dumb_create, | |
844 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
d38ceaf9 AD |
845 | .fops = &amdgpu_driver_kms_fops, |
846 | ||
847 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
848 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
849 | .gem_prime_export = amdgpu_gem_prime_export, | |
850 | .gem_prime_import = drm_gem_prime_import, | |
851 | .gem_prime_pin = amdgpu_gem_prime_pin, | |
852 | .gem_prime_unpin = amdgpu_gem_prime_unpin, | |
853 | .gem_prime_res_obj = amdgpu_gem_prime_res_obj, | |
854 | .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, | |
855 | .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, | |
856 | .gem_prime_vmap = amdgpu_gem_prime_vmap, | |
857 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, | |
858 | ||
859 | .name = DRIVER_NAME, | |
860 | .desc = DRIVER_DESC, | |
861 | .date = DRIVER_DATE, | |
862 | .major = KMS_DRIVER_MAJOR, | |
863 | .minor = KMS_DRIVER_MINOR, | |
864 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
865 | }; | |
866 | ||
867 | static struct drm_driver *driver; | |
868 | static struct pci_driver *pdriver; | |
869 | ||
870 | static struct pci_driver amdgpu_kms_pci_driver = { | |
871 | .name = DRIVER_NAME, | |
872 | .id_table = pciidlist, | |
873 | .probe = amdgpu_pci_probe, | |
874 | .remove = amdgpu_pci_remove, | |
61e11306 | 875 | .shutdown = amdgpu_pci_shutdown, |
d38ceaf9 AD |
876 | .driver.pm = &amdgpu_pm_ops, |
877 | }; | |
878 | ||
d573de2d RZ |
879 | |
880 | ||
d38ceaf9 AD |
881 | static int __init amdgpu_init(void) |
882 | { | |
245ae5e9 CK |
883 | int r; |
884 | ||
885 | r = amdgpu_sync_init(); | |
886 | if (r) | |
887 | goto error_sync; | |
888 | ||
889 | r = amdgpu_fence_slab_init(); | |
890 | if (r) | |
891 | goto error_fence; | |
892 | ||
893 | r = amd_sched_fence_slab_init(); | |
894 | if (r) | |
895 | goto error_sched; | |
896 | ||
d38ceaf9 AD |
897 | if (vgacon_text_force()) { |
898 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
899 | return -EINVAL; | |
900 | } | |
d38ceaf9 AD |
901 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
902 | driver = &kms_driver; | |
903 | pdriver = &amdgpu_kms_pci_driver; | |
d38ceaf9 AD |
904 | driver->num_ioctls = amdgpu_max_kms_ioctl; |
905 | amdgpu_register_atpx_handler(); | |
d38ceaf9 | 906 | /* let modprobe override vga console setting */ |
10631d72 | 907 | return pci_register_driver(pdriver); |
245ae5e9 CK |
908 | |
909 | error_sched: | |
910 | amdgpu_fence_slab_fini(); | |
911 | ||
912 | error_fence: | |
913 | amdgpu_sync_fini(); | |
914 | ||
915 | error_sync: | |
916 | return r; | |
d38ceaf9 AD |
917 | } |
918 | ||
919 | static void __exit amdgpu_exit(void) | |
920 | { | |
130e0371 | 921 | amdgpu_amdkfd_fini(); |
10631d72 | 922 | pci_unregister_driver(pdriver); |
d38ceaf9 | 923 | amdgpu_unregister_atpx_handler(); |
257bf15a | 924 | amdgpu_sync_fini(); |
c24784f0 | 925 | amd_sched_fence_slab_fini(); |
d573de2d | 926 | amdgpu_fence_slab_fini(); |
d38ceaf9 AD |
927 | } |
928 | ||
929 | module_init(amdgpu_init); | |
930 | module_exit(amdgpu_exit); | |
931 | ||
932 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
933 | MODULE_DESCRIPTION(DRIVER_DESC); | |
934 | MODULE_LICENSE("GPL and additional rights"); |