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drm/amdgpu: correct cp doorbell range
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
6848c291 26#include <drm/drm_aperture.h>
fdf2f6c5 27#include <drm/drm_drv.h>
d38ceaf9 28#include <drm/drm_gem.h>
fdf2f6c5 29#include <drm/drm_vblank.h>
8aba21b7 30#include <drm/drm_managed.h>
d38ceaf9
AD		 31#include "amdgpu_drv.h"
32
33#include <drm/drm_pciids.h>
d38ceaf9
AD		 34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
fcd70cd3 37#include <drm/drm_probe_helper.h>
c7d8b782 38#include <linux/mmu_notifier.h>
e25443d2 39#include <linux/suspend.h>
e9d1d2bb 40#include <linux/cc_platform.h>
b95dc06a 41#include <linux/fb.h>
d38ceaf9
AD		 42
43#include "amdgpu.h"
44#include "amdgpu_irq.h"
2fbd6f94 45#include "amdgpu_dma_buf.h"
5088d657 46#include "amdgpu_sched.h"
87444254 47#include "amdgpu_fdinfo.h"
130e0371
OG		 48#include "amdgpu_amdkfd.h"
49
7c6e68c7 50#include "amdgpu_ras.h"
e3c1b071 51#include "amdgpu_xgmi.h"
04442bf7 52#include "amdgpu_reset.h"
7c6e68c7 53
d38ceaf9
AD		 54/*
55 * KMS wrapper.
56 * - 3.0.0 - initial driver
6055f37a 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
59 * at the end of IBs.
d347ce66 60 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 62 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 64 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 65 * - 3.8.0 - Add support raster config init in the kernel
ef704318 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 69 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 70 * - 3.13.0 - Add PRT support
203eb0cb 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 72 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 73 * - 3.16.0 - Add reserved vmid support
68e2c5ff 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 75 * - 3.18.0 - Export gpu always on cu bitmap
33476319 76 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 77 * - 3.20.0 - Add support for local BOs
7ca24cf2 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 80 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 81 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
964d0fbf 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 93 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 98 * - 3.41.0 - Add video codec query
915821a7 99 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 100 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
ded81d5b 102 * - 3.45.0 - Add context ioctl stable pstate interface
5aa06147 103 * * 3.46.0 - To enable hot plug amdgpu tests in libdrm
d38ceaf9
AD		 104 */
105#define KMS_DRIVER_MAJOR 3
5aa06147 106#define KMS_DRIVER_MINOR 46
d38ceaf9
AD		 107#define KMS_DRIVER_PATCHLEVEL 0
108
87fb7833
DV		 109int amdgpu_vram_limit;
110int amdgpu_vis_vram_limit;
83e74db6 111int amdgpu_gart_size = -1; /* auto */
36d38372 112int amdgpu_gtt_size = -1; /* auto */
95844d20 113int amdgpu_moverate = -1; /* auto */
d38ceaf9 114int amdgpu_audio = -1;
87fb7833
DV		 115int amdgpu_disp_priority;
116int amdgpu_hw_i2c;
d38ceaf9
AD		 117int amdgpu_pcie_gen2 = -1;
118int amdgpu_msi = -1;
f440ff44 119char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 120int amdgpu_dpm = -1;
e635ee07 121int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 122int amdgpu_aspm = -1;
123int amdgpu_runtime_pm = -1;
0b693f0b 124uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 125int amdgpu_bapm = -1;
87fb7833 126int amdgpu_deep_color;
bab4fee7 127int amdgpu_vm_size = -1;
d07f14be 128int amdgpu_vm_fragment_size = -1;
d38ceaf9 129int amdgpu_vm_block_size = -1;
87fb7833
DV		 130int amdgpu_vm_fault_stop;
131int amdgpu_vm_debug;
9a4b7d4c 132int amdgpu_vm_update_mode = -1;
87fb7833 133int amdgpu_exp_hw_support;
4562236b 134int amdgpu_dc = -1;
b70f014d 135int amdgpu_sched_jobs = 32;
4afcb303 136int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 137uint amdgpu_pcie_gen_cap;
138uint amdgpu_pcie_lane_cap;
25faeddc 139u64 amdgpu_cg_mask = 0xffffffffffffffff;
0b693f0b
RZ		 140uint amdgpu_pg_mask = 0xffffffff;
141uint amdgpu_sdma_phase_quantum = 32;
6f8941a2 142char *amdgpu_disable_cu = NULL;
9accf2fd 143char *amdgpu_virtual_display = NULL;
680602d6
KF		 144
145/*
146 * OverDrive(bit 14) disabled by default
147 * GFX DCS(bit 19) disabled by default
148 */
149uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833
DV		 150uint amdgpu_force_long_training;
151int amdgpu_job_hang_limit;
e8835e0e 152int amdgpu_lbpw = -1;
4a75aefe 153int amdgpu_compute_multipipe = -1;
dcebf026 154int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 155int amdgpu_emu_mode;
156uint amdgpu_smu_memory_pool_size;
8738a82b 157int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 158/*
159 * FBC (bit 0) disabled by default
160 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
161 * - With this, for multiple monitors in sync(e.g. with the same model),
162 * mclk switching will be allowed. And the mclk will be not foced to the
163 * highest. That helps saving some idle power.
164 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
165 * PSR (bit 3) disabled by default
a5148245 166 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 167 */
168uint amdgpu_dc_feature_mask = 2;
87fb7833 169uint amdgpu_dc_debug_mask;
5bfca069 170int amdgpu_async_gfx_ring = 1;
87fb7833 171int amdgpu_mcbp;
63e2fef6 172int amdgpu_discovery = -1;
87fb7833 173int amdgpu_mes;
928fe236 174int amdgpu_mes_kiq;
d5cc02d9 175int amdgpu_noretry = -1;
4e66d7d2 176int amdgpu_force_asic_type = -1;
58aa7790 177int amdgpu_tmz = -1; /* auto */
273da6ff 178int amdgpu_reset_method = -1; /* auto */
a300de40 179int amdgpu_num_kcq = -1;
30d95a37 180int amdgpu_smartshift_bias;
158a05a0 181int amdgpu_use_xgmi_p2p = 1;
11eb648d 182int amdgpu_vcnfw_log;
7875a226 183
e3c1b071 184static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
185
62d73fbc
EQ		 186struct amdgpu_mgpu_info mgpu_info = {
187 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 188 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
189 mgpu_info.delayed_reset_work,
190 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 191};
1218252f 192int amdgpu_ras_enable = -1;
e53aec7e 193uint amdgpu_ras_mask = 0xffffffff;
acc0204c 194int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 195struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
196 .timeout_fatal_disable = false,
28a5d7a5 197 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 198};
d38ceaf9 199
8405cf39
SJ		 200/**
201 * DOC: vramlimit (int)
202 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
203 */
d38ceaf9
AD		 204MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
205module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
206
8405cf39
SJ		 207/**
208 * DOC: vis_vramlimit (int)
209 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
210 */
218b5dcd
JB		 211MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
212module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
213
8405cf39
SJ		 214/**
215 * DOC: gartsize (uint)
216 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
217 */
a4da14cc 218MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 219module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 220
8405cf39
SJ		 221/**
222 * DOC: gttsize (int)
223 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
224 * otherwise 3/4 RAM size).
225 */
36d38372
CK		 226MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
227module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 228
8405cf39
SJ		 229/**
230 * DOC: moverate (int)
231 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
232 */
95844d20
MO		 233MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
234module_param_named(moverate, amdgpu_moverate, int, 0600);
235
8405cf39
SJ		 236/**
237 * DOC: audio (int)
238 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
239 */
d38ceaf9
AD		 240MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
241module_param_named(audio, amdgpu_audio, int, 0444);
242
8405cf39
SJ		 243/**
244 * DOC: disp_priority (int)
245 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
246 */
d38ceaf9
AD		 247MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
248module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
249
8405cf39
SJ		 250/**
251 * DOC: hw_i2c (int)
252 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
253 */
d38ceaf9
AD		 254MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
255module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
256
8405cf39
SJ		 257/**
258 * DOC: pcie_gen2 (int)
259 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
260 */
d38ceaf9
AD		 261MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
262module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
263
8405cf39
SJ		 264/**
265 * DOC: msi (int)
266 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
267 */
d38ceaf9
AD		 268MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
269module_param_named(msi, amdgpu_msi, int, 0444);
270
8405cf39 271/**
912dfc84
EQ		 272 * DOC: lockup_timeout (string)
273 * Set GPU scheduler timeout value in ms.
274 *
275 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
276 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 277 * to the default timeout.
278 *
279 * - With one value specified, the setting will apply to all non-compute jobs.
280 * - With multiple values specified, the first one will be for GFX.
281 * The second one is for Compute. The third and fourth ones are
282 * for SDMA and Video.
283 *
912dfc84 284 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 285 * jobs is 10000. The timeout for compute is 60000.
912dfc84 286 */
67387dfe 287MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
bcccee89 288 "for passthrough or sriov, 10000 for all jobs."
71cc9ef3 289 " 0: keep default value. negative: infinity timeout), "
bcccee89
ED		 290 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
291 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 292module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 293
8405cf39
SJ		 294/**
295 * DOC: dpm (int)
54b998ca 296 * Override for dynamic power management setting
5c9a6272 297 * (0 = disable, 1 = enable)
54b998ca 298 * The default is -1 (auto).
8405cf39 299 */
d38ceaf9
AD		 300MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
301module_param_named(dpm, amdgpu_dpm, int, 0444);
302
8405cf39
SJ		 303/**
304 * DOC: fw_load_type (int)
ddb267b6
YD		 305 * Set different firmware loading type for debugging, if supported.
306 * Set to 0 to force direct loading if supported by the ASIC. Set
307 * to -1 to select the default loading mode for the ASIC, as defined
308 * by the driver. The default is -1 (auto).
8405cf39 309 */
ddb267b6 310MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)");
e635ee07 311module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 312
8405cf39
SJ		 313/**
314 * DOC: aspm (int)
315 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
316 */
d38ceaf9
AD		 317MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
318module_param_named(aspm, amdgpu_aspm, int, 0444);
319
8405cf39
SJ		 320/**
321 * DOC: runpm (int)
4d625a97
AD		 322 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
323 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
324 * Setting the value to 0 disables this functionality.
8405cf39 325 */
4d625a97 326MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
d38ceaf9
AD		 327module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
328
8405cf39
SJ		 329/**
330 * DOC: ip_block_mask (uint)
331 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
332 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
333 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
334 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
335 */
d38ceaf9
AD		 336MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
337module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
338
8405cf39
SJ		 339/**
340 * DOC: bapm (int)
341 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
342 * The default -1 (auto, enabled)
343 */
d38ceaf9
AD		 344MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
345module_param_named(bapm, amdgpu_bapm, int, 0444);
346
8405cf39
SJ		 347/**
348 * DOC: deep_color (int)
349 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
350 */
d38ceaf9
AD		 351MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
352module_param_named(deep_color, amdgpu_deep_color, int, 0444);
353
8405cf39
SJ		 354/**
355 * DOC: vm_size (int)
356 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
357 */
ed885b21 358MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 359module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 360
8405cf39
SJ		 361/**
362 * DOC: vm_fragment_size (int)
363 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
364 */
d07f14be
RH		 365MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
366module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 367
8405cf39
SJ		 368/**
369 * DOC: vm_block_size (int)
370 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
371 */
d38ceaf9
AD		 372MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
373module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
374
8405cf39
SJ		 375/**
376 * DOC: vm_fault_stop (int)
377 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
378 */
d9c13156
CK		 379MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
380module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
381
8405cf39
SJ		 382/**
383 * DOC: vm_debug (int)
384 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
385 */
b495bd3a
CK		 386MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
387module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
388
8405cf39
SJ		 389/**
390 * DOC: vm_update_mode (int)
391 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
392 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
393 */
9a4b7d4c
HK		 394MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
395module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
396
8405cf39
SJ		 397/**
398 * DOC: exp_hw_support (int)
399 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
400 */
d38ceaf9
AD		 401MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
402module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
403
8405cf39
SJ		 404/**
405 * DOC: dc (int)
406 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
407 */
4562236b
HW		 408MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
409module_param_named(dc, amdgpu_dc, int, 0444);
410
8405cf39
SJ		 411/**
412 * DOC: sched_jobs (int)
413 * Override the max number of jobs supported in the sw queue. The default is 32.
414 */
b70f014d 415MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 416module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
417
8405cf39
SJ		 418/**
419 * DOC: sched_hw_submission (int)
420 * Override the max number of HW submissions. The default is 2.
421 */
4afcb303
JZ		 422MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
423module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
424
8405cf39 425/**
7427a7a0 426 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 427 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
428 * The default is the current set of stable power features.
429 */
5141e9d2 430MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 431module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 432
367039bf
TY		 433/**
434 * DOC: forcelongtraining (uint)
435 * Force long memory training in resume.
436 * The default is zero, indicates short training in resume.
437 */
438MODULE_PARM_DESC(forcelongtraining, "force memory long training");
439module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
440
8405cf39
SJ		 441/**
442 * DOC: pcie_gen_cap (uint)
443 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
444 * The default is 0 (automatic for each asic).
445 */
cd474ba0
AD		 446MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
447module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
448
8405cf39
SJ		 449/**
450 * DOC: pcie_lane_cap (uint)
451 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
452 * The default is 0 (automatic for each asic).
453 */
cd474ba0
AD		 454MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
455module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
456
8405cf39 457/**
25faeddc 458 * DOC: cg_mask (ullong)
8405cf39 459 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
25faeddc 460 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
8405cf39 461 */
395d1fb9 462MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
25faeddc 463module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
395d1fb9 464
8405cf39
SJ		 465/**
466 * DOC: pg_mask (uint)
467 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
468 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
469 */
395d1fb9
NH		 470MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
471module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
472
8405cf39
SJ		 473/**
474 * DOC: sdma_phase_quantum (uint)
475 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
476 */
a667386c
FK		 477MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
478module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
479
8405cf39
SJ		 480/**
481 * DOC: disable_cu (charp)
482 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
483 */
6f8941a2
NH		 484MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
485module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
486
8405cf39
SJ		 487/**
488 * DOC: virtual_display (charp)
489 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
490 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
491 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
492 * device at 26:00.0. The default is NULL.
493 */
0f66356d
ED		 494MODULE_PARM_DESC(virtual_display,
495 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 496module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 497
8405cf39
SJ		 498/**
499 * DOC: job_hang_limit (int)
500 * Set how much time allow a job hang and not drop it. The default is 0.
501 */
65781c78
ML		 502MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
503module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
504
8405cf39
SJ		 505/**
506 * DOC: lbpw (int)
507 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
508 */
e8835e0e
HZ		 509MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
510module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 511
4a75aefe
AR		 512MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
513module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
514
8405cf39
SJ		 515/**
516 * DOC: gpu_recovery (int)
517 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
518 */
e6c6338f 519MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 520module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
521
8405cf39
SJ		 522/**
523 * DOC: emu_mode (int)
524 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
525 */
d869ae09 526MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 527module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
528
1218252f 529/**
2f3940e9 530 * DOC: ras_enable (int)
1218252f 531 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
532 */
2f3940e9 533MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 534module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
535
536/**
2f3940e9 537 * DOC: ras_mask (uint)
1218252f 538 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
539 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
540 */
2f3940e9 541MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 542module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
543
88f8575b
DL		 544/**
545 * DOC: timeout_fatal_disable (bool)
546 * Disable Watchdog timeout fatal error event
547 */
548MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
549module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
550
551/**
552 * DOC: timeout_period (uint)
553 * Modify the watchdog timeout max_cycles as (1 << period)
554 */
28a5d7a5 555MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 556module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
557
8405cf39
SJ		 558/**
559 * DOC: si_support (int)
560 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
561 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
562 * otherwise using amdgpu driver.
563 */
6dd13096 564#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 565
566#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 567int amdgpu_si_support = 0;
568MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 569#else
570int amdgpu_si_support = 1;
571MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
572#endif
573
6dd13096
FK		 574module_param_named(si_support, amdgpu_si_support, int, 0444);
575#endif
576
8405cf39
SJ		 577/**
578 * DOC: cik_support (int)
579 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
580 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
581 * otherwise using amdgpu driver.
582 */
7df28986 583#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 584
585#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 586int amdgpu_cik_support = 0;
587MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 588#else
589int amdgpu_cik_support = 1;
590MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
591#endif
592
7df28986
FK		 593module_param_named(cik_support, amdgpu_cik_support, int, 0444);
594#endif
595
8405cf39
SJ		 596/**
597 * DOC: smu_memory_pool_size (uint)
598 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
599 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
600 */
7951e376
RZ		 601MODULE_PARM_DESC(smu_memory_pool_size,
602 "reserve gtt for smu debug usage, 0 = disable,"
603 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
604module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
605
51bcce46
HZ		 606/**
607 * DOC: async_gfx_ring (int)
608 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
609 */
610MODULE_PARM_DESC(async_gfx_ring,
5bfca069 611 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 612module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
613
40562787
AD		 614/**
615 * DOC: mcbp (int)
616 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
617 */
b239c017
JX		 618MODULE_PARM_DESC(mcbp,
619 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
620module_param_named(mcbp, amdgpu_mcbp, int, 0444);
621
40562787
AD		 622/**
623 * DOC: discovery (int)
624 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 625 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 626 */
a190d1c7
XY		 627MODULE_PARM_DESC(discovery,
628 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
629module_param_named(discovery, amdgpu_discovery, int, 0444);
630
40562787
AD		 631/**
632 * DOC: mes (int)
633 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
634 * (0 = disabled (default), 1 = enabled)
635 */
38487284
JX		 636MODULE_PARM_DESC(mes,
637 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
638module_param_named(mes, amdgpu_mes, int, 0444);
639
928fe236
JX		 640/**
641 * DOC: mes_kiq (int)
642 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
643 * (0 = disabled (default), 1 = enabled)
644 */
645MODULE_PARM_DESC(mes_kiq,
646 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
647module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
648
d5cc02d9
AD		 649/**
650 * DOC: noretry (int)
9705c85f
FK		 651 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
652 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 653 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
654 */
75ee6487 655MODULE_PARM_DESC(noretry,
d5cc02d9 656 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 657module_param_named(noretry, amdgpu_noretry, int, 0644);
658
4e66d7d2
YZ		 659/**
660 * DOC: force_asic_type (int)
661 * A non negative value used to specify the asic type for all supported GPUs.
662 */
663MODULE_PARM_DESC(force_asic_type,
664 "A non negative value used to specify the asic type for all supported GPUs");
665module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
666
158a05a0
AS		 667/**
668 * DOC: use_xgmi_p2p (int)
669 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
670 */
671MODULE_PARM_DESC(use_xgmi_p2p,
672 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
673module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
4e66d7d2
YZ		 674
675
2690262e 676#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 677/**
678 * DOC: sched_policy (int)
679 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
680 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
681 * assigns queues to HQDs.
682 */
2690262e 683int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 684module_param(sched_policy, int, 0444);
685MODULE_PARM_DESC(sched_policy,
686 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
687
688/**
689 * DOC: hws_max_conc_proc (int)
690 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
691 * number of VMIDs assigned to the HWS, which is also the default.
692 */
b7dfbd2e 693int hws_max_conc_proc = -1;
521fb7d0
AL		 694module_param(hws_max_conc_proc, int, 0444);
695MODULE_PARM_DESC(hws_max_conc_proc,
696 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
697
698/**
699 * DOC: cwsr_enable (int)
700 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
701 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
702 * disables it.
703 */
2690262e 704int cwsr_enable = 1;
521fb7d0
AL		 705module_param(cwsr_enable, int, 0444);
706MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
707
708/**
709 * DOC: max_num_of_queues_per_device (int)
710 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
711 * is 4096.
712 */
2690262e 713int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 714module_param(max_num_of_queues_per_device, int, 0444);
715MODULE_PARM_DESC(max_num_of_queues_per_device,
716 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
717
718/**
719 * DOC: send_sigterm (int)
720 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
721 * but just print errors on dmesg. Setting 1 enables sending sigterm.
722 */
2690262e 723int send_sigterm;
521fb7d0
AL		 724module_param(send_sigterm, int, 0444);
725MODULE_PARM_DESC(send_sigterm,
726 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
727
728/**
729 * DOC: debug_largebar (int)
730 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
731 * system. This limits the VRAM size reported to ROCm applications to the visible
732 * size, usually 256MB.
733 * Default value is 0, diabled.
734 */
2690262e 735int debug_largebar;
521fb7d0
AL		 736module_param(debug_largebar, int, 0444);
737MODULE_PARM_DESC(debug_largebar,
738 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
739
740/**
741 * DOC: ignore_crat (int)
742 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
743 * table to get information about AMD APUs. This option can serve as a workaround on
744 * systems with a broken CRAT table.
6127896f
HR		 745 *
746 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
cec2cc7b 747 * whether use CRAT)
521fb7d0 748 */
2690262e 749int ignore_crat;
521fb7d0
AL		 750module_param(ignore_crat, int, 0444);
751MODULE_PARM_DESC(ignore_crat,
6127896f 752 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
521fb7d0 753
521fb7d0
AL		 754/**
755 * DOC: halt_if_hws_hang (int)
756 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
757 * Setting 1 enables halt on hang.
758 */
2690262e 759int halt_if_hws_hang;
521fb7d0
AL		 760module_param(halt_if_hws_hang, int, 0644);
761MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 762
763/**
764 * DOC: hws_gws_support(bool)
29633d0e
JG		 765 * Assume that HWS supports GWS barriers regardless of what firmware version
766 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 767 */
768bool hws_gws_support;
769module_param(hws_gws_support, bool, 0444);
29633d0e 770MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 771
772/**
773 * DOC: queue_preemption_timeout_ms (int)
774 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
775 */
f51af435 776int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 777module_param(queue_preemption_timeout_ms, int, 0644);
778MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 779
780/**
781 * DOC: debug_evictions(bool)
782 * Enable extra debug messages to help determine the cause of evictions
783 */
784bool debug_evictions;
785module_param(debug_evictions, bool, 0644);
786MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 787
788/**
789 * DOC: no_system_mem_limit(bool)
790 * Disable system memory limit, to support multiple process shared memory
791 */
792bool no_system_mem_limit;
793module_param(no_system_mem_limit, bool, 0644);
794MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
795
6d909c5d
OZ		 796/**
797 * DOC: no_queue_eviction_on_vm_fault (int)
798 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
799 */
800int amdgpu_no_queue_eviction_on_vm_fault = 0;
801MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
802module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 803#endif
521fb7d0 804
7875a226
AD		 805/**
806 * DOC: dcfeaturemask (uint)
807 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
808 * The default is the current set of stable display features.
809 */
810MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
811module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
812
8a791dab
HW		 813/**
814 * DOC: dcdebugmask (uint)
815 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
816 */
817MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
818module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
819
ad4de27f
NK		 820/**
821 * DOC: abmlevel (uint)
822 * Override the default ABM (Adaptive Backlight Management) level used for DC
823 * enabled hardware. Requires DMCU to be supported and loaded.
824 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
825 * default. Values 1-4 control the maximum allowable brightness reduction via
826 * the ABM algorithm, with 1 being the least reduction and 4 being the most
827 * reduction.
828 *
829 * Defaults to 0, or disabled. Userspace can still override this level later
830 * after boot.
831 */
87fb7833 832uint amdgpu_dm_abm_level;
ad4de27f
NK		 833MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
834module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
835
7a46f05e
TI		 836int amdgpu_backlight = -1;
837MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
838module_param_named(backlight, amdgpu_backlight, bint, 0444);
839
d7ccb38d
HR		 840/**
841 * DOC: tmz (int)
842 * Trusted Memory Zone (TMZ) is a method to protect data being written
843 * to or read from memory.
844 *
845 * The default value: 0 (off). TODO: change to auto till it is completed.
846 */
58aa7790 847MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 848module_param_named(tmz, amdgpu_tmz, int, 0444);
849
273da6ff
WS		 850/**
851 * DOC: reset_method (int)
2656fd23 852 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
273da6ff 853 */
2656fd23 854MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
273da6ff
WS		 855module_param_named(reset_method, amdgpu_reset_method, int, 0444);
856
acc0204c 857/**
e4e6a589
LT		 858 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
859 * threshold value of faulty pages detected by RAS ECC, which may
860 * result in the GPU entering bad status when the number of total
861 * faulty pages by ECC exceeds the threshold value.
acc0204c 862 */
68daadf3 863MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
acc0204c
GC		 864module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
865
a300de40
ML		 866MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
867module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
868
11eb648d
RD		 869/**
870 * DOC: vcnfw_log (int)
871 * Enable vcnfw log output for debugging, the default is disabled.
872 */
873MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
874module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
875
8738a82b
LL		 876/**
877 * DOC: smu_pptable_id (int)
878 * Used to override pptable id. id = 0 use VBIOS pptable.
879 * id > 0 use the soft pptable with specicfied id.
880 */
881MODULE_PARM_DESC(smu_pptable_id,
882 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
883module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
884
bdbeb0dd
AD		 885/* These devices are not supported by amdgpu.
886 * They are supported by the mach64, r128, radeon drivers
887 */
888static const u16 amdgpu_unsupported_pciidlist[] = {
889 /* mach64 */
890 0x4354,
891 0x4358,
892 0x4554,
893 0x4742,
894 0x4744,
895 0x4749,
896 0x474C,
897 0x474D,
898 0x474E,
899 0x474F,
900 0x4750,
901 0x4751,
902 0x4752,
903 0x4753,
904 0x4754,
905 0x4755,
906 0x4756,
907 0x4757,
908 0x4758,
909 0x4759,
910 0x475A,
911 0x4C42,
912 0x4C44,
913 0x4C47,
914 0x4C49,
915 0x4C4D,
916 0x4C4E,
917 0x4C50,
918 0x4C51,
919 0x4C52,
920 0x4C53,
921 0x5654,
922 0x5655,
923 0x5656,
924 /* r128 */
925 0x4c45,
926 0x4c46,
927 0x4d46,
928 0x4d4c,
929 0x5041,
930 0x5042,
931 0x5043,
932 0x5044,
933 0x5045,
934 0x5046,
935 0x5047,
936 0x5048,
937 0x5049,
938 0x504A,
939 0x504B,
940 0x504C,
941 0x504D,
942 0x504E,
943 0x504F,
944 0x5050,
945 0x5051,
946 0x5052,
947 0x5053,
948 0x5054,
949 0x5055,
950 0x5056,
951 0x5057,
952 0x5058,
953 0x5245,
954 0x5246,
955 0x5247,
956 0x524b,
957 0x524c,
958 0x534d,
959 0x5446,
960 0x544C,
961 0x5452,
962 /* radeon */
963 0x3150,
964 0x3151,
965 0x3152,
966 0x3154,
967 0x3155,
968 0x3E50,
969 0x3E54,
970 0x4136,
971 0x4137,
972 0x4144,
973 0x4145,
974 0x4146,
975 0x4147,
976 0x4148,
977 0x4149,
978 0x414A,
979 0x414B,
980 0x4150,
981 0x4151,
982 0x4152,
983 0x4153,
984 0x4154,
985 0x4155,
986 0x4156,
987 0x4237,
988 0x4242,
989 0x4336,
990 0x4337,
991 0x4437,
992 0x4966,
993 0x4967,
994 0x4A48,
995 0x4A49,
996 0x4A4A,
997 0x4A4B,
998 0x4A4C,
999 0x4A4D,
1000 0x4A4E,
1001 0x4A4F,
1002 0x4A50,
1003 0x4A54,
1004 0x4B48,
1005 0x4B49,
1006 0x4B4A,
1007 0x4B4B,
1008 0x4B4C,
1009 0x4C57,
1010 0x4C58,
1011 0x4C59,
1012 0x4C5A,
1013 0x4C64,
1014 0x4C66,
1015 0x4C67,
1016 0x4E44,
1017 0x4E45,
1018 0x4E46,
1019 0x4E47,
1020 0x4E48,
1021 0x4E49,
1022 0x4E4A,
1023 0x4E4B,
1024 0x4E50,
1025 0x4E51,
1026 0x4E52,
1027 0x4E53,
1028 0x4E54,
1029 0x4E56,
1030 0x5144,
1031 0x5145,
1032 0x5146,
1033 0x5147,
1034 0x5148,
1035 0x514C,
1036 0x514D,
1037 0x5157,
1038 0x5158,
1039 0x5159,
1040 0x515A,
1041 0x515E,
1042 0x5460,
1043 0x5462,
1044 0x5464,
1045 0x5548,
1046 0x5549,
1047 0x554A,
1048 0x554B,
1049 0x554C,
1050 0x554D,
1051 0x554E,
1052 0x554F,
1053 0x5550,
1054 0x5551,
1055 0x5552,
1056 0x5554,
1057 0x564A,
1058 0x564B,
1059 0x564F,
1060 0x5652,
1061 0x5653,
1062 0x5657,
1063 0x5834,
1064 0x5835,
1065 0x5954,
1066 0x5955,
1067 0x5974,
1068 0x5975,
1069 0x5960,
1070 0x5961,
1071 0x5962,
1072 0x5964,
1073 0x5965,
1074 0x5969,
1075 0x5a41,
1076 0x5a42,
1077 0x5a61,
1078 0x5a62,
1079 0x5b60,
1080 0x5b62,
1081 0x5b63,
1082 0x5b64,
1083 0x5b65,
1084 0x5c61,
1085 0x5c63,
1086 0x5d48,
1087 0x5d49,
1088 0x5d4a,
1089 0x5d4c,
1090 0x5d4d,
1091 0x5d4e,
1092 0x5d4f,
1093 0x5d50,
1094 0x5d52,
1095 0x5d57,
1096 0x5e48,
1097 0x5e4a,
1098 0x5e4b,
1099 0x5e4c,
1100 0x5e4d,
1101 0x5e4f,
1102 0x6700,
1103 0x6701,
1104 0x6702,
1105 0x6703,
1106 0x6704,
1107 0x6705,
1108 0x6706,
1109 0x6707,
1110 0x6708,
1111 0x6709,
1112 0x6718,
1113 0x6719,
1114 0x671c,
1115 0x671d,
1116 0x671f,
1117 0x6720,
1118 0x6721,
1119 0x6722,
1120 0x6723,
1121 0x6724,
1122 0x6725,
1123 0x6726,
1124 0x6727,
1125 0x6728,
1126 0x6729,
1127 0x6738,
1128 0x6739,
1129 0x673e,
1130 0x6740,
1131 0x6741,
1132 0x6742,
1133 0x6743,
1134 0x6744,
1135 0x6745,
1136 0x6746,
1137 0x6747,
1138 0x6748,
1139 0x6749,
1140 0x674A,
1141 0x6750,
1142 0x6751,
1143 0x6758,
1144 0x6759,
1145 0x675B,
1146 0x675D,
1147 0x675F,
1148 0x6760,
1149 0x6761,
1150 0x6762,
1151 0x6763,
1152 0x6764,
1153 0x6765,
1154 0x6766,
1155 0x6767,
1156 0x6768,
1157 0x6770,
1158 0x6771,
1159 0x6772,
1160 0x6778,
1161 0x6779,
1162 0x677B,
1163 0x6840,
1164 0x6841,
1165 0x6842,
1166 0x6843,
1167 0x6849,
1168 0x684C,
1169 0x6850,
1170 0x6858,
1171 0x6859,
1172 0x6880,
1173 0x6888,
1174 0x6889,
1175 0x688A,
1176 0x688C,
1177 0x688D,
1178 0x6898,
1179 0x6899,
1180 0x689b,
1181 0x689c,
1182 0x689d,
1183 0x689e,
1184 0x68a0,
1185 0x68a1,
1186 0x68a8,
1187 0x68a9,
1188 0x68b0,
1189 0x68b8,
1190 0x68b9,
1191 0x68ba,
1192 0x68be,
1193 0x68bf,
1194 0x68c0,
1195 0x68c1,
1196 0x68c7,
1197 0x68c8,
1198 0x68c9,
1199 0x68d8,
1200 0x68d9,
1201 0x68da,
1202 0x68de,
1203 0x68e0,
1204 0x68e1,
1205 0x68e4,
1206 0x68e5,
1207 0x68e8,
1208 0x68e9,
1209 0x68f1,
1210 0x68f2,
1211 0x68f8,
1212 0x68f9,
1213 0x68fa,
1214 0x68fe,
1215 0x7100,
1216 0x7101,
1217 0x7102,
1218 0x7103,
1219 0x7104,
1220 0x7105,
1221 0x7106,
1222 0x7108,
1223 0x7109,
1224 0x710A,
1225 0x710B,
1226 0x710C,
1227 0x710E,
1228 0x710F,
1229 0x7140,
1230 0x7141,
1231 0x7142,
1232 0x7143,
1233 0x7144,
1234 0x7145,
1235 0x7146,
1236 0x7147,
1237 0x7149,
1238 0x714A,
1239 0x714B,
1240 0x714C,
1241 0x714D,
1242 0x714E,
1243 0x714F,
1244 0x7151,
1245 0x7152,
1246 0x7153,
1247 0x715E,
1248 0x715F,
1249 0x7180,
1250 0x7181,
1251 0x7183,
1252 0x7186,
1253 0x7187,
1254 0x7188,
1255 0x718A,
1256 0x718B,
1257 0x718C,
1258 0x718D,
1259 0x718F,
1260 0x7193,
1261 0x7196,
1262 0x719B,
1263 0x719F,
1264 0x71C0,
1265 0x71C1,
1266 0x71C2,
1267 0x71C3,
1268 0x71C4,
1269 0x71C5,
1270 0x71C6,
1271 0x71C7,
1272 0x71CD,
1273 0x71CE,
1274 0x71D2,
1275 0x71D4,
1276 0x71D5,
1277 0x71D6,
1278 0x71DA,
1279 0x71DE,
1280 0x7200,
1281 0x7210,
1282 0x7211,
1283 0x7240,
1284 0x7243,
1285 0x7244,
1286 0x7245,
1287 0x7246,
1288 0x7247,
1289 0x7248,
1290 0x7249,
1291 0x724A,
1292 0x724B,
1293 0x724C,
1294 0x724D,
1295 0x724E,
1296 0x724F,
1297 0x7280,
1298 0x7281,
1299 0x7283,
1300 0x7284,
1301 0x7287,
1302 0x7288,
1303 0x7289,
1304 0x728B,
1305 0x728C,
1306 0x7290,
1307 0x7291,
1308 0x7293,
1309 0x7297,
1310 0x7834,
1311 0x7835,
1312 0x791e,
1313 0x791f,
1314 0x793f,
1315 0x7941,
1316 0x7942,
1317 0x796c,
1318 0x796d,
1319 0x796e,
1320 0x796f,
1321 0x9400,
1322 0x9401,
1323 0x9402,
1324 0x9403,
1325 0x9405,
1326 0x940A,
1327 0x940B,
1328 0x940F,
1329 0x94A0,
1330 0x94A1,
1331 0x94A3,
1332 0x94B1,
1333 0x94B3,
1334 0x94B4,
1335 0x94B5,
1336 0x94B9,
1337 0x9440,
1338 0x9441,
1339 0x9442,
1340 0x9443,
1341 0x9444,
1342 0x9446,
1343 0x944A,
1344 0x944B,
1345 0x944C,
1346 0x944E,
1347 0x9450,
1348 0x9452,
1349 0x9456,
1350 0x945A,
1351 0x945B,
1352 0x945E,
1353 0x9460,
1354 0x9462,
1355 0x946A,
1356 0x946B,
1357 0x947A,
1358 0x947B,
1359 0x9480,
1360 0x9487,
1361 0x9488,
1362 0x9489,
1363 0x948A,
1364 0x948F,
1365 0x9490,
1366 0x9491,
1367 0x9495,
1368 0x9498,
1369 0x949C,
1370 0x949E,
1371 0x949F,
1372 0x94C0,
1373 0x94C1,
1374 0x94C3,
1375 0x94C4,
1376 0x94C5,
1377 0x94C6,
1378 0x94C7,
1379 0x94C8,
1380 0x94C9,
1381 0x94CB,
1382 0x94CC,
1383 0x94CD,
1384 0x9500,
1385 0x9501,
1386 0x9504,
1387 0x9505,
1388 0x9506,
1389 0x9507,
1390 0x9508,
1391 0x9509,
1392 0x950F,
1393 0x9511,
1394 0x9515,
1395 0x9517,
1396 0x9519,
1397 0x9540,
1398 0x9541,
1399 0x9542,
1400 0x954E,
1401 0x954F,
1402 0x9552,
1403 0x9553,
1404 0x9555,
1405 0x9557,
1406 0x955f,
1407 0x9580,
1408 0x9581,
1409 0x9583,
1410 0x9586,
1411 0x9587,
1412 0x9588,
1413 0x9589,
1414 0x958A,
1415 0x958B,
1416 0x958C,
1417 0x958D,
1418 0x958E,
1419 0x958F,
1420 0x9590,
1421 0x9591,
1422 0x9593,
1423 0x9595,
1424 0x9596,
1425 0x9597,
1426 0x9598,
1427 0x9599,
1428 0x959B,
1429 0x95C0,
1430 0x95C2,
1431 0x95C4,
1432 0x95C5,
1433 0x95C6,
1434 0x95C7,
1435 0x95C9,
1436 0x95CC,
1437 0x95CD,
1438 0x95CE,
1439 0x95CF,
1440 0x9610,
1441 0x9611,
1442 0x9612,
1443 0x9613,
1444 0x9614,
1445 0x9615,
1446 0x9616,
1447 0x9640,
1448 0x9641,
1449 0x9642,
1450 0x9643,
1451 0x9644,
1452 0x9645,
1453 0x9647,
1454 0x9648,
1455 0x9649,
1456 0x964a,
1457 0x964b,
1458 0x964c,
1459 0x964e,
1460 0x964f,
1461 0x9710,
1462 0x9711,
1463 0x9712,
1464 0x9713,
1465 0x9714,
1466 0x9715,
1467 0x9802,
1468 0x9803,
1469 0x9804,
1470 0x9805,
1471 0x9806,
1472 0x9807,
1473 0x9808,
1474 0x9809,
1475 0x980A,
1476 0x9900,
1477 0x9901,
1478 0x9903,
1479 0x9904,
1480 0x9905,
1481 0x9906,
1482 0x9907,
1483 0x9908,
1484 0x9909,
1485 0x990A,
1486 0x990B,
1487 0x990C,
1488 0x990D,
1489 0x990E,
1490 0x990F,
1491 0x9910,
1492 0x9913,
1493 0x9917,
1494 0x9918,
1495 0x9919,
1496 0x9990,
1497 0x9991,
1498 0x9992,
1499 0x9993,
1500 0x9994,
1501 0x9995,
1502 0x9996,
1503 0x9997,
1504 0x9998,
1505 0x9999,
1506 0x999A,
1507 0x999B,
1508 0x999C,
1509 0x999D,
1510 0x99A0,
1511 0x99A2,
1512 0x99A4,
9e5a14bc
AD		 1513 /* radeon secondary ids */
1514 0x3171,
1515 0x3e70,
1516 0x4164,
1517 0x4165,
1518 0x4166,
1519 0x4168,
1520 0x4170,
1521 0x4171,
1522 0x4172,
1523 0x4173,
1524 0x496e,
1525 0x4a69,
1526 0x4a6a,
1527 0x4a6b,
1528 0x4a70,
1529 0x4a74,
1530 0x4b69,
1531 0x4b6b,
1532 0x4b6c,
1533 0x4c6e,
1534 0x4e64,
1535 0x4e65,
1536 0x4e66,
1537 0x4e67,
1538 0x4e68,
1539 0x4e69,
1540 0x4e6a,
1541 0x4e71,
1542 0x4f73,
1543 0x5569,
1544 0x556b,
1545 0x556d,
1546 0x556f,
1547 0x5571,
1548 0x5854,
1549 0x5874,
1550 0x5940,
1551 0x5941,
1552 0x5b72,
1553 0x5b73,
1554 0x5b74,
1555 0x5b75,
1556 0x5d44,
1557 0x5d45,
1558 0x5d6d,
1559 0x5d6f,
1560 0x5d72,
1561 0x5d77,
1562 0x5e6b,
1563 0x5e6d,
1564 0x7120,
1565 0x7124,
1566 0x7129,
1567 0x712e,
1568 0x712f,
1569 0x7162,
1570 0x7163,
1571 0x7166,
1572 0x7167,
1573 0x7172,
1574 0x7173,
1575 0x71a0,
1576 0x71a1,
1577 0x71a3,
1578 0x71a7,
1579 0x71bb,
1580 0x71e0,
1581 0x71e1,
1582 0x71e2,
1583 0x71e6,
1584 0x71e7,
1585 0x71f2,
1586 0x7269,
1587 0x726b,
1588 0x726e,
1589 0x72a0,
1590 0x72a8,
1591 0x72b1,
1592 0x72b3,
1593 0x793f,
bdbeb0dd
AD		 1594};
1595
f498d9ed 1596static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 1597#ifdef CONFIG_DRM_AMDGPU_SI
1598 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1599 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1600 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1601 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1602 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1603 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1604 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1605 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1606 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1607 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1608 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1609 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1610 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1611 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1612 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1613 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1614 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1615 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1616 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1617 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1618 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1619 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1620 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1621 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1622 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1623 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1624 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1625 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1626 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1627 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1628 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1629 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1630 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1631 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1632 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1633 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1634 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1635 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1636 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1637 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1638 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1639 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1640 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1641 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1642 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1643 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1644 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1645 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1646 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1647 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1648 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1649 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1650 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1651 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1652 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1653 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1654 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1655 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1656 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1657 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1658 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1659 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1660 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1661 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1662 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1663 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1664 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1665 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1666 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1667 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1668 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1669 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1670#endif
89330c39
AD		 1671#ifdef CONFIG_DRM_AMDGPU_CIK
1672 /* Kaveri */
2f7d10b3
JZ		 1673 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1674 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1675 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1676 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1677 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1678 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1679 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1680 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1681 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1682 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1683 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1684 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1685 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1686 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1687 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1688 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1689 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1690 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1691 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1692 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1693 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1694 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1695 /* Bonaire */
2f7d10b3
JZ		 1696 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1697 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1698 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1699 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1700 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1701 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1702 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1703 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1704 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1705 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1706 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1707 /* Hawaii */
1708 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1709 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1710 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1711 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1712 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1713 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1714 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1715 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1716 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1717 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1718 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1719 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1720 /* Kabini */
2f7d10b3
JZ		 1721 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1722 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1723 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1724 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1725 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1726 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1727 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1728 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1729 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1730 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1731 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1732 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1733 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1734 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1735 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1736 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1737 /* mullins */
2f7d10b3
JZ		 1738 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1739 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1740 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1741 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1742 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1743 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1744 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1745 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1746 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1747 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1748 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1749 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1750 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1751 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1752 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1753 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1754#endif
1256a8b8 1755 /* topaz */
dba280b2
AD		 1756 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1757 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1758 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1759 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1760 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1761 /* tonga */
1762 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1763 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1764 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1765 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1766 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1767 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1768 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1769 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1770 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1771 /* fiji */
1772 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1773 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1774 /* carrizo */
2f7d10b3
JZ		 1775 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1776 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1777 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1778 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1779 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1780 /* stoney */
1781 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1782 /* Polaris11 */
1783 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1784 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1785 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1786 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1787 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1788 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1789 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1790 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1791 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1792 /* Polaris10 */
1793 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1794 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1795 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1796 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1797 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1798 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1799 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1800 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1801 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1802 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1803 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1804 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1805 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1806 /* Polaris12 */
1807 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1808 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1809 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1810 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1811 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1812 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1813 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1814 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1815 /* VEGAM */
1816 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1817 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1818 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1819 /* Vega 10 */
dfbf0c14
AD		 1820 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1821 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1822 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1823 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1824 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1825 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1826 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1827 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1828 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1829 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1830 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1831 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1832 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1833 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1834 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1835 /* Vega 12 */
1836 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1837 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1838 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1839 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1840 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1841 /* Vega 20 */
6dddaeef
AD		 1842 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1843 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1844 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1845 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1846 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1847 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1848 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1849 /* Raven */
acc34503 1850 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1851 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1852 /* Arcturus */
12c5365e
AD		 1853 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1854 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1855 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1856 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 1857 /* Navi10 */
1858 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1859 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1860 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1861 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1862 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1863 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 1864 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1865 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1866 /* Navi14 */
b62d9554
AD		 1867 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1868 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1869 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1870 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1871
61bdb39c 1872 /* Renoir */
775da830 1873 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 1874 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 1875 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 1876 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1877
10e85054 1878 /* Navi12 */
d34c7b7b
AD		 1879 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1880 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1881
61278d14
LG		 1882 /* Sienna_Cichlid */
1883 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 1884 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 1885 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1886 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1887 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1888 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1889 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1890 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1891 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1892 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1893 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 1894 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1895 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 1896
894052d6
HR		 1897 /* Van Gogh */
1898 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1899
27f5355f
AL		 1900 /* Yellow Carp */
1901 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1902 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1903
2c1eaddd
TZ		 1904 /* Navy_Flounder */
1905 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1906 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1907 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 1908 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1909 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1910 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1911 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1912 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 1913 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1914
e7de4aee
TZ		 1915 /* DIMGREY_CAVEFISH */
1916 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1917 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1918 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 1919 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 1920 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1921 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1922 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1923 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1924 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1925 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1926 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 1927 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1928
4c2e5f51 1929 /* Aldebaran */
3786a9bc
AD		 1930 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1931 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1932 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
1933 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
4c2e5f51 1934
a8f70696
TZ		 1935 /* CYAN_SKILLFISH */
1936 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
dfcc3e8c 1937 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
a8f70696 1938
a2e9b166
CG		 1939 /* BEIGE_GOBY */
1940 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1941 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1942 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1943 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1944 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1945
eb4fd29a
AD		 1946 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1947 .class = PCI_CLASS_DISPLAY_VGA << 8,
1948 .class_mask = 0xffffff,
d0761fd2 1949 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 1950
1951 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1952 .class = PCI_CLASS_DISPLAY_OTHER << 8,
1953 .class_mask = 0xffffff,
d0761fd2 1954 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 1955
d38ceaf9
AD		 1956 {0, 0, 0}
1957};
1958
1959MODULE_DEVICE_TABLE(pci, pciidlist);
1960
5088d657 1961static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 1962
b95dc06a
AD		 1963static bool amdgpu_is_fw_framebuffer(resource_size_t base,
1964 resource_size_t size)
1965{
1966 bool found = false;
1967#if IS_REACHABLE(CONFIG_FB)
1968 struct apertures_struct *a;
1969
1970 a = alloc_apertures(1);
1971 if (!a)
1972 return false;
1973
1974 a->ranges[0].base = base;
1975 a->ranges[0].size = size;
1976
1977 found = is_firmware_framebuffer(a);
1978 kfree(a);
1979#endif
1980 return found;
1981}
1982
243c719e 1983static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
d0d66b8c
AD		 1984{
1985 struct pci_dev *p = NULL;
243c719e 1986 int i;
d0d66b8c 1987
243c719e
AD		 1988 /* 0 - GPU
1989 * 1 - audio
1990 * 2 - USB
1991 * 3 - UCSI
1992 */
1993 for (i = 1; i < 4; i++) {
1994 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
1995 adev->pdev->bus->number, i);
1996 if (p) {
1997 pm_runtime_get_sync(&p->dev);
1998 pm_runtime_mark_last_busy(&p->dev);
1999 pm_runtime_put_autosuspend(&p->dev);
2000 pci_dev_put(p);
2001 }
d0d66b8c
AD		 2002 }
2003}
2004
d38ceaf9
AD		 2005static int amdgpu_pci_probe(struct pci_dev *pdev,
2006 const struct pci_device_id *ent)
2007{
8aba21b7 2008 struct drm_device *ddev;
c6385e50 2009 struct amdgpu_device *adev;
d38ceaf9 2010 unsigned long flags = ent->driver_data;
bdbeb0dd 2011 int ret, retry = 0, i;
3fa203af 2012 bool supports_atomic = false;
b95dc06a
AD		 2013 bool is_fw_fb;
2014 resource_size_t base, size;
3fa203af 2015
bdbeb0dd
AD		 2016 /* skip devices which are owned by radeon */
2017 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2018 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2019 return -ENODEV;
2020 }
2021
7294863a
ML		 2022 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2023 amdgpu_aspm = 0;
2024
84ec374b 2025 if (amdgpu_virtual_display ||
3fa203af
AD		 2026 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2027 supports_atomic = true;
d38ceaf9 2028
2f7d10b3 2029 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 2030 DRM_INFO("This hardware requires experimental hardware support.\n"
2031 "See modparam exp_hw_support\n");
2032 return -ENODEV;
2033 }
2034
ea68573d
AD		 2035 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2036 * however, SME requires an indirect IOMMU mapping because the encryption
2037 * bit is beyond the DMA mask of the chip.
2038 */
e9d1d2bb
TL		 2039 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2040 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 2041 dev_info(&pdev->dev,
2042 "SME is not compatible with RAVEN\n");
2043 return -ENOTSUPP;
2044 }
2045
984d7a92
HG		 2046#ifdef CONFIG_DRM_AMDGPU_SI
2047 if (!amdgpu_si_support) {
2048 switch (flags & AMD_ASIC_MASK) {
2049 case CHIP_TAHITI:
2050 case CHIP_PITCAIRN:
2051 case CHIP_VERDE:
2052 case CHIP_OLAND:
2053 case CHIP_HAINAN:
2054 dev_info(&pdev->dev,
2055 "SI support provided by radeon.\n");
2056 dev_info(&pdev->dev,
2057 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2058 );
2059 return -ENODEV;
2060 }
2061 }
2062#endif
2063#ifdef CONFIG_DRM_AMDGPU_CIK
2064 if (!amdgpu_cik_support) {
2065 switch (flags & AMD_ASIC_MASK) {
2066 case CHIP_KAVERI:
2067 case CHIP_BONAIRE:
2068 case CHIP_HAWAII:
2069 case CHIP_KABINI:
2070 case CHIP_MULLINS:
2071 dev_info(&pdev->dev,
2072 "CIK support provided by radeon.\n");
2073 dev_info(&pdev->dev,
2074 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2075 );
2076 return -ENODEV;
2077 }
2078 }
2079#endif
2080
b95dc06a
AD		 2081 base = pci_resource_start(pdev, 0);
2082 size = pci_resource_len(pdev, 0);
2083 is_fw_fb = amdgpu_is_fw_framebuffer(base, size);
2084
d38ceaf9 2085 /* Get rid of things like offb */
97c9bfe3 2086 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
d38ceaf9
AD		 2087 if (ret)
2088 return ret;
2089
5088d657 2090 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 2091 if (IS_ERR(adev))
2092 return PTR_ERR(adev);
8aba21b7
LT		 2093
2094 adev->dev = &pdev->dev;
2095 adev->pdev = pdev;
2096 ddev = adev_to_drm(adev);
b95dc06a 2097 adev->is_fw_fb = is_fw_fb;
b58c1131 2098
351c4dbe 2099 if (!supports_atomic)
8aba21b7 2100 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 2101
b58c1131
AD		 2102 ret = pci_enable_device(pdev);
2103 if (ret)
df2ce459 2104 return ret;
b58c1131 2105
8aba21b7 2106 pci_set_drvdata(pdev, ddev);
b58c1131 2107
8aba21b7 2108 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
7504d3bb
LC		 2109 if (ret)
2110 goto err_pci;
c6385e50 2111
1daee8b4 2112retry_init:
8aba21b7 2113 ret = drm_dev_register(ddev, ent->driver_data);
1daee8b4
PD		 2114 if (ret == -EAGAIN && ++retry <= 3) {
2115 DRM_INFO("retry init %d\n", retry);
2116 /* Don't request EX mode too frequently which is attacking */
2117 msleep(5000);
2118 goto retry_init;
8aba21b7 2119 } else if (ret) {
b58c1131 2120 goto err_pci;
8aba21b7 2121 }
b58c1131 2122
087451f3
EQ		 2123 /*
2124 * 1. don't init fbdev on hw without DCE
2125 * 2. don't init fbdev if there are no connectors
2126 */
2127 if (adev->mode_info.mode_config_initialized &&
2128 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2129 /* select 8 bpp console on low vram cards */
2130 if (adev->gmc.real_vram_size <= (32*1024*1024))
2131 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2132 else
2133 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2134 }
2135
c6385e50
AD		 2136 ret = amdgpu_debugfs_init(adev);
2137 if (ret)
2138 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2139
d0d66b8c
AD		 2140 if (adev->runpm) {
2141 /* only need to skip on ATPX */
2142 if (amdgpu_device_supports_px(ddev))
2143 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2144 /* we want direct complete for BOCO */
2145 if (amdgpu_device_supports_boco(ddev))
2146 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2147 DPM_FLAG_SMART_SUSPEND |
2148 DPM_FLAG_MAY_SKIP_RESUME);
2149 pm_runtime_use_autosuspend(ddev->dev);
2150 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2151
2152 pm_runtime_allow(ddev->dev);
2153
2154 pm_runtime_mark_last_busy(ddev->dev);
2155 pm_runtime_put_autosuspend(ddev->dev);
2156
2157 /*
2158 * For runpm implemented via BACO, PMFW will handle the
2159 * timing for BACO in and out:
2160 * - put ASIC into BACO state only when both video and
2161 * audio functions are in D3 state.
2162 * - pull ASIC out of BACO state when either video or
2163 * audio function is in D0 state.
2164 * Also, at startup, PMFW assumes both functions are in
2165 * D0 state.
2166 *
2167 * So if snd driver was loaded prior to amdgpu driver
2168 * and audio function was put into D3 state, there will
2169 * be no PMFW-aware D-state transition(D0->D3) on runpm
2170 * suspend. Thus the BACO will be not correctly kicked in.
2171 *
243c719e 2172 * Via amdgpu_get_secondary_funcs(), the audio dev is put
d0d66b8c
AD		 2173 * into D0 state. Then there will be a PMFW-aware D-state
2174 * transition(D0->D3) on runpm suspend.
2175 */
2176 if (amdgpu_device_supports_baco(ddev) &&
2177 !(adev->flags & AMD_IS_APU) &&
2178 (adev->asic_type >= CHIP_NAVI10))
243c719e 2179 amdgpu_get_secondary_funcs(adev);
d0d66b8c
AD		 2180 }
2181
b58c1131
AD		 2182 return 0;
2183
2184err_pci:
2185 pci_disable_device(pdev);
b58c1131 2186 return ret;
d38ceaf9
AD		 2187}
2188
2189static void
2190amdgpu_pci_remove(struct pci_dev *pdev)
2191{
2192 struct drm_device *dev = pci_get_drvdata(pdev);
d0d66b8c 2193 struct amdgpu_device *adev = drm_to_adev(dev);
d38ceaf9 2194
88b35d83 2195 drm_dev_unplug(dev);
d0d66b8c
AD		 2196
2197 if (adev->runpm) {
2198 pm_runtime_get_sync(dev->dev);
2199 pm_runtime_forbid(dev->dev);
2200 }
2201
c6385e50 2202 amdgpu_driver_unload_kms(dev);
72c8c97b 2203
98c6e6a7
AG		 2204 /*
2205 * Flush any in flight DMA operations from device.
2206 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2207 * StatusTransactions Pending bit.
2208 */
fd4495e5 2209 pci_disable_device(pdev);
98c6e6a7 2210 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2211}
2212
61e11306
AD		 2213static void
2214amdgpu_pci_shutdown(struct pci_dev *pdev)
2215{
faefba95 2216 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2217 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2218
7c6e68c7
AG		 2219 if (amdgpu_ras_intr_triggered())
2220 return;
2221
61e11306 2222 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2223 * torn down properly on reboot/shutdown.
2224 * unfortunately we can't detect certain
2225 * hypervisors so just do this all the time.
61e11306 2226 */
05cac1ae
ND		 2227 if (!amdgpu_passthrough(adev))
2228 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2229 amdgpu_device_ip_suspend(adev);
a3a09142 2230 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2231}
2232
e3c1b071 2233/**
2234 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2235 *
2236 * @work: work_struct.
2237 */
2238static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2239{
2240 struct list_head device_list;
2241 struct amdgpu_device *adev;
2242 int i, r;
04442bf7
LL		 2243 struct amdgpu_reset_context reset_context;
2244
2245 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2246
2247 mutex_lock(&mgpu_info.mutex);
2248 if (mgpu_info.pending_reset == true) {
2249 mutex_unlock(&mgpu_info.mutex);
2250 return;
2251 }
2252 mgpu_info.pending_reset = true;
2253 mutex_unlock(&mgpu_info.mutex);
2254
04442bf7
LL		 2255 /* Use a common context, just need to make sure full reset is done */
2256 reset_context.method = AMD_RESET_METHOD_NONE;
2257 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2258
e3c1b071 2259 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2260 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2261 reset_context.reset_req_dev = adev;
2262 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2263 if (r) {
2264 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2265 r, adev_to_drm(adev)->unique);
2266 }
2267 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2268 r = -EALREADY;
2269 }
2270 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2271 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2272 flush_work(&adev->xgmi_reset_work);
050743da 2273 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2274 }
2275
2276 /* reset function will rebuild the xgmi hive info , clear it now */
2277 for (i = 0; i < mgpu_info.num_dgpu; i++)
2278 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2279
2280 INIT_LIST_HEAD(&device_list);
2281
2282 for (i = 0; i < mgpu_info.num_dgpu; i++)
2283 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2284
2285 /* unregister the GPU first, reset function will add them back */
2286 list_for_each_entry(adev, &device_list, reset_list)
2287 amdgpu_unregister_gpu_instance(adev);
2288
04442bf7
LL		 2289 /* Use a common context, just need to make sure full reset is done */
2290 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2291 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2292
e3c1b071 2293 if (r) {
2294 DRM_ERROR("reinit gpus failure");
2295 return;
2296 }
2297 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2298 adev = mgpu_info.gpu_ins[i].adev;
2299 if (!adev->kfd.init_complete)
2300 amdgpu_amdkfd_device_init(adev);
2301 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2302 }
2303 return;
2304}
2305
e25443d2
AD		 2306static int amdgpu_pmops_prepare(struct device *dev)
2307{
2308 struct drm_device *drm_dev = dev_get_drvdata(dev);
d2a197a4 2309 struct amdgpu_device *adev = drm_to_adev(drm_dev);
e25443d2
AD		 2310
2311 /* Return a positive number here so
2312 * DPM_FLAG_SMART_SUSPEND works properly
2313 */
b98c6299 2314 if (amdgpu_device_supports_boco(drm_dev))
9308a49d 2315 return pm_runtime_suspended(dev);
e25443d2 2316
d2a197a4
ML		 2317 /* if we will not support s3 or s2i for the device
2318 * then skip suspend
2319 */
2320 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2321 !amdgpu_acpi_is_s3_active(adev))
2322 return 1;
e25443d2
AD		 2323
2324 return 0;
2325}
2326
2327static void amdgpu_pmops_complete(struct device *dev)
2328{
2329 /* nothing to do */
2330}
2331
d38ceaf9
AD		 2332static int amdgpu_pmops_suspend(struct device *dev)
2333{
911d8b30 2334 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733 2335 struct amdgpu_device *adev = drm_to_adev(drm_dev);
74b0b157 2336
d0260f62 2337 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2338 adev->in_s0ix = true;
eac4c54b
ML		 2339 else
2340 adev->in_s3 = true;
9e051720
KHF		 2341 return amdgpu_device_suspend(drm_dev, true);
2342}
2343
2344static int amdgpu_pmops_suspend_noirq(struct device *dev)
2345{
2346 struct drm_device *drm_dev = dev_get_drvdata(dev);
2347 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2348
daf8de08 2349 if (!adev->in_s0ix)
9e051720
KHF		 2350 return amdgpu_asic_reset(adev);
2351
2352 return 0;
d38ceaf9
AD		 2353}
2354
2355static int amdgpu_pmops_resume(struct device *dev)
2356{
911d8b30 2357 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2358 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2359 int r;
85e154c2 2360
ebe86a57
AG		 2361 /* Avoids registers access if device is physically gone */
2362 if (!pci_device_is_present(adev->pdev))
2363 adev->no_hw_access = true;
2364
62498733 2365 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2366 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2367 adev->in_s0ix = false;
eac4c54b
ML		 2368 else
2369 adev->in_s3 = false;
62498733 2370 return r;
d38ceaf9
AD		 2371}
2372
2373static int amdgpu_pmops_freeze(struct device *dev)
2374{
911d8b30 2375 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2376 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2377 int r;
74b0b157 2378
62498733 2379 adev->in_s4 = true;
de185019 2380 r = amdgpu_device_suspend(drm_dev, true);
62498733 2381 adev->in_s4 = false;
897483d8
AD		 2382 if (r)
2383 return r;
2384 return amdgpu_asic_reset(adev);
d38ceaf9
AD		 2385}
2386
2387static int amdgpu_pmops_thaw(struct device *dev)
2388{
911d8b30 2389 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2390
de185019 2391 return amdgpu_device_resume(drm_dev, true);
74b0b157 2392}
2393
2394static int amdgpu_pmops_poweroff(struct device *dev)
2395{
911d8b30 2396 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2397
62498733 2398 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2399}
2400
2401static int amdgpu_pmops_restore(struct device *dev)
2402{
911d8b30 2403 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2404
de185019 2405 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2406}
2407
4020c228
AD		 2408static int amdgpu_runtime_idle_check_display(struct device *dev)
2409{
2410 struct pci_dev *pdev = to_pci_dev(dev);
2411 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2412 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2413
2414 if (adev->mode_info.num_crtc) {
2415 struct drm_connector *list_connector;
2416 struct drm_connector_list_iter iter;
2417 int ret = 0;
2418
2419 /* XXX: Return busy if any displays are connected to avoid
2420 * possible display wakeups after runtime resume due to
2421 * hotplug events in case any displays were connected while
2422 * the GPU was in suspend. Remove this once that is fixed.
2423 */
2424 mutex_lock(&drm_dev->mode_config.mutex);
2425 drm_connector_list_iter_begin(drm_dev, &iter);
2426 drm_for_each_connector_iter(list_connector, &iter) {
2427 if (list_connector->status == connector_status_connected) {
2428 ret = -EBUSY;
2429 break;
2430 }
2431 }
2432 drm_connector_list_iter_end(&iter);
2433 mutex_unlock(&drm_dev->mode_config.mutex);
2434
2435 if (ret)
2436 return ret;
2437
2438 if (amdgpu_device_has_dc_support(adev)) {
2439 struct drm_crtc *crtc;
2440
2441 drm_for_each_crtc(crtc, drm_dev) {
2442 drm_modeset_lock(&crtc->mutex, NULL);
2443 if (crtc->state->active)
2444 ret = -EBUSY;
2445 drm_modeset_unlock(&crtc->mutex);
2446 if (ret < 0)
2447 break;
2448 }
2449 } else {
2450 mutex_lock(&drm_dev->mode_config.mutex);
2451 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2452
2453 drm_connector_list_iter_begin(drm_dev, &iter);
2454 drm_for_each_connector_iter(list_connector, &iter) {
2455 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2456 ret = -EBUSY;
2457 break;
2458 }
2459 }
2460
2461 drm_connector_list_iter_end(&iter);
2462
2463 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2464 mutex_unlock(&drm_dev->mode_config.mutex);
2465 }
2466 if (ret)
2467 return ret;
2468 }
2469
2470 return 0;
2471}
2472
d38ceaf9
AD		 2473static int amdgpu_pmops_runtime_suspend(struct device *dev)
2474{
2475 struct pci_dev *pdev = to_pci_dev(dev);
2476 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2477 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2478 int ret, i;
d38ceaf9 2479
6ae6c7d4 2480 if (!adev->runpm) {
d38ceaf9
AD		 2481 pm_runtime_forbid(dev);
2482 return -EBUSY;
2483 }
2484
4020c228
AD		 2485 ret = amdgpu_runtime_idle_check_display(dev);
2486 if (ret)
2487 return ret;
2488
719423f6
AD		 2489 /* wait for all rings to drain before suspending */
2490 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2491 struct amdgpu_ring *ring = adev->rings[i];
2492 if (ring && ring->sched.ready) {
2493 ret = amdgpu_fence_wait_empty(ring);
2494 if (ret)
2495 return -EBUSY;
2496 }
2497 }
2498
f0f7ddfc 2499 adev->in_runpm = true;
b98c6299 2500 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2501 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2502
7be3be2b
EQ		 2503 /*
2504 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2505 * proper cleanups and put itself into a state ready for PNP. That
2506 * can address some random resuming failure observed on BOCO capable
2507 * platforms.
2508 * TODO: this may be also needed for PX capable platform.
2509 */
2510 if (amdgpu_device_supports_boco(drm_dev))
2511 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2512
de185019 2513 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2514 if (ret) {
2515 adev->in_runpm = false;
7be3be2b
EQ		 2516 if (amdgpu_device_supports_boco(drm_dev))
2517 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2518 return ret;
cef8b03b 2519 }
70bedd68 2520
7be3be2b
EQ		 2521 if (amdgpu_device_supports_boco(drm_dev))
2522 adev->mp1_state = PP_MP1_STATE_NONE;
2523
b98c6299 2524 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2525 /* Only need to handle PCI state in the driver for ATPX
2526 * PCI core handles it for _PR3.
2527 */
b98c6299
AD		 2528 amdgpu_device_cache_pci_state(pdev);
2529 pci_disable_device(pdev);
2530 pci_ignore_hotplug(pdev);
2531 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2532 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2533 } else if (amdgpu_device_supports_boco(drm_dev)) {
2534 /* nothing to do */
19134317
AD		 2535 } else if (amdgpu_device_supports_baco(drm_dev)) {
2536 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2537 }
d38ceaf9
AD		 2538
2539 return 0;
2540}
2541
2542static int amdgpu_pmops_runtime_resume(struct device *dev)
2543{
2544 struct pci_dev *pdev = to_pci_dev(dev);
2545 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2546 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2547 int ret;
2548
6ae6c7d4 2549 if (!adev->runpm)
d38ceaf9
AD		 2550 return -EINVAL;
2551
e1543d83
AG		 2552 /* Avoids registers access if device is physically gone */
2553 if (!pci_device_is_present(adev->pdev))
2554 adev->no_hw_access = true;
2555
b98c6299 2556 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2557 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2558
562b49fc
AD		 2559 /* Only need to handle PCI state in the driver for ATPX
2560 * PCI core handles it for _PR3.
2561 */
b98c6299
AD		 2562 pci_set_power_state(pdev, PCI_D0);
2563 amdgpu_device_load_pci_state(pdev);
2564 ret = pci_enable_device(pdev);
2565 if (ret)
2566 return ret;
637bb036 2567 pci_set_master(pdev);
fd496ca8
AD		 2568 } else if (amdgpu_device_supports_boco(drm_dev)) {
2569 /* Only need to handle PCI state in the driver for ATPX
2570 * PCI core handles it for _PR3.
2571 */
2572 pci_set_master(pdev);
19134317
AD		 2573 } else if (amdgpu_device_supports_baco(drm_dev)) {
2574 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2575 }
de185019 2576 ret = amdgpu_device_resume(drm_dev, false);
b45aeb2d
PKR		 2577 if (ret)
2578 return ret;
2579
b98c6299 2580 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2581 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2582 adev->in_runpm = false;
d38ceaf9
AD		 2583 return 0;
2584}
2585
2586static int amdgpu_pmops_runtime_idle(struct device *dev)
2587{
911d8b30 2588 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2589 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 2590 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2591 int ret = 1;
d38ceaf9 2592
6ae6c7d4 2593 if (!adev->runpm) {
d38ceaf9
AD		 2594 pm_runtime_forbid(dev);
2595 return -EBUSY;
2596 }
2597
4020c228 2598 ret = amdgpu_runtime_idle_check_display(dev);
97f6a21b 2599
d38ceaf9
AD		 2600 pm_runtime_mark_last_busy(dev);
2601 pm_runtime_autosuspend(dev);
97f6a21b 2602 return ret;
d38ceaf9
AD		 2603}
2604
2605long amdgpu_drm_ioctl(struct file *filp,
2606 unsigned int cmd, unsigned long arg)
2607{
2608 struct drm_file *file_priv = filp->private_data;
2609 struct drm_device *dev;
2610 long ret;
2611 dev = file_priv->minor->dev;
2612 ret = pm_runtime_get_sync(dev->dev);
2613 if (ret < 0)
5509ac65 2614 goto out;
d38ceaf9
AD		 2615
2616 ret = drm_ioctl(filp, cmd, arg);
2617
2618 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2619out:
d38ceaf9
AD		 2620 pm_runtime_put_autosuspend(dev->dev);
2621 return ret;
2622}
2623
2624static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2625 .prepare = amdgpu_pmops_prepare,
2626 .complete = amdgpu_pmops_complete,
d38ceaf9 2627 .suspend = amdgpu_pmops_suspend,
9e051720 2628 .suspend_noirq = amdgpu_pmops_suspend_noirq,
d38ceaf9
AD		 2629 .resume = amdgpu_pmops_resume,
2630 .freeze = amdgpu_pmops_freeze,
2631 .thaw = amdgpu_pmops_thaw,
74b0b157 2632 .poweroff = amdgpu_pmops_poweroff,
2633 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2634 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2635 .runtime_resume = amdgpu_pmops_runtime_resume,
2636 .runtime_idle = amdgpu_pmops_runtime_idle,
2637};
2638
48ad368a
AG		 2639static int amdgpu_flush(struct file *f, fl_owner_t id)
2640{
2641 struct drm_file *file_priv = f->private_data;
2642 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2643 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2644
56753e73
CK		 2645 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2646 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2647
56753e73 2648 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2649}
2650
d38ceaf9
AD		 2651static const struct file_operations amdgpu_driver_kms_fops = {
2652 .owner = THIS_MODULE,
2653 .open = drm_open,
48ad368a 2654 .flush = amdgpu_flush,
d38ceaf9
AD		 2655 .release = drm_release,
2656 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2657 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2658 .poll = drm_poll,
2659 .read = drm_read,
2660#ifdef CONFIG_COMPAT
2661 .compat_ioctl = amdgpu_kms_compat_ioctl,
2662#endif
87444254
RS		 2663#ifdef CONFIG_PROC_FS
2664 .show_fdinfo = amdgpu_show_fdinfo
2665#endif
d38ceaf9
AD		 2666};
2667
021830d2
BN		 2668int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2669{
f3729f7b 2670 struct drm_file *file;
021830d2
BN		 2671
2672 if (!filp)
2673 return -EINVAL;
2674
2675 if (filp->f_op != &amdgpu_driver_kms_fops) {
2676 return -EINVAL;
2677 }
2678
2679 file = filp->private_data;
2680 *fpriv = file->driver_priv;
2681 return 0;
2682}
2683
5088d657
LT		 2684const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2685 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2686 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2687 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2688 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2689 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2690 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2691 /* KMS */
2692 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2693 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2694 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2695 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2696 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2697 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2698 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2699 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2700 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2701 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2702};
2703
2704static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2705 .driver_features =
f3ed6739 2706 DRIVER_ATOMIC |
1ff49481 2707 DRIVER_GEM |
db4ff423
CZ		 2708 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2709 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2710 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2711 .postclose = amdgpu_driver_postclose_kms,
2712 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2713 .ioctls = amdgpu_ioctls_kms,
5088d657 2714 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2715 .dumb_create = amdgpu_mode_dumb_create,
2716 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2717 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2718 .release = &amdgpu_driver_release_kms,
d38ceaf9
AD		 2719
2720 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2721 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
09052fc3 2722 .gem_prime_import = amdgpu_gem_prime_import,
71df0368 2723 .gem_prime_mmap = drm_gem_prime_mmap,
d38ceaf9
AD		 2724
2725 .name = DRIVER_NAME,
2726 .desc = DRIVER_DESC,
2727 .date = DRIVER_DATE,
2728 .major = KMS_DRIVER_MAJOR,
2729 .minor = KMS_DRIVER_MINOR,
2730 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2731};
2732
c9a6b82f
AG		 2733static struct pci_error_handlers amdgpu_pci_err_handler = {
2734 .error_detected = amdgpu_pci_error_detected,
2735 .mmio_enabled = amdgpu_pci_mmio_enabled,
2736 .slot_reset = amdgpu_pci_slot_reset,
2737 .resume = amdgpu_pci_resume,
2738};
2739
35bba831
AG		 2740extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2741extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2742extern const struct attribute_group amdgpu_vbios_version_attr_group;
2743
2744static const struct attribute_group *amdgpu_sysfs_groups[] = {
2745 &amdgpu_vram_mgr_attr_group,
2746 &amdgpu_gtt_mgr_attr_group,
2747 &amdgpu_vbios_version_attr_group,
2748 NULL,
2749};
2750
2751
d38ceaf9
AD		 2752static struct pci_driver amdgpu_kms_pci_driver = {
2753 .name = DRIVER_NAME,
2754 .id_table = pciidlist,
2755 .probe = amdgpu_pci_probe,
2756 .remove = amdgpu_pci_remove,
61e11306 2757 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2758 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2759 .err_handler = &amdgpu_pci_err_handler,
35bba831 2760 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2761};
2762
2763static int __init amdgpu_init(void)
2764{
245ae5e9
CK		 2765 int r;
2766
6a2d2ddf 2767 if (drm_firmware_drivers_only())
c60e22f7 2768 return -EINVAL;
c60e22f7 2769
245ae5e9
CK		 2770 r = amdgpu_sync_init();
2771 if (r)
2772 goto error_sync;
2773
2774 r = amdgpu_fence_slab_init();
2775 if (r)
2776 goto error_fence;
2777
d38ceaf9 2778 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 2779 amdgpu_register_atpx_handler();
f9b7f370 2780 amdgpu_acpi_detect();
03a1c08d
FK		 2781
2782 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2783 amdgpu_amdkfd_init();
2784
d38ceaf9 2785 /* let modprobe override vga console setting */
448d1051 2786 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 2787
245ae5e9
CK		 2788error_fence:
2789 amdgpu_sync_fini();
2790
2791error_sync:
2792 return r;
d38ceaf9
AD		 2793}
2794
2795static void __exit amdgpu_exit(void)
2796{
130e0371 2797 amdgpu_amdkfd_fini();
448d1051 2798 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 2799 amdgpu_unregister_atpx_handler();
257bf15a 2800 amdgpu_sync_fini();
d573de2d 2801 amdgpu_fence_slab_fini();
c7d8b782 2802 mmu_notifier_synchronize();
d38ceaf9
AD		 2803}
2804
2805module_init(amdgpu_init);
2806module_exit(amdgpu_exit);
2807
2808MODULE_AUTHOR(DRIVER_AUTHOR);
2809MODULE_DESCRIPTION(DRIVER_DESC);
2810MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)