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drm/amd/display: Enable Freesync Video Mode by default
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
6848c291 26#include <drm/drm_aperture.h>
fdf2f6c5 27#include <drm/drm_drv.h>
d38ceaf9 28#include <drm/drm_gem.h>
fdf2f6c5 29#include <drm/drm_vblank.h>
8aba21b7 30#include <drm/drm_managed.h>
d38ceaf9
AD		 31#include "amdgpu_drv.h"
32
33#include <drm/drm_pciids.h>
d38ceaf9
AD		 34#include <linux/module.h>
35#include <linux/pm_runtime.h>
36#include <linux/vga_switcheroo.h>
fcd70cd3 37#include <drm/drm_probe_helper.h>
c7d8b782 38#include <linux/mmu_notifier.h>
e25443d2 39#include <linux/suspend.h>
e9d1d2bb 40#include <linux/cc_platform.h>
d38ceaf9
AD		 41
42#include "amdgpu.h"
43#include "amdgpu_irq.h"
2fbd6f94 44#include "amdgpu_dma_buf.h"
5088d657 45#include "amdgpu_sched.h"
87444254 46#include "amdgpu_fdinfo.h"
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
7c6e68c7 49#include "amdgpu_ras.h"
e3c1b071 50#include "amdgpu_xgmi.h"
04442bf7 51#include "amdgpu_reset.h"
7c6e68c7 52
d38ceaf9
AD		 53/*
54 * KMS wrapper.
55 * - 3.0.0 - initial driver
6055f37a 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
58 * at the end of IBs.
d347ce66 59 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 61 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 63 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 64 * - 3.8.0 - Add support raster config init in the kernel
ef704318 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 68 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 69 * - 3.13.0 - Add PRT support
203eb0cb 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 71 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 72 * - 3.16.0 - Add reserved vmid support
68e2c5ff 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 74 * - 3.18.0 - Export gpu always on cu bitmap
33476319 75 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 76 * - 3.20.0 - Add support for local BOs
7ca24cf2 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 79 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 80 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
964d0fbf 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 92 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 93 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 94 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 95 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 96 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 97 * - 3.41.0 - Add video codec query
915821a7 98 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 99 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 100 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
d38ceaf9
AD		 101 */
102#define KMS_DRIVER_MAJOR 3
f2e7d856 103#define KMS_DRIVER_MINOR 44
d38ceaf9
AD		 104#define KMS_DRIVER_PATCHLEVEL 0
105
87fb7833
DV		 106int amdgpu_vram_limit;
107int amdgpu_vis_vram_limit;
83e74db6 108int amdgpu_gart_size = -1; /* auto */
36d38372 109int amdgpu_gtt_size = -1; /* auto */
95844d20 110int amdgpu_moverate = -1; /* auto */
87fb7833
DV		 111int amdgpu_benchmarking;
112int amdgpu_testing;
d38ceaf9 113int amdgpu_audio = -1;
87fb7833
DV		 114int amdgpu_disp_priority;
115int amdgpu_hw_i2c;
d38ceaf9
AD		 116int amdgpu_pcie_gen2 = -1;
117int amdgpu_msi = -1;
f440ff44 118char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 119int amdgpu_dpm = -1;
e635ee07 120int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 121int amdgpu_aspm = -1;
122int amdgpu_runtime_pm = -1;
0b693f0b 123uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 124int amdgpu_bapm = -1;
87fb7833 125int amdgpu_deep_color;
bab4fee7 126int amdgpu_vm_size = -1;
d07f14be 127int amdgpu_vm_fragment_size = -1;
d38ceaf9 128int amdgpu_vm_block_size = -1;
87fb7833
DV		 129int amdgpu_vm_fault_stop;
130int amdgpu_vm_debug;
9a4b7d4c 131int amdgpu_vm_update_mode = -1;
87fb7833 132int amdgpu_exp_hw_support;
4562236b 133int amdgpu_dc = -1;
b70f014d 134int amdgpu_sched_jobs = 32;
4afcb303 135int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 136uint amdgpu_pcie_gen_cap;
137uint amdgpu_pcie_lane_cap;
0b693f0b
RZ		 138uint amdgpu_cg_mask = 0xffffffff;
139uint amdgpu_pg_mask = 0xffffffff;
140uint amdgpu_sdma_phase_quantum = 32;
6f8941a2 141char *amdgpu_disable_cu = NULL;
9accf2fd 142char *amdgpu_virtual_display = NULL;
680602d6
KF		 143
144/*
145 * OverDrive(bit 14) disabled by default
146 * GFX DCS(bit 19) disabled by default
147 */
148uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833
DV		 149uint amdgpu_force_long_training;
150int amdgpu_job_hang_limit;
e8835e0e 151int amdgpu_lbpw = -1;
4a75aefe 152int amdgpu_compute_multipipe = -1;
dcebf026 153int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 154int amdgpu_emu_mode;
155uint amdgpu_smu_memory_pool_size;
8738a82b 156int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 157/*
158 * FBC (bit 0) disabled by default
159 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
160 * - With this, for multiple monitors in sync(e.g. with the same model),
161 * mclk switching will be allowed. And the mclk will be not foced to the
162 * highest. That helps saving some idle power.
163 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
164 * PSR (bit 3) disabled by default
a5148245 165 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 166 */
167uint amdgpu_dc_feature_mask = 2;
87fb7833 168uint amdgpu_dc_debug_mask;
5bfca069 169int amdgpu_async_gfx_ring = 1;
87fb7833 170int amdgpu_mcbp;
63e2fef6 171int amdgpu_discovery = -1;
87fb7833 172int amdgpu_mes;
d5cc02d9 173int amdgpu_noretry = -1;
4e66d7d2 174int amdgpu_force_asic_type = -1;
58aa7790 175int amdgpu_tmz = -1; /* auto */
273da6ff 176int amdgpu_reset_method = -1; /* auto */
a300de40 177int amdgpu_num_kcq = -1;
30d95a37 178int amdgpu_smartshift_bias;
7875a226 179
e3c1b071 180static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
181
62d73fbc
EQ		 182struct amdgpu_mgpu_info mgpu_info = {
183 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 184 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
185 mgpu_info.delayed_reset_work,
186 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 187};
1218252f 188int amdgpu_ras_enable = -1;
e53aec7e 189uint amdgpu_ras_mask = 0xffffffff;
acc0204c 190int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 191struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
192 .timeout_fatal_disable = false,
28a5d7a5 193 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 194};
d38ceaf9 195
8405cf39
SJ		 196/**
197 * DOC: vramlimit (int)
198 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
199 */
d38ceaf9
AD		 200MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
201module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
202
8405cf39
SJ		 203/**
204 * DOC: vis_vramlimit (int)
205 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
206 */
218b5dcd
JB		 207MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
208module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
209
8405cf39
SJ		 210/**
211 * DOC: gartsize (uint)
212 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic).
213 */
a4da14cc 214MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 215module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 216
8405cf39
SJ		 217/**
218 * DOC: gttsize (int)
219 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM,
220 * otherwise 3/4 RAM size).
221 */
36d38372
CK		 222MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
223module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 224
8405cf39
SJ		 225/**
226 * DOC: moverate (int)
227 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
228 */
95844d20
MO		 229MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
230module_param_named(moverate, amdgpu_moverate, int, 0600);
231
8405cf39
SJ		 232/**
233 * DOC: benchmark (int)
234 * Run benchmarks. The default is 0 (Skip benchmarks).
235 */
d38ceaf9
AD		 236MODULE_PARM_DESC(benchmark, "Run benchmark");
237module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
238
8405cf39
SJ		 239/**
240 * DOC: test (int)
241 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test).
242 */
d38ceaf9
AD		 243MODULE_PARM_DESC(test, "Run tests");
244module_param_named(test, amdgpu_testing, int, 0444);
245
8405cf39
SJ		 246/**
247 * DOC: audio (int)
248 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
249 */
d38ceaf9
AD		 250MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
251module_param_named(audio, amdgpu_audio, int, 0444);
252
8405cf39
SJ		 253/**
254 * DOC: disp_priority (int)
255 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
256 */
d38ceaf9
AD		 257MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
258module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
259
8405cf39
SJ		 260/**
261 * DOC: hw_i2c (int)
262 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
263 */
d38ceaf9
AD		 264MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
265module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
266
8405cf39
SJ		 267/**
268 * DOC: pcie_gen2 (int)
269 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
270 */
d38ceaf9
AD		 271MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
272module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
273
8405cf39
SJ		 274/**
275 * DOC: msi (int)
276 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
277 */
d38ceaf9
AD		 278MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
279module_param_named(msi, amdgpu_msi, int, 0444);
280
8405cf39 281/**
912dfc84
EQ		 282 * DOC: lockup_timeout (string)
283 * Set GPU scheduler timeout value in ms.
284 *
285 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
286 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 287 * to the default timeout.
288 *
289 * - With one value specified, the setting will apply to all non-compute jobs.
290 * - With multiple values specified, the first one will be for GFX.
291 * The second one is for Compute. The third and fourth ones are
292 * for SDMA and Video.
293 *
912dfc84 294 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 295 * jobs is 10000. The timeout for compute is 60000.
912dfc84 296 */
67387dfe 297MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
bcccee89 298 "for passthrough or sriov, 10000 for all jobs."
71cc9ef3 299 " 0: keep default value. negative: infinity timeout), "
bcccee89
ED		 300 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
301 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 302module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 303
8405cf39
SJ		 304/**
305 * DOC: dpm (int)
54b998ca 306 * Override for dynamic power management setting
5c9a6272 307 * (0 = disable, 1 = enable)
54b998ca 308 * The default is -1 (auto).
8405cf39 309 */
d38ceaf9
AD		 310MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
311module_param_named(dpm, amdgpu_dpm, int, 0444);
312
8405cf39
SJ		 313/**
314 * DOC: fw_load_type (int)
ddb267b6
YD		 315 * Set different firmware loading type for debugging, if supported.
316 * Set to 0 to force direct loading if supported by the ASIC. Set
317 * to -1 to select the default loading mode for the ASIC, as defined
318 * by the driver. The default is -1 (auto).
8405cf39 319 */
ddb267b6 320MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = force direct if supported, -1 = auto)");
e635ee07 321module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 322
8405cf39
SJ		 323/**
324 * DOC: aspm (int)
325 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
326 */
d38ceaf9
AD		 327MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
328module_param_named(aspm, amdgpu_aspm, int, 0444);
329
8405cf39
SJ		 330/**
331 * DOC: runpm (int)
937ed9c8
AD		 332 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
333 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
334 * Setting the value to 0 disables this functionality.
8405cf39 335 */
937ed9c8 336MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)");
d38ceaf9
AD		 337module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
338
8405cf39
SJ		 339/**
340 * DOC: ip_block_mask (uint)
341 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
342 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
343 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
344 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
345 */
d38ceaf9
AD		 346MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
347module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
348
8405cf39
SJ		 349/**
350 * DOC: bapm (int)
351 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
352 * The default -1 (auto, enabled)
353 */
d38ceaf9
AD		 354MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
355module_param_named(bapm, amdgpu_bapm, int, 0444);
356
8405cf39
SJ		 357/**
358 * DOC: deep_color (int)
359 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
360 */
d38ceaf9
AD		 361MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
362module_param_named(deep_color, amdgpu_deep_color, int, 0444);
363
8405cf39
SJ		 364/**
365 * DOC: vm_size (int)
366 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
367 */
ed885b21 368MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 369module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 370
8405cf39
SJ		 371/**
372 * DOC: vm_fragment_size (int)
373 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
374 */
d07f14be
RH		 375MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
376module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 377
8405cf39
SJ		 378/**
379 * DOC: vm_block_size (int)
380 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
381 */
d38ceaf9
AD		 382MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
383module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
384
8405cf39
SJ		 385/**
386 * DOC: vm_fault_stop (int)
387 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
388 */
d9c13156
CK		 389MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
390module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
391
8405cf39
SJ		 392/**
393 * DOC: vm_debug (int)
394 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled).
395 */
b495bd3a
CK		 396MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
397module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
398
8405cf39
SJ		 399/**
400 * DOC: vm_update_mode (int)
401 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
402 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
403 */
9a4b7d4c
HK		 404MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
405module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
406
8405cf39
SJ		 407/**
408 * DOC: exp_hw_support (int)
409 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
410 */
d38ceaf9
AD		 411MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
412module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
413
8405cf39
SJ		 414/**
415 * DOC: dc (int)
416 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
417 */
4562236b
HW		 418MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
419module_param_named(dc, amdgpu_dc, int, 0444);
420
8405cf39
SJ		 421/**
422 * DOC: sched_jobs (int)
423 * Override the max number of jobs supported in the sw queue. The default is 32.
424 */
b70f014d 425MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 426module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
427
8405cf39
SJ		 428/**
429 * DOC: sched_hw_submission (int)
430 * Override the max number of HW submissions. The default is 2.
431 */
4afcb303
JZ		 432MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
433module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
434
8405cf39 435/**
7427a7a0 436 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 437 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
438 * The default is the current set of stable power features.
439 */
5141e9d2 440MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 441module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 442
367039bf
TY		 443/**
444 * DOC: forcelongtraining (uint)
445 * Force long memory training in resume.
446 * The default is zero, indicates short training in resume.
447 */
448MODULE_PARM_DESC(forcelongtraining, "force memory long training");
449module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
450
8405cf39
SJ		 451/**
452 * DOC: pcie_gen_cap (uint)
453 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
454 * The default is 0 (automatic for each asic).
455 */
cd474ba0
AD		 456MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
457module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
458
8405cf39
SJ		 459/**
460 * DOC: pcie_lane_cap (uint)
461 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
462 * The default is 0 (automatic for each asic).
463 */
cd474ba0
AD		 464MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
465module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
466
8405cf39
SJ		 467/**
468 * DOC: cg_mask (uint)
469 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
470 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
471 */
395d1fb9
NH		 472MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
473module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
474
8405cf39
SJ		 475/**
476 * DOC: pg_mask (uint)
477 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
478 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
479 */
395d1fb9
NH		 480MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
481module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
482
8405cf39
SJ		 483/**
484 * DOC: sdma_phase_quantum (uint)
485 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
486 */
a667386c
FK		 487MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
488module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
489
8405cf39
SJ		 490/**
491 * DOC: disable_cu (charp)
492 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
493 */
6f8941a2
NH		 494MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
495module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
496
8405cf39
SJ		 497/**
498 * DOC: virtual_display (charp)
499 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
500 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
501 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
502 * device at 26:00.0. The default is NULL.
503 */
0f66356d
ED		 504MODULE_PARM_DESC(virtual_display,
505 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 506module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 507
8405cf39
SJ		 508/**
509 * DOC: job_hang_limit (int)
510 * Set how much time allow a job hang and not drop it. The default is 0.
511 */
65781c78
ML		 512MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
513module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
514
8405cf39
SJ		 515/**
516 * DOC: lbpw (int)
517 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
518 */
e8835e0e
HZ		 519MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
520module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 521
4a75aefe
AR		 522MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
523module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
524
8405cf39
SJ		 525/**
526 * DOC: gpu_recovery (int)
527 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
528 */
e6c6338f 529MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 530module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
531
8405cf39
SJ		 532/**
533 * DOC: emu_mode (int)
534 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
535 */
d869ae09 536MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 537module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
538
1218252f 539/**
2f3940e9 540 * DOC: ras_enable (int)
1218252f 541 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
542 */
2f3940e9 543MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 544module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
545
546/**
2f3940e9 547 * DOC: ras_mask (uint)
1218252f 548 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
549 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
550 */
2f3940e9 551MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 552module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
553
88f8575b
DL		 554/**
555 * DOC: timeout_fatal_disable (bool)
556 * Disable Watchdog timeout fatal error event
557 */
558MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
559module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
560
561/**
562 * DOC: timeout_period (uint)
563 * Modify the watchdog timeout max_cycles as (1 << period)
564 */
28a5d7a5 565MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 566module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
567
8405cf39
SJ		 568/**
569 * DOC: si_support (int)
570 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
571 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
572 * otherwise using amdgpu driver.
573 */
6dd13096 574#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56
MD		 575
576#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
6dd13096
FK		 577int amdgpu_si_support = 0;
578MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 579#else
580int amdgpu_si_support = 1;
581MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
582#endif
583
6dd13096
FK		 584module_param_named(si_support, amdgpu_si_support, int, 0444);
585#endif
586
8405cf39
SJ		 587/**
588 * DOC: cik_support (int)
589 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
590 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
591 * otherwise using amdgpu driver.
592 */
7df28986 593#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56
MD		 594
595#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
2b059658
MD		 596int amdgpu_cik_support = 0;
597MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 598#else
599int amdgpu_cik_support = 1;
600MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
601#endif
602
7df28986
FK		 603module_param_named(cik_support, amdgpu_cik_support, int, 0444);
604#endif
605
8405cf39
SJ		 606/**
607 * DOC: smu_memory_pool_size (uint)
608 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
609 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
610 */
7951e376
RZ		 611MODULE_PARM_DESC(smu_memory_pool_size,
612 "reserve gtt for smu debug usage, 0 = disable,"
613 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
614module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
615
51bcce46
HZ		 616/**
617 * DOC: async_gfx_ring (int)
618 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
619 */
620MODULE_PARM_DESC(async_gfx_ring,
5bfca069 621 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 622module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
623
40562787
AD		 624/**
625 * DOC: mcbp (int)
626 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled)
627 */
b239c017
JX		 628MODULE_PARM_DESC(mcbp,
629 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
630module_param_named(mcbp, amdgpu_mcbp, int, 0444);
631
40562787
AD		 632/**
633 * DOC: discovery (int)
634 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 635 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 636 */
a190d1c7
XY		 637MODULE_PARM_DESC(discovery,
638 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
639module_param_named(discovery, amdgpu_discovery, int, 0444);
640
40562787
AD		 641/**
642 * DOC: mes (int)
643 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
644 * (0 = disabled (default), 1 = enabled)
645 */
38487284
JX		 646MODULE_PARM_DESC(mes,
647 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
648module_param_named(mes, amdgpu_mes, int, 0444);
649
d5cc02d9
AD		 650/**
651 * DOC: noretry (int)
9705c85f
FK		 652 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
653 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 654 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
655 */
75ee6487 656MODULE_PARM_DESC(noretry,
d5cc02d9 657 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 658module_param_named(noretry, amdgpu_noretry, int, 0644);
659
4e66d7d2
YZ		 660/**
661 * DOC: force_asic_type (int)
662 * A non negative value used to specify the asic type for all supported GPUs.
663 */
664MODULE_PARM_DESC(force_asic_type,
665 "A non negative value used to specify the asic type for all supported GPUs");
666module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
667
668
669
2690262e 670#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 671/**
672 * DOC: sched_policy (int)
673 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
674 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
675 * assigns queues to HQDs.
676 */
2690262e 677int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 678module_param(sched_policy, int, 0444);
679MODULE_PARM_DESC(sched_policy,
680 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
681
682/**
683 * DOC: hws_max_conc_proc (int)
684 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
685 * number of VMIDs assigned to the HWS, which is also the default.
686 */
2690262e 687int hws_max_conc_proc = 8;
521fb7d0
AL		 688module_param(hws_max_conc_proc, int, 0444);
689MODULE_PARM_DESC(hws_max_conc_proc,
690 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
691
692/**
693 * DOC: cwsr_enable (int)
694 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
695 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
696 * disables it.
697 */
2690262e 698int cwsr_enable = 1;
521fb7d0
AL		 699module_param(cwsr_enable, int, 0444);
700MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
701
702/**
703 * DOC: max_num_of_queues_per_device (int)
704 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
705 * is 4096.
706 */
2690262e 707int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 708module_param(max_num_of_queues_per_device, int, 0444);
709MODULE_PARM_DESC(max_num_of_queues_per_device,
710 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
711
712/**
713 * DOC: send_sigterm (int)
714 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
715 * but just print errors on dmesg. Setting 1 enables sending sigterm.
716 */
2690262e 717int send_sigterm;
521fb7d0
AL		 718module_param(send_sigterm, int, 0444);
719MODULE_PARM_DESC(send_sigterm,
720 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
721
722/**
723 * DOC: debug_largebar (int)
724 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar
725 * system. This limits the VRAM size reported to ROCm applications to the visible
726 * size, usually 256MB.
727 * Default value is 0, diabled.
728 */
2690262e 729int debug_largebar;
521fb7d0
AL		 730module_param(debug_largebar, int, 0444);
731MODULE_PARM_DESC(debug_largebar,
732 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
733
734/**
735 * DOC: ignore_crat (int)
736 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT
737 * table to get information about AMD APUs. This option can serve as a workaround on
738 * systems with a broken CRAT table.
6127896f
HR		 739 *
740 * Default is auto (according to asic type, iommu_v2, and crat table, to decide
741 * whehter use CRAT)
521fb7d0 742 */
2690262e 743int ignore_crat;
521fb7d0
AL		 744module_param(ignore_crat, int, 0444);
745MODULE_PARM_DESC(ignore_crat,
6127896f 746 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
521fb7d0 747
521fb7d0
AL		 748/**
749 * DOC: halt_if_hws_hang (int)
750 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
751 * Setting 1 enables halt on hang.
752 */
2690262e 753int halt_if_hws_hang;
521fb7d0
AL		 754module_param(halt_if_hws_hang, int, 0644);
755MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 756
757/**
758 * DOC: hws_gws_support(bool)
29633d0e
JG		 759 * Assume that HWS supports GWS barriers regardless of what firmware version
760 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 761 */
762bool hws_gws_support;
763module_param(hws_gws_support, bool, 0444);
29633d0e 764MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 765
766/**
767 * DOC: queue_preemption_timeout_ms (int)
768 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
769 */
f51af435 770int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 771module_param(queue_preemption_timeout_ms, int, 0644);
772MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 773
774/**
775 * DOC: debug_evictions(bool)
776 * Enable extra debug messages to help determine the cause of evictions
777 */
778bool debug_evictions;
779module_param(debug_evictions, bool, 0644);
780MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 781
782/**
783 * DOC: no_system_mem_limit(bool)
784 * Disable system memory limit, to support multiple process shared memory
785 */
786bool no_system_mem_limit;
787module_param(no_system_mem_limit, bool, 0644);
788MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
789
6d909c5d
OZ		 790/**
791 * DOC: no_queue_eviction_on_vm_fault (int)
792 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
793 */
794int amdgpu_no_queue_eviction_on_vm_fault = 0;
795MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
796module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 797#endif
521fb7d0 798
7875a226
AD		 799/**
800 * DOC: dcfeaturemask (uint)
801 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
802 * The default is the current set of stable display features.
803 */
804MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
805module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
806
8a791dab
HW		 807/**
808 * DOC: dcdebugmask (uint)
809 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
810 */
811MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
812module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
813
ad4de27f
NK		 814/**
815 * DOC: abmlevel (uint)
816 * Override the default ABM (Adaptive Backlight Management) level used for DC
817 * enabled hardware. Requires DMCU to be supported and loaded.
818 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
819 * default. Values 1-4 control the maximum allowable brightness reduction via
820 * the ABM algorithm, with 1 being the least reduction and 4 being the most
821 * reduction.
822 *
823 * Defaults to 0, or disabled. Userspace can still override this level later
824 * after boot.
825 */
87fb7833 826uint amdgpu_dm_abm_level;
ad4de27f
NK		 827MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
828module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
829
7a46f05e
TI		 830int amdgpu_backlight = -1;
831MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
832module_param_named(backlight, amdgpu_backlight, bint, 0444);
833
d7ccb38d
HR		 834/**
835 * DOC: tmz (int)
836 * Trusted Memory Zone (TMZ) is a method to protect data being written
837 * to or read from memory.
838 *
839 * The default value: 0 (off). TODO: change to auto till it is completed.
840 */
58aa7790 841MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 842module_param_named(tmz, amdgpu_tmz, int, 0444);
843
273da6ff
WS		 844/**
845 * DOC: reset_method (int)
af484df8 846 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci)
273da6ff 847 */
af484df8 848MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
273da6ff
WS		 849module_param_named(reset_method, amdgpu_reset_method, int, 0444);
850
acc0204c 851/**
e4e6a589
LT		 852 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
853 * threshold value of faulty pages detected by RAS ECC, which may
854 * result in the GPU entering bad status when the number of total
855 * faulty pages by ECC exceeds the threshold value.
acc0204c 856 */
68daadf3 857MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)");
acc0204c
GC		 858module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
859
a300de40
ML		 860MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
861module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
862
8738a82b
LL		 863/**
864 * DOC: smu_pptable_id (int)
865 * Used to override pptable id. id = 0 use VBIOS pptable.
866 * id > 0 use the soft pptable with specicfied id.
867 */
868MODULE_PARM_DESC(smu_pptable_id,
869 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
870module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
871
bdbeb0dd
AD		 872/* These devices are not supported by amdgpu.
873 * They are supported by the mach64, r128, radeon drivers
874 */
875static const u16 amdgpu_unsupported_pciidlist[] = {
876 /* mach64 */
877 0x4354,
878 0x4358,
879 0x4554,
880 0x4742,
881 0x4744,
882 0x4749,
883 0x474C,
884 0x474D,
885 0x474E,
886 0x474F,
887 0x4750,
888 0x4751,
889 0x4752,
890 0x4753,
891 0x4754,
892 0x4755,
893 0x4756,
894 0x4757,
895 0x4758,
896 0x4759,
897 0x475A,
898 0x4C42,
899 0x4C44,
900 0x4C47,
901 0x4C49,
902 0x4C4D,
903 0x4C4E,
904 0x4C50,
905 0x4C51,
906 0x4C52,
907 0x4C53,
908 0x5654,
909 0x5655,
910 0x5656,
911 /* r128 */
912 0x4c45,
913 0x4c46,
914 0x4d46,
915 0x4d4c,
916 0x5041,
917 0x5042,
918 0x5043,
919 0x5044,
920 0x5045,
921 0x5046,
922 0x5047,
923 0x5048,
924 0x5049,
925 0x504A,
926 0x504B,
927 0x504C,
928 0x504D,
929 0x504E,
930 0x504F,
931 0x5050,
932 0x5051,
933 0x5052,
934 0x5053,
935 0x5054,
936 0x5055,
937 0x5056,
938 0x5057,
939 0x5058,
940 0x5245,
941 0x5246,
942 0x5247,
943 0x524b,
944 0x524c,
945 0x534d,
946 0x5446,
947 0x544C,
948 0x5452,
949 /* radeon */
950 0x3150,
951 0x3151,
952 0x3152,
953 0x3154,
954 0x3155,
955 0x3E50,
956 0x3E54,
957 0x4136,
958 0x4137,
959 0x4144,
960 0x4145,
961 0x4146,
962 0x4147,
963 0x4148,
964 0x4149,
965 0x414A,
966 0x414B,
967 0x4150,
968 0x4151,
969 0x4152,
970 0x4153,
971 0x4154,
972 0x4155,
973 0x4156,
974 0x4237,
975 0x4242,
976 0x4336,
977 0x4337,
978 0x4437,
979 0x4966,
980 0x4967,
981 0x4A48,
982 0x4A49,
983 0x4A4A,
984 0x4A4B,
985 0x4A4C,
986 0x4A4D,
987 0x4A4E,
988 0x4A4F,
989 0x4A50,
990 0x4A54,
991 0x4B48,
992 0x4B49,
993 0x4B4A,
994 0x4B4B,
995 0x4B4C,
996 0x4C57,
997 0x4C58,
998 0x4C59,
999 0x4C5A,
1000 0x4C64,
1001 0x4C66,
1002 0x4C67,
1003 0x4E44,
1004 0x4E45,
1005 0x4E46,
1006 0x4E47,
1007 0x4E48,
1008 0x4E49,
1009 0x4E4A,
1010 0x4E4B,
1011 0x4E50,
1012 0x4E51,
1013 0x4E52,
1014 0x4E53,
1015 0x4E54,
1016 0x4E56,
1017 0x5144,
1018 0x5145,
1019 0x5146,
1020 0x5147,
1021 0x5148,
1022 0x514C,
1023 0x514D,
1024 0x5157,
1025 0x5158,
1026 0x5159,
1027 0x515A,
1028 0x515E,
1029 0x5460,
1030 0x5462,
1031 0x5464,
1032 0x5548,
1033 0x5549,
1034 0x554A,
1035 0x554B,
1036 0x554C,
1037 0x554D,
1038 0x554E,
1039 0x554F,
1040 0x5550,
1041 0x5551,
1042 0x5552,
1043 0x5554,
1044 0x564A,
1045 0x564B,
1046 0x564F,
1047 0x5652,
1048 0x5653,
1049 0x5657,
1050 0x5834,
1051 0x5835,
1052 0x5954,
1053 0x5955,
1054 0x5974,
1055 0x5975,
1056 0x5960,
1057 0x5961,
1058 0x5962,
1059 0x5964,
1060 0x5965,
1061 0x5969,
1062 0x5a41,
1063 0x5a42,
1064 0x5a61,
1065 0x5a62,
1066 0x5b60,
1067 0x5b62,
1068 0x5b63,
1069 0x5b64,
1070 0x5b65,
1071 0x5c61,
1072 0x5c63,
1073 0x5d48,
1074 0x5d49,
1075 0x5d4a,
1076 0x5d4c,
1077 0x5d4d,
1078 0x5d4e,
1079 0x5d4f,
1080 0x5d50,
1081 0x5d52,
1082 0x5d57,
1083 0x5e48,
1084 0x5e4a,
1085 0x5e4b,
1086 0x5e4c,
1087 0x5e4d,
1088 0x5e4f,
1089 0x6700,
1090 0x6701,
1091 0x6702,
1092 0x6703,
1093 0x6704,
1094 0x6705,
1095 0x6706,
1096 0x6707,
1097 0x6708,
1098 0x6709,
1099 0x6718,
1100 0x6719,
1101 0x671c,
1102 0x671d,
1103 0x671f,
1104 0x6720,
1105 0x6721,
1106 0x6722,
1107 0x6723,
1108 0x6724,
1109 0x6725,
1110 0x6726,
1111 0x6727,
1112 0x6728,
1113 0x6729,
1114 0x6738,
1115 0x6739,
1116 0x673e,
1117 0x6740,
1118 0x6741,
1119 0x6742,
1120 0x6743,
1121 0x6744,
1122 0x6745,
1123 0x6746,
1124 0x6747,
1125 0x6748,
1126 0x6749,
1127 0x674A,
1128 0x6750,
1129 0x6751,
1130 0x6758,
1131 0x6759,
1132 0x675B,
1133 0x675D,
1134 0x675F,
1135 0x6760,
1136 0x6761,
1137 0x6762,
1138 0x6763,
1139 0x6764,
1140 0x6765,
1141 0x6766,
1142 0x6767,
1143 0x6768,
1144 0x6770,
1145 0x6771,
1146 0x6772,
1147 0x6778,
1148 0x6779,
1149 0x677B,
1150 0x6840,
1151 0x6841,
1152 0x6842,
1153 0x6843,
1154 0x6849,
1155 0x684C,
1156 0x6850,
1157 0x6858,
1158 0x6859,
1159 0x6880,
1160 0x6888,
1161 0x6889,
1162 0x688A,
1163 0x688C,
1164 0x688D,
1165 0x6898,
1166 0x6899,
1167 0x689b,
1168 0x689c,
1169 0x689d,
1170 0x689e,
1171 0x68a0,
1172 0x68a1,
1173 0x68a8,
1174 0x68a9,
1175 0x68b0,
1176 0x68b8,
1177 0x68b9,
1178 0x68ba,
1179 0x68be,
1180 0x68bf,
1181 0x68c0,
1182 0x68c1,
1183 0x68c7,
1184 0x68c8,
1185 0x68c9,
1186 0x68d8,
1187 0x68d9,
1188 0x68da,
1189 0x68de,
1190 0x68e0,
1191 0x68e1,
1192 0x68e4,
1193 0x68e5,
1194 0x68e8,
1195 0x68e9,
1196 0x68f1,
1197 0x68f2,
1198 0x68f8,
1199 0x68f9,
1200 0x68fa,
1201 0x68fe,
1202 0x7100,
1203 0x7101,
1204 0x7102,
1205 0x7103,
1206 0x7104,
1207 0x7105,
1208 0x7106,
1209 0x7108,
1210 0x7109,
1211 0x710A,
1212 0x710B,
1213 0x710C,
1214 0x710E,
1215 0x710F,
1216 0x7140,
1217 0x7141,
1218 0x7142,
1219 0x7143,
1220 0x7144,
1221 0x7145,
1222 0x7146,
1223 0x7147,
1224 0x7149,
1225 0x714A,
1226 0x714B,
1227 0x714C,
1228 0x714D,
1229 0x714E,
1230 0x714F,
1231 0x7151,
1232 0x7152,
1233 0x7153,
1234 0x715E,
1235 0x715F,
1236 0x7180,
1237 0x7181,
1238 0x7183,
1239 0x7186,
1240 0x7187,
1241 0x7188,
1242 0x718A,
1243 0x718B,
1244 0x718C,
1245 0x718D,
1246 0x718F,
1247 0x7193,
1248 0x7196,
1249 0x719B,
1250 0x719F,
1251 0x71C0,
1252 0x71C1,
1253 0x71C2,
1254 0x71C3,
1255 0x71C4,
1256 0x71C5,
1257 0x71C6,
1258 0x71C7,
1259 0x71CD,
1260 0x71CE,
1261 0x71D2,
1262 0x71D4,
1263 0x71D5,
1264 0x71D6,
1265 0x71DA,
1266 0x71DE,
1267 0x7200,
1268 0x7210,
1269 0x7211,
1270 0x7240,
1271 0x7243,
1272 0x7244,
1273 0x7245,
1274 0x7246,
1275 0x7247,
1276 0x7248,
1277 0x7249,
1278 0x724A,
1279 0x724B,
1280 0x724C,
1281 0x724D,
1282 0x724E,
1283 0x724F,
1284 0x7280,
1285 0x7281,
1286 0x7283,
1287 0x7284,
1288 0x7287,
1289 0x7288,
1290 0x7289,
1291 0x728B,
1292 0x728C,
1293 0x7290,
1294 0x7291,
1295 0x7293,
1296 0x7297,
1297 0x7834,
1298 0x7835,
1299 0x791e,
1300 0x791f,
1301 0x793f,
1302 0x7941,
1303 0x7942,
1304 0x796c,
1305 0x796d,
1306 0x796e,
1307 0x796f,
1308 0x9400,
1309 0x9401,
1310 0x9402,
1311 0x9403,
1312 0x9405,
1313 0x940A,
1314 0x940B,
1315 0x940F,
1316 0x94A0,
1317 0x94A1,
1318 0x94A3,
1319 0x94B1,
1320 0x94B3,
1321 0x94B4,
1322 0x94B5,
1323 0x94B9,
1324 0x9440,
1325 0x9441,
1326 0x9442,
1327 0x9443,
1328 0x9444,
1329 0x9446,
1330 0x944A,
1331 0x944B,
1332 0x944C,
1333 0x944E,
1334 0x9450,
1335 0x9452,
1336 0x9456,
1337 0x945A,
1338 0x945B,
1339 0x945E,
1340 0x9460,
1341 0x9462,
1342 0x946A,
1343 0x946B,
1344 0x947A,
1345 0x947B,
1346 0x9480,
1347 0x9487,
1348 0x9488,
1349 0x9489,
1350 0x948A,
1351 0x948F,
1352 0x9490,
1353 0x9491,
1354 0x9495,
1355 0x9498,
1356 0x949C,
1357 0x949E,
1358 0x949F,
1359 0x94C0,
1360 0x94C1,
1361 0x94C3,
1362 0x94C4,
1363 0x94C5,
1364 0x94C6,
1365 0x94C7,
1366 0x94C8,
1367 0x94C9,
1368 0x94CB,
1369 0x94CC,
1370 0x94CD,
1371 0x9500,
1372 0x9501,
1373 0x9504,
1374 0x9505,
1375 0x9506,
1376 0x9507,
1377 0x9508,
1378 0x9509,
1379 0x950F,
1380 0x9511,
1381 0x9515,
1382 0x9517,
1383 0x9519,
1384 0x9540,
1385 0x9541,
1386 0x9542,
1387 0x954E,
1388 0x954F,
1389 0x9552,
1390 0x9553,
1391 0x9555,
1392 0x9557,
1393 0x955f,
1394 0x9580,
1395 0x9581,
1396 0x9583,
1397 0x9586,
1398 0x9587,
1399 0x9588,
1400 0x9589,
1401 0x958A,
1402 0x958B,
1403 0x958C,
1404 0x958D,
1405 0x958E,
1406 0x958F,
1407 0x9590,
1408 0x9591,
1409 0x9593,
1410 0x9595,
1411 0x9596,
1412 0x9597,
1413 0x9598,
1414 0x9599,
1415 0x959B,
1416 0x95C0,
1417 0x95C2,
1418 0x95C4,
1419 0x95C5,
1420 0x95C6,
1421 0x95C7,
1422 0x95C9,
1423 0x95CC,
1424 0x95CD,
1425 0x95CE,
1426 0x95CF,
1427 0x9610,
1428 0x9611,
1429 0x9612,
1430 0x9613,
1431 0x9614,
1432 0x9615,
1433 0x9616,
1434 0x9640,
1435 0x9641,
1436 0x9642,
1437 0x9643,
1438 0x9644,
1439 0x9645,
1440 0x9647,
1441 0x9648,
1442 0x9649,
1443 0x964a,
1444 0x964b,
1445 0x964c,
1446 0x964e,
1447 0x964f,
1448 0x9710,
1449 0x9711,
1450 0x9712,
1451 0x9713,
1452 0x9714,
1453 0x9715,
1454 0x9802,
1455 0x9803,
1456 0x9804,
1457 0x9805,
1458 0x9806,
1459 0x9807,
1460 0x9808,
1461 0x9809,
1462 0x980A,
1463 0x9900,
1464 0x9901,
1465 0x9903,
1466 0x9904,
1467 0x9905,
1468 0x9906,
1469 0x9907,
1470 0x9908,
1471 0x9909,
1472 0x990A,
1473 0x990B,
1474 0x990C,
1475 0x990D,
1476 0x990E,
1477 0x990F,
1478 0x9910,
1479 0x9913,
1480 0x9917,
1481 0x9918,
1482 0x9919,
1483 0x9990,
1484 0x9991,
1485 0x9992,
1486 0x9993,
1487 0x9994,
1488 0x9995,
1489 0x9996,
1490 0x9997,
1491 0x9998,
1492 0x9999,
1493 0x999A,
1494 0x999B,
1495 0x999C,
1496 0x999D,
1497 0x99A0,
1498 0x99A2,
1499 0x99A4,
1500};
1501
f498d9ed 1502static const struct pci_device_id pciidlist[] = {
78fbb685
KW		 1503#ifdef CONFIG_DRM_AMDGPU_SI
1504 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1505 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1506 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1507 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1508 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1509 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1510 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1511 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1512 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1513 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1514 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1515 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1516 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1517 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1518 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1519 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1520 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1521 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1522 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1523 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1524 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1525 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1526 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1527 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1528 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1529 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1530 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1531 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1532 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1533 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1534 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1535 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1536 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1537 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1538 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1539 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1540 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1541 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1542 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1543 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1544 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1545 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1546 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1547 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1548 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1549 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1550 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1551 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1552 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1553 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1554 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1555 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1556 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1557 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1558 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1559 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1560 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1561 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1562 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1563 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1564 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1565 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1566 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1567 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1568 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1569 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1570 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1571 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1572 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1573 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1574 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1575 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1576#endif
89330c39
AD		 1577#ifdef CONFIG_DRM_AMDGPU_CIK
1578 /* Kaveri */
2f7d10b3
JZ		 1579 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1580 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1581 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1582 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1583 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1584 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1585 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1586 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1587 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1588 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1589 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1590 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1591 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1592 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1593 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1594 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1595 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1596 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1597 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1598 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1599 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1600 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1601 /* Bonaire */
2f7d10b3
JZ		 1602 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1603 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1604 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1605 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1606 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1607 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1608 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1609 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1610 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1611 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1612 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1613 /* Hawaii */
1614 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1615 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1616 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1617 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1618 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1619 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1620 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1621 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1622 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1623 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1624 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1625 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1626 /* Kabini */
2f7d10b3
JZ		 1627 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1628 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1629 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1630 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1631 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1632 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1633 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1634 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1635 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1636 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1637 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1638 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1639 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1640 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1641 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1642 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1643 /* mullins */
2f7d10b3
JZ		 1644 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1645 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1646 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1647 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1648 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1649 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1650 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1651 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1652 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1653 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1654 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1655 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1656 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1657 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1658 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1659 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1660#endif
1256a8b8 1661 /* topaz */
dba280b2
AD		 1662 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1663 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1664 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1665 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1666 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1667 /* tonga */
1668 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1669 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1670 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1671 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1672 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1673 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1674 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1675 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1676 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1677 /* fiji */
1678 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1679 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1680 /* carrizo */
2f7d10b3
JZ		 1681 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1682 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1683 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1684 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1685 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1686 /* stoney */
1687 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1688 /* Polaris11 */
1689 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1690 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1691 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1692 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1693 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1694 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1695 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1696 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1697 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1698 /* Polaris10 */
1699 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1700 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1701 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1702 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1703 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1704 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1705 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1706 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1707 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1708 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1709 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1710 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1711 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1712 /* Polaris12 */
1713 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1714 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1715 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1716 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1717 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1718 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1719 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1720 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1721 /* VEGAM */
1722 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1723 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1724 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1725 /* Vega 10 */
dfbf0c14
AD		 1726 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1727 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1728 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1729 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1730 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1731 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1732 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1733 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1734 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1735 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1736 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1737 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1738 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1739 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1740 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1741 /* Vega 12 */
1742 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1743 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1744 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1745 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1746 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1747 /* Vega 20 */
6dddaeef
AD		 1748 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1749 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1750 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1751 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1752 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1753 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1754 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1755 /* Raven */
acc34503 1756 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 1757 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 1758 /* Arcturus */
12c5365e
AD		 1759 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1760 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1761 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1762 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 1763 /* Navi10 */
1764 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1765 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1766 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1767 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1768 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 1769 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 1770 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 1771 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 1772 /* Navi14 */
b62d9554
AD		 1773 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1774 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1775 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1776 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 1777
61bdb39c 1778 /* Renoir */
775da830 1779 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 1780 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 1781 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 1782 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 1783
10e85054 1784 /* Navi12 */
d34c7b7b
AD		 1785 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1786 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 1787
61278d14
LG		 1788 /* Sienna_Cichlid */
1789 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 1790 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 1791 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1792 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1793 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1794 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1795 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1796 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 1797 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1798 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1799 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 1800 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 1801 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 1802
894052d6
HR		 1803 /* Van Gogh */
1804 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1805
27f5355f
AL		 1806 /* Yellow Carp */
1807 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1808 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1809
2c1eaddd
TZ		 1810 /* Navy_Flounder */
1811 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1812 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1813 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 1814 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1815 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1816 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1817 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1818 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 1819 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1820
e7de4aee
TZ		 1821 /* DIMGREY_CAVEFISH */
1822 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1823 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1824 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 1825 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 1826 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1827 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1828 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1829 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1830 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1831 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1832 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 1833 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1834
4c2e5f51 1835 /* Aldebaran */
b1625687
FK		 1836 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1837 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1838 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
838eb73c 1839 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
4c2e5f51 1840
a8f70696
TZ		 1841 /* CYAN_SKILLFISH */
1842 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1843
a2e9b166
CG		 1844 /* BEIGE_GOBY */
1845 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1846 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1847 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1848 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1849 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1850
eb4fd29a
AD		 1851 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1852 .class = PCI_CLASS_DISPLAY_VGA << 8,
1853 .class_mask = 0xffffff,
d0761fd2 1854 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 1855
1856 { PCI_DEVICE(0x1002, PCI_ANY_ID),
1857 .class = PCI_CLASS_DISPLAY_OTHER << 8,
1858 .class_mask = 0xffffff,
d0761fd2 1859 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 1860
d38ceaf9
AD		 1861 {0, 0, 0}
1862};
1863
1864MODULE_DEVICE_TABLE(pci, pciidlist);
1865
5088d657 1866static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 1867
d38ceaf9
AD		 1868static int amdgpu_pci_probe(struct pci_dev *pdev,
1869 const struct pci_device_id *ent)
1870{
8aba21b7 1871 struct drm_device *ddev;
c6385e50 1872 struct amdgpu_device *adev;
d38ceaf9 1873 unsigned long flags = ent->driver_data;
bdbeb0dd 1874 int ret, retry = 0, i;
3fa203af
AD		 1875 bool supports_atomic = false;
1876
bdbeb0dd
AD		 1877 /* skip devices which are owned by radeon */
1878 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
1879 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
1880 return -ENODEV;
1881 }
1882
eb4fd29a
AD		 1883 if (flags == 0) {
1884 DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n");
1885 return -ENODEV;
1886 }
1887
84ec374b 1888 if (amdgpu_virtual_display ||
3fa203af
AD		 1889 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1890 supports_atomic = true;
d38ceaf9 1891
2f7d10b3 1892 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 1893 DRM_INFO("This hardware requires experimental hardware support.\n"
1894 "See modparam exp_hw_support\n");
1895 return -ENODEV;
1896 }
1897
ea68573d
AD		 1898 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
1899 * however, SME requires an indirect IOMMU mapping because the encryption
1900 * bit is beyond the DMA mask of the chip.
1901 */
e9d1d2bb
TL		 1902 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
1903 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 1904 dev_info(&pdev->dev,
1905 "SME is not compatible with RAVEN\n");
1906 return -ENOTSUPP;
1907 }
1908
984d7a92
HG		 1909#ifdef CONFIG_DRM_AMDGPU_SI
1910 if (!amdgpu_si_support) {
1911 switch (flags & AMD_ASIC_MASK) {
1912 case CHIP_TAHITI:
1913 case CHIP_PITCAIRN:
1914 case CHIP_VERDE:
1915 case CHIP_OLAND:
1916 case CHIP_HAINAN:
1917 dev_info(&pdev->dev,
1918 "SI support provided by radeon.\n");
1919 dev_info(&pdev->dev,
1920 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1921 );
1922 return -ENODEV;
1923 }
1924 }
1925#endif
1926#ifdef CONFIG_DRM_AMDGPU_CIK
1927 if (!amdgpu_cik_support) {
1928 switch (flags & AMD_ASIC_MASK) {
1929 case CHIP_KAVERI:
1930 case CHIP_BONAIRE:
1931 case CHIP_HAWAII:
1932 case CHIP_KABINI:
1933 case CHIP_MULLINS:
1934 dev_info(&pdev->dev,
1935 "CIK support provided by radeon.\n");
1936 dev_info(&pdev->dev,
1937 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1938 );
1939 return -ENODEV;
1940 }
1941 }
1942#endif
1943
d38ceaf9 1944 /* Get rid of things like offb */
97c9bfe3 1945 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
d38ceaf9
AD		 1946 if (ret)
1947 return ret;
1948
5088d657 1949 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 1950 if (IS_ERR(adev))
1951 return PTR_ERR(adev);
8aba21b7
LT		 1952
1953 adev->dev = &pdev->dev;
1954 adev->pdev = pdev;
1955 ddev = adev_to_drm(adev);
b58c1131 1956
351c4dbe 1957 if (!supports_atomic)
8aba21b7 1958 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 1959
b58c1131
AD		 1960 ret = pci_enable_device(pdev);
1961 if (ret)
df2ce459 1962 return ret;
b58c1131 1963
8aba21b7 1964 pci_set_drvdata(pdev, ddev);
b58c1131 1965
8aba21b7 1966 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
7504d3bb
LC		 1967 if (ret)
1968 goto err_pci;
c6385e50 1969
1daee8b4 1970retry_init:
8aba21b7 1971 ret = drm_dev_register(ddev, ent->driver_data);
1daee8b4
PD		 1972 if (ret == -EAGAIN && ++retry <= 3) {
1973 DRM_INFO("retry init %d\n", retry);
1974 /* Don't request EX mode too frequently which is attacking */
1975 msleep(5000);
1976 goto retry_init;
8aba21b7 1977 } else if (ret) {
b58c1131 1978 goto err_pci;
8aba21b7 1979 }
b58c1131 1980
087451f3
EQ		 1981 /*
1982 * 1. don't init fbdev on hw without DCE
1983 * 2. don't init fbdev if there are no connectors
1984 */
1985 if (adev->mode_info.mode_config_initialized &&
1986 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
1987 /* select 8 bpp console on low vram cards */
1988 if (adev->gmc.real_vram_size <= (32*1024*1024))
1989 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
1990 else
1991 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
1992 }
1993
c6385e50
AD		 1994 ret = amdgpu_debugfs_init(adev);
1995 if (ret)
1996 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
1997
b58c1131
AD		 1998 return 0;
1999
2000err_pci:
2001 pci_disable_device(pdev);
b58c1131 2002 return ret;
d38ceaf9
AD		 2003}
2004
2005static void
2006amdgpu_pci_remove(struct pci_dev *pdev)
2007{
2008 struct drm_device *dev = pci_get_drvdata(pdev);
2009
88b35d83 2010 drm_dev_unplug(dev);
c6385e50 2011 amdgpu_driver_unload_kms(dev);
72c8c97b 2012
98c6e6a7
AG		 2013 /*
2014 * Flush any in flight DMA operations from device.
2015 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2016 * StatusTransactions Pending bit.
2017 */
fd4495e5 2018 pci_disable_device(pdev);
98c6e6a7 2019 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2020}
2021
61e11306
AD		 2022static void
2023amdgpu_pci_shutdown(struct pci_dev *pdev)
2024{
faefba95 2025 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2026 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2027
7c6e68c7
AG		 2028 if (amdgpu_ras_intr_triggered())
2029 return;
2030
61e11306 2031 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2032 * torn down properly on reboot/shutdown.
2033 * unfortunately we can't detect certain
2034 * hypervisors so just do this all the time.
61e11306 2035 */
05cac1ae
ND		 2036 if (!amdgpu_passthrough(adev))
2037 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2038 amdgpu_device_ip_suspend(adev);
a3a09142 2039 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2040}
2041
e3c1b071 2042/**
2043 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2044 *
2045 * @work: work_struct.
2046 */
2047static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2048{
2049 struct list_head device_list;
2050 struct amdgpu_device *adev;
2051 int i, r;
04442bf7
LL		 2052 struct amdgpu_reset_context reset_context;
2053
2054 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2055
2056 mutex_lock(&mgpu_info.mutex);
2057 if (mgpu_info.pending_reset == true) {
2058 mutex_unlock(&mgpu_info.mutex);
2059 return;
2060 }
2061 mgpu_info.pending_reset = true;
2062 mutex_unlock(&mgpu_info.mutex);
2063
04442bf7
LL		 2064 /* Use a common context, just need to make sure full reset is done */
2065 reset_context.method = AMD_RESET_METHOD_NONE;
2066 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2067
e3c1b071 2068 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2069 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2070 reset_context.reset_req_dev = adev;
2071 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2072 if (r) {
2073 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2074 r, adev_to_drm(adev)->unique);
2075 }
2076 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2077 r = -EALREADY;
2078 }
2079 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2080 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2081 flush_work(&adev->xgmi_reset_work);
050743da 2082 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2083 }
2084
2085 /* reset function will rebuild the xgmi hive info , clear it now */
2086 for (i = 0; i < mgpu_info.num_dgpu; i++)
2087 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2088
2089 INIT_LIST_HEAD(&device_list);
2090
2091 for (i = 0; i < mgpu_info.num_dgpu; i++)
2092 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2093
2094 /* unregister the GPU first, reset function will add them back */
2095 list_for_each_entry(adev, &device_list, reset_list)
2096 amdgpu_unregister_gpu_instance(adev);
2097
04442bf7
LL		 2098 /* Use a common context, just need to make sure full reset is done */
2099 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2100 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2101
e3c1b071 2102 if (r) {
2103 DRM_ERROR("reinit gpus failure");
2104 return;
2105 }
2106 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2107 adev = mgpu_info.gpu_ins[i].adev;
2108 if (!adev->kfd.init_complete)
2109 amdgpu_amdkfd_device_init(adev);
2110 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2111 }
2112 return;
2113}
2114
e25443d2
AD		 2115static int amdgpu_pmops_prepare(struct device *dev)
2116{
2117 struct drm_device *drm_dev = dev_get_drvdata(dev);
2118
2119 /* Return a positive number here so
2120 * DPM_FLAG_SMART_SUSPEND works properly
2121 */
b98c6299 2122 if (amdgpu_device_supports_boco(drm_dev))
e25443d2
AD		 2123 return pm_runtime_suspended(dev) &&
2124 pm_suspend_via_firmware();
2125
2126 return 0;
2127}
2128
2129static void amdgpu_pmops_complete(struct device *dev)
2130{
2131 /* nothing to do */
2132}
2133
d38ceaf9
AD		 2134static int amdgpu_pmops_suspend(struct device *dev)
2135{
911d8b30 2136 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2137 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2138 int r;
74b0b157 2139
d0260f62 2140 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2141 adev->in_s0ix = true;
eac4c54b
ML		 2142 else
2143 adev->in_s3 = true;
62498733 2144 r = amdgpu_device_suspend(drm_dev, true);
6dc8265f
AD		 2145 if (r)
2146 return r;
2147 if (!adev->in_s0ix)
2148 r = amdgpu_asic_reset(adev);
62498733 2149 return r;
d38ceaf9
AD		 2150}
2151
2152static int amdgpu_pmops_resume(struct device *dev)
2153{
911d8b30 2154 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2155 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2156 int r;
85e154c2 2157
ebe86a57
AG		 2158 /* Avoids registers access if device is physically gone */
2159 if (!pci_device_is_present(adev->pdev))
2160 adev->no_hw_access = true;
2161
62498733 2162 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2163 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2164 adev->in_s0ix = false;
eac4c54b
ML		 2165 else
2166 adev->in_s3 = false;
62498733 2167 return r;
d38ceaf9
AD		 2168}
2169
2170static int amdgpu_pmops_freeze(struct device *dev)
2171{
911d8b30 2172 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2173 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2174 int r;
74b0b157 2175
62498733 2176 adev->in_s4 = true;
de185019 2177 r = amdgpu_device_suspend(drm_dev, true);
62498733 2178 adev->in_s4 = false;
897483d8
AD		 2179 if (r)
2180 return r;
2181 return amdgpu_asic_reset(adev);
d38ceaf9
AD		 2182}
2183
2184static int amdgpu_pmops_thaw(struct device *dev)
2185{
911d8b30 2186 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2187
de185019 2188 return amdgpu_device_resume(drm_dev, true);
74b0b157 2189}
2190
2191static int amdgpu_pmops_poweroff(struct device *dev)
2192{
911d8b30 2193 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2194
62498733 2195 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2196}
2197
2198static int amdgpu_pmops_restore(struct device *dev)
2199{
911d8b30 2200 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2201
de185019 2202 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2203}
2204
2205static int amdgpu_pmops_runtime_suspend(struct device *dev)
2206{
2207 struct pci_dev *pdev = to_pci_dev(dev);
2208 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2209 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2210 int ret, i;
d38ceaf9 2211
6ae6c7d4 2212 if (!adev->runpm) {
d38ceaf9
AD		 2213 pm_runtime_forbid(dev);
2214 return -EBUSY;
2215 }
2216
719423f6
AD		 2217 /* wait for all rings to drain before suspending */
2218 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2219 struct amdgpu_ring *ring = adev->rings[i];
2220 if (ring && ring->sched.ready) {
2221 ret = amdgpu_fence_wait_empty(ring);
2222 if (ret)
2223 return -EBUSY;
2224 }
2225 }
2226
f0f7ddfc 2227 adev->in_runpm = true;
b98c6299 2228 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2229 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2230
4a700546
EQ		 2231 /*
2232 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2233 * proper cleanups and put itself into a state ready for PNP. That
2234 * can address some random resuming failure observed on BOCO capable
2235 * platforms.
2236 * TODO: this may be also needed for PX capable platform.
2237 */
2238 if (amdgpu_device_supports_boco(drm_dev))
2239 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2240
de185019 2241 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2242 if (ret) {
2243 adev->in_runpm = false;
4a700546
EQ		 2244 if (amdgpu_device_supports_boco(drm_dev))
2245 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2246 return ret;
cef8b03b 2247 }
70bedd68 2248
4a700546
EQ		 2249 if (amdgpu_device_supports_boco(drm_dev))
2250 adev->mp1_state = PP_MP1_STATE_NONE;
2251
b98c6299 2252 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2253 /* Only need to handle PCI state in the driver for ATPX
2254 * PCI core handles it for _PR3.
2255 */
b98c6299
AD		 2256 amdgpu_device_cache_pci_state(pdev);
2257 pci_disable_device(pdev);
2258 pci_ignore_hotplug(pdev);
2259 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2260 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2261 } else if (amdgpu_device_supports_boco(drm_dev)) {
2262 /* nothing to do */
19134317
AD		 2263 } else if (amdgpu_device_supports_baco(drm_dev)) {
2264 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2265 }
d38ceaf9
AD		 2266
2267 return 0;
2268}
2269
2270static int amdgpu_pmops_runtime_resume(struct device *dev)
2271{
2272 struct pci_dev *pdev = to_pci_dev(dev);
2273 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2274 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2275 int ret;
2276
6ae6c7d4 2277 if (!adev->runpm)
d38ceaf9
AD		 2278 return -EINVAL;
2279
e1543d83
AG		 2280 /* Avoids registers access if device is physically gone */
2281 if (!pci_device_is_present(adev->pdev))
2282 adev->no_hw_access = true;
2283
b98c6299 2284 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2285 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2286
562b49fc
AD		 2287 /* Only need to handle PCI state in the driver for ATPX
2288 * PCI core handles it for _PR3.
2289 */
b98c6299
AD		 2290 pci_set_power_state(pdev, PCI_D0);
2291 amdgpu_device_load_pci_state(pdev);
2292 ret = pci_enable_device(pdev);
2293 if (ret)
2294 return ret;
637bb036 2295 pci_set_master(pdev);
fd496ca8
AD		 2296 } else if (amdgpu_device_supports_boco(drm_dev)) {
2297 /* Only need to handle PCI state in the driver for ATPX
2298 * PCI core handles it for _PR3.
2299 */
2300 pci_set_master(pdev);
19134317
AD		 2301 } else if (amdgpu_device_supports_baco(drm_dev)) {
2302 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2303 }
de185019 2304 ret = amdgpu_device_resume(drm_dev, false);
b45aeb2d
PKR		 2305 if (ret)
2306 return ret;
2307
b98c6299 2308 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2309 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2310 adev->in_runpm = false;
d38ceaf9
AD		 2311 return 0;
2312}
2313
2314static int amdgpu_pmops_runtime_idle(struct device *dev)
2315{
911d8b30 2316 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2317 struct amdgpu_device *adev = drm_to_adev(drm_dev);
97f6a21b
AG		 2318 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
2319 int ret = 1;
d38ceaf9 2320
6ae6c7d4 2321 if (!adev->runpm) {
d38ceaf9
AD		 2322 pm_runtime_forbid(dev);
2323 return -EBUSY;
2324 }
2325
97f6a21b
AG		 2326 if (amdgpu_device_has_dc_support(adev)) {
2327 struct drm_crtc *crtc;
2328
97f6a21b 2329 drm_for_each_crtc(crtc, drm_dev) {
fb637265
FDF		 2330 drm_modeset_lock(&crtc->mutex, NULL);
2331 if (crtc->state->active)
97f6a21b 2332 ret = -EBUSY;
fb637265
FDF		 2333 drm_modeset_unlock(&crtc->mutex);
2334 if (ret < 0)
97f6a21b 2335 break;
d38ceaf9 2336 }
97f6a21b 2337
97f6a21b
AG		 2338 } else {
2339 struct drm_connector *list_connector;
2340 struct drm_connector_list_iter iter;
2341
2342 mutex_lock(&drm_dev->mode_config.mutex);
2343 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2344
2345 drm_connector_list_iter_begin(drm_dev, &iter);
2346 drm_for_each_connector_iter(list_connector, &iter) {
2347 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2348 ret = -EBUSY;
2349 break;
2350 }
2351 }
2352
2353 drm_connector_list_iter_end(&iter);
2354
2355 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2356 mutex_unlock(&drm_dev->mode_config.mutex);
d38ceaf9
AD		 2357 }
2358
97f6a21b
AG		 2359 if (ret == -EBUSY)
2360 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
2361
d38ceaf9
AD		 2362 pm_runtime_mark_last_busy(dev);
2363 pm_runtime_autosuspend(dev);
97f6a21b 2364 return ret;
d38ceaf9
AD		 2365}
2366
2367long amdgpu_drm_ioctl(struct file *filp,
2368 unsigned int cmd, unsigned long arg)
2369{
2370 struct drm_file *file_priv = filp->private_data;
2371 struct drm_device *dev;
2372 long ret;
2373 dev = file_priv->minor->dev;
2374 ret = pm_runtime_get_sync(dev->dev);
2375 if (ret < 0)
5509ac65 2376 goto out;
d38ceaf9
AD		 2377
2378 ret = drm_ioctl(filp, cmd, arg);
2379
2380 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2381out:
d38ceaf9
AD		 2382 pm_runtime_put_autosuspend(dev->dev);
2383 return ret;
2384}
2385
2386static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2387 .prepare = amdgpu_pmops_prepare,
2388 .complete = amdgpu_pmops_complete,
d38ceaf9
AD		 2389 .suspend = amdgpu_pmops_suspend,
2390 .resume = amdgpu_pmops_resume,
2391 .freeze = amdgpu_pmops_freeze,
2392 .thaw = amdgpu_pmops_thaw,
74b0b157 2393 .poweroff = amdgpu_pmops_poweroff,
2394 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2395 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2396 .runtime_resume = amdgpu_pmops_runtime_resume,
2397 .runtime_idle = amdgpu_pmops_runtime_idle,
2398};
2399
48ad368a
AG		 2400static int amdgpu_flush(struct file *f, fl_owner_t id)
2401{
2402 struct drm_file *file_priv = f->private_data;
2403 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2404 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2405
56753e73
CK		 2406 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2407 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2408
56753e73 2409 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2410}
2411
d38ceaf9
AD		 2412static const struct file_operations amdgpu_driver_kms_fops = {
2413 .owner = THIS_MODULE,
2414 .open = drm_open,
48ad368a 2415 .flush = amdgpu_flush,
d38ceaf9
AD		 2416 .release = drm_release,
2417 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2418 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2419 .poll = drm_poll,
2420 .read = drm_read,
2421#ifdef CONFIG_COMPAT
2422 .compat_ioctl = amdgpu_kms_compat_ioctl,
2423#endif
87444254
RS		 2424#ifdef CONFIG_PROC_FS
2425 .show_fdinfo = amdgpu_show_fdinfo
2426#endif
d38ceaf9
AD		 2427};
2428
021830d2
BN		 2429int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2430{
f3729f7b 2431 struct drm_file *file;
021830d2
BN		 2432
2433 if (!filp)
2434 return -EINVAL;
2435
2436 if (filp->f_op != &amdgpu_driver_kms_fops) {
2437 return -EINVAL;
2438 }
2439
2440 file = filp->private_data;
2441 *fpriv = file->driver_priv;
2442 return 0;
2443}
2444
5088d657
LT		 2445const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2446 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2447 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2448 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2449 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2450 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2451 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2452 /* KMS */
2453 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2454 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2455 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2456 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2457 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2458 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2459 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2460 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2461 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2462 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2463};
2464
2465static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2466 .driver_features =
f3ed6739 2467 DRIVER_ATOMIC |
1ff49481 2468 DRIVER_GEM |
db4ff423
CZ		 2469 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2470 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2471 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2472 .postclose = amdgpu_driver_postclose_kms,
2473 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2474 .ioctls = amdgpu_ioctls_kms,
5088d657 2475 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2476 .dumb_create = amdgpu_mode_dumb_create,
2477 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2478 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2479 .release = &amdgpu_driver_release_kms,
d38ceaf9
AD		 2480
2481 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2482 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
09052fc3 2483 .gem_prime_import = amdgpu_gem_prime_import,
71df0368 2484 .gem_prime_mmap = drm_gem_prime_mmap,
d38ceaf9
AD		 2485
2486 .name = DRIVER_NAME,
2487 .desc = DRIVER_DESC,
2488 .date = DRIVER_DATE,
2489 .major = KMS_DRIVER_MAJOR,
2490 .minor = KMS_DRIVER_MINOR,
2491 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2492};
2493
c9a6b82f
AG		 2494static struct pci_error_handlers amdgpu_pci_err_handler = {
2495 .error_detected = amdgpu_pci_error_detected,
2496 .mmio_enabled = amdgpu_pci_mmio_enabled,
2497 .slot_reset = amdgpu_pci_slot_reset,
2498 .resume = amdgpu_pci_resume,
2499};
2500
35bba831
AG		 2501extern const struct attribute_group amdgpu_vram_mgr_attr_group;
2502extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
2503extern const struct attribute_group amdgpu_vbios_version_attr_group;
2504
2505static const struct attribute_group *amdgpu_sysfs_groups[] = {
2506 &amdgpu_vram_mgr_attr_group,
2507 &amdgpu_gtt_mgr_attr_group,
2508 &amdgpu_vbios_version_attr_group,
2509 NULL,
2510};
2511
2512
d38ceaf9
AD		 2513static struct pci_driver amdgpu_kms_pci_driver = {
2514 .name = DRIVER_NAME,
2515 .id_table = pciidlist,
2516 .probe = amdgpu_pci_probe,
2517 .remove = amdgpu_pci_remove,
61e11306 2518 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2519 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2520 .err_handler = &amdgpu_pci_err_handler,
35bba831 2521 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2522};
2523
2524static int __init amdgpu_init(void)
2525{
245ae5e9
CK		 2526 int r;
2527
6a2d2ddf 2528 if (drm_firmware_drivers_only())
c60e22f7 2529 return -EINVAL;
c60e22f7 2530
245ae5e9
CK		 2531 r = amdgpu_sync_init();
2532 if (r)
2533 goto error_sync;
2534
2535 r = amdgpu_fence_slab_init();
2536 if (r)
2537 goto error_fence;
2538
d38ceaf9 2539 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 2540 amdgpu_register_atpx_handler();
f9b7f370 2541 amdgpu_acpi_detect();
03a1c08d
FK		 2542
2543 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
2544 amdgpu_amdkfd_init();
2545
d38ceaf9 2546 /* let modprobe override vga console setting */
448d1051 2547 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 2548
245ae5e9
CK		 2549error_fence:
2550 amdgpu_sync_fini();
2551
2552error_sync:
2553 return r;
d38ceaf9
AD		 2554}
2555
2556static void __exit amdgpu_exit(void)
2557{
130e0371 2558 amdgpu_amdkfd_fini();
448d1051 2559 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 2560 amdgpu_unregister_atpx_handler();
257bf15a 2561 amdgpu_sync_fini();
d573de2d 2562 amdgpu_fence_slab_fini();
c7d8b782 2563 mmu_notifier_synchronize();
d38ceaf9
AD		 2564}
2565
2566module_init(amdgpu_init);
2567module_exit(amdgpu_exit);
2568
2569MODULE_AUTHOR(DRIVER_AUTHOR);
2570MODULE_DESCRIPTION(DRIVER_DESC);
2571MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)