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drm/amdgpu: add option to stop on VM fault
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/**
2 * \file amdgpu_drv.c
3 * AMD Amdgpu driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#include <drm/drmP.h>
33#include <drm/amdgpu_drm.h>
34#include <drm/drm_gem.h>
35#include "amdgpu_drv.h"
36
37#include <drm/drm_pciids.h>
38#include <linux/console.h>
39#include <linux/module.h>
40#include <linux/pm_runtime.h>
41#include <linux/vga_switcheroo.h>
42#include "drm_crtc_helper.h"
43
44#include "amdgpu.h"
45#include "amdgpu_irq.h"
46
130e0371
OG		 47#include "amdgpu_amdkfd.h"
48
d38ceaf9
AD		 49/*
50 * KMS wrapper.
51 * - 3.0.0 - initial driver
6055f37a 52 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
d38ceaf9
AD		 53 */
54#define KMS_DRIVER_MAJOR 3
6055f37a 55#define KMS_DRIVER_MINOR 1
d38ceaf9
AD		 56#define KMS_DRIVER_PATCHLEVEL 0
57
58int amdgpu_vram_limit = 0;
59int amdgpu_gart_size = -1; /* auto */
60int amdgpu_benchmarking = 0;
61int amdgpu_testing = 0;
62int amdgpu_audio = -1;
63int amdgpu_disp_priority = 0;
64int amdgpu_hw_i2c = 0;
65int amdgpu_pcie_gen2 = -1;
66int amdgpu_msi = -1;
a895c222 67int amdgpu_lockup_timeout = 0;
d38ceaf9
AD		 68int amdgpu_dpm = -1;
69int amdgpu_smc_load_fw = 1;
70int amdgpu_aspm = -1;
71int amdgpu_runtime_pm = -1;
72int amdgpu_hard_reset = 0;
73unsigned amdgpu_ip_block_mask = 0xffffffff;
74int amdgpu_bapm = -1;
75int amdgpu_deep_color = 0;
76int amdgpu_vm_size = 8;
77int amdgpu_vm_block_size = -1;
d9c13156 78int amdgpu_vm_fault_stop = 0;
d38ceaf9 79int amdgpu_exp_hw_support = 0;
36b4ba07 80int amdgpu_enable_scheduler = 1;
1333f723 81int amdgpu_sched_jobs = 16;
4afcb303 82int amdgpu_sched_hw_submission = 2;
d4edda3f 83int amdgpu_enable_semaphores = 0;
d38ceaf9
AD		 84
85MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
86module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
87
88MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
89module_param_named(gartsize, amdgpu_gart_size, int, 0600);
90
91MODULE_PARM_DESC(benchmark, "Run benchmark");
92module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
93
94MODULE_PARM_DESC(test, "Run tests");
95module_param_named(test, amdgpu_testing, int, 0444);
96
97MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
98module_param_named(audio, amdgpu_audio, int, 0444);
99
100MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
101module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
102
103MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
104module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
105
106MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
107module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
108
109MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
110module_param_named(msi, amdgpu_msi, int, 0444);
111
a895c222 112MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)");
d38ceaf9
AD		 113module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
114
115MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
116module_param_named(dpm, amdgpu_dpm, int, 0444);
117
118MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
119module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
120
121MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
122module_param_named(aspm, amdgpu_aspm, int, 0444);
123
124MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
125module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
126
127MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
128module_param_named(hard_reset, amdgpu_hard_reset, int, 0444);
129
130MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
131module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
132
133MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
134module_param_named(bapm, amdgpu_bapm, int, 0444);
135
136MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
137module_param_named(deep_color, amdgpu_deep_color, int, 0444);
138
8dacc127 139MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)");
d38ceaf9
AD		 140module_param_named(vm_size, amdgpu_vm_size, int, 0444);
141
142MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
143module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
144
d9c13156
CK		 145MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
146module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
147
d38ceaf9
AD		 148MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
149module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
150
36b4ba07 151MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");
02b9f0bf
JZ		 152module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
153
1333f723
JZ		 154MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
155module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
156
4afcb303
JZ		 157MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
158module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
159
d4edda3f 160MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))");
3daea9e3
CK		 161module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
162
d38ceaf9 163static struct pci_device_id pciidlist[] = {
89330c39
AD		 164#ifdef CONFIG_DRM_AMDGPU_CIK
165 /* Kaveri */
2f7d10b3
JZ		 166 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
167 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
168 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
169 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
170 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
171 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
172 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
173 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
174 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
175 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
176 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
177 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
178 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
179 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
180 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
181 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
182 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
183 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
184 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
185 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
186 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
187 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 188 /* Bonaire */
2f7d10b3
JZ		 189 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
190 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
191 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
192 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 193 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
194 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
195 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
196 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
197 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
198 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 199 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 200 /* Hawaii */
201 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
202 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
203 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
204 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
205 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
206 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
207 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
208 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
209 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
210 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
211 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
212 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
213 /* Kabini */
2f7d10b3
JZ		 214 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
215 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
216 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
217 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
218 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
219 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
220 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
221 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
222 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
223 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
224 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
225 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
226 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
227 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
228 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
229 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 230 /* mullins */
2f7d10b3
JZ		 231 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
232 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
233 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
234 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
235 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
236 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
237 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
238 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
239 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
240 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
241 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
242 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
243 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
244 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
245 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
246 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 247#endif
1256a8b8
AD		 248 /* topaz */
249 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
250 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
251 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
252 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
253 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
254 /* tonga */
255 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
256 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
257 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 258 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 259 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
260 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 261 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 262 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
263 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 264 /* fiji */
265 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 266 /* carrizo */
2f7d10b3
JZ		 267 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
268 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
269 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
270 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
271 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
d38ceaf9
AD		 272
273 {0, 0, 0}
274};
275
276MODULE_DEVICE_TABLE(pci, pciidlist);
277
278static struct drm_driver kms_driver;
279
280static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
281{
282 struct apertures_struct *ap;
283 bool primary = false;
284
285 ap = alloc_apertures(1);
286 if (!ap)
287 return -ENOMEM;
288
289 ap->ranges[0].base = pci_resource_start(pdev, 0);
290 ap->ranges[0].size = pci_resource_len(pdev, 0);
291
292#ifdef CONFIG_X86
293 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
294#endif
295 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
296 kfree(ap);
297
298 return 0;
299}
300
301static int amdgpu_pci_probe(struct pci_dev *pdev,
302 const struct pci_device_id *ent)
303{
304 unsigned long flags = ent->driver_data;
305 int ret;
306
2f7d10b3 307 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 308 DRM_INFO("This hardware requires experimental hardware support.\n"
309 "See modparam exp_hw_support\n");
310 return -ENODEV;
311 }
312
313 /* Get rid of things like offb */
314 ret = amdgpu_kick_out_firmware_fb(pdev);
315 if (ret)
316 return ret;
317
318 return drm_get_pci_dev(pdev, ent, &kms_driver);
319}
320
321static void
322amdgpu_pci_remove(struct pci_dev *pdev)
323{
324 struct drm_device *dev = pci_get_drvdata(pdev);
325
326 drm_put_dev(dev);
327}
328
329static int amdgpu_pmops_suspend(struct device *dev)
330{
331 struct pci_dev *pdev = to_pci_dev(dev);
332 struct drm_device *drm_dev = pci_get_drvdata(pdev);
333 return amdgpu_suspend_kms(drm_dev, true, true);
334}
335
336static int amdgpu_pmops_resume(struct device *dev)
337{
338 struct pci_dev *pdev = to_pci_dev(dev);
339 struct drm_device *drm_dev = pci_get_drvdata(pdev);
340 return amdgpu_resume_kms(drm_dev, true, true);
341}
342
343static int amdgpu_pmops_freeze(struct device *dev)
344{
345 struct pci_dev *pdev = to_pci_dev(dev);
346 struct drm_device *drm_dev = pci_get_drvdata(pdev);
347 return amdgpu_suspend_kms(drm_dev, false, true);
348}
349
350static int amdgpu_pmops_thaw(struct device *dev)
351{
352 struct pci_dev *pdev = to_pci_dev(dev);
353 struct drm_device *drm_dev = pci_get_drvdata(pdev);
354 return amdgpu_resume_kms(drm_dev, false, true);
355}
356
357static int amdgpu_pmops_runtime_suspend(struct device *dev)
358{
359 struct pci_dev *pdev = to_pci_dev(dev);
360 struct drm_device *drm_dev = pci_get_drvdata(pdev);
361 int ret;
362
363 if (!amdgpu_device_is_px(drm_dev)) {
364 pm_runtime_forbid(dev);
365 return -EBUSY;
366 }
367
368 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
369 drm_kms_helper_poll_disable(drm_dev);
370 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
371
372 ret = amdgpu_suspend_kms(drm_dev, false, false);
373 pci_save_state(pdev);
374 pci_disable_device(pdev);
375 pci_ignore_hotplug(pdev);
376 pci_set_power_state(pdev, PCI_D3cold);
377 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
378
379 return 0;
380}
381
382static int amdgpu_pmops_runtime_resume(struct device *dev)
383{
384 struct pci_dev *pdev = to_pci_dev(dev);
385 struct drm_device *drm_dev = pci_get_drvdata(pdev);
386 int ret;
387
388 if (!amdgpu_device_is_px(drm_dev))
389 return -EINVAL;
390
391 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
392
393 pci_set_power_state(pdev, PCI_D0);
394 pci_restore_state(pdev);
395 ret = pci_enable_device(pdev);
396 if (ret)
397 return ret;
398 pci_set_master(pdev);
399
400 ret = amdgpu_resume_kms(drm_dev, false, false);
401 drm_kms_helper_poll_enable(drm_dev);
402 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
403 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
404 return 0;
405}
406
407static int amdgpu_pmops_runtime_idle(struct device *dev)
408{
409 struct pci_dev *pdev = to_pci_dev(dev);
410 struct drm_device *drm_dev = pci_get_drvdata(pdev);
411 struct drm_crtc *crtc;
412
413 if (!amdgpu_device_is_px(drm_dev)) {
414 pm_runtime_forbid(dev);
415 return -EBUSY;
416 }
417
418 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
419 if (crtc->enabled) {
420 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
421 return -EBUSY;
422 }
423 }
424
425 pm_runtime_mark_last_busy(dev);
426 pm_runtime_autosuspend(dev);
427 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
428 return 1;
429}
430
431long amdgpu_drm_ioctl(struct file *filp,
432 unsigned int cmd, unsigned long arg)
433{
434 struct drm_file *file_priv = filp->private_data;
435 struct drm_device *dev;
436 long ret;
437 dev = file_priv->minor->dev;
438 ret = pm_runtime_get_sync(dev->dev);
439 if (ret < 0)
440 return ret;
441
442 ret = drm_ioctl(filp, cmd, arg);
443
444 pm_runtime_mark_last_busy(dev->dev);
445 pm_runtime_put_autosuspend(dev->dev);
446 return ret;
447}
448
449static const struct dev_pm_ops amdgpu_pm_ops = {
450 .suspend = amdgpu_pmops_suspend,
451 .resume = amdgpu_pmops_resume,
452 .freeze = amdgpu_pmops_freeze,
453 .thaw = amdgpu_pmops_thaw,
454 .poweroff = amdgpu_pmops_freeze,
455 .restore = amdgpu_pmops_resume,
456 .runtime_suspend = amdgpu_pmops_runtime_suspend,
457 .runtime_resume = amdgpu_pmops_runtime_resume,
458 .runtime_idle = amdgpu_pmops_runtime_idle,
459};
460
461static const struct file_operations amdgpu_driver_kms_fops = {
462 .owner = THIS_MODULE,
463 .open = drm_open,
464 .release = drm_release,
465 .unlocked_ioctl = amdgpu_drm_ioctl,
466 .mmap = amdgpu_mmap,
467 .poll = drm_poll,
468 .read = drm_read,
469#ifdef CONFIG_COMPAT
470 .compat_ioctl = amdgpu_kms_compat_ioctl,
471#endif
472};
473
474static struct drm_driver kms_driver = {
475 .driver_features =
476 DRIVER_USE_AGP |
477 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
478 DRIVER_PRIME | DRIVER_RENDER,
479 .dev_priv_size = 0,
480 .load = amdgpu_driver_load_kms,
481 .open = amdgpu_driver_open_kms,
482 .preclose = amdgpu_driver_preclose_kms,
483 .postclose = amdgpu_driver_postclose_kms,
484 .lastclose = amdgpu_driver_lastclose_kms,
485 .set_busid = drm_pci_set_busid,
486 .unload = amdgpu_driver_unload_kms,
487 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
488 .enable_vblank = amdgpu_enable_vblank_kms,
489 .disable_vblank = amdgpu_disable_vblank_kms,
490 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
491 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
492#if defined(CONFIG_DEBUG_FS)
493 .debugfs_init = amdgpu_debugfs_init,
494 .debugfs_cleanup = amdgpu_debugfs_cleanup,
495#endif
496 .irq_preinstall = amdgpu_irq_preinstall,
497 .irq_postinstall = amdgpu_irq_postinstall,
498 .irq_uninstall = amdgpu_irq_uninstall,
499 .irq_handler = amdgpu_irq_handler,
500 .ioctls = amdgpu_ioctls_kms,
501 .gem_free_object = amdgpu_gem_object_free,
502 .gem_open_object = amdgpu_gem_object_open,
503 .gem_close_object = amdgpu_gem_object_close,
504 .dumb_create = amdgpu_mode_dumb_create,
505 .dumb_map_offset = amdgpu_mode_dumb_mmap,
506 .dumb_destroy = drm_gem_dumb_destroy,
507 .fops = &amdgpu_driver_kms_fops,
508
509 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
510 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
511 .gem_prime_export = amdgpu_gem_prime_export,
512 .gem_prime_import = drm_gem_prime_import,
513 .gem_prime_pin = amdgpu_gem_prime_pin,
514 .gem_prime_unpin = amdgpu_gem_prime_unpin,
515 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
516 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
517 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
518 .gem_prime_vmap = amdgpu_gem_prime_vmap,
519 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
520
521 .name = DRIVER_NAME,
522 .desc = DRIVER_DESC,
523 .date = DRIVER_DATE,
524 .major = KMS_DRIVER_MAJOR,
525 .minor = KMS_DRIVER_MINOR,
526 .patchlevel = KMS_DRIVER_PATCHLEVEL,
527};
528
529static struct drm_driver *driver;
530static struct pci_driver *pdriver;
531
532static struct pci_driver amdgpu_kms_pci_driver = {
533 .name = DRIVER_NAME,
534 .id_table = pciidlist,
535 .probe = amdgpu_pci_probe,
536 .remove = amdgpu_pci_remove,
537 .driver.pm = &amdgpu_pm_ops,
538};
539
540static int __init amdgpu_init(void)
541{
542#ifdef CONFIG_VGA_CONSOLE
543 if (vgacon_text_force()) {
544 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
545 return -EINVAL;
546 }
547#endif
548 DRM_INFO("amdgpu kernel modesetting enabled.\n");
549 driver = &kms_driver;
550 pdriver = &amdgpu_kms_pci_driver;
551 driver->driver_features |= DRIVER_MODESET;
552 driver->num_ioctls = amdgpu_max_kms_ioctl;
553 amdgpu_register_atpx_handler();
554
130e0371
OG		 555 amdgpu_amdkfd_init();
556
d38ceaf9
AD		 557 /* let modprobe override vga console setting */
558 return drm_pci_init(driver, pdriver);
559}
560
561static void __exit amdgpu_exit(void)
562{
130e0371 563 amdgpu_amdkfd_fini();
d38ceaf9
AD		 564 drm_pci_exit(driver, pdriver);
565 amdgpu_unregister_atpx_handler();
566}
567
568module_init(amdgpu_init);
569module_exit(amdgpu_exit);
570
571MODULE_AUTHOR(DRIVER_AUTHOR);
572MODULE_DESCRIPTION(DRIVER_DESC);
573MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)