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drm/amdgpu: remove misleading amdgpu_pmops_runtime_idle() comment
[linux-block.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_drv.c
CommitLineData
d38ceaf9
AD		 1/*
2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
d38ceaf9 25#include <drm/amdgpu_drm.h>
fdf2f6c5 26#include <drm/drm_drv.h>
8ab59da2 27#include <drm/drm_fbdev_generic.h>
d38ceaf9 28#include <drm/drm_gem.h>
8aba21b7 29#include <drm/drm_managed.h>
d38ceaf9 30#include <drm/drm_pciids.h>
fcd70cd3 31#include <drm/drm_probe_helper.h>
e2e42edf
SS		 32#include <drm/drm_vblank.h>
33
e9d1d2bb 34#include <linux/cc_platform.h>
f158936b 35#include <linux/dynamic_debug.h>
e2e42edf
SS		 36#include <linux/module.h>
37#include <linux/mmu_notifier.h>
38#include <linux/pm_runtime.h>
39#include <linux/suspend.h>
40#include <linux/vga_switcheroo.h>
d38ceaf9
AD		 41
42#include "amdgpu.h"
e2e42edf 43#include "amdgpu_amdkfd.h"
2fbd6f94 44#include "amdgpu_dma_buf.h"
e2e42edf 45#include "amdgpu_drv.h"
87444254 46#include "amdgpu_fdinfo.h"
e2e42edf 47#include "amdgpu_irq.h"
4e2abc19 48#include "amdgpu_psp.h"
7c6e68c7 49#include "amdgpu_ras.h"
04442bf7 50#include "amdgpu_reset.h"
e2e42edf
SS		 51#include "amdgpu_sched.h"
52#include "amdgpu_xgmi.h"
9938333a 53#include "../amdxcp/amdgpu_xcp_drv.h"
7c6e68c7 54
d38ceaf9
AD		 55/*
56 * KMS wrapper.
57 * - 3.0.0 - initial driver
6055f37a 58 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
f84e63f2
MO		 59 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
60 * at the end of IBs.
d347ce66 61 * - 3.3.0 - Add VM support for UVD on supported hardware.
83a59b63 62 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS.
8dd31d74 63 * - 3.5.0 - Add support for new UVD_NO_OP register.
753ad49c 64 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer.
9cee3c1f 65 * - 3.7.0 - Add support for VCE clock list packet
b62b5931 66 * - 3.8.0 - Add support raster config init in the kernel
ef704318 67 * - 3.9.0 - Add support for memory query info about VRAM and GTT.
a5b11dac 68 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags
5ebbac4b 69 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc).
dfe38bd8 70 * - 3.12.0 - Add query for double offchip LDS buffers
8eafd505 71 * - 3.13.0 - Add PRT support
203eb0cb 72 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality
44eb8c1b 73 * - 3.15.0 - Export more gpu info for gfx9
b98b8dbc 74 * - 3.16.0 - Add reserved vmid support
68e2c5ff 75 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS.
dbfe85ea 76 * - 3.18.0 - Export gpu always on cu bitmap
33476319 77 * - 3.19.0 - Add support for UVD MJPEG decode
fd8bf087 78 * - 3.20.0 - Add support for local BOs
7ca24cf2 79 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl
b285f1db 80 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl
c057c114 81 * - 3.23.0 - Add query for VRAM lost counter
f8e3e0ee 82 * - 3.24.0 - Add high priority compute support for gfx9
7b158d16 83 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk).
d240cd9e 84 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE.
c19a23fa 85 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation.
67dd1a36 86 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
41cca166 87 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID
767e06a9 88 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE.
df8368be 89 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC
1afeb314 90 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS.
635e2c5f 91 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS.
965ebe3d 92 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
815fb4c9 93 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
664fe85a 94 * - 3.36.0 - Allow reading more status registers on si/cik
ff532461 95 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness
43c8546b 96 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
174b328b 97 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync
16c642ec 98 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ
b50368da 99 * - 3.41.0 - Add video codec query
915821a7 100 * - 3.42.0 - Add 16bpc fixed point display support
5c67ff3a 101 * - 3.43.0 - Add device hot plug/unplug support
f2e7d856 102 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B
ded81d5b 103 * - 3.45.0 - Add context ioctl stable pstate interface
08cffb3e 104 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm
465576ca
AD		 105 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags
106 * - 3.48.0 - Add IP discovery version info to HW INFO
cf5cf349
EQ		 107 * - 3.49.0 - Add gang submit into CS IOCTL
108 * - 3.50.0 - Update AMDGPU_INFO_DEV_INFO IOCTL for minimum engine and memory clock
109 * Update AMDGPU_INFO_SENSOR IOCTL for PEAK_PSTATE engine and memory clock
e3e84b0a 110 * 3.51.0 - Return the PCIe gen and lanes from the INFO ioctl
b299221f
MO		 111 * 3.52.0 - Add AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, add device_info fields:
112 * tcp_cache_size, num_sqc_per_wgp, sqc_data_cache_size, sqc_inst_cache_size,
113 * gl1c_cache_size, gl2c_cache_size, mall_size, enabled_rb_pipes_mask_hi
8a93c691 114 * 3.53.0 - Support for GFX11 CP GFX shadowing
489763af 115 * 3.54.0 - Add AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS support
7a41ed8b 116 * - 3.55.0 - Add AMDGPU_INFO_GPUVM_FAULT query
6cb8e3ee 117 * - 3.56.0 - Update IB start address and size alignment for decode and encode
91963397 118 * - 3.57.0 - Compute tunneling on GFX10+
d38ceaf9
AD		 119 */
120#define KMS_DRIVER_MAJOR 3
91963397 121#define KMS_DRIVER_MINOR 57
d38ceaf9
AD		 122#define KMS_DRIVER_PATCHLEVEL 0
123
887db1e4
AA		 124/*
125 * amdgpu.debug module options. Are all disabled by default
126 */
127enum AMDGPU_DEBUG_MASK {
128 AMDGPU_DEBUG_VM = BIT(0),
129 AMDGPU_DEBUG_LARGEBAR = BIT(1),
ffde7210 130 AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2),
d20e1aec 131 AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3),
887db1e4
AA		 132};
133
0b04ea39 134unsigned int amdgpu_vram_limit = UINT_MAX;
87fb7833 135int amdgpu_vis_vram_limit;
83e74db6 136int amdgpu_gart_size = -1; /* auto */
36d38372 137int amdgpu_gtt_size = -1; /* auto */
95844d20 138int amdgpu_moverate = -1; /* auto */
d38ceaf9 139int amdgpu_audio = -1;
87fb7833
DV		 140int amdgpu_disp_priority;
141int amdgpu_hw_i2c;
d38ceaf9
AD		 142int amdgpu_pcie_gen2 = -1;
143int amdgpu_msi = -1;
f440ff44 144char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
d38ceaf9 145int amdgpu_dpm = -1;
e635ee07 146int amdgpu_fw_load_type = -1;
d38ceaf9
AD		 147int amdgpu_aspm = -1;
148int amdgpu_runtime_pm = -1;
0b693f0b 149uint amdgpu_ip_block_mask = 0xffffffff;
d38ceaf9 150int amdgpu_bapm = -1;
87fb7833 151int amdgpu_deep_color;
bab4fee7 152int amdgpu_vm_size = -1;
d07f14be 153int amdgpu_vm_fragment_size = -1;
d38ceaf9 154int amdgpu_vm_block_size = -1;
87fb7833 155int amdgpu_vm_fault_stop;
9a4b7d4c 156int amdgpu_vm_update_mode = -1;
87fb7833 157int amdgpu_exp_hw_support;
4562236b 158int amdgpu_dc = -1;
b70f014d 159int amdgpu_sched_jobs = 32;
4afcb303 160int amdgpu_sched_hw_submission = 2;
87fb7833
DV		 161uint amdgpu_pcie_gen_cap;
162uint amdgpu_pcie_lane_cap;
25faeddc 163u64 amdgpu_cg_mask = 0xffffffffffffffff;
0b693f0b
RZ		 164uint amdgpu_pg_mask = 0xffffffff;
165uint amdgpu_sdma_phase_quantum = 32;
e86c30e9
SS		 166char *amdgpu_disable_cu;
167char *amdgpu_virtual_display;
80e709ee 168bool enforce_isolation;
680602d6
KF		 169/*
170 * OverDrive(bit 14) disabled by default
171 * GFX DCS(bit 19) disabled by default
172 */
173uint amdgpu_pp_feature_mask = 0xfff7bfff;
87fb7833 174uint amdgpu_force_long_training;
e8835e0e 175int amdgpu_lbpw = -1;
4a75aefe 176int amdgpu_compute_multipipe = -1;
dcebf026 177int amdgpu_gpu_recovery = -1; /* auto */
87fb7833
DV		 178int amdgpu_emu_mode;
179uint amdgpu_smu_memory_pool_size;
8738a82b 180int amdgpu_smu_pptable_id = -1;
191a3c04
EQ		 181/*
182 * FBC (bit 0) disabled by default
183 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default
184 * - With this, for multiple monitors in sync(e.g. with the same model),
185 * mclk switching will be allowed. And the mclk will be not foced to the
186 * highest. That helps saving some idle power.
187 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
188 * PSR (bit 3) disabled by default
a5148245 189 * EDP NO POWER SEQUENCING (bit 4) disabled by default
191a3c04
EQ		 190 */
191uint amdgpu_dc_feature_mask = 2;
87fb7833 192uint amdgpu_dc_debug_mask;
792a0cdd 193uint amdgpu_dc_visual_confirm;
5bfca069 194int amdgpu_async_gfx_ring = 1;
50a7c876 195int amdgpu_mcbp = -1;
63e2fef6 196int amdgpu_discovery = -1;
87fb7833 197int amdgpu_mes;
928fe236 198int amdgpu_mes_kiq;
d5cc02d9 199int amdgpu_noretry = -1;
4e66d7d2 200int amdgpu_force_asic_type = -1;
58aa7790 201int amdgpu_tmz = -1; /* auto */
959143da 202uint amdgpu_freesync_vid_mode;
273da6ff 203int amdgpu_reset_method = -1; /* auto */
a300de40 204int amdgpu_num_kcq = -1;
30d95a37 205int amdgpu_smartshift_bias;
158a05a0 206int amdgpu_use_xgmi_p2p = 1;
11eb648d 207int amdgpu_vcnfw_log;
bf0207e1 208int amdgpu_sg_display = -1; /* auto */
570de94b 209int amdgpu_user_partt_mode = AMDGPU_AUTO_COMPUTE_PARTITION_MODE;
eebb06d1 210int amdgpu_umsch_mm;
5dc270d3 211int amdgpu_seamless = -1; /* auto */
887db1e4 212uint amdgpu_debug_mask;
6ba5b613 213int amdgpu_agp = -1; /* auto */
b8b39de6 214int amdgpu_wbrf = -1;
fc184dbe 215int amdgpu_damage_clips = -1; /* auto */
7875a226 216
e3c1b071 217static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
218
f158936b
JC		 219DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
220 "DRM_UT_CORE",
221 "DRM_UT_DRIVER",
222 "DRM_UT_KMS",
223 "DRM_UT_PRIME",
224 "DRM_UT_ATOMIC",
225 "DRM_UT_VBL",
226 "DRM_UT_STATE",
227 "DRM_UT_LEASE",
228 "DRM_UT_DP",
229 "DRM_UT_DRMRES");
230
62d73fbc
EQ		 231struct amdgpu_mgpu_info mgpu_info = {
232 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
e3c1b071 233 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
234 mgpu_info.delayed_reset_work,
235 amdgpu_drv_delayed_reset_work_handler, 0),
62d73fbc 236};
1218252f 237int amdgpu_ras_enable = -1;
e53aec7e 238uint amdgpu_ras_mask = 0xffffffff;
acc0204c 239int amdgpu_bad_page_threshold = -1;
88f8575b
DL		 240struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
241 .timeout_fatal_disable = false,
28a5d7a5 242 .period = 0x0, /* default to 0x0 (timeout disable) */
88f8575b 243};
d38ceaf9 244
8405cf39
SJ		 245/**
246 * DOC: vramlimit (int)
247 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM).
248 */
d38ceaf9
AD		 249MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
250module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
251
8405cf39
SJ		 252/**
253 * DOC: vis_vramlimit (int)
254 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM).
255 */
218b5dcd
JB		 256MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
257module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
258
8405cf39
SJ		 259/**
260 * DOC: gartsize (uint)
570513ba
PM		 261 * Restrict the size of GART (for kernel use) in Mib (32, 64, etc.) for testing.
262 * The default is -1 (The size depends on asic).
8405cf39 263 */
570513ba 264MODULE_PARM_DESC(gartsize, "Size of kernel GART to setup in megabytes (32, 64, etc., -1=auto)");
f9321cc4 265module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
d38ceaf9 266
8405cf39
SJ		 267/**
268 * DOC: gttsize (int)
570513ba
PM		 269 * Restrict the size of GTT domain (for userspace use) in MiB for testing.
270 * The default is -1 (Use 1/2 RAM, minimum value is 3GB).
8405cf39 271 */
570513ba 272MODULE_PARM_DESC(gttsize, "Size of the GTT userspace domain in megabytes (-1 = auto)");
36d38372 273module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
d38ceaf9 274
8405cf39
SJ		 275/**
276 * DOC: moverate (int)
277 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
278 */
95844d20
MO		 279MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
280module_param_named(moverate, amdgpu_moverate, int, 0600);
281
8405cf39
SJ		 282/**
283 * DOC: audio (int)
284 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it.
285 */
d38ceaf9
AD		 286MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
287module_param_named(audio, amdgpu_audio, int, 0444);
288
8405cf39
SJ		 289/**
290 * DOC: disp_priority (int)
291 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto).
292 */
d38ceaf9
AD		 293MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
294module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
295
8405cf39
SJ		 296/**
297 * DOC: hw_i2c (int)
298 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled).
299 */
d38ceaf9
AD		 300MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
301module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
302
8405cf39
SJ		 303/**
304 * DOC: pcie_gen2 (int)
305 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled).
306 */
d38ceaf9
AD		 307MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
308module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
309
8405cf39
SJ		 310/**
311 * DOC: msi (int)
312 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled).
313 */
d38ceaf9
AD		 314MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
315module_param_named(msi, amdgpu_msi, int, 0444);
316
8405cf39 317/**
912dfc84
EQ		 318 * DOC: lockup_timeout (string)
319 * Set GPU scheduler timeout value in ms.
320 *
321 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
322 * multiple values specified. 0 and negative values are invalidated. They will be adjusted
879e723d
AZ		 323 * to the default timeout.
324 *
325 * - With one value specified, the setting will apply to all non-compute jobs.
326 * - With multiple values specified, the first one will be for GFX.
327 * The second one is for Compute. The third and fourth ones are
328 * for SDMA and Video.
329 *
912dfc84 330 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
67387dfe 331 * jobs is 10000. The timeout for compute is 60000.
912dfc84 332 */
67387dfe 333MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
f9acfafc 334 "for passthrough or sriov, 10000 for all jobs. 0: keep default value. negative: infinity timeout), format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
bcccee89 335 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
912dfc84 336module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
d38ceaf9 337
8405cf39
SJ		 338/**
339 * DOC: dpm (int)
54b998ca 340 * Override for dynamic power management setting
5c9a6272 341 * (0 = disable, 1 = enable)
54b998ca 342 * The default is -1 (auto).
8405cf39 343 */
d38ceaf9
AD		 344MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
345module_param_named(dpm, amdgpu_dpm, int, 0444);
346
8405cf39
SJ		 347/**
348 * DOC: fw_load_type (int)
ddb267b6
YD		 349 * Set different firmware loading type for debugging, if supported.
350 * Set to 0 to force direct loading if supported by the ASIC. Set
351 * to -1 to select the default loading mode for the ASIC, as defined
352 * by the driver. The default is -1 (auto).
8405cf39 353 */
a76be7bb 354MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)");
e635ee07 355module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
d38ceaf9 356
8405cf39
SJ		 357/**
358 * DOC: aspm (int)
359 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled).
360 */
d38ceaf9
AD		 361MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
362module_param_named(aspm, amdgpu_aspm, int, 0444);
363
8405cf39
SJ		 364/**
365 * DOC: runpm (int)
4d625a97
AD		 366 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down
367 * the dGPUs when they are idle if supported. The default is -1 (auto enable).
368 * Setting the value to 0 disables this functionality.
4d6fc55a 369 * Setting the value to -2 is auto enabled with power down when displays are attached.
8405cf39 370 */
39a82d30 371MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto, -2 = auto with displays)");
d38ceaf9
AD		 372module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
373
8405cf39
SJ		 374/**
375 * DOC: ip_block_mask (uint)
376 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.).
377 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have
378 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in
379 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device).
380 */
d38ceaf9
AD		 381MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
382module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
383
8405cf39
SJ		 384/**
385 * DOC: bapm (int)
386 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it.
387 * The default -1 (auto, enabled)
388 */
d38ceaf9
AD		 389MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
390module_param_named(bapm, amdgpu_bapm, int, 0444);
391
8405cf39
SJ		 392/**
393 * DOC: deep_color (int)
394 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled).
395 */
d38ceaf9
AD		 396MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
397module_param_named(deep_color, amdgpu_deep_color, int, 0444);
398
8405cf39
SJ		 399/**
400 * DOC: vm_size (int)
401 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic).
402 */
ed885b21 403MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
d38ceaf9 404module_param_named(vm_size, amdgpu_vm_size, int, 0444);
d07f14be 405
8405cf39
SJ		 406/**
407 * DOC: vm_fragment_size (int)
408 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic).
409 */
d07f14be
RH		 410MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
411module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
d38ceaf9 412
8405cf39
SJ		 413/**
414 * DOC: vm_block_size (int)
415 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic).
416 */
d38ceaf9
AD		 417MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
418module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
419
8405cf39
SJ		 420/**
421 * DOC: vm_fault_stop (int)
422 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop).
423 */
d9c13156
CK		 424MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
425module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
426
8405cf39
SJ		 427/**
428 * DOC: vm_update_mode (int)
429 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default
430 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never).
431 */
9a4b7d4c
HK		 432MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
433module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
434
8405cf39
SJ		 435/**
436 * DOC: exp_hw_support (int)
437 * Enable experimental hw support (1 = enable). The default is 0 (disabled).
438 */
d38ceaf9
AD		 439MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
440module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
441
8405cf39
SJ		 442/**
443 * DOC: dc (int)
444 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic).
445 */
4562236b
HW		 446MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
447module_param_named(dc, amdgpu_dc, int, 0444);
448
8405cf39
SJ		 449/**
450 * DOC: sched_jobs (int)
451 * Override the max number of jobs supported in the sw queue. The default is 32.
452 */
b70f014d 453MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
1333f723
JZ		 454module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
455
8405cf39
SJ		 456/**
457 * DOC: sched_hw_submission (int)
458 * Override the max number of HW submissions. The default is 2.
459 */
4afcb303
JZ		 460MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
461module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
462
8405cf39 463/**
7427a7a0 464 * DOC: ppfeaturemask (hexint)
8405cf39
SJ		 465 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
466 * The default is the current set of stable power features.
467 */
5141e9d2 468MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
7427a7a0 469module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
3a74f6f2 470
367039bf
TY		 471/**
472 * DOC: forcelongtraining (uint)
473 * Force long memory training in resume.
474 * The default is zero, indicates short training in resume.
475 */
476MODULE_PARM_DESC(forcelongtraining, "force memory long training");
477module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
478
8405cf39
SJ		 479/**
480 * DOC: pcie_gen_cap (uint)
481 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
482 * The default is 0 (automatic for each asic).
483 */
cd474ba0
AD		 484MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
485module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
486
8405cf39
SJ		 487/**
488 * DOC: pcie_lane_cap (uint)
489 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h.
490 * The default is 0 (automatic for each asic).
491 */
cd474ba0
AD		 492MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
493module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
494
8405cf39 495/**
25faeddc 496 * DOC: cg_mask (ullong)
8405cf39 497 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in
25faeddc 498 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled).
8405cf39 499 */
395d1fb9 500MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
25faeddc 501module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444);
395d1fb9 502
8405cf39
SJ		 503/**
504 * DOC: pg_mask (uint)
505 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in
506 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled).
507 */
395d1fb9
NH		 508MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
509module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
510
8405cf39
SJ		 511/**
512 * DOC: sdma_phase_quantum (uint)
513 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32.
514 */
a667386c
FK		 515MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
516module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
517
8405cf39
SJ		 518/**
519 * DOC: disable_cu (charp)
520 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL.
521 */
6f8941a2
NH		 522MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
523module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
524
8405cf39
SJ		 525/**
526 * DOC: virtual_display (charp)
527 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards
528 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of
529 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci
530 * device at 26:00.0. The default is NULL.
531 */
0f66356d
ED		 532MODULE_PARM_DESC(virtual_display,
533 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
9accf2fd 534module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
e443059d 535
8405cf39
SJ		 536/**
537 * DOC: lbpw (int)
538 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled).
539 */
e8835e0e
HZ		 540MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
541module_param_named(lbpw, amdgpu_lbpw, int, 0444);
bce23e00 542
4a75aefe
AR		 543MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
544module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
545
8405cf39
SJ		 546/**
547 * DOC: gpu_recovery (int)
548 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV).
549 */
06a2d7cc 550MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)");
dcebf026
AG		 551module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
552
8405cf39
SJ		 553/**
554 * DOC: emu_mode (int)
555 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled).
556 */
d869ae09 557MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
bfca0289
SL		 558module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
559
1218252f 560/**
2f3940e9 561 * DOC: ras_enable (int)
1218252f 562 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
563 */
2f3940e9 564MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
1218252f 565module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
566
567/**
2f3940e9 568 * DOC: ras_mask (uint)
1218252f 569 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
570 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
571 */
2f3940e9 572MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
1218252f 573module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
574
88f8575b
DL		 575/**
576 * DOC: timeout_fatal_disable (bool)
577 * Disable Watchdog timeout fatal error event
578 */
579MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
580module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
581
582/**
583 * DOC: timeout_period (uint)
584 * Modify the watchdog timeout max_cycles as (1 << period)
585 */
28a5d7a5 586MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
88f8575b
DL		 587module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
588
8405cf39
SJ		 589/**
590 * DOC: si_support (int)
591 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
592 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
593 * otherwise using amdgpu driver.
594 */
6dd13096 595#ifdef CONFIG_DRM_AMDGPU_SI
53efaf56 596
b25b3599 597#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
b679566b 598int amdgpu_si_support;
6dd13096 599MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 600#else
601int amdgpu_si_support = 1;
602MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
603#endif
604
6dd13096
FK		 605module_param_named(si_support, amdgpu_si_support, int, 0444);
606#endif
607
8405cf39
SJ		 608/**
609 * DOC: cik_support (int)
610 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled,
611 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available,
612 * otherwise using amdgpu driver.
613 */
7df28986 614#ifdef CONFIG_DRM_AMDGPU_CIK
53efaf56 615
b25b3599 616#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE)
b679566b 617int amdgpu_cik_support;
2b059658 618MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
53efaf56
MD		 619#else
620int amdgpu_cik_support = 1;
621MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
622#endif
623
7df28986
FK		 624module_param_named(cik_support, amdgpu_cik_support, int, 0444);
625#endif
626
8405cf39
SJ		 627/**
628 * DOC: smu_memory_pool_size (uint)
629 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB.
630 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled).
631 */
7951e376 632MODULE_PARM_DESC(smu_memory_pool_size,
f9acfafc 633 "reserve gtt for smu debug usage, 0 = disable,0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
7951e376
RZ		 634module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
635
51bcce46
HZ		 636/**
637 * DOC: async_gfx_ring (int)
638 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
639 */
640MODULE_PARM_DESC(async_gfx_ring,
5bfca069 641 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
51bcce46
HZ		 642module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
643
40562787
AD		 644/**
645 * DOC: mcbp (int)
50a7c876 646 * It is used to enable mid command buffer preemption. (0 = disabled, 1 = enabled, -1 auto (default))
40562787 647 */
b239c017 648MODULE_PARM_DESC(mcbp,
50a7c876 649 "Enable Mid-command buffer preemption (0 = disabled, 1 = enabled), -1 = auto (default)");
b239c017
JX		 650module_param_named(mcbp, amdgpu_mcbp, int, 0444);
651
40562787
AD		 652/**
653 * DOC: discovery (int)
654 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM.
a79d3709 655 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file)
40562787 656 */
a190d1c7
XY		 657MODULE_PARM_DESC(discovery,
658 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
659module_param_named(discovery, amdgpu_discovery, int, 0444);
660
40562787
AD		 661/**
662 * DOC: mes (int)
663 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute.
664 * (0 = disabled (default), 1 = enabled)
665 */
38487284
JX		 666MODULE_PARM_DESC(mes,
667 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
668module_param_named(mes, amdgpu_mes, int, 0444);
669
928fe236
JX		 670/**
671 * DOC: mes_kiq (int)
672 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq.
673 * (0 = disabled (default), 1 = enabled)
674 */
675MODULE_PARM_DESC(mes_kiq,
676 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)");
677module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444);
678
d5cc02d9
AD		 679/**
680 * DOC: noretry (int)
9705c85f
FK		 681 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that
682 * do not support per-process XNACK this also disables retry page faults.
d5cc02d9
AD		 683 * (0 = retry enabled, 1 = retry disabled, -1 auto (default))
684 */
75ee6487 685MODULE_PARM_DESC(noretry,
d5cc02d9 686 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
75ee6487
FK		 687module_param_named(noretry, amdgpu_noretry, int, 0644);
688
4e66d7d2
YZ		 689/**
690 * DOC: force_asic_type (int)
691 * A non negative value used to specify the asic type for all supported GPUs.
692 */
693MODULE_PARM_DESC(force_asic_type,
694 "A non negative value used to specify the asic type for all supported GPUs");
695module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
696
158a05a0
AS		 697/**
698 * DOC: use_xgmi_p2p (int)
699 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable).
700 */
701MODULE_PARM_DESC(use_xgmi_p2p,
702 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))");
703module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444);
4e66d7d2
YZ		 704
705
2690262e 706#ifdef CONFIG_HSA_AMD
521fb7d0
AL		 707/**
708 * DOC: sched_policy (int)
709 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription.
710 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically
711 * assigns queues to HQDs.
712 */
2690262e 713int sched_policy = KFD_SCHED_POLICY_HWS;
521fb7d0
AL		 714module_param(sched_policy, int, 0444);
715MODULE_PARM_DESC(sched_policy,
716 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
717
718/**
719 * DOC: hws_max_conc_proc (int)
720 * Maximum number of processes that HWS can schedule concurrently. The maximum is the
721 * number of VMIDs assigned to the HWS, which is also the default.
722 */
b7dfbd2e 723int hws_max_conc_proc = -1;
521fb7d0
AL		 724module_param(hws_max_conc_proc, int, 0444);
725MODULE_PARM_DESC(hws_max_conc_proc,
726 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
727
728/**
729 * DOC: cwsr_enable (int)
730 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in
731 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0
732 * disables it.
733 */
2690262e 734int cwsr_enable = 1;
521fb7d0
AL		 735module_param(cwsr_enable, int, 0444);
736MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
737
738/**
739 * DOC: max_num_of_queues_per_device (int)
740 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default
741 * is 4096.
742 */
2690262e 743int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
521fb7d0
AL		 744module_param(max_num_of_queues_per_device, int, 0444);
745MODULE_PARM_DESC(max_num_of_queues_per_device,
746 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
747
748/**
749 * DOC: send_sigterm (int)
750 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm
751 * but just print errors on dmesg. Setting 1 enables sending sigterm.
752 */
2690262e 753int send_sigterm;
521fb7d0
AL		 754module_param(send_sigterm, int, 0444);
755MODULE_PARM_DESC(send_sigterm,
756 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
757
521fb7d0
AL		 758/**
759 * DOC: halt_if_hws_hang (int)
760 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang.
761 * Setting 1 enables halt on hang.
762 */
2690262e 763int halt_if_hws_hang;
521fb7d0
AL		 764module_param(halt_if_hws_hang, int, 0644);
765MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
29e76462
OZ		 766
767/**
768 * DOC: hws_gws_support(bool)
29633d0e
JG		 769 * Assume that HWS supports GWS barriers regardless of what firmware version
770 * check says. Default value: false (rely on MEC2 firmware version check).
29e76462
OZ		 771 */
772bool hws_gws_support;
773module_param(hws_gws_support, bool, 0444);
29633d0e 774MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
14328aa5
PC		 775
776/**
f9acfafc
SS		 777 * DOC: queue_preemption_timeout_ms (int)
778 * queue preemption timeout in ms (1 = Minimum, 9000 = default)
779 */
f51af435 780int queue_preemption_timeout_ms = 9000;
14328aa5
PC		 781module_param(queue_preemption_timeout_ms, int, 0644);
782MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
b2057956
FK		 783
784/**
785 * DOC: debug_evictions(bool)
786 * Enable extra debug messages to help determine the cause of evictions
787 */
788bool debug_evictions;
789module_param(debug_evictions, bool, 0644);
790MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
b80f050f
PY		 791
792/**
793 * DOC: no_system_mem_limit(bool)
794 * Disable system memory limit, to support multiple process shared memory
795 */
796bool no_system_mem_limit;
797module_param(no_system_mem_limit, bool, 0644);
798MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
799
6d909c5d
OZ		 800/**
801 * DOC: no_queue_eviction_on_vm_fault (int)
802 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction).
803 */
120ceaf7 804int amdgpu_no_queue_eviction_on_vm_fault;
6d909c5d
OZ		 805MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
806module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
2690262e 807#endif
521fb7d0 808
895797d9 809/**
76eb9c95 810 * DOC: mtype_local (int)
895797d9 811 */
76eb9c95 812int amdgpu_mtype_local;
b9cbd510 813MODULE_PARM_DESC(mtype_local, "MTYPE for local memory (0 = MTYPE_RW (default), 1 = MTYPE_NC, 2 = MTYPE_CC)");
76eb9c95 814module_param_named(mtype_local, amdgpu_mtype_local, int, 0444);
895797d9 815
08a2fd23
RE		 816/**
817 * DOC: pcie_p2p (bool)
818 * Enable PCIe P2P (requires large-BAR). Default value: true (on)
819 */
820#ifdef CONFIG_HSA_AMD_P2P
821bool pcie_p2p = true;
822module_param(pcie_p2p, bool, 0444);
823MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))");
824#endif
825
7875a226
AD		 826/**
827 * DOC: dcfeaturemask (uint)
828 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
829 * The default is the current set of stable display features.
830 */
831MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
832module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
833
8a791dab
HW		 834/**
835 * DOC: dcdebugmask (uint)
836 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
837 */
838MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
839module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
840
792a0cdd
LL		 841MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)");
842module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444);
843
ad4de27f
NK		 844/**
845 * DOC: abmlevel (uint)
846 * Override the default ABM (Adaptive Backlight Management) level used for DC
847 * enabled hardware. Requires DMCU to be supported and loaded.
848 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by
849 * default. Values 1-4 control the maximum allowable brightness reduction via
850 * the ABM algorithm, with 1 being the least reduction and 4 being the most
851 * reduction.
852 *
040fdcde
HM		 853 * Defaults to -1, or disabled. Userspace can only override this level after
854 * boot if it's set to auto.
ad4de27f 855 */
040fdcde
HM		 856int amdgpu_dm_abm_level = -1;
857MODULE_PARM_DESC(abmlevel,
858 "ABM level (0 = off, 1-4 = backlight reduction level, -1 auto (default))");
859module_param_named(abmlevel, amdgpu_dm_abm_level, int, 0444);
ad4de27f 860
7a46f05e
TI		 861int amdgpu_backlight = -1;
862MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
863module_param_named(backlight, amdgpu_backlight, bint, 0444);
864
fc184dbe
HM		 865/**
866 * DOC: damageclips (int)
867 * Enable or disable damage clips support. If damage clips support is disabled,
868 * we will force full frame updates, irrespective of what user space sends to
869 * us.
870 *
871 * Defaults to -1 (where it is enabled unless a PSR-SU display is detected).
872 */
873MODULE_PARM_DESC(damageclips,
874 "Damage clips support (0 = disable, 1 = enable, -1 auto (default))");
875module_param_named(damageclips, amdgpu_damage_clips, int, 0444);
876
d7ccb38d
HR		 877/**
878 * DOC: tmz (int)
879 * Trusted Memory Zone (TMZ) is a method to protect data being written
880 * to or read from memory.
881 *
882 * The default value: 0 (off). TODO: change to auto till it is completed.
883 */
58aa7790 884MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
d7ccb38d
HR		 885module_param_named(tmz, amdgpu_tmz, int, 0444);
886
959143da
AD		 887/**
888 * DOC: freesync_video (uint)
889 * Enable the optimization to adjust front porch timing to achieve seamless
890 * mode change experience when setting a freesync supported mode for which full
891 * modeset is not needed.
892 *
893 * The Display Core will add a set of modes derived from the base FreeSync
894 * video mode into the corresponding connector's mode list based on commonly
895 * used refresh rates and VRR range of the connected display, when users enable
896 * this feature. From the userspace perspective, they can see a seamless mode
897 * change experience when the change between different refresh rates under the
898 * same resolution. Additionally, userspace applications such as Video playback
899 * can read this modeset list and change the refresh rate based on the video
900 * frame rate. Finally, the userspace can also derive an appropriate mode for a
901 * particular refresh rate based on the FreeSync Mode and add it to the
902 * connector's mode list.
903 *
904 * Note: This is an experimental feature.
905 *
906 * The default value: 0 (off).
907 */
908MODULE_PARM_DESC(
909 freesync_video,
910 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
911module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
912
273da6ff
WS		 913/**
914 * DOC: reset_method (int)
2656fd23 915 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)
273da6ff 916 */
2656fd23 917MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
273da6ff
WS		 918module_param_named(reset_method, amdgpu_reset_method, int, 0444);
919
acc0204c 920/**
e4e6a589
LT		 921 * DOC: bad_page_threshold (int) Bad page threshold is specifies the
922 * threshold value of faulty pages detected by RAS ECC, which may
923 * result in the GPU entering bad status when the number of total
924 * faulty pages by ECC exceeds the threshold value.
acc0204c 925 */
f3cbe70e 926MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = ignore threshold (default value), 0 = disable bad page retirement, -2 = driver sets threshold)");
acc0204c
GC		 927module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
928
a300de40
ML		 929MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
930module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
931
11eb648d
RD		 932/**
933 * DOC: vcnfw_log (int)
934 * Enable vcnfw log output for debugging, the default is disabled.
935 */
936MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)");
937module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444);
938
bf0207e1
AD		 939/**
940 * DOC: sg_display (int)
941 * Disable S/G (scatter/gather) display (i.e., display from system memory).
942 * This option is only relevant on APUs. Set this option to 0 to disable
943 * S/G display if you experience flickering or other issues under memory
944 * pressure and report the issue.
945 */
946MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)");
947module_param_named(sg_display, amdgpu_sg_display, int, 0444);
948
eebb06d1
LY		 949/**
950 * DOC: umsch_mm (int)
951 * Enable Multi Media User Mode Scheduler. This is a HW scheduling engine for VCN and VPE.
952 * (0 = disabled (default), 1 = enabled)
953 */
954MODULE_PARM_DESC(umsch_mm,
955 "Enable Multi Media User Mode Scheduler (0 = disabled (default), 1 = enabled)");
956module_param_named(umsch_mm, amdgpu_umsch_mm, int, 0444);
957
8738a82b
LL		 958/**
959 * DOC: smu_pptable_id (int)
960 * Used to override pptable id. id = 0 use VBIOS pptable.
961 * id > 0 use the soft pptable with specicfied id.
962 */
963MODULE_PARM_DESC(smu_pptable_id,
964 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
965module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
966
0fa49d10
SZ		 967/**
968 * DOC: partition_mode (int)
969 * Used to override the default SPX mode.
970 */
570de94b
LL		 971MODULE_PARM_DESC(
972 user_partt_mode,
973 "specify partition mode to be used (-2 = AMDGPU_AUTO_COMPUTE_PARTITION_MODE(default value) \
974 0 = AMDGPU_SPX_PARTITION_MODE, \
0fa49d10
SZ		 975 1 = AMDGPU_DPX_PARTITION_MODE, \
976 2 = AMDGPU_TPX_PARTITION_MODE, \
977 3 = AMDGPU_QPX_PARTITION_MODE, \
978 4 = AMDGPU_CPX_PARTITION_MODE)");
979module_param_named(user_partt_mode, amdgpu_user_partt_mode, uint, 0444);
980
80e709ee
CL		 981
982/**
983 * DOC: enforce_isolation (bool)
984 * enforce process isolation between graphics and compute via using the same reserved vmid.
985 */
986module_param(enforce_isolation, bool, 0444);
987MODULE_PARM_DESC(enforce_isolation, "enforce process isolation between graphics and compute . enforce_isolation = on");
988
5dc270d3
ML		 989/**
990 * DOC: seamless (int)
991 * Seamless boot will keep the image on the screen during the boot process.
992 */
993MODULE_PARM_DESC(seamless, "Seamless boot (-1 = auto (default), 0 = disable, 1 = enable)");
994module_param_named(seamless, amdgpu_seamless, int, 0444);
995
887db1e4
AA		 996/**
997 * DOC: debug_mask (uint)
998 * Debug options for amdgpu, work as a binary mask with the following options:
999 *
1000 * - 0x1: Debug VM handling
1001 * - 0x2: Enable simulating large-bar capability on non-large bar system. This
1002 * limits the VRAM size reported to ROCm applications to the visible
1003 * size, usually 256MB.
ffde7210 1004 * - 0x4: Disable GPU soft recovery, always do a full reset
887db1e4
AA		 1005 */
1006MODULE_PARM_DESC(debug_mask, "debug options for amdgpu, disabled by default");
1007module_param_named(debug_mask, amdgpu_debug_mask, uint, 0444);
1008
6ba5b613
AD		 1009/**
1010 * DOC: agp (int)
1011 * Enable the AGP aperture. This provides an aperture in the GPU's internal
1012 * address space for direct access to system memory. Note that these accesses
1013 * are non-snooped, so they are only used for access to uncached memory.
1014 */
1015MODULE_PARM_DESC(agp, "AGP (-1 = auto (default), 0 = disable, 1 = enable)");
1016module_param_named(agp, amdgpu_agp, int, 0444);
1017
b8b39de6
EQ		 1018/**
1019 * DOC: wbrf (int)
1020 * Enable Wifi RFI interference mitigation feature.
1021 * Due to electrical and mechanical constraints there may be likely interference of
1022 * relatively high-powered harmonics of the (G-)DDR memory clocks with local radio
1023 * module frequency bands used by Wifi 6/6e/7. To mitigate the possible RFI interference,
1024 * with this feature enabled, PMFW will use either “shadowed P-State” or “P-State” based
1025 * on active list of frequencies in-use (to be avoided) as part of initial setting or
1026 * P-state transition. However, there may be potential performance impact with this
1027 * feature enabled.
1028 * (0 = disabled, 1 = enabled, -1 = auto (default setting, will be enabled if supported))
1029 */
1030MODULE_PARM_DESC(wbrf,
1031 "Enable Wifi RFI interference mitigation (0 = disabled, 1 = enabled, -1 = auto(default)");
1032module_param_named(wbrf, amdgpu_wbrf, int, 0444);
1033
bdbeb0dd
AD		 1034/* These devices are not supported by amdgpu.
1035 * They are supported by the mach64, r128, radeon drivers
1036 */
1037static const u16 amdgpu_unsupported_pciidlist[] = {
1038 /* mach64 */
1039 0x4354,
1040 0x4358,
1041 0x4554,
1042 0x4742,
1043 0x4744,
1044 0x4749,
1045 0x474C,
1046 0x474D,
1047 0x474E,
1048 0x474F,
1049 0x4750,
1050 0x4751,
1051 0x4752,
1052 0x4753,
1053 0x4754,
1054 0x4755,
1055 0x4756,
1056 0x4757,
1057 0x4758,
1058 0x4759,
1059 0x475A,
1060 0x4C42,
1061 0x4C44,
1062 0x4C47,
1063 0x4C49,
1064 0x4C4D,
1065 0x4C4E,
1066 0x4C50,
1067 0x4C51,
1068 0x4C52,
1069 0x4C53,
1070 0x5654,
1071 0x5655,
1072 0x5656,
1073 /* r128 */
1074 0x4c45,
1075 0x4c46,
1076 0x4d46,
1077 0x4d4c,
1078 0x5041,
1079 0x5042,
1080 0x5043,
1081 0x5044,
1082 0x5045,
1083 0x5046,
1084 0x5047,
1085 0x5048,
1086 0x5049,
1087 0x504A,
1088 0x504B,
1089 0x504C,
1090 0x504D,
1091 0x504E,
1092 0x504F,
1093 0x5050,
1094 0x5051,
1095 0x5052,
1096 0x5053,
1097 0x5054,
1098 0x5055,
1099 0x5056,
1100 0x5057,
1101 0x5058,
1102 0x5245,
1103 0x5246,
1104 0x5247,
1105 0x524b,
1106 0x524c,
1107 0x534d,
1108 0x5446,
1109 0x544C,
1110 0x5452,
1111 /* radeon */
1112 0x3150,
1113 0x3151,
1114 0x3152,
1115 0x3154,
1116 0x3155,
1117 0x3E50,
1118 0x3E54,
1119 0x4136,
1120 0x4137,
1121 0x4144,
1122 0x4145,
1123 0x4146,
1124 0x4147,
1125 0x4148,
1126 0x4149,
1127 0x414A,
1128 0x414B,
1129 0x4150,
1130 0x4151,
1131 0x4152,
1132 0x4153,
1133 0x4154,
1134 0x4155,
1135 0x4156,
1136 0x4237,
1137 0x4242,
1138 0x4336,
1139 0x4337,
1140 0x4437,
1141 0x4966,
1142 0x4967,
1143 0x4A48,
1144 0x4A49,
1145 0x4A4A,
1146 0x4A4B,
1147 0x4A4C,
1148 0x4A4D,
1149 0x4A4E,
1150 0x4A4F,
1151 0x4A50,
1152 0x4A54,
1153 0x4B48,
1154 0x4B49,
1155 0x4B4A,
1156 0x4B4B,
1157 0x4B4C,
1158 0x4C57,
1159 0x4C58,
1160 0x4C59,
1161 0x4C5A,
1162 0x4C64,
1163 0x4C66,
1164 0x4C67,
1165 0x4E44,
1166 0x4E45,
1167 0x4E46,
1168 0x4E47,
1169 0x4E48,
1170 0x4E49,
1171 0x4E4A,
1172 0x4E4B,
1173 0x4E50,
1174 0x4E51,
1175 0x4E52,
1176 0x4E53,
1177 0x4E54,
1178 0x4E56,
1179 0x5144,
1180 0x5145,
1181 0x5146,
1182 0x5147,
1183 0x5148,
1184 0x514C,
1185 0x514D,
1186 0x5157,
1187 0x5158,
1188 0x5159,
1189 0x515A,
1190 0x515E,
1191 0x5460,
1192 0x5462,
1193 0x5464,
1194 0x5548,
1195 0x5549,
1196 0x554A,
1197 0x554B,
1198 0x554C,
1199 0x554D,
1200 0x554E,
1201 0x554F,
1202 0x5550,
1203 0x5551,
1204 0x5552,
1205 0x5554,
1206 0x564A,
1207 0x564B,
1208 0x564F,
1209 0x5652,
1210 0x5653,
1211 0x5657,
1212 0x5834,
1213 0x5835,
1214 0x5954,
1215 0x5955,
1216 0x5974,
1217 0x5975,
1218 0x5960,
1219 0x5961,
1220 0x5962,
1221 0x5964,
1222 0x5965,
1223 0x5969,
1224 0x5a41,
1225 0x5a42,
1226 0x5a61,
1227 0x5a62,
1228 0x5b60,
1229 0x5b62,
1230 0x5b63,
1231 0x5b64,
1232 0x5b65,
1233 0x5c61,
1234 0x5c63,
1235 0x5d48,
1236 0x5d49,
1237 0x5d4a,
1238 0x5d4c,
1239 0x5d4d,
1240 0x5d4e,
1241 0x5d4f,
1242 0x5d50,
1243 0x5d52,
1244 0x5d57,
1245 0x5e48,
1246 0x5e4a,
1247 0x5e4b,
1248 0x5e4c,
1249 0x5e4d,
1250 0x5e4f,
1251 0x6700,
1252 0x6701,
1253 0x6702,
1254 0x6703,
1255 0x6704,
1256 0x6705,
1257 0x6706,
1258 0x6707,
1259 0x6708,
1260 0x6709,
1261 0x6718,
1262 0x6719,
1263 0x671c,
1264 0x671d,
1265 0x671f,
1266 0x6720,
1267 0x6721,
1268 0x6722,
1269 0x6723,
1270 0x6724,
1271 0x6725,
1272 0x6726,
1273 0x6727,
1274 0x6728,
1275 0x6729,
1276 0x6738,
1277 0x6739,
1278 0x673e,
1279 0x6740,
1280 0x6741,
1281 0x6742,
1282 0x6743,
1283 0x6744,
1284 0x6745,
1285 0x6746,
1286 0x6747,
1287 0x6748,
1288 0x6749,
1289 0x674A,
1290 0x6750,
1291 0x6751,
1292 0x6758,
1293 0x6759,
1294 0x675B,
1295 0x675D,
1296 0x675F,
1297 0x6760,
1298 0x6761,
1299 0x6762,
1300 0x6763,
1301 0x6764,
1302 0x6765,
1303 0x6766,
1304 0x6767,
1305 0x6768,
1306 0x6770,
1307 0x6771,
1308 0x6772,
1309 0x6778,
1310 0x6779,
1311 0x677B,
1312 0x6840,
1313 0x6841,
1314 0x6842,
1315 0x6843,
1316 0x6849,
1317 0x684C,
1318 0x6850,
1319 0x6858,
1320 0x6859,
1321 0x6880,
1322 0x6888,
1323 0x6889,
1324 0x688A,
1325 0x688C,
1326 0x688D,
1327 0x6898,
1328 0x6899,
1329 0x689b,
1330 0x689c,
1331 0x689d,
1332 0x689e,
1333 0x68a0,
1334 0x68a1,
1335 0x68a8,
1336 0x68a9,
1337 0x68b0,
1338 0x68b8,
1339 0x68b9,
1340 0x68ba,
1341 0x68be,
1342 0x68bf,
1343 0x68c0,
1344 0x68c1,
1345 0x68c7,
1346 0x68c8,
1347 0x68c9,
1348 0x68d8,
1349 0x68d9,
1350 0x68da,
1351 0x68de,
1352 0x68e0,
1353 0x68e1,
1354 0x68e4,
1355 0x68e5,
1356 0x68e8,
1357 0x68e9,
1358 0x68f1,
1359 0x68f2,
1360 0x68f8,
1361 0x68f9,
1362 0x68fa,
1363 0x68fe,
1364 0x7100,
1365 0x7101,
1366 0x7102,
1367 0x7103,
1368 0x7104,
1369 0x7105,
1370 0x7106,
1371 0x7108,
1372 0x7109,
1373 0x710A,
1374 0x710B,
1375 0x710C,
1376 0x710E,
1377 0x710F,
1378 0x7140,
1379 0x7141,
1380 0x7142,
1381 0x7143,
1382 0x7144,
1383 0x7145,
1384 0x7146,
1385 0x7147,
1386 0x7149,
1387 0x714A,
1388 0x714B,
1389 0x714C,
1390 0x714D,
1391 0x714E,
1392 0x714F,
1393 0x7151,
1394 0x7152,
1395 0x7153,
1396 0x715E,
1397 0x715F,
1398 0x7180,
1399 0x7181,
1400 0x7183,
1401 0x7186,
1402 0x7187,
1403 0x7188,
1404 0x718A,
1405 0x718B,
1406 0x718C,
1407 0x718D,
1408 0x718F,
1409 0x7193,
1410 0x7196,
1411 0x719B,
1412 0x719F,
1413 0x71C0,
1414 0x71C1,
1415 0x71C2,
1416 0x71C3,
1417 0x71C4,
1418 0x71C5,
1419 0x71C6,
1420 0x71C7,
1421 0x71CD,
1422 0x71CE,
1423 0x71D2,
1424 0x71D4,
1425 0x71D5,
1426 0x71D6,
1427 0x71DA,
1428 0x71DE,
1429 0x7200,
1430 0x7210,
1431 0x7211,
1432 0x7240,
1433 0x7243,
1434 0x7244,
1435 0x7245,
1436 0x7246,
1437 0x7247,
1438 0x7248,
1439 0x7249,
1440 0x724A,
1441 0x724B,
1442 0x724C,
1443 0x724D,
1444 0x724E,
1445 0x724F,
1446 0x7280,
1447 0x7281,
1448 0x7283,
1449 0x7284,
1450 0x7287,
1451 0x7288,
1452 0x7289,
1453 0x728B,
1454 0x728C,
1455 0x7290,
1456 0x7291,
1457 0x7293,
1458 0x7297,
1459 0x7834,
1460 0x7835,
1461 0x791e,
1462 0x791f,
1463 0x793f,
1464 0x7941,
1465 0x7942,
1466 0x796c,
1467 0x796d,
1468 0x796e,
1469 0x796f,
1470 0x9400,
1471 0x9401,
1472 0x9402,
1473 0x9403,
1474 0x9405,
1475 0x940A,
1476 0x940B,
1477 0x940F,
1478 0x94A0,
1479 0x94A1,
1480 0x94A3,
1481 0x94B1,
1482 0x94B3,
1483 0x94B4,
1484 0x94B5,
1485 0x94B9,
1486 0x9440,
1487 0x9441,
1488 0x9442,
1489 0x9443,
1490 0x9444,
1491 0x9446,
1492 0x944A,
1493 0x944B,
1494 0x944C,
1495 0x944E,
1496 0x9450,
1497 0x9452,
1498 0x9456,
1499 0x945A,
1500 0x945B,
1501 0x945E,
1502 0x9460,
1503 0x9462,
1504 0x946A,
1505 0x946B,
1506 0x947A,
1507 0x947B,
1508 0x9480,
1509 0x9487,
1510 0x9488,
1511 0x9489,
1512 0x948A,
1513 0x948F,
1514 0x9490,
1515 0x9491,
1516 0x9495,
1517 0x9498,
1518 0x949C,
1519 0x949E,
1520 0x949F,
1521 0x94C0,
1522 0x94C1,
1523 0x94C3,
1524 0x94C4,
1525 0x94C5,
1526 0x94C6,
1527 0x94C7,
1528 0x94C8,
1529 0x94C9,
1530 0x94CB,
1531 0x94CC,
1532 0x94CD,
1533 0x9500,
1534 0x9501,
1535 0x9504,
1536 0x9505,
1537 0x9506,
1538 0x9507,
1539 0x9508,
1540 0x9509,
1541 0x950F,
1542 0x9511,
1543 0x9515,
1544 0x9517,
1545 0x9519,
1546 0x9540,
1547 0x9541,
1548 0x9542,
1549 0x954E,
1550 0x954F,
1551 0x9552,
1552 0x9553,
1553 0x9555,
1554 0x9557,
1555 0x955f,
1556 0x9580,
1557 0x9581,
1558 0x9583,
1559 0x9586,
1560 0x9587,
1561 0x9588,
1562 0x9589,
1563 0x958A,
1564 0x958B,
1565 0x958C,
1566 0x958D,
1567 0x958E,
1568 0x958F,
1569 0x9590,
1570 0x9591,
1571 0x9593,
1572 0x9595,
1573 0x9596,
1574 0x9597,
1575 0x9598,
1576 0x9599,
1577 0x959B,
1578 0x95C0,
1579 0x95C2,
1580 0x95C4,
1581 0x95C5,
1582 0x95C6,
1583 0x95C7,
1584 0x95C9,
1585 0x95CC,
1586 0x95CD,
1587 0x95CE,
1588 0x95CF,
1589 0x9610,
1590 0x9611,
1591 0x9612,
1592 0x9613,
1593 0x9614,
1594 0x9615,
1595 0x9616,
1596 0x9640,
1597 0x9641,
1598 0x9642,
1599 0x9643,
1600 0x9644,
1601 0x9645,
1602 0x9647,
1603 0x9648,
1604 0x9649,
1605 0x964a,
1606 0x964b,
1607 0x964c,
1608 0x964e,
1609 0x964f,
1610 0x9710,
1611 0x9711,
1612 0x9712,
1613 0x9713,
1614 0x9714,
1615 0x9715,
1616 0x9802,
1617 0x9803,
1618 0x9804,
1619 0x9805,
1620 0x9806,
1621 0x9807,
1622 0x9808,
1623 0x9809,
1624 0x980A,
1625 0x9900,
1626 0x9901,
1627 0x9903,
1628 0x9904,
1629 0x9905,
1630 0x9906,
1631 0x9907,
1632 0x9908,
1633 0x9909,
1634 0x990A,
1635 0x990B,
1636 0x990C,
1637 0x990D,
1638 0x990E,
1639 0x990F,
1640 0x9910,
1641 0x9913,
1642 0x9917,
1643 0x9918,
1644 0x9919,
1645 0x9990,
1646 0x9991,
1647 0x9992,
1648 0x9993,
1649 0x9994,
1650 0x9995,
1651 0x9996,
1652 0x9997,
1653 0x9998,
1654 0x9999,
1655 0x999A,
1656 0x999B,
1657 0x999C,
1658 0x999D,
1659 0x99A0,
1660 0x99A2,
1661 0x99A4,
9e5a14bc
AD		 1662 /* radeon secondary ids */
1663 0x3171,
1664 0x3e70,
1665 0x4164,
1666 0x4165,
1667 0x4166,
1668 0x4168,
1669 0x4170,
1670 0x4171,
1671 0x4172,
1672 0x4173,
1673 0x496e,
1674 0x4a69,
1675 0x4a6a,
1676 0x4a6b,
1677 0x4a70,
1678 0x4a74,
1679 0x4b69,
1680 0x4b6b,
1681 0x4b6c,
1682 0x4c6e,
1683 0x4e64,
1684 0x4e65,
1685 0x4e66,
1686 0x4e67,
1687 0x4e68,
1688 0x4e69,
1689 0x4e6a,
1690 0x4e71,
1691 0x4f73,
1692 0x5569,
1693 0x556b,
1694 0x556d,
1695 0x556f,
1696 0x5571,
1697 0x5854,
1698 0x5874,
1699 0x5940,
1700 0x5941,
c1ac2ea8 1701 0x5b70,
9e5a14bc
AD		 1702 0x5b72,
1703 0x5b73,
1704 0x5b74,
1705 0x5b75,
1706 0x5d44,
1707 0x5d45,
1708 0x5d6d,
1709 0x5d6f,
1710 0x5d72,
1711 0x5d77,
1712 0x5e6b,
1713 0x5e6d,
1714 0x7120,
1715 0x7124,
1716 0x7129,
1717 0x712e,
1718 0x712f,
1719 0x7162,
1720 0x7163,
1721 0x7166,
1722 0x7167,
1723 0x7172,
1724 0x7173,
1725 0x71a0,
1726 0x71a1,
1727 0x71a3,
1728 0x71a7,
1729 0x71bb,
1730 0x71e0,
1731 0x71e1,
1732 0x71e2,
1733 0x71e6,
1734 0x71e7,
1735 0x71f2,
1736 0x7269,
1737 0x726b,
1738 0x726e,
1739 0x72a0,
1740 0x72a8,
1741 0x72b1,
1742 0x72b3,
1743 0x793f,
bdbeb0dd
AD		 1744};
1745
f498d9ed 1746static const struct pci_device_id pciidlist[] = {
47fc644f 1747#ifdef CONFIG_DRM_AMDGPU_SI
78fbb685
KW		 1748 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1749 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1750 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1751 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1752 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1753 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1754 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1755 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1756 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1757 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1758 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1759 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1760 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
1761 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1762 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1763 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
1764 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1765 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1766 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1767 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1768 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1769 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1770 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1771 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1772 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
1773 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1774 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1775 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1776 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1777 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1778 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1779 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1780 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1781 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1782 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1783 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1784 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1785 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1786 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1787 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1788 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
1789 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
1790 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1791 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1792 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1793 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1794 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1795 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1796 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1797 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1798 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1799 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1800 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1801 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1802 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1803 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1804 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1805 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1806 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
1807 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1808 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1809 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1810 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1811 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1812 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1813 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
1814 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1815 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1816 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1817 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1818 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1819 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
1820#endif
89330c39
AD		 1821#ifdef CONFIG_DRM_AMDGPU_CIK
1822 /* Kaveri */
2f7d10b3
JZ		 1823 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1824 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1825 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1826 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1827 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1828 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1829 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1830 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1831 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1832 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1833 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1834 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1835 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1836 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1837 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1838 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1839 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1840 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1841 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
1842 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1843 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
1844 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
89330c39 1845 /* Bonaire */
2f7d10b3
JZ		 1846 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1847 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1848 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
1849 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
89330c39
AD		 1850 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1851 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1852 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1853 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1854 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1855 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
fb4f1737 1856 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
89330c39
AD		 1857 /* Hawaii */
1858 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1859 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1860 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1861 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1862 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1863 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1864 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1865 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1866 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1867 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1868 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1869 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1870 /* Kabini */
2f7d10b3
JZ		 1871 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1872 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1873 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1874 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1875 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1876 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1877 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1878 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1879 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1880 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1881 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1882 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1883 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1884 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1885 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1886 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
89330c39 1887 /* mullins */
2f7d10b3
JZ		 1888 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1889 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1890 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1891 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1892 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1893 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1894 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1895 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1896 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1897 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1898 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1899 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1900 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1901 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1902 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1903 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
89330c39 1904#endif
1256a8b8 1905 /* topaz */
dba280b2
AD		 1906 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1907 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1908 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1909 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1910 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1256a8b8
AD		 1911 /* tonga */
1912 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1913 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1914 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1915 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1916 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1917 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1f8d9625 1918 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1256a8b8
AD		 1919 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1920 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
2da78e21
DZ		 1921 /* fiji */
1922 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
e1d99217 1923 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1256a8b8 1924 /* carrizo */
2f7d10b3
JZ		 1925 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1926 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1927 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1928 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1929 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
81b1509a
SL		 1930 /* stoney */
1931 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
2cc0c0b5
FC		 1932 /* Polaris11 */
1933 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1934 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1935 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1936 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80 1937 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5 1938 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
35621b80
FC		 1939 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1940 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1941 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
2cc0c0b5
FC		 1942 /* Polaris10 */
1943 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1944 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1945 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1946 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1947 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
7dae6181 1948 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
2cc0c0b5 1949 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1dcf4801
FC		 1950 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1951 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1952 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1953 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1954 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
30f3984e 1955 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
fc8e9c54
JZ		 1956 /* Polaris12 */
1957 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1958 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1959 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1960 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1961 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
cf8c73af 1962 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
6e88491c 1963 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
fc8e9c54 1964 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
e9307932
LL		 1965 /* VEGAM */
1966 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1967 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
f6653a0e 1968 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
ca2f1cca 1969 /* Vega 10 */
dfbf0c14
AD		 1970 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1971 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1972 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1973 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1974 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1975 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1976 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1977 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1978 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1979 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1980 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
2244b588
AD		 1981 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1982 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1983 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dfbf0c14 1984 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
dc53d543
AD		 1985 /* Vega 12 */
1986 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1987 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1988 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1989 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1990 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1204a26e 1991 /* Vega 20 */
6dddaeef
AD		 1992 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1993 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1994 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1995 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
ec5b2020 1996 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
6dddaeef
AD		 1997 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1998 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
df515052 1999 /* Raven */
acc34503 2000 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
741deade 2001 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
48c69cda 2002 /* Arcturus */
12c5365e
AD		 2003 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2004 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2005 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
2006 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
bd1c0fdf
AD		 2007 /* Navi10 */
2008 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2009 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
2010 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 2011 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 2012 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
4f56d9d4 2013 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
89428811 2014 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
bd1c0fdf 2015 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
26051720 2016 /* Navi14 */
b62d9554
AD		 2017 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2018 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2019 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
2020 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
df515052 2021
61bdb39c 2022 /* Renoir */
775da830 2023 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
23fe1390 2024 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
8bf08351 2025 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
278cdb68 2026 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
61bdb39c 2027
10e85054 2028 /* Navi12 */
d34c7b7b
AD		 2029 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
2030 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
10e85054 2031
61278d14
LG		 2032 /* Sienna_Cichlid */
2033 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
d26bbbcc 2034 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14
LG		 2035 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2036 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 2037 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2038 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2039 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 2040 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
8f0c93f4
AD		 2041 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
2042 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 2043 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
ed098aa3 2044 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
61278d14 2045 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
10e85054 2046
27f5355f
AL		 2047 /* Yellow Carp */
2048 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2049 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
2050
2c1eaddd
TZ		 2051 /* Navy_Flounder */
2052 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2053 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2054 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
8f0c93f4
AD		 2055 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2056 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2057 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2058 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2059 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2c1eaddd
TZ		 2060 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
2061
e7de4aee
TZ		 2062 /* DIMGREY_CAVEFISH */
2063 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2064 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2065 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
06ac9b6c 2066 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
8f0c93f4
AD		 2067 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2068 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2069 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2070 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2071 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2072 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2073 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
e7de4aee
TZ		 2074 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
2075
4c2e5f51 2076 /* Aldebaran */
3786a9bc
AD		 2077 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2078 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2079 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
2080 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN},
4c2e5f51 2081
a8f70696
TZ		 2082 /* CYAN_SKILLFISH */
2083 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
dfcc3e8c 2084 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
a8f70696 2085
a2e9b166
CG		 2086 /* BEIGE_GOBY */
2087 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2088 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2089 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2090 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
62e9bd20 2091 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
a2e9b166
CG		 2092 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
2093
eb4fd29a
AD		 2094 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2095 .class = PCI_CLASS_DISPLAY_VGA << 8,
2096 .class_mask = 0xffffff,
d0761fd2 2097 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a
AD		 2098
2099 { PCI_DEVICE(0x1002, PCI_ANY_ID),
2100 .class = PCI_CLASS_DISPLAY_OTHER << 8,
2101 .class_mask = 0xffffff,
d0761fd2 2102 .driver_data = CHIP_IP_DISCOVERY },
eb4fd29a 2103
5d6cd200 2104 { PCI_DEVICE(0x1002, PCI_ANY_ID),
9d65b1b4 2105 .class = PCI_CLASS_ACCELERATOR_PROCESSING << 8,
5d6cd200
SZ		 2106 .class_mask = 0xffffff,
2107 .driver_data = CHIP_IP_DISCOVERY },
2108
d38ceaf9
AD		 2109 {0, 0, 0}
2110};
2111
2112MODULE_DEVICE_TABLE(pci, pciidlist);
2113
dbab6356
MJ		 2114static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
2115 /* differentiate between P10 and P11 asics with the same DID */
2116 {0x67FF, 0xE3, CHIP_POLARIS10},
2117 {0x67FF, 0xE7, CHIP_POLARIS10},
2118 {0x67FF, 0xF3, CHIP_POLARIS10},
2119 {0x67FF, 0xF7, CHIP_POLARIS10},
2120};
2121
5088d657 2122static const struct drm_driver amdgpu_kms_driver;
d38ceaf9 2123
243c719e 2124static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev)
d0d66b8c
AD		 2125{
2126 struct pci_dev *p = NULL;
243c719e 2127 int i;
d0d66b8c 2128
243c719e
AD		 2129 /* 0 - GPU
2130 * 1 - audio
2131 * 2 - USB
2132 * 3 - UCSI
2133 */
2134 for (i = 1; i < 4; i++) {
2135 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
2136 adev->pdev->bus->number, i);
2137 if (p) {
2138 pm_runtime_get_sync(&p->dev);
2139 pm_runtime_mark_last_busy(&p->dev);
2140 pm_runtime_put_autosuspend(&p->dev);
2141 pci_dev_put(p);
2142 }
d0d66b8c
AD		 2143 }
2144}
2145
887db1e4
AA		 2146static void amdgpu_init_debug_options(struct amdgpu_device *adev)
2147{
2148 if (amdgpu_debug_mask & AMDGPU_DEBUG_VM) {
2149 pr_info("debug: VM handling debug enabled\n");
2150 adev->debug_vm = true;
2151 }
2152
2153 if (amdgpu_debug_mask & AMDGPU_DEBUG_LARGEBAR) {
2154 pr_info("debug: enabled simulating large-bar capability on non-large bar system\n");
2155 adev->debug_largebar = true;
2156 }
ffde7210
AA		 2157
2158 if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY) {
2159 pr_info("debug: soft reset for GPU recovery disabled\n");
2160 adev->debug_disable_soft_recovery = true;
2161 }
d20e1aec
LM		 2162
2163 if (amdgpu_debug_mask & AMDGPU_DEBUG_USE_VRAM_FW_BUF) {
2164 pr_info("debug: place fw in vram for frontdoor loading\n");
2165 adev->debug_use_vram_fw_buf = true;
2166 }
887db1e4
AA		 2167}
2168
dbab6356
MJ		 2169static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags)
2170{
2171 int i;
2172
2173 for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
2174 if (pdev->device == asic_type_quirks[i].device &&
2175 pdev->revision == asic_type_quirks[i].revision) {
2176 flags &= ~AMD_ASIC_MASK;
2177 flags |= asic_type_quirks[i].type;
2178 break;
2179 }
2180 }
2181
2182 return flags;
2183}
2184
d38ceaf9
AD		 2185static int amdgpu_pci_probe(struct pci_dev *pdev,
2186 const struct pci_device_id *ent)
2187{
8aba21b7 2188 struct drm_device *ddev;
c6385e50 2189 struct amdgpu_device *adev;
d38ceaf9 2190 unsigned long flags = ent->driver_data;
bdbeb0dd 2191 int ret, retry = 0, i;
3fa203af
AD		 2192 bool supports_atomic = false;
2193
bdbeb0dd
AD		 2194 /* skip devices which are owned by radeon */
2195 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) {
2196 if (amdgpu_unsupported_pciidlist[i] == pdev->device)
2197 return -ENODEV;
2198 }
2199
7294863a
ML		 2200 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev))
2201 amdgpu_aspm = 0;
2202
84ec374b 2203 if (amdgpu_virtual_display ||
3fa203af
AD		 2204 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
2205 supports_atomic = true;
d38ceaf9 2206
2f7d10b3 2207 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
d38ceaf9
AD		 2208 DRM_INFO("This hardware requires experimental hardware support.\n"
2209 "See modparam exp_hw_support\n");
2210 return -ENODEV;
2211 }
dbab6356
MJ		 2212
2213 flags = amdgpu_fix_asic_type(pdev, flags);
d38ceaf9 2214
ea68573d
AD		 2215 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping,
2216 * however, SME requires an indirect IOMMU mapping because the encryption
2217 * bit is beyond the DMA mask of the chip.
2218 */
e9d1d2bb
TL		 2219 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
2220 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
ea68573d
AD		 2221 dev_info(&pdev->dev,
2222 "SME is not compatible with RAVEN\n");
2223 return -ENOTSUPP;
2224 }
2225
984d7a92
HG		 2226#ifdef CONFIG_DRM_AMDGPU_SI
2227 if (!amdgpu_si_support) {
2228 switch (flags & AMD_ASIC_MASK) {
2229 case CHIP_TAHITI:
2230 case CHIP_PITCAIRN:
2231 case CHIP_VERDE:
2232 case CHIP_OLAND:
2233 case CHIP_HAINAN:
2234 dev_info(&pdev->dev,
2235 "SI support provided by radeon.\n");
2236 dev_info(&pdev->dev,
2237 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
2238 );
2239 return -ENODEV;
2240 }
2241 }
2242#endif
2243#ifdef CONFIG_DRM_AMDGPU_CIK
2244 if (!amdgpu_cik_support) {
2245 switch (flags & AMD_ASIC_MASK) {
2246 case CHIP_KAVERI:
2247 case CHIP_BONAIRE:
2248 case CHIP_HAWAII:
2249 case CHIP_KABINI:
2250 case CHIP_MULLINS:
2251 dev_info(&pdev->dev,
2252 "CIK support provided by radeon.\n");
2253 dev_info(&pdev->dev,
2254 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
2255 );
2256 return -ENODEV;
2257 }
2258 }
2259#endif
2260
5088d657 2261 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
df2ce459
LT		 2262 if (IS_ERR(adev))
2263 return PTR_ERR(adev);
8aba21b7
LT		 2264
2265 adev->dev = &pdev->dev;
2266 adev->pdev = pdev;
2267 ddev = adev_to_drm(adev);
b58c1131 2268
351c4dbe 2269 if (!supports_atomic)
8aba21b7 2270 ddev->driver_features &= ~DRIVER_ATOMIC;
351c4dbe 2271
b58c1131
AD		 2272 ret = pci_enable_device(pdev);
2273 if (ret)
df2ce459 2274 return ret;
b58c1131 2275
8aba21b7 2276 pci_set_drvdata(pdev, ddev);
b58c1131 2277
51258acd
LM		 2278 amdgpu_init_debug_options(adev);
2279
1d4624cd 2280 ret = amdgpu_driver_load_kms(adev, flags);
7504d3bb
LC		 2281 if (ret)
2282 goto err_pci;
c6385e50 2283
1daee8b4 2284retry_init:
1d4624cd 2285 ret = drm_dev_register(ddev, flags);
1daee8b4
PD		 2286 if (ret == -EAGAIN && ++retry <= 3) {
2287 DRM_INFO("retry init %d\n", retry);
2288 /* Don't request EX mode too frequently which is attacking */
2289 msleep(5000);
2290 goto retry_init;
8aba21b7 2291 } else if (ret) {
b58c1131 2292 goto err_pci;
8aba21b7 2293 }
b58c1131 2294
2c1c7ba4
JZ		 2295 ret = amdgpu_xcp_dev_register(adev, ent);
2296 if (ret)
2297 goto err_pci;
2298
c0125b84
LM		 2299 ret = amdgpu_amdkfd_drm_client_create(adev);
2300 if (ret)
2301 goto err_pci;
2302
087451f3
EQ		 2303 /*
2304 * 1. don't init fbdev on hw without DCE
2305 * 2. don't init fbdev if there are no connectors
2306 */
2307 if (adev->mode_info.mode_config_initialized &&
2308 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) {
2309 /* select 8 bpp console on low vram cards */
2310 if (adev->gmc.real_vram_size <= (32*1024*1024))
2311 drm_fbdev_generic_setup(adev_to_drm(adev), 8);
2312 else
2313 drm_fbdev_generic_setup(adev_to_drm(adev), 32);
2314 }
2315
c6385e50
AD		 2316 ret = amdgpu_debugfs_init(adev);
2317 if (ret)
2318 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
2319
9c913f38 2320 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2321 /* only need to skip on ATPX */
2322 if (amdgpu_device_supports_px(ddev))
2323 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
2324 /* we want direct complete for BOCO */
2325 if (amdgpu_device_supports_boco(ddev))
2326 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE |
2327 DPM_FLAG_SMART_SUSPEND |
2328 DPM_FLAG_MAY_SKIP_RESUME);
2329 pm_runtime_use_autosuspend(ddev->dev);
2330 pm_runtime_set_autosuspend_delay(ddev->dev, 5000);
2331
2332 pm_runtime_allow(ddev->dev);
2333
2334 pm_runtime_mark_last_busy(ddev->dev);
2335 pm_runtime_put_autosuspend(ddev->dev);
2336
bd1f6a31
ML		 2337 pci_wake_from_d3(pdev, TRUE);
2338
d0d66b8c
AD		 2339 /*
2340 * For runpm implemented via BACO, PMFW will handle the
2341 * timing for BACO in and out:
2342 * - put ASIC into BACO state only when both video and
2343 * audio functions are in D3 state.
2344 * - pull ASIC out of BACO state when either video or
2345 * audio function is in D0 state.
2346 * Also, at startup, PMFW assumes both functions are in
2347 * D0 state.
2348 *
2349 * So if snd driver was loaded prior to amdgpu driver
2350 * and audio function was put into D3 state, there will
2351 * be no PMFW-aware D-state transition(D0->D3) on runpm
2352 * suspend. Thus the BACO will be not correctly kicked in.
2353 *
243c719e 2354 * Via amdgpu_get_secondary_funcs(), the audio dev is put
d0d66b8c
AD		 2355 * into D0 state. Then there will be a PMFW-aware D-state
2356 * transition(D0->D3) on runpm suspend.
2357 */
2358 if (amdgpu_device_supports_baco(ddev) &&
2359 !(adev->flags & AMD_IS_APU) &&
2360 (adev->asic_type >= CHIP_NAVI10))
243c719e 2361 amdgpu_get_secondary_funcs(adev);
d0d66b8c
AD		 2362 }
2363
b58c1131
AD		 2364 return 0;
2365
2366err_pci:
2367 pci_disable_device(pdev);
b58c1131 2368 return ret;
d38ceaf9
AD		 2369}
2370
2371static void
2372amdgpu_pci_remove(struct pci_dev *pdev)
2373{
2374 struct drm_device *dev = pci_get_drvdata(pdev);
d0d66b8c 2375 struct amdgpu_device *adev = drm_to_adev(dev);
d38ceaf9 2376
2c1c7ba4 2377 amdgpu_xcp_dev_unplug(adev);
39934d3e
VP		 2378 drm_dev_unplug(dev);
2379
9c913f38 2380 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) {
d0d66b8c
AD		 2381 pm_runtime_get_sync(dev->dev);
2382 pm_runtime_forbid(dev->dev);
2383 }
2384
c6385e50 2385 amdgpu_driver_unload_kms(dev);
72c8c97b 2386
98c6e6a7
AG		 2387 /*
2388 * Flush any in flight DMA operations from device.
2389 * Clear the Bus Master Enable bit and then wait on the PCIe Device
2390 * StatusTransactions Pending bit.
2391 */
fd4495e5 2392 pci_disable_device(pdev);
98c6e6a7 2393 pci_wait_for_pending_transaction(pdev);
d38ceaf9
AD		 2394}
2395
61e11306
AD		 2396static void
2397amdgpu_pci_shutdown(struct pci_dev *pdev)
2398{
faefba95 2399 struct drm_device *dev = pci_get_drvdata(pdev);
1348969a 2400 struct amdgpu_device *adev = drm_to_adev(dev);
faefba95 2401
7c6e68c7
AG		 2402 if (amdgpu_ras_intr_triggered())
2403 return;
2404
61e11306 2405 /* if we are running in a VM, make sure the device
00ea8cba
AD		 2406 * torn down properly on reboot/shutdown.
2407 * unfortunately we can't detect certain
2408 * hypervisors so just do this all the time.
61e11306 2409 */
05cac1ae
ND		 2410 if (!amdgpu_passthrough(adev))
2411 adev->mp1_state = PP_MP1_STATE_UNLOAD;
cdd61df6 2412 amdgpu_device_ip_suspend(adev);
a3a09142 2413 adev->mp1_state = PP_MP1_STATE_NONE;
61e11306
AD		 2414}
2415
e3c1b071 2416/**
2417 * amdgpu_drv_delayed_reset_work_handler - work handler for reset
2418 *
2419 * @work: work_struct.
2420 */
2421static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
2422{
2423 struct list_head device_list;
2424 struct amdgpu_device *adev;
2425 int i, r;
04442bf7
LL		 2426 struct amdgpu_reset_context reset_context;
2427
2428 memset(&reset_context, 0, sizeof(reset_context));
e3c1b071 2429
2430 mutex_lock(&mgpu_info.mutex);
2431 if (mgpu_info.pending_reset == true) {
2432 mutex_unlock(&mgpu_info.mutex);
2433 return;
2434 }
2435 mgpu_info.pending_reset = true;
2436 mutex_unlock(&mgpu_info.mutex);
2437
04442bf7
LL		 2438 /* Use a common context, just need to make sure full reset is done */
2439 reset_context.method = AMD_RESET_METHOD_NONE;
2440 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
2441
e3c1b071 2442 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2443 adev = mgpu_info.gpu_ins[i].adev;
04442bf7
LL		 2444 reset_context.reset_req_dev = adev;
2445 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
e3c1b071 2446 if (r) {
2447 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
2448 r, adev_to_drm(adev)->unique);
2449 }
2450 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
2451 r = -EALREADY;
2452 }
2453 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2454 adev = mgpu_info.gpu_ins[i].adev;
e3c1b071 2455 flush_work(&adev->xgmi_reset_work);
050743da 2456 adev->gmc.xgmi.pending_reset = false;
e3c1b071 2457 }
2458
2459 /* reset function will rebuild the xgmi hive info , clear it now */
2460 for (i = 0; i < mgpu_info.num_dgpu; i++)
2461 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
2462
2463 INIT_LIST_HEAD(&device_list);
2464
2465 for (i = 0; i < mgpu_info.num_dgpu; i++)
2466 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
2467
2468 /* unregister the GPU first, reset function will add them back */
2469 list_for_each_entry(adev, &device_list, reset_list)
2470 amdgpu_unregister_gpu_instance(adev);
2471
04442bf7
LL		 2472 /* Use a common context, just need to make sure full reset is done */
2473 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
2474 r = amdgpu_do_asic_reset(&device_list, &reset_context);
2475
e3c1b071 2476 if (r) {
2477 DRM_ERROR("reinit gpus failure");
2478 return;
2479 }
2480 for (i = 0; i < mgpu_info.num_dgpu; i++) {
2481 adev = mgpu_info.gpu_ins[i].adev;
2482 if (!adev->kfd.init_complete)
2483 amdgpu_amdkfd_device_init(adev);
2484 amdgpu_ttm_set_buffer_funcs_status(adev, true);
2485 }
e3c1b071 2486}
2487
e25443d2
AD		 2488static int amdgpu_pmops_prepare(struct device *dev)
2489{
2490 struct drm_device *drm_dev = dev_get_drvdata(dev);
d2a197a4 2491 struct amdgpu_device *adev = drm_to_adev(drm_dev);
e25443d2
AD		 2492
2493 /* Return a positive number here so
2494 * DPM_FLAG_SMART_SUSPEND works properly
2495 */
5095d541
ML		 2496 if (amdgpu_device_supports_boco(drm_dev) &&
2497 pm_runtime_suspended(dev))
2498 return 1;
e25443d2 2499
d2a197a4
ML		 2500 /* if we will not support s3 or s2i for the device
2501 * then skip suspend
2502 */
2503 if (!amdgpu_acpi_is_s0ix_active(adev) &&
2504 !amdgpu_acpi_is_s3_active(adev))
2505 return 1;
e25443d2 2506
5095d541 2507 return amdgpu_device_prepare(drm_dev);
e25443d2
AD		 2508}
2509
2510static void amdgpu_pmops_complete(struct device *dev)
2511{
2512 /* nothing to do */
2513}
2514
d38ceaf9
AD		 2515static int amdgpu_pmops_suspend(struct device *dev)
2516{
911d8b30 2517 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733 2518 struct amdgpu_device *adev = drm_to_adev(drm_dev);
74b0b157 2519
0326de4c 2520 adev->suspend_complete = false;
d0260f62 2521 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2522 adev->in_s0ix = true;
ca475186 2523 else if (amdgpu_acpi_is_s3_active(adev))
eac4c54b 2524 adev->in_s3 = true;
ca475186
ML		 2525 if (!adev->in_s0ix && !adev->in_s3)
2526 return 0;
9e051720
KHF		 2527 return amdgpu_device_suspend(drm_dev, true);
2528}
2529
2530static int amdgpu_pmops_suspend_noirq(struct device *dev)
2531{
2532 struct drm_device *drm_dev = dev_get_drvdata(dev);
2533 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2534
0326de4c 2535 adev->suspend_complete = true;
0223e516 2536 if (amdgpu_acpi_should_gpu_reset(adev))
9e051720
KHF		 2537 return amdgpu_asic_reset(adev);
2538
2539 return 0;
d38ceaf9
AD		 2540}
2541
2542static int amdgpu_pmops_resume(struct device *dev)
2543{
911d8b30 2544 struct drm_device *drm_dev = dev_get_drvdata(dev);
62498733
AD		 2545 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2546 int r;
85e154c2 2547
ca475186
ML		 2548 if (!adev->in_s0ix && !adev->in_s3)
2549 return 0;
2550
ebe86a57
AG		 2551 /* Avoids registers access if device is physically gone */
2552 if (!pci_device_is_present(adev->pdev))
2553 adev->no_hw_access = true;
2554
62498733 2555 r = amdgpu_device_resume(drm_dev, true);
d0260f62 2556 if (amdgpu_acpi_is_s0ix_active(adev))
62498733 2557 adev->in_s0ix = false;
eac4c54b
ML		 2558 else
2559 adev->in_s3 = false;
62498733 2560 return r;
d38ceaf9
AD		 2561}
2562
2563static int amdgpu_pmops_freeze(struct device *dev)
2564{
911d8b30 2565 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2566 struct amdgpu_device *adev = drm_to_adev(drm_dev);
897483d8 2567 int r;
74b0b157 2568
62498733 2569 adev->in_s4 = true;
de185019 2570 r = amdgpu_device_suspend(drm_dev, true);
62498733 2571 adev->in_s4 = false;
897483d8
AD		 2572 if (r)
2573 return r;
af1f2985
TH		 2574
2575 if (amdgpu_acpi_should_gpu_reset(adev))
2576 return amdgpu_asic_reset(adev);
2577 return 0;
d38ceaf9
AD		 2578}
2579
2580static int amdgpu_pmops_thaw(struct device *dev)
2581{
911d8b30 2582 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2583
de185019 2584 return amdgpu_device_resume(drm_dev, true);
74b0b157 2585}
2586
2587static int amdgpu_pmops_poweroff(struct device *dev)
2588{
911d8b30 2589 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2590
62498733 2591 return amdgpu_device_suspend(drm_dev, true);
74b0b157 2592}
2593
2594static int amdgpu_pmops_restore(struct device *dev)
2595{
911d8b30 2596 struct drm_device *drm_dev = dev_get_drvdata(dev);
74b0b157 2597
de185019 2598 return amdgpu_device_resume(drm_dev, true);
d38ceaf9
AD		 2599}
2600
4020c228
AD		 2601static int amdgpu_runtime_idle_check_display(struct device *dev)
2602{
2603 struct pci_dev *pdev = to_pci_dev(dev);
2604 struct drm_device *drm_dev = pci_get_drvdata(pdev);
2605 struct amdgpu_device *adev = drm_to_adev(drm_dev);
2606
2607 if (adev->mode_info.num_crtc) {
2608 struct drm_connector *list_connector;
2609 struct drm_connector_list_iter iter;
2610 int ret = 0;
2611
4d6fc55a
AD		 2612 if (amdgpu_runtime_pm != -2) {
2613 /* XXX: Return busy if any displays are connected to avoid
2614 * possible display wakeups after runtime resume due to
2615 * hotplug events in case any displays were connected while
2616 * the GPU was in suspend. Remove this once that is fixed.
2617 */
2618 mutex_lock(&drm_dev->mode_config.mutex);
2619 drm_connector_list_iter_begin(drm_dev, &iter);
2620 drm_for_each_connector_iter(list_connector, &iter) {
2621 if (list_connector->status == connector_status_connected) {
2622 ret = -EBUSY;
2623 break;
2624 }
4020c228 2625 }
4d6fc55a
AD		 2626 drm_connector_list_iter_end(&iter);
2627 mutex_unlock(&drm_dev->mode_config.mutex);
4020c228 2628
4d6fc55a
AD		 2629 if (ret)
2630 return ret;
2631 }
4020c228 2632
d09ef243 2633 if (adev->dc_enabled) {
4020c228
AD		 2634 struct drm_crtc *crtc;
2635
2636 drm_for_each_crtc(crtc, drm_dev) {
2637 drm_modeset_lock(&crtc->mutex, NULL);
2638 if (crtc->state->active)
2639 ret = -EBUSY;
2640 drm_modeset_unlock(&crtc->mutex);
2641 if (ret < 0)
2642 break;
2643 }
2644 } else {
2645 mutex_lock(&drm_dev->mode_config.mutex);
2646 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2647
2648 drm_connector_list_iter_begin(drm_dev, &iter);
2649 drm_for_each_connector_iter(list_connector, &iter) {
2650 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
2651 ret = -EBUSY;
2652 break;
2653 }
2654 }
2655
2656 drm_connector_list_iter_end(&iter);
2657
2658 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2659 mutex_unlock(&drm_dev->mode_config.mutex);
2660 }
2661 if (ret)
2662 return ret;
2663 }
2664
2665 return 0;
2666}
2667
d38ceaf9
AD		 2668static int amdgpu_pmops_runtime_suspend(struct device *dev)
2669{
2670 struct pci_dev *pdev = to_pci_dev(dev);
2671 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2672 struct amdgpu_device *adev = drm_to_adev(drm_dev);
719423f6 2673 int ret, i;
d38ceaf9 2674
9c913f38 2675 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2676 pm_runtime_forbid(dev);
2677 return -EBUSY;
2678 }
2679
4020c228
AD		 2680 ret = amdgpu_runtime_idle_check_display(dev);
2681 if (ret)
2682 return ret;
2683
719423f6
AD		 2684 /* wait for all rings to drain before suspending */
2685 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
2686 struct amdgpu_ring *ring = adev->rings[i];
f9acfafc 2687
719423f6
AD		 2688 if (ring && ring->sched.ready) {
2689 ret = amdgpu_fence_wait_empty(ring);
2690 if (ret)
2691 return -EBUSY;
2692 }
2693 }
2694
f0f7ddfc 2695 adev->in_runpm = true;
b98c6299 2696 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2697 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
d38ceaf9 2698
7be3be2b
EQ		 2699 /*
2700 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some
2701 * proper cleanups and put itself into a state ready for PNP. That
2702 * can address some random resuming failure observed on BOCO capable
2703 * platforms.
2704 * TODO: this may be also needed for PX capable platform.
2705 */
2706 if (amdgpu_device_supports_boco(drm_dev))
2707 adev->mp1_state = PP_MP1_STATE_UNLOAD;
2708
5095d541
ML		 2709 ret = amdgpu_device_prepare(drm_dev);
2710 if (ret)
2711 return ret;
de185019 2712 ret = amdgpu_device_suspend(drm_dev, false);
cef8b03b
AD		 2713 if (ret) {
2714 adev->in_runpm = false;
7be3be2b
EQ		 2715 if (amdgpu_device_supports_boco(drm_dev))
2716 adev->mp1_state = PP_MP1_STATE_NONE;
70bedd68 2717 return ret;
cef8b03b 2718 }
70bedd68 2719
7be3be2b
EQ		 2720 if (amdgpu_device_supports_boco(drm_dev))
2721 adev->mp1_state = PP_MP1_STATE_NONE;
2722
b98c6299 2723 if (amdgpu_device_supports_px(drm_dev)) {
562b49fc
AD		 2724 /* Only need to handle PCI state in the driver for ATPX
2725 * PCI core handles it for _PR3.
2726 */
b98c6299
AD		 2727 amdgpu_device_cache_pci_state(pdev);
2728 pci_disable_device(pdev);
2729 pci_ignore_hotplug(pdev);
2730 pci_set_power_state(pdev, PCI_D3cold);
b97e9d47 2731 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
11e612a0
AD		 2732 } else if (amdgpu_device_supports_boco(drm_dev)) {
2733 /* nothing to do */
19134317
AD		 2734 } else if (amdgpu_device_supports_baco(drm_dev)) {
2735 amdgpu_device_baco_enter(drm_dev);
b97e9d47 2736 }
d38ceaf9 2737
abcb2ace 2738 dev_dbg(&pdev->dev, "asic/device is runtime suspended\n");
f4b09c29 2739
d38ceaf9
AD		 2740 return 0;
2741}
2742
2743static int amdgpu_pmops_runtime_resume(struct device *dev)
2744{
2745 struct pci_dev *pdev = to_pci_dev(dev);
2746 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1348969a 2747 struct amdgpu_device *adev = drm_to_adev(drm_dev);
d38ceaf9
AD		 2748 int ret;
2749
9c913f38 2750 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE)
d38ceaf9
AD		 2751 return -EINVAL;
2752
e1543d83
AG		 2753 /* Avoids registers access if device is physically gone */
2754 if (!pci_device_is_present(adev->pdev))
2755 adev->no_hw_access = true;
2756
b98c6299 2757 if (amdgpu_device_supports_px(drm_dev)) {
b97e9d47
AD		 2758 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
2759
562b49fc
AD		 2760 /* Only need to handle PCI state in the driver for ATPX
2761 * PCI core handles it for _PR3.
2762 */
b98c6299
AD		 2763 pci_set_power_state(pdev, PCI_D0);
2764 amdgpu_device_load_pci_state(pdev);
2765 ret = pci_enable_device(pdev);
2766 if (ret)
2767 return ret;
637bb036 2768 pci_set_master(pdev);
fd496ca8
AD		 2769 } else if (amdgpu_device_supports_boco(drm_dev)) {
2770 /* Only need to handle PCI state in the driver for ATPX
2771 * PCI core handles it for _PR3.
2772 */
2773 pci_set_master(pdev);
19134317
AD		 2774 } else if (amdgpu_device_supports_baco(drm_dev)) {
2775 amdgpu_device_baco_exit(drm_dev);
b97e9d47 2776 }
de185019 2777 ret = amdgpu_device_resume(drm_dev, false);
6b11af6d
YY		 2778 if (ret) {
2779 if (amdgpu_device_supports_px(drm_dev))
2780 pci_disable_device(pdev);
b45aeb2d 2781 return ret;
6b11af6d 2782 }
b45aeb2d 2783
b98c6299 2784 if (amdgpu_device_supports_px(drm_dev))
b97e9d47 2785 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
f0f7ddfc 2786 adev->in_runpm = false;
d38ceaf9
AD		 2787 return 0;
2788}
2789
2790static int amdgpu_pmops_runtime_idle(struct device *dev)
2791{
911d8b30 2792 struct drm_device *drm_dev = dev_get_drvdata(dev);
1348969a 2793 struct amdgpu_device *adev = drm_to_adev(drm_dev);
b07395d5 2794 int ret;
d38ceaf9 2795
9c913f38 2796 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) {
d38ceaf9
AD		 2797 pm_runtime_forbid(dev);
2798 return -EBUSY;
2799 }
2800
4020c228 2801 ret = amdgpu_runtime_idle_check_display(dev);
97f6a21b 2802
d38ceaf9
AD		 2803 pm_runtime_mark_last_busy(dev);
2804 pm_runtime_autosuspend(dev);
97f6a21b 2805 return ret;
d38ceaf9
AD		 2806}
2807
2808long amdgpu_drm_ioctl(struct file *filp,
2809 unsigned int cmd, unsigned long arg)
2810{
2811 struct drm_file *file_priv = filp->private_data;
2812 struct drm_device *dev;
2813 long ret;
f9acfafc 2814
d38ceaf9
AD		 2815 dev = file_priv->minor->dev;
2816 ret = pm_runtime_get_sync(dev->dev);
2817 if (ret < 0)
5509ac65 2818 goto out;
d38ceaf9
AD		 2819
2820 ret = drm_ioctl(filp, cmd, arg);
2821
2822 pm_runtime_mark_last_busy(dev->dev);
5509ac65 2823out:
d38ceaf9
AD		 2824 pm_runtime_put_autosuspend(dev->dev);
2825 return ret;
2826}
2827
2828static const struct dev_pm_ops amdgpu_pm_ops = {
e25443d2
AD		 2829 .prepare = amdgpu_pmops_prepare,
2830 .complete = amdgpu_pmops_complete,
d38ceaf9 2831 .suspend = amdgpu_pmops_suspend,
9e051720 2832 .suspend_noirq = amdgpu_pmops_suspend_noirq,
d38ceaf9
AD		 2833 .resume = amdgpu_pmops_resume,
2834 .freeze = amdgpu_pmops_freeze,
2835 .thaw = amdgpu_pmops_thaw,
74b0b157 2836 .poweroff = amdgpu_pmops_poweroff,
2837 .restore = amdgpu_pmops_restore,
d38ceaf9
AD		 2838 .runtime_suspend = amdgpu_pmops_runtime_suspend,
2839 .runtime_resume = amdgpu_pmops_runtime_resume,
2840 .runtime_idle = amdgpu_pmops_runtime_idle,
2841};
2842
48ad368a
AG		 2843static int amdgpu_flush(struct file *f, fl_owner_t id)
2844{
2845 struct drm_file *file_priv = f->private_data;
2846 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
56753e73 2847 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
48ad368a 2848
56753e73
CK		 2849 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
2850 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
48ad368a 2851
56753e73 2852 return timeout >= 0 ? 0 : timeout;
48ad368a
AG		 2853}
2854
d38ceaf9
AD		 2855static const struct file_operations amdgpu_driver_kms_fops = {
2856 .owner = THIS_MODULE,
2857 .open = drm_open,
48ad368a 2858 .flush = amdgpu_flush,
d38ceaf9
AD		 2859 .release = drm_release,
2860 .unlocked_ioctl = amdgpu_drm_ioctl,
71df0368 2861 .mmap = drm_gem_mmap,
d38ceaf9
AD		 2862 .poll = drm_poll,
2863 .read = drm_read,
2864#ifdef CONFIG_COMPAT
2865 .compat_ioctl = amdgpu_kms_compat_ioctl,
2866#endif
87444254 2867#ifdef CONFIG_PROC_FS
376c25f8 2868 .show_fdinfo = drm_show_fdinfo,
87444254 2869#endif
d38ceaf9
AD		 2870};
2871
021830d2
BN		 2872int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
2873{
f3729f7b 2874 struct drm_file *file;
021830d2
BN		 2875
2876 if (!filp)
2877 return -EINVAL;
2878
f9acfafc 2879 if (filp->f_op != &amdgpu_driver_kms_fops)
021830d2 2880 return -EINVAL;
021830d2
BN		 2881
2882 file = filp->private_data;
2883 *fpriv = file->driver_priv;
2884 return 0;
2885}
2886
5088d657
LT		 2887const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
2888 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2889 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2890 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2891 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
2892 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2893 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2894 /* KMS */
2895 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2896 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2897 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2898 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2899 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2900 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2901 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2902 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2903 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2904 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2905};
2906
2907static const struct drm_driver amdgpu_kms_driver = {
d38ceaf9 2908 .driver_features =
f3ed6739 2909 DRIVER_ATOMIC |
1ff49481 2910 DRIVER_GEM |
db4ff423
CZ		 2911 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
2912 DRIVER_SYNCOBJ_TIMELINE,
d38ceaf9 2913 .open = amdgpu_driver_open_kms,
d38ceaf9
AD		 2914 .postclose = amdgpu_driver_postclose_kms,
2915 .lastclose = amdgpu_driver_lastclose_kms,
d38ceaf9 2916 .ioctls = amdgpu_ioctls_kms,
5088d657 2917 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
d38ceaf9
AD		 2918 .dumb_create = amdgpu_mode_dumb_create,
2919 .dumb_map_offset = amdgpu_mode_dumb_mmap,
d38ceaf9 2920 .fops = &amdgpu_driver_kms_fops,
72c8c97b 2921 .release = &amdgpu_driver_release_kms,
1a56fcf0 2922#ifdef CONFIG_PROC_FS
376c25f8 2923 .show_fdinfo = amdgpu_show_fdinfo,
1a56fcf0 2924#endif
d38ceaf9 2925
09052fc3 2926 .gem_prime_import = amdgpu_gem_prime_import,
d38ceaf9
AD		 2927
2928 .name = DRIVER_NAME,
2929 .desc = DRIVER_DESC,
2930 .date = DRIVER_DATE,
2931 .major = KMS_DRIVER_MAJOR,
2932 .minor = KMS_DRIVER_MINOR,
2933 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2934};
2935
2c1c7ba4
JZ		 2936const struct drm_driver amdgpu_partition_driver = {
2937 .driver_features =
2938 DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ |
2939 DRIVER_SYNCOBJ_TIMELINE,
2940 .open = amdgpu_driver_open_kms,
2941 .postclose = amdgpu_driver_postclose_kms,
2942 .lastclose = amdgpu_driver_lastclose_kms,
2943 .ioctls = amdgpu_ioctls_kms,
2944 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
2945 .dumb_create = amdgpu_mode_dumb_create,
2946 .dumb_map_offset = amdgpu_mode_dumb_mmap,
2947 .fops = &amdgpu_driver_kms_fops,
2948 .release = &amdgpu_driver_release_kms,
2949
2c1c7ba4 2950 .gem_prime_import = amdgpu_gem_prime_import,
d38ceaf9
AD		 2951
2952 .name = DRIVER_NAME,
2953 .desc = DRIVER_DESC,
2954 .date = DRIVER_DATE,
2955 .major = KMS_DRIVER_MAJOR,
2956 .minor = KMS_DRIVER_MINOR,
2957 .patchlevel = KMS_DRIVER_PATCHLEVEL,
2958};
2959
c9a6b82f
AG		 2960static struct pci_error_handlers amdgpu_pci_err_handler = {
2961 .error_detected = amdgpu_pci_error_detected,
2962 .mmio_enabled = amdgpu_pci_mmio_enabled,
2963 .slot_reset = amdgpu_pci_slot_reset,
2964 .resume = amdgpu_pci_resume,
2965};
2966
35bba831
AG		 2967static const struct attribute_group *amdgpu_sysfs_groups[] = {
2968 &amdgpu_vram_mgr_attr_group,
2969 &amdgpu_gtt_mgr_attr_group,
521289d2 2970 &amdgpu_flash_attr_group,
35bba831
AG		 2971 NULL,
2972};
2973
d38ceaf9
AD		 2974static struct pci_driver amdgpu_kms_pci_driver = {
2975 .name = DRIVER_NAME,
2976 .id_table = pciidlist,
2977 .probe = amdgpu_pci_probe,
2978 .remove = amdgpu_pci_remove,
61e11306 2979 .shutdown = amdgpu_pci_shutdown,
d38ceaf9 2980 .driver.pm = &amdgpu_pm_ops,
c9a6b82f 2981 .err_handler = &amdgpu_pci_err_handler,
35bba831 2982 .dev_groups = amdgpu_sysfs_groups,
d38ceaf9
AD		 2983};
2984
2985static int __init amdgpu_init(void)
2986{
245ae5e9
CK		 2987 int r;
2988
6a2d2ddf 2989 if (drm_firmware_drivers_only())
c60e22f7 2990 return -EINVAL;
c60e22f7 2991
245ae5e9
CK		 2992 r = amdgpu_sync_init();
2993 if (r)
2994 goto error_sync;
2995
2996 r = amdgpu_fence_slab_init();
2997 if (r)
2998 goto error_fence;
2999
d38ceaf9 3000 DRM_INFO("amdgpu kernel modesetting enabled.\n");
d38ceaf9 3001 amdgpu_register_atpx_handler();
f9b7f370 3002 amdgpu_acpi_detect();
03a1c08d
FK		 3003
3004 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
3005 amdgpu_amdkfd_init();
3006
d38ceaf9 3007 /* let modprobe override vga console setting */
448d1051 3008 return pci_register_driver(&amdgpu_kms_pci_driver);
245ae5e9 3009
245ae5e9
CK		 3010error_fence:
3011 amdgpu_sync_fini();
3012
3013error_sync:
3014 return r;
d38ceaf9
AD		 3015}
3016
3017static void __exit amdgpu_exit(void)
3018{
130e0371 3019 amdgpu_amdkfd_fini();
448d1051 3020 pci_unregister_driver(&amdgpu_kms_pci_driver);
d38ceaf9 3021 amdgpu_unregister_atpx_handler();
4d5275ab 3022 amdgpu_acpi_release();
257bf15a 3023 amdgpu_sync_fini();
d573de2d 3024 amdgpu_fence_slab_fini();
c7d8b782 3025 mmu_notifier_synchronize();
9938333a 3026 amdgpu_xcp_drv_release();
d38ceaf9
AD		 3027}
3028
3029module_init(amdgpu_init);
3030module_exit(amdgpu_exit);
3031
3032MODULE_AUTHOR(DRIVER_AUTHOR);
3033MODULE_DESCRIPTION(DRIVER_DESC);
3034MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)